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DS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification12006–2015Xilinx,Inc.
,Xilinx,theXilinxlogo,Artix,ISE,Kintex,Spartan,UltraScale,Virtex,Vivado,Zynq,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.
PCI,PCIe,andPCIExpressaretrademarksofPCI-SIGandusedunderlicense.
PowerPCisatrademarkofIBMCorp.
andisusedunderlicense.
Allothertrademarksarethepropertyoftheirrespectiveowners.
GeneralDescriptionUsingthesecondgenerationASMBL(AdvancedSiliconModularBlock)column-basedarchitecture,theVirtex-5familycontainsfivedistinctplatforms(sub-families),themostchoiceofferedbyanyFPGAfamily.
Eachplatformcontainsadifferentratiooffeaturestoaddresstheneedsofawidevarietyofadvancedlogicdesigns.
Inadditiontothemostadvanced,high-performancelogicfabric,Virtex-5FPGAscontainmanyhard-IPsystemlevelblocks,includingpowerful36-KbitblockRAM/FIFOs,secondgeneration25x18DSPslices,SelectIOtechnologywithbuilt-indigitally-controlledimpedance,ChipSyncsource-synchronousinterfaceblocks,systemmonitorfunctionality,enhancedclockmanagementtileswithintegratedDCM(DigitalClockManagers)andphase-locked-loop(PLL)clockgenerators,andadvancedconfigurationoptions.
Additionalplatformdependantfeaturesincludepower-optimizedhigh-speedserialtransceiverblocksforenhancedserialconnectivity,PCIExpresscompliantintegratedEndpointblocks,tri-modeEthernetMACs(MediaAccessControllers),andhigh-performancePowerPC440microprocessorembeddedblocks.
ThesefeaturesallowadvancedlogicdesignerstobuildthehighestlevelsofperformanceandfunctionalityintotheirFPGA-basedsystems.
Builtona65-nmstate-of-the-artcopperprocesstechnology,Virtex-5FPGAsareaprogrammablealternativetocustomASICtechnology.
MostadvancedsystemdesignsrequiretheprogrammablestrengthofFPGAs.
Virtex-5FPGAsofferthebestsolutionforaddressingtheneedsofhigh-performancelogicdesigners,high-performanceDSPdesigners,andhigh-performanceembeddedsystemsdesignerswithunprecedentedlogic,DSP,hard/softmicroprocessor,andconnectivitycapabilities.
TheVirtex-5LXT,SXT,TXT,andFXTplatformsincludeadvancedhigh-speedserialconnectivityandlink/transactionlayercapability.
SummaryofVirtex-5FPGAFeaturesFiveplatformsLX,LXT,SXT,TXT,andFXTVirtex-5LX:High-performancegenerallogicapplicationsVirtex-5LXT:High-performancelogicwithadvancedserialconnectivityVirtex-5SXT:High-performancesignalprocessingapplicationswithadvancedserialconnectivityVirtex-5TXT:High-performancesystemswithdoubledensityadvancedserialconnectivityVirtex-5FXT:High-performanceembeddedsystemswithadvancedserialconnectivityCross-platformcompatibilityLXT,SXT,andFXTdevicesarefootprintcompatibleinthesamepackageusingadjustablevoltageregulatorsMostadvanced,high-performance,optimal-utilization,FPGAfabricReal6-inputlook-uptable(LUT)technologyDual5-LUToptionImprovedreduced-hoprouting64-bitdistributedRAMoptionSRL32/DualSRL16optionPowerfulclockmanagementtile(CMT)clockingDigitalClockManager(DCM)blocksforzerodelaybuffering,frequencysynthesis,andclockphaseshiftingPLLblocksforinputjitterfiltering,zerodelaybuffering,frequencysynthesis,andphase-matchedclockdivision36-KbitblockRAM/FIFOsTruedual-portRAMblocksEnhancedoptionalprogrammableFIFOlogicProgrammable-Truedual-portwidthsuptox36-Simpledual-portwidthsuptox72Built-inoptionalerror-correctioncircuitryOptionallyprogrameachblockastwoindependent18-KbitblocksHigh-performanceparallelSelectIOtechnology1.
2to3.
3VI/OOperationSource-synchronousinterfacingusingChipSynctechnologyDigitally-controlledimpedance(DCI)activeterminationFlexiblefine-grainedI/ObankingHigh-speedmemoryinterfacesupportAdvancedDSP48Eslices25x18,two'scomplement,multiplicationOptionaladder,subtracter,andaccumulatorOptionalpipeliningOptionalbitwiselogicalfunctionalityDedicatedcascadeconnectionsFlexibleconfigurationoptionsSPIandParallelFLASHinterfaceMulti-bitstreamsupportwithdedicatedfallbackreconfigurationlogicAutobuswidthdetectioncapabilitySystemMonitoringcapabilityonalldevicesOn-chip/Off-chipthermalmonitoringOn-chip/Off-chippowersupplymonitoringJTAGaccesstoallmonitoredquantitiesIntegratedEndpointblocksforPCIExpressDesignsLXT,SXT,TXT,andFXTPlatformsCompliantwiththePCIExpressBaseSpecification1.
1x1,x4,orx8lanesupportperblockWorksinconjunctionwithRocketIOtransceiversTri-mode10/100/1000Mb/sEthernetMACsLXT,SXT,TXT,andFXTPlatformsRocketIOtransceiverscanbeusedasPHYorconnecttoexternalPHYusingmanysoftMII(MediaIndependentInterface)optionsRocketIOGTPtransceivers100Mb/sto3.
75Gb/sLXTandSXTPlatformsRocketIOGTXtransceivers150Mb/sto6.
5Gb/sTXTandFXTPlatformsPowerPC440MicroprocessorsFXTPlatformonlyRISCarchitecture7-stagepipeline32-KbyteinstructionanddatacachesincludedOptimizedprocessorinterfacestructure(crossbar)65-nmcopperCMOSprocesstechnology1.
0VcorevoltageHighsignal-integrityflip-chippackagingavailableinstandardorPb-freepackageoptions0Virtex-5FamilyOverviewDS100(v5.
1)August21,201500ProductSpecificationRVirtex-5FamilyOverview2www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRTable1:Virtex-5FPGAFamilyMembersDeviceConfigurableLogicBlocks(CLBs)DSP48ESlices(2)BlockRAMBlocksCMTs(4)PowerPCProcessorBlocksEndpointBlocksforPCIExpressEthernetMACs(5)MaxRocketIOTransceivers(6)TotalI/OBanks(8)MaxUserI/O(7)Array(RowxCol)Virtex-5Slices(1)MaxDistributedRAM(Kb)18Kb(3)36KbMax(Kb)GTPGTXXC5VLX3080x304,8003203264321,1522N/AN/AN/AN/AN/A13400XC5VLX50120x307,2004804896481,7286N/AN/AN/AN/AN/A17560XC5VLX85120x5412,96084048192963,4566N/AN/AN/AN/AN/A17560XC5VLX110160x5417,2801,120642561284,6086N/AN/AN/AN/AN/A23800XC5VLX155160x7624,3201,6401283841926,9126N/AN/AN/AN/AN/A23800XC5VLX220160x10834,5602,2801283841926,9126N/AN/AN/AN/AN/A23800XC5VLX330240x10851,8403,42019257628810,3686N/AN/AN/AN/AN/A331,200XC5VLX20T60x263,1202102452269361N/A124N/A7172XC5VLX30T80x304,8003203272361,2962N/A148N/A12360XC5VLX50T120x307,20048048120602,1606N/A1412N/A15480XC5VLX85T120x5412,960840482161083,8886N/A1412N/A15480XC5VLX110T160x5417,2801,120642961485,3286N/A1416N/A20680XC5VLX155T160x7624,3201,6401284242127,6326N/A1416N/A20680XC5VLX220T160x10834,5602,2801284242127,6326N/A1416N/A20680XC5VLX330T240x10851,8403,42019264832411,6646N/A1424N/A27960XC5VSX35T80x345,440520192168843,0242N/A148N/A12360XC5VSX50T120x348,1607802882641324,7526N/A1412N/A15480XC5VSX95T160x4614,7201,5206404882448,7846N/A1416N/A19640XC5VSX240T240x7837,4404,2001,0561,03251618,5766N/A1424N/A27960XC5VTX150T200x5823,2001,500804562288,2086N/A14N/A4020680XC5VTX240T240x7837,4402,4009664832411,6646N/A14N/A4820680XC5VFX30T80x385,12038064136682,4482114N/A812360XC5VFX70T160x3811,2008201282961485,3286134N/A1619640XC5VFX100T160x5616,0001,2402564562288,2086234N/A1620680XC5VFX130T200x5620,4801,58032059629810,7286236N/A2024840XC5VFX200T240x6830,7202,28038491245616,4166248N/A2427960Notes:1.
Virtex-5FPGAslicesareorganizeddifferentlyfrompreviousgenerations.
EachVirtex-5FPGAslicecontainsfourLUTsandfourflip-flops(previouslyitwastwoLUTsandtwoflip-flops.
)2.
EachDSP48Eslicecontainsa25x18multiplier,anadder,andanaccumulator.
3.
BlockRAMsarefundamentally36Kbitsinsize.
Eachblockcanalsobeusedastwoindependent18-Kbitblocks.
4.
EachClockManagementTile(CMT)containstwoDCMsandonePLL.
5.
ThistablelistsseparateEthernetMACsperdevice.
6.
RocketIOGTPtransceiversaredesignedtorunfrom100Mb/sto3.
75Gb/s.
RocketIOGTXtransceiversaredesignedtorunfrom150Mb/sto6.
5Gb/s.
7.
ThisnumberdoesnotincludeRocketIOtransceivers.
8.
IncludesconfigurationBank0.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification3RVirtex-5FPGALogicOnaverage,onetotwospeedgradeimprovementoverVirtex-4devicesCascadable32-bitvariableshiftregistersor64-bitdistributedmemorycapabilitySuperiorroutingarchitecturewithenhanceddiagonalroutingsupportsblock-to-blockconnectivitywithminimalhopsUpto330,000logiccellsincluding:Upto207,360internalfabricflip-flopswithclockenable(XC5VLX330)Upto207,360real6-inputlook-uptables(LUTs)withgreaterthan13milliontotalLUTbitsTwooutputsfordual5-LUTmodegivesenhancedutilizationLogicexpandingmultiplexersandI/Oregisters550MHzClockTechnologyUptosixClockManagementTiles(CMTs)EachCMTcontainstwoDCMsandonePLL—uptoeighteentotalclockgeneratorsFlexibleDCM-to-PLLorPLL-to-DCMcascadePrecisionclockdeskewandphaseshiftFlexiblefrequencysynthesisMultipleoperatingmodestoeaseperformancetrade-offdecisionsImprovedmaximuminput/outputfrequencyFine-grainedphaseshiftingresolutionInputjitterfilteringLow-poweroperationWidephaseshiftrangeDifferentialclocktreestructureforoptimizedlow-jitterclockingandprecisedutycycle32globalclocknetworksRegional,I/O,andlocalclocksinadditiontoglobalclocksSelectIOTechnologyUpto1,200userI/OsWideselectionofI/Ostandardsfrom1.
2Vto3.
3VExtremelyhigh-performanceUpto800Mb/sHSTLandSSTL(onallsingle-endedI/Os)Upto1.
25Gb/sLVDS(onalldifferentialI/Opairs)Truedifferentialterminationon-chipSameedgecaptureatinputandoutputI/OsExtensivememoryinterfacesupport550MHzIntegratedBlockMemoryUpto16.
4Mbitsofintegratedblockmemory36-Kbitblockswithoptionaldual18-KbitmodeTruedual-portRAMcellsIndependentportwidthselection(x1tox72)Uptox36totalperportfortruedualportoperationUptox72totalperportforsimpledualportoperation(oneReadportandoneWriteport)Memorybitsplusparity/sidebandmemorysupportforx9,x18,x36,andx72widthsConfigurationsfrom32Kx1to512x72(8Kx4to512x72forFIFOoperation)MultirateFIFOsupportlogicFullandEmptyflagwithfullyprogrammableAlmostFullandAlmostEmptyflagsSynchronousFIFOsupportwithoutFlaguncertaintyOptionalpipelinestagesforhigherperformanceByte-writecapabilityDedicatedcascaderoutingtoform64Kx1memorywithoutusingFPGAroutingIntegratedoptionalECCforhigh-reliabilitymemoryrequirementsSpecialreduced-powerdesignfor18Kbit(andbelow)operation550MHzDSP48ESlices25x18two'scomplementmultiplicationOptionalpipelinestagesforenhancedperformanceOptional48-bitaccumulatorformultiplyaccumulate(MACC)operationwithoptionalaccumulatorcascadeto96-bitsIntegratedadderforcomplex-multiplyormultiply-addoperationOptionalbitwiselogicaloperationmodesIndependentCregisterspersliceFullycascadableinaDSPcolumnwithoutexternalroutingresourcesChipSyncSource-SynchronousInterfacingLogicWorksinconjunctionwithSelectIOtechnologytosimplifysource-synchronousinterfacesPer-bitdeskewcapabilitybuiltintoallI/Oblocks(variabledelaylineonallinputsandoutputs)DedicatedI/Oandregionalclockingresources(pinsandtrees)Built-indataserializer/deserializerlogicwithcorrespondingclockdividersupportinallI/ONetworking/telecommunicationinterfacesupto1.
25Gb/sperI/OVirtex-5FamilyOverview4www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRDigitallyControlledImpedance(DCI)ActiveI/OTerminationOptionalseriesorparallelterminationTemperatureandvoltagecompensationMakesboardlayoutmucheasierReducesresistorsPlacesterminationintheideallocation,atthesignalsourceordestinationConfigurationSupportforplatformFlash,standardSPIFlash,orstandardparallelNORFlashconfigurationBitstreamsupportwithdedicatedfallbackreconfigurationlogic256-bitAESbitstreamdecryptionprovidesintellectualpropertysecurityandpreventsdesigncopyingImprovedbitstreamerrordetection/correctioncapabilityAutobuswidthdetectioncapabilityPartialReconfigurationviaICAPportAdvancedFlip-ChipPackagingPre-engineeredpackagingtechnologyforprovensuperiorsignalintegrityMinimizedinductiveloopsfromsignaltoreturnOptimalsignal-to-PWR/GNDratiosReducesSSOinducednoisebyupto7xPb-FreeandstandardpackagesSystemMonitorOn-Chiptemperaturemeasurement(±4°C)On-Chippowersupplymeasurement(±1%)Easytouse,self-containedNodesignrequiredforbasicoperationAutonomousmonitoringofallon-chipsensorsUserprogrammablealarmthresholdsforon-chipsensorsUseraccessible10-bit200kSPSADCAutomaticcalibrationofoffsetandgainerrorDNL=±0.
9LSBsmaximumUpto17externalanaloginputchannelssupported0Vto1VinputrangeMonitorexternalsensorse.
g.
,voltage,temperatureGeneralpurposeanaloginputsFullaccessfromfabricorJTAGTAPtoSystemMonitorFullyoperationalpriortoFPGAconfigurationandduringdevicepowerdown(accessviaJTAGTAPonly)65-nmCopperCMOSProcess1.
0VCoreVoltage12-layermetalprovidesmaximumroutingcapabilityandaccommodateshard-IPimmersionTriple-oxidetechnologyforprovenreducedstaticpowerconsumptionSystemBlocksSpecifictotheLXT,SXT,TXT,andFXTDevicesIntegratedEndpointBlockforPCIExpressComplianceWorksinconjunctionwithRocketIOGTPtransceivers(LXTandSXT)andGTXtransceivers(TXTandFXT)todeliverfullPCIExpressEndpointfunctionalitywithminimalFPGAlogicutilization.
CompliantwiththePCIExpressBaseSpecification1.
1PCIExpressEndpointblockorLegacyPCIExpressEndpointblockx8,x4,orx1lanewidthPowermanagementsupportBlockRAMsusedforbufferingFullybufferedtransmitandreceiveManagementinterfacetoaccessPCIExpressconfigurationspaceandinternalconfigurationSupportsthefullrangeofmaximumpayloadsizesUpto6x32bitor3x64bitBARs(oracombinationof32bitand64bit)Tri-ModeEthernetMediaAccessControllerDesignedtotheIEEE802.
3-2002specificationOperatesat10,100,and1,000Mb/sSupportstri-modeauto-negotiationReceiveaddressfilter(5addressentries)Fullymonolithic1000Base-XsolutionwithRocketIOGTPtransceiversSupportsmultipleexternalPHYconnections(RGMII,GMII,etc.
)interfacesthroughsoftlogicandSelectIOresourcesSupportsconnectiontoexternalPHYdevicethroughSGMIIusingsoftlogicandRocketIOGTPtransceiversReceiveandtransmitstatisticsavailablethroughseparateinterfaceSeparatehostandclientinterfacesSupportforjumboframesSupportforVLANFlexible,user-configurablehostinterfaceSupportsIEEE802.
3ah-2004unidirectionalmodeVirtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification5RRocketIOGTPTransceivers(LXT/SXTonly)Full-duplexserialtransceivercapableof100Mb/sto3.
75Gb/sbaudrates8B/10B,user-definedFPGAlogic,ornoencodingoptionsChannelbondingsupportCRCgenerationandcheckingProgrammablepre-emphasisorpre-equalizationforthetransmitterProgrammableterminationandvoltageswingProgrammableequalizationforthereceiverReceiversignaldetectandlossofsignalindicatorUserdynamicreconfigurationusingsecondaryconfigurationbusOutofBand(OOB)supportforSerialATA(SATA)Electricalidle,beaconing,receiverdetection,andPCIExpressandSATAspread-spectrumclockingsupportLessthan100mWtypicalpowerconsumptionBuilt-inPRBSGeneratorsandCheckersRocketIOGTXTransceivers(TXT/FXTonly)Full-duplexserialtransceivercapableof150Mb/sto6.
5Gb/sbaudrates8B/10Bencodingandprogrammablegearboxtosupport64B/66Band64B/67Bencoding,user-definedFPGAlogic,ornoencodingoptionsChannelbondingsupportCRCgenerationandcheckingProgrammablepre-emphasisorpre-equalizationforthetransmitterProgrammableterminationandvoltageswingProgrammablecontinuoustimeequalizationforthereceiverProgrammabledecisionfeedbackequalizationforthereceiverReceiversignaldetectandlossofsignalindicatorUserdynamicreconfigurationusingsecondaryconfigurationbusOOBsupport(SATA)Electricalidle,beaconing,receiverdetection,andPCIExpressspread-spectrumclockingsupportLow-poweroperationatalllineratesPowerPC440RISCCores(FXTonly)EmbeddedPowerPC440(PPC440)coresUpto550MHzoperationGreaterthan1000DMIPSpercoreSeven-stagepipelineMultipleinstructionspercycleOut-of-orderexecution32Kbyte,64-waysetassociativelevel1instructioncache32Kbyte,64-waysetassociativelevel1datacacheBookEcompliantIntegratedcrossbarforenhancedsystemperformance128-bitProcessorLocalBuses(PLBs)Integratedscatter/gatherDMAcontrollersDedicatedinterfaceforconnectiontoDDR2memorycontrollerAuto-synchronizationfornon-integerPLB-to-CPUclockratiosAuxiliaryProcessorUnit(APU)InterfaceandControllerDirectconnectionfromPPC440embeddedblocktoFPGAfabric-basedcoprocessors128-bitwidepipelinedAPULoad/StoreSupportofautonomousinstructions:nopipelinestallsProgrammabledecodeforcustominstructionsVirtex-5FamilyOverview6www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRArchitecturalDescriptionVirtex-5FPGAArrayOverviewVirtex-5devicesareuser-programmablegatearrayswithvariousconfigurableelementsandembeddedcoresoptimizedforhigh-densityandhigh-performancesystemdesigns.
Virtex-5devicesimplementthefollowingfunctionality:I/Oblocksprovidetheinterfacebetweenpackagepinsandtheinternalconfigurablelogic.
Mostpopularandleading-edgeI/OstandardsaresupportedbyprogrammableI/Oblocks(IOBs).
TheIOBscanbeconnectedtoveryflexibleChipSynclogicforenhancedsource-synchronousinterfacing.
Source-synchronousoptimizationsincludeper-bitdeskew(onbothinputandoutputsignals),dataserializers/deserializers,clockdividers,anddedicatedI/Oandlocalclockingresources.
ConfigurableLogicBlocks(CLBs),thebasiclogicelementsforXilinxFPGAs,providecombinatorialandsynchronouslogicaswellasdistributedmemoryandSRL32shiftregistercapability.
Virtex-5FPGACLBsarebasedonreal6-inputlook-uptabletechnologyandprovidesuperiorcapabilitiesandperformancecomparedtopreviousgenerationsofprogrammablelogic.
BlockRAMmodulesprovideflexible36Kbittruedual-portRAMthatarecascadabletoformlargermemoryblocks.
Inaddition,Virtex-5FPGAblockRAMscontainoptionalprogrammableFIFOlogicforincreaseddeviceutilization.
EachblockRAMcanalsobeconfiguredastwoindependent18Kbittruedual-portRAMblocks,providingmemorygranularityfordesignsneedingsmallerRAMblocks.
CascadableembeddedDSP48Esliceswith25x18two'scomplementmultipliersand48-bitadder/subtracter/accumulatorprovidemassivelyparallelDSPalgorithmsupport.
Inaddition,eachDSP48Eslicecanbeusedtoperformbitwiselogicalfunctions.
ClockManagementTile(CMT)blocksprovidethemostflexible,highest-performanceclockingforFPGAs.
EachCMTcontainstwoDigitalClockManager(DCM)blocks(self-calibrating,fullydigital),andonePLLblock(self-calibrating,analog)forclockdistributiondelaycompensation,clockmultiplication/division,coarse-/fine-grainedclockphaseshifting,andinputclockjitterfiltering.
Additionally,LXT,SXT,TXT,andFXTdevicesalsocontain:IntegratedEndpointblocksforPCIExpressdesignsprovidingx1,x4,orx8PCIExpressEndpointfunctionality.
WhenusedinconjunctionwithRocketIOtransceivers,acompletePCIExpressEndpointcanbeimplementedwithminimalFPGAlogicutilization.
10/100/1000Mb/sEthernetmedia-accesscontrolblocksofferEthernetcapability.
LXTandSXTdevicescontain:RocketIOGTPtransceiverscapableofrunningupto3.
75Gb/s.
EachGTPtransceiversupportsfull-duplex,clock-and-datarecovery.
TXTandFXTdevicescontain:GTXtransceiverscapableofrunningupto6.
5Gb/s.
EachGTXtransceiversupportsfull-duplex,clock-and-datarecovery.
FXTdevicescontain:EmbeddedIBMPowerPC440RISCCPUs.
EachPowerPC440CPUiscapableofrunningupto550MHz.
EachPowerPC440CPUalsohasanAPU(AuxiliaryProcessorUnit)interfacethatsupportshardwareacceleration,andanintegratedcross-barforhighdatathroughput.
Thegeneralroutingmatrix(GRM)providesanarrayofroutingswitchesbetweeneachinternalcomponent.
Eachprogrammableelementistiedtoaswitchmatrix,allowingmultipleconnectionstothegeneralroutingmatrix.
Theoverallprogrammableinterconnectionishierarchicalanddesignedtosupporthigh-speeddesigns.
InVirtex-5devices,theroutingconnectionsareoptimizedtosupportCLBinterconnectioninthefewestnumberof"hops.
"Reducinghopsgreatlyincreasespostplace-and-route(PAR)designperformance.
Allprogrammableelements,includingtheroutingresources,arecontrolledbyvaluesstoredinstaticstorageelements.
ThesevaluesareloadedintotheFPGAduringconfigurationandcanbereloadedtochangethefunctionsoftheprogrammableelements.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification7RVirtex-5FPGAFeaturesThissectionbrieflydescribesthefeaturesoftheVirtex-5familyofFPGAs.
Input/OutputBlocks(SelectIO)IOBsareprogrammableandcanbecategorizedasfollows:Programmablesingle-endedordifferential(LVDS)operationInputblockwithanoptionalsingledatarate(SDR)ordoubledatarate(DDR)registerOutputblockwithanoptionalSDRorDDRregisterBidirectionalblockPer-bitdeskewcircuitryDedicatedI/OandregionalclockingresourcesBuilt-indataserializer/deserializerTheIOBregistersareeitheredge-triggeredD-typeflip-flopsorlevel-sensitivelatches.
IOBssupportthefollowingsingle-endedstandards:LVTTLLVCMOS(3.
3V,2.
5V,1.
8V,1.
5V,and1.
2V)PCI(33and66MHz)PCI-XGTLandGTLPHSTL1.
5Vand1.
8V(ClassI,II,III,andIV)HSTL1.
2V(Class1)SSTL1.
8Vand2.
5V(ClassIandII)TheDigitallyControlledImpedance(DCI)I/Ofeaturecanbeconfiguredtoprovideon-chipterminationforeachsingle-endedI/OstandardandsomedifferentialI/Ostandards.
TheIOBelementsalsosupportthefollowingdifferentialsignalingI/Ostandards:LVDSandExtendedLVDS(2.
5Vonly)BLVDS(BusLVDS)ULVDSHypertransportDifferentialHSTL1.
5Vand1.
8V(ClassIandII)DifferentialSSTL1.
8Vand2.
5V(ClassIandII)RSDS(2.
5Vpoint-to-point)Twoadjacentpadsareusedforeachdifferentialpair.
TwoorfourIOBblocksconnecttooneswitchmatrixtoaccesstheroutingresources.
Per-bitdeskewcircuitryallowsforprogrammablesignaldelayinternaltotheFPGA.
Per-bitdeskewflexiblyprovidesfine-grainedincrementsofdelaytocarefullyproducearangeofsignaldelays.
Thisisespeciallyusefulforsynchronizingsignaledgesinsource-synchronousinterfaces.
GeneralpurposeI/Oinselectlocations(eightperbank)aredesignedtobe"regionalclockcapable"I/ObyaddingspecialhardwareconnectionsforI/Ointhesamelocality.
TheseregionalclockinputsaredistributedwithinalimitedregiontominimizeclockskewbetweenIOBs.
RegionalI/Oclockingsupplementstheglobalclockingresources.
Dataserializer/deserializercapabilityisaddedtoeveryI/Otosupportsource-synchronousinterfaces.
Aserial-to-parallelconverterwithassociatedclockdividerisincludedintheinputpath,andaparallel-to-serialconverterintheoutputpath.
Anin-depthguidetotheVirtex-5FPGAIOBisfoundintheVirtex-5FPGATri-ModeEthernetMACUserGuide.
ConfigurableLogicBlocks(CLBs)AVirtex-5FPGACLBresourceismadeupoftwoslices.
Eachsliceisequivalentandcontains:FourfunctiongeneratorsFourstorageelementsArithmeticlogicgatesLargemultiplexersFastcarrylook-aheadchainThefunctiongeneratorsareconfigurableas6-inputLUTsordual-output5-inputLUTs.
SLICEMsinsomeCLBscanbeconfiguredtooperateas32-bitshiftregisters(or16-bitx2shiftregisters)oras64-bitdistributedRAM.
Inaddition,thefourstorageelementscanbeconfiguredaseitheredge-triggeredD-typeflip-flopsorlevelsensitivelatches.
EachCLBhasinternalfastinterconnectandconnectstoaswitchmatrixtoaccessgeneralroutingresources.
TheVirtex-5FPGACLBsarefurtherdiscussedintheVirtex-5FPGAUserGuide.
BlockRAMThe36Kbittruedual-portRAMblockresourcesareprogrammablefrom32Kx1to512x72,invariousdepthandwidthconfigurations.
Inaddition,each36-Kbitblockcanalsobeconfiguredtooperateastwo,independent18-Kbitdual-portRAMblocks.
Eachportistotallysynchronousandindependent,offeringthree"read-during-write"modes.
BlockRAMiscascadabletoimplementlargeembeddedstorageblocks.
Additionally,back-endpipelineregisters,clockcontrolcircuitry,built-inFIFOsupport,ECC,andbytewriteenablefeaturesarealsoprovidedasoptions.
TheblockRAMfeatureinVirtex-5devicesisfurtherdiscussedintheVirtex-5FPGAUserGuide.
Virtex-5FamilyOverview8www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRGlobalClockingTheCMTsandglobal-clockmultiplexerbuffersprovideacompletesolutionfordesigninghigh-speedclocknetworks.
EachCMTcontainstwoDCMsandonePLL.
TheDCMsandPLLscanbeusedindependentlyorextensivelycascaded.
UptosixCMTblocksareavailable,providinguptoeighteentotalclockgeneratorelements.
EachDCMprovidesfamiliarclockgenerationcapability.
Togeneratedeskewedinternalorexternalclocks,eachDCMcanbeusedtoeliminateclockdistributiondelay.
TheDCMalsoprovides90°,180°,and270°phase-shiftedversionsoftheoutputclocks.
Fine-grainedphaseshiftingoffershigher-resolutionphaseadjustmentwithfractionoftheclockperiodincrements.
Flexiblefrequencysynthesisprovidesaclockoutputfrequencyequaltoafractionalorintegermultipleoftheinputclockfrequency.
ToaugmenttheDCMcapability,Virtex-5FPGACMTsalsocontainaPLL.
Thisblockprovidesreferenceclockjitterfilteringandfurtherfrequencysynthesisoptions.
Virtex-5deviceshave32global-clockMUXbuffers.
Theclocktreeisdesignedtobedifferential.
Differentialclockinghelpsreducejitteranddutycycledistortion.
DSP48ESlicesDSP48Esliceresourcescontaina25x18two'scomplementmultiplieranda48-bitadder/subtacter/accumulator.
EachDSP48Eslicealsocontainsextensivecascadecapabilitytoefficientlyimplementhigh-speedDSPalgorithms.
TheVirtex-5FPGADSP48EslicefeaturesarefurtherdiscussedinVirtex-5FPGAXtremeDSPDesignConsiderations.
RoutingResourcesAllcomponentsinVirtex-5devicesusethesameinterconnectschemeandthesameaccesstotheglobalroutingmatrix.
Inaddition,theCLB-to-CLBroutingisdesignedtoofferacompletesetofconnectivityinasfewhopsaspossible.
Timingmodelsareshared,greatlyimprovingthepredictabilityoftheperformanceforhigh-speeddesigns.
BoundaryScanBoundary-ScaninstructionsandassociateddataregisterssupportastandardmethodologyforaccessingandconfiguringVirtex-5devices,complyingwithIEEEstandards1149.
1and1532.
ConfigurationVirtex-5devicesareconfiguredbyloadingthebitstreamintointernalconfigurationmemoryusingoneofthefollowingmodes:Slave-serialmodeMaster-serialmodeSlaveSelectMAPmodeMasterSelectMAPmodeBoundary-Scanmode(IEEE-1532and-1149)SPImode(SerialPeripheralInterfacestandardFlash)BPI-up/BPI-downmodes(Byte-widePeripheralinterfacestandardx8orx16NORFlash)Inaddition,Virtex-5devicesalsosupportthefollowingconfigurationoptions:256-bitAESbitstreamdecryptionforIPprotectionMulti-bitstreammanagement(MBM)forcold/warmbootsupportParallelconfigurationbuswidthauto-detectionParalleldaisychainConfigurationCRCandECCsupportforthemostrobust,flexibledeviceintegritycheckingVirtex-5deviceconfigurationisfurtherdiscussedintheVirtex-5FPGAConfigurationGuide.
SystemMonitorFPGAsareanimportantbuildingblockinhighavailability/reliabilityinfrastructure.
Therefore,thereisneedtobettermonitortheon-chipphysicalenvironmentoftheFPGAanditsimmediatesurroundingswithinthesystem.
Forthefirsttime,theVirtex-5familySystemMonitorfacilitateseasiermonitoringoftheFPGAanditsexternalenvironment.
EverymemberoftheVirtex-5familycontainsaSystemMonitorblock.
TheSystemMonitorisbuiltarounda10-bit200kSPSADC(Analog-to-DigitalConverter).
ThisADCisusedtodigitizeanumberofon-chipsensorstoprovideinformationaboutthephysicalenvironmentwithintheFPGA.
On-chipsensorsincludeatemperaturesensorandpowersupplysensors.
Accesstotheexternalenvironmentisprovidedviaanumberofexternalanaloginputchannels.
Theseanaloginputsaregeneralpurposeandcanbeusedtodigitizeawidevarietyofvoltagesignaltypes.
Supportforunipolar,bipolar,andtruedifferentialinputschemesisprovided.
Thereisfullaccesstotheon-chipsensorsandexternalchannelsviatheJTAGTAP,allowingtheexistingJTAGinfrastructureonthePCboardtobeusedforanalogtestandadvanceddiagnosticsduringdevelopmentorafterdeploymentinthefield.
TheSystemMonitorisfullyoperationalafterpowerupandbeforeconfigurationoftheFPGA.
SystemMonitordoesnotrequireanexplicitinstantiationinadesigntogainaccesstoitsbasicfunctionality.
ThisallowstheSystemMonitortobeusedevenatalatestageinthedesigncycle.
TheVirtex-5FPGASystemMonitorisfurtherdiscussedintheVirtex-5FPGASystemMonitorUserGuide.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification9RVirtex-5LXT,SXT,TXT,andFXTPlatformFeaturesThissectionbrieflydescribesblocksavailableonlyinLXT,SXT,TXT,andFXTdevices.
Tri-Mode(10/100/1000Mb/s)EthernetMACsVirtex-5LXT,SXT,TXT,andFXTdevicescontainuptoeightembeddedEthernetMACs,twoperEthernetMACblock.
Theblockshavethefollowingcharacteristics:DesignedtotheIEEE802.
3-2002specificationUNH-compliancetestedRGMII/GMIIInterfacewithSelectIOorSGMIIinterfacewhenusedwithRocketIOtransceiversHalforfullduplexSupportsJumboframes1000Base-XPCS/PMA:WhenusedwithRocketIOGTPtransceiver,canprovidecomplete1000Base-Ximplementationon-chipDCR-busconnectiontomicroprocessorsIntegratedEndpointBlocksforPCIExpressVirtex-5LXT,SXT,TXT,andFXTdevicescontainuptofourintegratedEndpointblocks.
TheseblocksimplementTransactionLayer,DataLinkLayer,andPhysicalLayerfunctionstoprovidecompletePCIExpressEndpointfunctionalitywithminimalFPGAlogicutilization.
Theblockshavethefollowingcharacteristics:CompliantwiththePCIExpressBaseSpecification1.
1WorksinconjunctionwithRocketIOtransceiverstoprovidecompleteendpointfunctionality1,4,or8lanesupportperblockVirtex-5LXTandSXTPlatformFeaturesThissectionbrieflydescribesblocksavailableonlyinLXTandSXTdevices.
RocketIOGTPTransceivers4-24channelRocketIOGTPtransceiverscapableofrunning100Mb/sto3.
75Gb/s.
Fullclockanddatarecovery8/16-bitor10/20-bitdatapathsupportOptional8B/10BorFPGA-basedencode/decodeIntegratedFIFO/elasticbufferChannelbondingandclockcorrectionsupportEmbedded32-bitCRCgeneration/checkingIntegratedcomma-detectorA1/A2detectionProgrammablepre-emphasis(AKAtransmitterequalization)ProgrammabletransmitteroutputswingProgrammablereceiverequalizationProgrammablereceiverterminationEmbeddedsupportfor:OutofBand(OOB)signalling:SerialATABeaconing,electricalidle,andPCIExpressreceiverdetectionBuilt-inPRBSgenerator/checkerVirtex-5FPGARocketIOGTPtransceiversarefurtherdiscussedintheVirtex-5FPGARocketIOGTPTransceiverUserGuide.
Virtex-5FamilyOverview10www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRVirtex-5TXTandFXTPlatformFeaturesThissectiondescribesblocksonlyavailableinTXTandFXTdevices.
RocketIOGTXSerialTransceivers(TXT/FXT)8-48channelsRocketIOserialtransceiverscapableofrunning150Mb/sto6.
5Gb/sFullClockandDataRecovery8/16/32-bitor10/20/40-bitdatapathsupportOptional8B/10Bencoding,gearboxforprogrammable64B/66Bor64B/67Bencoding,orFPGA-basedencode/decodeIntegratedFIFO/ElasticBufferChannelbondingandclockcorrectionsupportDualembedded32-bitCRCgeneration/checkingIntegratedprogrammablecharacterdetectionProgrammablede-emphasis(AKAtransmitterequalization)ProgrammabletransmitteroutputswingsProgrammablereceiverequalizationProgrammablereceiverterminationEmbeddedsupportfor:SerialATA:OutofBand(OOB)signallingPCIExpress:Beaconing,electricalidle,andreceiverdetectionBuilt-inPRBSgenerator/checkerVirtex-5FPGARocketIOGTXtransceiversarefurtherdiscussedintheVirtex-5FPGARocketIOGTXTransceiverUserGuide.
OneorTwoPowerPC440ProcessorCores(FXTonly)SuperscalarRISCarchitecture32-bitBookEcompliant7-StageexecutionpipelineMultipleinstructionspercycleOut-of-orderexecutionIntegrated32KBLevel1InstructionCacheand32KBLevel1DataCache(64-waysetassociative)CoreConnectBusArchitectureCross-barconnectionforoptimizedprocessorbandwidthPLBSynchronizationLogic(Enablesnon-integerCPU-to-PLBclockratios)AuxiliaryProcessorUnit(APU)interfacewithanintegratedAPUcontrollerOptimizedFPGA-basedCoprocessorconnection-AutomaticdecodeofPowerPCfloating-pointinstructionsAllowscustominstructionsExtremelyefficientmicrocontroller-styleinterfacingThePowerPC440processorsarefurtherdiscussedintheEmbeddedProcessorBlockinVirtex-5FPGAsReferenceGuide.
IntellectualPropertyCoresXilinxoffersIPcoresforcommonlyusedcomplexfunctionsincludingDSP,businterfaces,processors,andprocessorperipherals.
UsingXilinxLogiCOREproductsandcoresfromthirdpartyAllianceCOREparticipants,customerscanshortendevelopmenttime,reducedesignrisk,andobtainsuperiorperformancefortheirdesigns.
Additionally,theCOREGeneratorsystemallowscustomerstoimplementIPcoresintoVirtex-5FPGAswithpredictableandrepeatableperformance.
Itoffersasimpleuserinterfacetogenerateparameter-basedcoresoptimizedforourFPGAs.
TheSystemGeneratorforDSPtoolallowssystemarchitectstoquicklymodelandimplementDSPfunctionsusinghandcraftedIPandfeaturesaninterfacetothird-partysystemlevelDSPdesigntools.
SystemGeneratorforDSPimplementsmanyofthehigh-performanceDSPcoressupportingVirtex-5FPGAsincludingtheXilinxForwardErrorCorrectionSolutionwithInterleaver/De-interleaver,Reed-Solomonencoder/decoders,andViterbidecoders.
Theseareidealforcreatinghighly-flexible,concatenatedcodecstosupportthecommunicationsmarket.
UsingVirtex-5FPGARocketIOtransceivers,industryleadingconnectivityandnetworkingIPcoresincludeleading-edgePCIExpress,SerialRapidIO,FibreChannel,and10GbEthernetcorescanbeimplemented.
TheXilinxSPI-4.
2IPcoreutilizestheVirtex-5FPGAChipSynctechnologytoimplementdynamicphasealignmentforhigh-performancesource-synchronousoperation.
XilinxalsoprovidesPCIcoresforadvancedsystem-synchronousoperation.
TheMicroBlaze32-bitprocessorcoreprovidestheindustry'sfastestsoftprocessingsolutionforbuildingcomplexsystemsforthenetworking,telecommunication,datacommunication,embedded,andconsumermarkets.
TheMicroBlazeprocessorfeaturesaRISCarchitecturewithHarvard-styleseparate32-bitinstructionanddatabusesrunningatfullspeedtoexecuteprogramsandaccessdatafrombothon-chipandexternalmemory.
AstandardsetofperipheralsarealsoCoreConnectenabledtoofferMicroBlazedesignerscompatibilityandreuse.
AllIPcoresforVirtex-5FPGAsarefoundontheXilinxIPCenterInternetportalpresentingthelatestintellectualpropertycoresandreferencedesignsusingSmartSearchforfasteraccess.
Virtex-5FPGALogiCOREEndpointBlockPlusWrapperforPCIExpressThisistherecommendedwrappertoconfiguretheintegratedEndpointblockforPCIExpressdeliveredthroughtheCOREGeneratorsystem.
Itprovidesmanyease-of-usefeaturesandoptimalconfigurationforEndpointapplicationsimplifyingthedesignprocessandreducingthetime-to-market.
Accesstothecore,includingbitstreamgenerationcapabilitycanbeobtainedthroughregistrationatnoextracharge.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification11RVirtex-5DeviceandPackageCombinationsandMaximumI/OsTable2:Virtex-5DeviceandPackageCombinationsandMaximumAvailableI/OsPackageFF323FFG323FFV323FF324FFG324FFV324FF676FFG676FFV676FF1153FFG1153FFV1153(1)FF1760FFG1760FFV1760(2)FF665FFG665FFV665FF1136FFG1136FFV1136(3)FF1156FFG1156FF1738FFG1738FFV1738(4)FF1759FFG1759Size(mm)19x1919x1927x2735x3542.
5x42.
527x2735x3535x3542.
5x42.
542.
5x42.
5DeviceGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OXC5VLX30N/A220N/A400XC5VLX50N/A220N/A440N/A560XC5VLX85N/A440N/A560XC5VLX110N/A440N/A800N/A800XC5VLX155N/A800N/A800XC5VLX220N/A800XC5VLX330N/A1,200XC5VLX20T4GTPs172XC5VLX30T4GTPs1728GTPs360XC5VLX50T8GTPs36012GTPs480XC5VLX85T12GTPs480XC5VLX110T16GTPs64016GTPs680XC5VLX155T16GTPs64016GTPs680XC5VLX220T16GTPs680XC5VLX330T24GTPs960XC5VSX35T8GTPs360XC5VSX50T8GTPs36012GTPs480XC5VSX95T16GTPs640XC5VSX240T24GTPs960XC5VTX150T40GTXs36040GTXs680XC5VTX240T48GTXs680XC5VFX30T8GTXs360XC5VFX70T8GTXs36016GTXs640XC5VFX100T16GTXs64016GTXs680XC5VFX130T20GTXs840XC5VFX200T24GTXs960Notes:1.
FFV1153packageisnotavailableintheLX155device.
2.
FFV1760packageisavailableintheLX110deviceonly.
3.
FFV1136packageisnotavailableintheLX155TandFX100Tdevices.
4.
FFV1738packageisavailableintheLX110Tdeviceonly.
Virtex-5FamilyOverview12www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRVirtex-5FPGAOrderingInformationVirtex-5FPGAorderinginformationshowninFigure1appliestoallpackagesincludingPb-Free.
X-RefTarget-Figure1Figure1:Virtex-5FPGAOrderingInformationExample:XC5VLX50T-1FFG665CDeviceTypeTemperatureRange:C=Commercial(TJ=0°Cto+85°C)I=Industrial(TJ=–40°Cto+100°C)NumberofPinsPackageTypeSpeedGrade(-1,-2,-3(1))Pb-FreeV=RoHS6/6G=RoHS6/6withexemption15DS100_01_071515Note:1)-3speedgradeisnotavailableinalldevicesVirtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification13RRevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.
DateVersionRevision04/14/061.
0InitialXilinxrelease.
05/12/061.
1FirstversionpostedtotheXilinxwebsite.
Minortypographicaleditsanddescriptionupdatestohighlightnewfeatures.
RemovedLUTutilizationbulletfrom"Virtex-5FPGALogic,"page3.
09/06/062.
0AddedLXTplatformtoentiredocument.
ThisincludesdescriptionsoftheRocketIOGTPtransceivers,theEthernetMACs,andthePCIExpressEndpointblock.
10/12/062.
1AddedLX85Tdevices.
AddedSystemMonitordescriptionsandfunctionality.
12/28/062.
2AddedLX220Tdevices.
RevisedtheTotalI/ObanksfortheLX330inTable1.
RevisedtheXC5VLX50T-FFG665exampleinFigure1.
Clarifiedsupportfor"DifferentialSSTL1.
8Vand2.
5V(ClassIandII),"page7.
02/02/073.
0AddedtheSXTplatformtoentiredocument.
05/23/073.
1RemovedsupportforIEEE1149.
609/04/073.
2Revisedmaximumlineratefrom3.
2Gb/sto3.
75Gb/sinentiredocument.
12/11/073.
3AddedLX20T,LX155T,andLX155devices.
12/17/073.
4AddedDisclaimer.
RevisedCMTsectiononpage3.
Clarified"Virtex-5FPGALogiCOREEndpointBlockPlusWrapperforPCIExpress,"page10.
03/31/084.
0AddedFXTplatformtoentiredocument.
Clarifiedinformationinthefollowingsections:"IntegratedEndpointBlockforPCIExpressCompliance"and"Tri-ModeEthernetMediaAccessController.
"ToavoidconfusionwithPLLfunctionality,removedPMCDreferencesin"GlobalClocking,"page8.
04/25/084.
1AddedXC5VSX240Ttoentiredocument.
05/07/084.
2UpdatedthroughoutdatasheetthattheRocketIOGTXtransceiversaredesignedtorunfrom150Mb/sto6.
5Gb/s.
ClarifiedPPC440MC_DDR2memorycontrolleronpage5.
06/18/084.
3RevisedEthernetMACcolumninTable1,page2andaddedNote5.
Alsoupdated"Tri-Mode(10/100/1000Mb/s)EthernetMACs,"page9.
09/23/084.
4AddedTXTplatformtoentiredocument.
RevisedRocketIOGTXtranscieverdatapathsupportonpage10.
02/6/095.
0ChangeddocumentclassificationtoProductSpecificationfromAdvanceProductSpecification.
08/21/155.
1UpdatedTable2andFigure1withRoHSpackageinformation.
Virtex-5FamilyOverview14www.
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comDS100(v5.
1)August21,2015ProductSpecificationRDisclaimerTheinformationdisclosedtoyouhereunder(the"Materials")isprovidedsolelyfortheselectionanduseofXilinxproducts.
Tothemaximumextentpermittedbyapplicablelaw:(1)Materialsaremadeavailable"ASIS"andwithallfaults,XilinxherebyDISCLAIMSALLWARRANTIESANDCONDITIONS,EXPRESS,IMPLIED,ORSTATUTORY,INCLUDINGBUTNOTLIMITEDTOWARRANTIESOFMERCHANTABILITY,NON-INFRINGEMENT,ORFITNESSFORANYPARTICULARPURPOSE;and(2)Xilinxshallnotbeliable(whetherincontractortort,includingnegligence,orunderanyothertheoryofliability)foranylossordamageofanykindornaturerelatedto,arisingunder,orinconnectionwith,theMaterials(includingyouruseoftheMaterials),includingforanydirect,indirect,special,incidental,orconsequentiallossordamage(includinglossofdata,profits,goodwill,oranytypeoflossordamagesufferedasaresultofanyactionbroughtbyathirdparty)evenifsuchdamageorlosswasreasonablyforeseeableorXilinxhadbeenadvisedofthepossibilityofthesame.
XilinxassumesnoobligationtocorrectanyerrorscontainedintheMaterialsortonotifyyouofupdatestotheMaterialsortoproductspecifications.
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Thisdocumentcontainspreliminaryinformationandissubjecttochangewithoutnotice.
Informationprovidedhereinrelatestoproductsand/orservicesnotyetavailableforsale,andprovidedsolelyforinformationpurposesandarenotintended,ortobeconstrued,asanofferforsaleoranattemptedcommercializationoftheproductsand/orservicesreferredtoherein.
AutomotiveApplicationsDisclaimerXILINXPRODUCTSARENOTDESIGNEDORINTENDEDTOBEFAIL-SAFE,ORFORUSEINANYAPPLICATIONREQUIRINGFAIL-SAFEPERFORMANCE,SUCHASAPPLICATIONSRELATEDTO:(I)THEDEPLOYMENTOFAIRBAGS,(II)CONTROLOFAVEHICLE,UNLESSTHEREISAFAIL-SAFEORREDUNDANCYFEATURE(WHICHDOESNOTINCLUDEUSEOFSOFTWAREINTHEXILINXDEVICETOIMPLEMENTTHEREDUNDANCY)ANDAWARNINGSIGNALUPONFAILURETOTHEOPERATOR,OR(III)USESTHATCOULDLEADTODEATHORPERSONALINJURY.
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Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification15RVirtex-5FPGADocumentationCompleteandup-to-datedocumentationoftheVirtex-5familyofFPGAsisavailableontheXilinxwebsite.
InadditiontothemostrecentVirtex-5FamilyOverview,thefollowingfilesarealsoavailablefordownload:Virtex-5FPGADataSheet:DCandSwitchingCharacteristics(DS202)ThisdatasheetcontainstheDCandSwitchingCharacteristicspecificationsfortheVirtex-5family.
Virtex-5FPGAUserGuide(UG190)Thisguideincludeschapterson:ClockingResourcesClockManagementTechnology(CMT)Phase-LockedLoops(PLL)BlockRAMConfigurableLogicBlocks(CLBs)SelectIOResourcesSelectIOLogicResourcesAdvancedSelectIOLogicResourcesVirtex-5FPGAXtremeDSPDesignConsiderations(UG193)ThisguidedescribestheDSP48EsliceandincludesreferencedesignsforusingDSP48Emathfunctionsandvariousfilters.
Virtex-5FPGAConfigurationGuide(UG191)Thisall-encompassingconfigurationguideincludeschaptersonconfigurationinterfaces(serialandparallel),multi-bitstreammanagement,bitstreamencryption,Boundary-ScanandJTAGconfiguration,andreconfigurationtechniques.
Virtex-5FPGAPackagingandPinoutSpecification(UG195)Thisspecificationincludesthetablesfordevice/packagecombinationsandmaximumI/Os,pindefinitions,pinouttables,pinoutdiagrams,mechanicaldrawings,andthermalspecifications.
Virtex-5FPGAPCBDesigner'sGuide(UG203)ThisguideprovidesinformationonPCBdesignforVirtex-5devices,withafocusonstrategiesformakingdesigndecisionsatthePCBandinterfacelevel.
Virtex-5FPGASystemMonitorUserGuide(UG192)TheSystemMonitorfunctionalityisoutlinedinthisguide.
Virtex-5FPGARocketIOGTPTransceiverUserGuide(UG196)ThisguidedescribestheRocketIOGTPtransceiversavailableintheVirtex-5LXTandSXTplatforms.
Virtex-5FPGARocketIOGTXTransceiverUserGuide(UG198)ThisguidedescribestheRocketIOGTXtransceiversavailableintheVirtex-5TXTandFXTplatforms.
Virtex-5FPGATri-ModeEthernetMACUserGuide(UG194)ThisguidedescribesthededicatedTri-ModeEthernetMediaAccessControlleravailableintheVirtex-5LXT,SXT,TXT,andFXTplatforms.
Virtex-5FPGAIntegratedEndpointBlockforPCIExpressDesignsUserGuide(UG197)ThisguidedescribestheintegratedEndpointblocksintheVirtex-5LXT,SXT,TXT,andFXTplatformsthatarePCIExpresscompliant.
EmbeddedProcessorBlockinVirtex-5FPGAsReferenceGuide(UG200)ThisreferenceguideisadescriptionoftheembeddedprocessorblockavailableintheVirtex-5FXTplatform.
1)August21,2015www.
xilinx.
comProductSpecification12006–2015Xilinx,Inc.
,Xilinx,theXilinxlogo,Artix,ISE,Kintex,Spartan,UltraScale,Virtex,Vivado,Zynq,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.
PCI,PCIe,andPCIExpressaretrademarksofPCI-SIGandusedunderlicense.
PowerPCisatrademarkofIBMCorp.
andisusedunderlicense.
Allothertrademarksarethepropertyoftheirrespectiveowners.
GeneralDescriptionUsingthesecondgenerationASMBL(AdvancedSiliconModularBlock)column-basedarchitecture,theVirtex-5familycontainsfivedistinctplatforms(sub-families),themostchoiceofferedbyanyFPGAfamily.
Eachplatformcontainsadifferentratiooffeaturestoaddresstheneedsofawidevarietyofadvancedlogicdesigns.
Inadditiontothemostadvanced,high-performancelogicfabric,Virtex-5FPGAscontainmanyhard-IPsystemlevelblocks,includingpowerful36-KbitblockRAM/FIFOs,secondgeneration25x18DSPslices,SelectIOtechnologywithbuilt-indigitally-controlledimpedance,ChipSyncsource-synchronousinterfaceblocks,systemmonitorfunctionality,enhancedclockmanagementtileswithintegratedDCM(DigitalClockManagers)andphase-locked-loop(PLL)clockgenerators,andadvancedconfigurationoptions.
Additionalplatformdependantfeaturesincludepower-optimizedhigh-speedserialtransceiverblocksforenhancedserialconnectivity,PCIExpresscompliantintegratedEndpointblocks,tri-modeEthernetMACs(MediaAccessControllers),andhigh-performancePowerPC440microprocessorembeddedblocks.
ThesefeaturesallowadvancedlogicdesignerstobuildthehighestlevelsofperformanceandfunctionalityintotheirFPGA-basedsystems.
Builtona65-nmstate-of-the-artcopperprocesstechnology,Virtex-5FPGAsareaprogrammablealternativetocustomASICtechnology.
MostadvancedsystemdesignsrequiretheprogrammablestrengthofFPGAs.
Virtex-5FPGAsofferthebestsolutionforaddressingtheneedsofhigh-performancelogicdesigners,high-performanceDSPdesigners,andhigh-performanceembeddedsystemsdesignerswithunprecedentedlogic,DSP,hard/softmicroprocessor,andconnectivitycapabilities.
TheVirtex-5LXT,SXT,TXT,andFXTplatformsincludeadvancedhigh-speedserialconnectivityandlink/transactionlayercapability.
SummaryofVirtex-5FPGAFeaturesFiveplatformsLX,LXT,SXT,TXT,andFXTVirtex-5LX:High-performancegenerallogicapplicationsVirtex-5LXT:High-performancelogicwithadvancedserialconnectivityVirtex-5SXT:High-performancesignalprocessingapplicationswithadvancedserialconnectivityVirtex-5TXT:High-performancesystemswithdoubledensityadvancedserialconnectivityVirtex-5FXT:High-performanceembeddedsystemswithadvancedserialconnectivityCross-platformcompatibilityLXT,SXT,andFXTdevicesarefootprintcompatibleinthesamepackageusingadjustablevoltageregulatorsMostadvanced,high-performance,optimal-utilization,FPGAfabricReal6-inputlook-uptable(LUT)technologyDual5-LUToptionImprovedreduced-hoprouting64-bitdistributedRAMoptionSRL32/DualSRL16optionPowerfulclockmanagementtile(CMT)clockingDigitalClockManager(DCM)blocksforzerodelaybuffering,frequencysynthesis,andclockphaseshiftingPLLblocksforinputjitterfiltering,zerodelaybuffering,frequencysynthesis,andphase-matchedclockdivision36-KbitblockRAM/FIFOsTruedual-portRAMblocksEnhancedoptionalprogrammableFIFOlogicProgrammable-Truedual-portwidthsuptox36-Simpledual-portwidthsuptox72Built-inoptionalerror-correctioncircuitryOptionallyprogrameachblockastwoindependent18-KbitblocksHigh-performanceparallelSelectIOtechnology1.
2to3.
3VI/OOperationSource-synchronousinterfacingusingChipSynctechnologyDigitally-controlledimpedance(DCI)activeterminationFlexiblefine-grainedI/ObankingHigh-speedmemoryinterfacesupportAdvancedDSP48Eslices25x18,two'scomplement,multiplicationOptionaladder,subtracter,andaccumulatorOptionalpipeliningOptionalbitwiselogicalfunctionalityDedicatedcascadeconnectionsFlexibleconfigurationoptionsSPIandParallelFLASHinterfaceMulti-bitstreamsupportwithdedicatedfallbackreconfigurationlogicAutobuswidthdetectioncapabilitySystemMonitoringcapabilityonalldevicesOn-chip/Off-chipthermalmonitoringOn-chip/Off-chippowersupplymonitoringJTAGaccesstoallmonitoredquantitiesIntegratedEndpointblocksforPCIExpressDesignsLXT,SXT,TXT,andFXTPlatformsCompliantwiththePCIExpressBaseSpecification1.
1x1,x4,orx8lanesupportperblockWorksinconjunctionwithRocketIOtransceiversTri-mode10/100/1000Mb/sEthernetMACsLXT,SXT,TXT,andFXTPlatformsRocketIOtransceiverscanbeusedasPHYorconnecttoexternalPHYusingmanysoftMII(MediaIndependentInterface)optionsRocketIOGTPtransceivers100Mb/sto3.
75Gb/sLXTandSXTPlatformsRocketIOGTXtransceivers150Mb/sto6.
5Gb/sTXTandFXTPlatformsPowerPC440MicroprocessorsFXTPlatformonlyRISCarchitecture7-stagepipeline32-KbyteinstructionanddatacachesincludedOptimizedprocessorinterfacestructure(crossbar)65-nmcopperCMOSprocesstechnology1.
0VcorevoltageHighsignal-integrityflip-chippackagingavailableinstandardorPb-freepackageoptions0Virtex-5FamilyOverviewDS100(v5.
1)August21,201500ProductSpecificationRVirtex-5FamilyOverview2www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRTable1:Virtex-5FPGAFamilyMembersDeviceConfigurableLogicBlocks(CLBs)DSP48ESlices(2)BlockRAMBlocksCMTs(4)PowerPCProcessorBlocksEndpointBlocksforPCIExpressEthernetMACs(5)MaxRocketIOTransceivers(6)TotalI/OBanks(8)MaxUserI/O(7)Array(RowxCol)Virtex-5Slices(1)MaxDistributedRAM(Kb)18Kb(3)36KbMax(Kb)GTPGTXXC5VLX3080x304,8003203264321,1522N/AN/AN/AN/AN/A13400XC5VLX50120x307,2004804896481,7286N/AN/AN/AN/AN/A17560XC5VLX85120x5412,96084048192963,4566N/AN/AN/AN/AN/A17560XC5VLX110160x5417,2801,120642561284,6086N/AN/AN/AN/AN/A23800XC5VLX155160x7624,3201,6401283841926,9126N/AN/AN/AN/AN/A23800XC5VLX220160x10834,5602,2801283841926,9126N/AN/AN/AN/AN/A23800XC5VLX330240x10851,8403,42019257628810,3686N/AN/AN/AN/AN/A331,200XC5VLX20T60x263,1202102452269361N/A124N/A7172XC5VLX30T80x304,8003203272361,2962N/A148N/A12360XC5VLX50T120x307,20048048120602,1606N/A1412N/A15480XC5VLX85T120x5412,960840482161083,8886N/A1412N/A15480XC5VLX110T160x5417,2801,120642961485,3286N/A1416N/A20680XC5VLX155T160x7624,3201,6401284242127,6326N/A1416N/A20680XC5VLX220T160x10834,5602,2801284242127,6326N/A1416N/A20680XC5VLX330T240x10851,8403,42019264832411,6646N/A1424N/A27960XC5VSX35T80x345,440520192168843,0242N/A148N/A12360XC5VSX50T120x348,1607802882641324,7526N/A1412N/A15480XC5VSX95T160x4614,7201,5206404882448,7846N/A1416N/A19640XC5VSX240T240x7837,4404,2001,0561,03251618,5766N/A1424N/A27960XC5VTX150T200x5823,2001,500804562288,2086N/A14N/A4020680XC5VTX240T240x7837,4402,4009664832411,6646N/A14N/A4820680XC5VFX30T80x385,12038064136682,4482114N/A812360XC5VFX70T160x3811,2008201282961485,3286134N/A1619640XC5VFX100T160x5616,0001,2402564562288,2086234N/A1620680XC5VFX130T200x5620,4801,58032059629810,7286236N/A2024840XC5VFX200T240x6830,7202,28038491245616,4166248N/A2427960Notes:1.
Virtex-5FPGAslicesareorganizeddifferentlyfrompreviousgenerations.
EachVirtex-5FPGAslicecontainsfourLUTsandfourflip-flops(previouslyitwastwoLUTsandtwoflip-flops.
)2.
EachDSP48Eslicecontainsa25x18multiplier,anadder,andanaccumulator.
3.
BlockRAMsarefundamentally36Kbitsinsize.
Eachblockcanalsobeusedastwoindependent18-Kbitblocks.
4.
EachClockManagementTile(CMT)containstwoDCMsandonePLL.
5.
ThistablelistsseparateEthernetMACsperdevice.
6.
RocketIOGTPtransceiversaredesignedtorunfrom100Mb/sto3.
75Gb/s.
RocketIOGTXtransceiversaredesignedtorunfrom150Mb/sto6.
5Gb/s.
7.
ThisnumberdoesnotincludeRocketIOtransceivers.
8.
IncludesconfigurationBank0.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification3RVirtex-5FPGALogicOnaverage,onetotwospeedgradeimprovementoverVirtex-4devicesCascadable32-bitvariableshiftregistersor64-bitdistributedmemorycapabilitySuperiorroutingarchitecturewithenhanceddiagonalroutingsupportsblock-to-blockconnectivitywithminimalhopsUpto330,000logiccellsincluding:Upto207,360internalfabricflip-flopswithclockenable(XC5VLX330)Upto207,360real6-inputlook-uptables(LUTs)withgreaterthan13milliontotalLUTbitsTwooutputsfordual5-LUTmodegivesenhancedutilizationLogicexpandingmultiplexersandI/Oregisters550MHzClockTechnologyUptosixClockManagementTiles(CMTs)EachCMTcontainstwoDCMsandonePLL—uptoeighteentotalclockgeneratorsFlexibleDCM-to-PLLorPLL-to-DCMcascadePrecisionclockdeskewandphaseshiftFlexiblefrequencysynthesisMultipleoperatingmodestoeaseperformancetrade-offdecisionsImprovedmaximuminput/outputfrequencyFine-grainedphaseshiftingresolutionInputjitterfilteringLow-poweroperationWidephaseshiftrangeDifferentialclocktreestructureforoptimizedlow-jitterclockingandprecisedutycycle32globalclocknetworksRegional,I/O,andlocalclocksinadditiontoglobalclocksSelectIOTechnologyUpto1,200userI/OsWideselectionofI/Ostandardsfrom1.
2Vto3.
3VExtremelyhigh-performanceUpto800Mb/sHSTLandSSTL(onallsingle-endedI/Os)Upto1.
25Gb/sLVDS(onalldifferentialI/Opairs)Truedifferentialterminationon-chipSameedgecaptureatinputandoutputI/OsExtensivememoryinterfacesupport550MHzIntegratedBlockMemoryUpto16.
4Mbitsofintegratedblockmemory36-Kbitblockswithoptionaldual18-KbitmodeTruedual-portRAMcellsIndependentportwidthselection(x1tox72)Uptox36totalperportfortruedualportoperationUptox72totalperportforsimpledualportoperation(oneReadportandoneWriteport)Memorybitsplusparity/sidebandmemorysupportforx9,x18,x36,andx72widthsConfigurationsfrom32Kx1to512x72(8Kx4to512x72forFIFOoperation)MultirateFIFOsupportlogicFullandEmptyflagwithfullyprogrammableAlmostFullandAlmostEmptyflagsSynchronousFIFOsupportwithoutFlaguncertaintyOptionalpipelinestagesforhigherperformanceByte-writecapabilityDedicatedcascaderoutingtoform64Kx1memorywithoutusingFPGAroutingIntegratedoptionalECCforhigh-reliabilitymemoryrequirementsSpecialreduced-powerdesignfor18Kbit(andbelow)operation550MHzDSP48ESlices25x18two'scomplementmultiplicationOptionalpipelinestagesforenhancedperformanceOptional48-bitaccumulatorformultiplyaccumulate(MACC)operationwithoptionalaccumulatorcascadeto96-bitsIntegratedadderforcomplex-multiplyormultiply-addoperationOptionalbitwiselogicaloperationmodesIndependentCregisterspersliceFullycascadableinaDSPcolumnwithoutexternalroutingresourcesChipSyncSource-SynchronousInterfacingLogicWorksinconjunctionwithSelectIOtechnologytosimplifysource-synchronousinterfacesPer-bitdeskewcapabilitybuiltintoallI/Oblocks(variabledelaylineonallinputsandoutputs)DedicatedI/Oandregionalclockingresources(pinsandtrees)Built-indataserializer/deserializerlogicwithcorrespondingclockdividersupportinallI/ONetworking/telecommunicationinterfacesupto1.
25Gb/sperI/OVirtex-5FamilyOverview4www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRDigitallyControlledImpedance(DCI)ActiveI/OTerminationOptionalseriesorparallelterminationTemperatureandvoltagecompensationMakesboardlayoutmucheasierReducesresistorsPlacesterminationintheideallocation,atthesignalsourceordestinationConfigurationSupportforplatformFlash,standardSPIFlash,orstandardparallelNORFlashconfigurationBitstreamsupportwithdedicatedfallbackreconfigurationlogic256-bitAESbitstreamdecryptionprovidesintellectualpropertysecurityandpreventsdesigncopyingImprovedbitstreamerrordetection/correctioncapabilityAutobuswidthdetectioncapabilityPartialReconfigurationviaICAPportAdvancedFlip-ChipPackagingPre-engineeredpackagingtechnologyforprovensuperiorsignalintegrityMinimizedinductiveloopsfromsignaltoreturnOptimalsignal-to-PWR/GNDratiosReducesSSOinducednoisebyupto7xPb-FreeandstandardpackagesSystemMonitorOn-Chiptemperaturemeasurement(±4°C)On-Chippowersupplymeasurement(±1%)Easytouse,self-containedNodesignrequiredforbasicoperationAutonomousmonitoringofallon-chipsensorsUserprogrammablealarmthresholdsforon-chipsensorsUseraccessible10-bit200kSPSADCAutomaticcalibrationofoffsetandgainerrorDNL=±0.
9LSBsmaximumUpto17externalanaloginputchannelssupported0Vto1VinputrangeMonitorexternalsensorse.
g.
,voltage,temperatureGeneralpurposeanaloginputsFullaccessfromfabricorJTAGTAPtoSystemMonitorFullyoperationalpriortoFPGAconfigurationandduringdevicepowerdown(accessviaJTAGTAPonly)65-nmCopperCMOSProcess1.
0VCoreVoltage12-layermetalprovidesmaximumroutingcapabilityandaccommodateshard-IPimmersionTriple-oxidetechnologyforprovenreducedstaticpowerconsumptionSystemBlocksSpecifictotheLXT,SXT,TXT,andFXTDevicesIntegratedEndpointBlockforPCIExpressComplianceWorksinconjunctionwithRocketIOGTPtransceivers(LXTandSXT)andGTXtransceivers(TXTandFXT)todeliverfullPCIExpressEndpointfunctionalitywithminimalFPGAlogicutilization.
CompliantwiththePCIExpressBaseSpecification1.
1PCIExpressEndpointblockorLegacyPCIExpressEndpointblockx8,x4,orx1lanewidthPowermanagementsupportBlockRAMsusedforbufferingFullybufferedtransmitandreceiveManagementinterfacetoaccessPCIExpressconfigurationspaceandinternalconfigurationSupportsthefullrangeofmaximumpayloadsizesUpto6x32bitor3x64bitBARs(oracombinationof32bitand64bit)Tri-ModeEthernetMediaAccessControllerDesignedtotheIEEE802.
3-2002specificationOperatesat10,100,and1,000Mb/sSupportstri-modeauto-negotiationReceiveaddressfilter(5addressentries)Fullymonolithic1000Base-XsolutionwithRocketIOGTPtransceiversSupportsmultipleexternalPHYconnections(RGMII,GMII,etc.
)interfacesthroughsoftlogicandSelectIOresourcesSupportsconnectiontoexternalPHYdevicethroughSGMIIusingsoftlogicandRocketIOGTPtransceiversReceiveandtransmitstatisticsavailablethroughseparateinterfaceSeparatehostandclientinterfacesSupportforjumboframesSupportforVLANFlexible,user-configurablehostinterfaceSupportsIEEE802.
3ah-2004unidirectionalmodeVirtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification5RRocketIOGTPTransceivers(LXT/SXTonly)Full-duplexserialtransceivercapableof100Mb/sto3.
75Gb/sbaudrates8B/10B,user-definedFPGAlogic,ornoencodingoptionsChannelbondingsupportCRCgenerationandcheckingProgrammablepre-emphasisorpre-equalizationforthetransmitterProgrammableterminationandvoltageswingProgrammableequalizationforthereceiverReceiversignaldetectandlossofsignalindicatorUserdynamicreconfigurationusingsecondaryconfigurationbusOutofBand(OOB)supportforSerialATA(SATA)Electricalidle,beaconing,receiverdetection,andPCIExpressandSATAspread-spectrumclockingsupportLessthan100mWtypicalpowerconsumptionBuilt-inPRBSGeneratorsandCheckersRocketIOGTXTransceivers(TXT/FXTonly)Full-duplexserialtransceivercapableof150Mb/sto6.
5Gb/sbaudrates8B/10Bencodingandprogrammablegearboxtosupport64B/66Band64B/67Bencoding,user-definedFPGAlogic,ornoencodingoptionsChannelbondingsupportCRCgenerationandcheckingProgrammablepre-emphasisorpre-equalizationforthetransmitterProgrammableterminationandvoltageswingProgrammablecontinuoustimeequalizationforthereceiverProgrammabledecisionfeedbackequalizationforthereceiverReceiversignaldetectandlossofsignalindicatorUserdynamicreconfigurationusingsecondaryconfigurationbusOOBsupport(SATA)Electricalidle,beaconing,receiverdetection,andPCIExpressspread-spectrumclockingsupportLow-poweroperationatalllineratesPowerPC440RISCCores(FXTonly)EmbeddedPowerPC440(PPC440)coresUpto550MHzoperationGreaterthan1000DMIPSpercoreSeven-stagepipelineMultipleinstructionspercycleOut-of-orderexecution32Kbyte,64-waysetassociativelevel1instructioncache32Kbyte,64-waysetassociativelevel1datacacheBookEcompliantIntegratedcrossbarforenhancedsystemperformance128-bitProcessorLocalBuses(PLBs)Integratedscatter/gatherDMAcontrollersDedicatedinterfaceforconnectiontoDDR2memorycontrollerAuto-synchronizationfornon-integerPLB-to-CPUclockratiosAuxiliaryProcessorUnit(APU)InterfaceandControllerDirectconnectionfromPPC440embeddedblocktoFPGAfabric-basedcoprocessors128-bitwidepipelinedAPULoad/StoreSupportofautonomousinstructions:nopipelinestallsProgrammabledecodeforcustominstructionsVirtex-5FamilyOverview6www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRArchitecturalDescriptionVirtex-5FPGAArrayOverviewVirtex-5devicesareuser-programmablegatearrayswithvariousconfigurableelementsandembeddedcoresoptimizedforhigh-densityandhigh-performancesystemdesigns.
Virtex-5devicesimplementthefollowingfunctionality:I/Oblocksprovidetheinterfacebetweenpackagepinsandtheinternalconfigurablelogic.
Mostpopularandleading-edgeI/OstandardsaresupportedbyprogrammableI/Oblocks(IOBs).
TheIOBscanbeconnectedtoveryflexibleChipSynclogicforenhancedsource-synchronousinterfacing.
Source-synchronousoptimizationsincludeper-bitdeskew(onbothinputandoutputsignals),dataserializers/deserializers,clockdividers,anddedicatedI/Oandlocalclockingresources.
ConfigurableLogicBlocks(CLBs),thebasiclogicelementsforXilinxFPGAs,providecombinatorialandsynchronouslogicaswellasdistributedmemoryandSRL32shiftregistercapability.
Virtex-5FPGACLBsarebasedonreal6-inputlook-uptabletechnologyandprovidesuperiorcapabilitiesandperformancecomparedtopreviousgenerationsofprogrammablelogic.
BlockRAMmodulesprovideflexible36Kbittruedual-portRAMthatarecascadabletoformlargermemoryblocks.
Inaddition,Virtex-5FPGAblockRAMscontainoptionalprogrammableFIFOlogicforincreaseddeviceutilization.
EachblockRAMcanalsobeconfiguredastwoindependent18Kbittruedual-portRAMblocks,providingmemorygranularityfordesignsneedingsmallerRAMblocks.
CascadableembeddedDSP48Esliceswith25x18two'scomplementmultipliersand48-bitadder/subtracter/accumulatorprovidemassivelyparallelDSPalgorithmsupport.
Inaddition,eachDSP48Eslicecanbeusedtoperformbitwiselogicalfunctions.
ClockManagementTile(CMT)blocksprovidethemostflexible,highest-performanceclockingforFPGAs.
EachCMTcontainstwoDigitalClockManager(DCM)blocks(self-calibrating,fullydigital),andonePLLblock(self-calibrating,analog)forclockdistributiondelaycompensation,clockmultiplication/division,coarse-/fine-grainedclockphaseshifting,andinputclockjitterfiltering.
Additionally,LXT,SXT,TXT,andFXTdevicesalsocontain:IntegratedEndpointblocksforPCIExpressdesignsprovidingx1,x4,orx8PCIExpressEndpointfunctionality.
WhenusedinconjunctionwithRocketIOtransceivers,acompletePCIExpressEndpointcanbeimplementedwithminimalFPGAlogicutilization.
10/100/1000Mb/sEthernetmedia-accesscontrolblocksofferEthernetcapability.
LXTandSXTdevicescontain:RocketIOGTPtransceiverscapableofrunningupto3.
75Gb/s.
EachGTPtransceiversupportsfull-duplex,clock-and-datarecovery.
TXTandFXTdevicescontain:GTXtransceiverscapableofrunningupto6.
5Gb/s.
EachGTXtransceiversupportsfull-duplex,clock-and-datarecovery.
FXTdevicescontain:EmbeddedIBMPowerPC440RISCCPUs.
EachPowerPC440CPUiscapableofrunningupto550MHz.
EachPowerPC440CPUalsohasanAPU(AuxiliaryProcessorUnit)interfacethatsupportshardwareacceleration,andanintegratedcross-barforhighdatathroughput.
Thegeneralroutingmatrix(GRM)providesanarrayofroutingswitchesbetweeneachinternalcomponent.
Eachprogrammableelementistiedtoaswitchmatrix,allowingmultipleconnectionstothegeneralroutingmatrix.
Theoverallprogrammableinterconnectionishierarchicalanddesignedtosupporthigh-speeddesigns.
InVirtex-5devices,theroutingconnectionsareoptimizedtosupportCLBinterconnectioninthefewestnumberof"hops.
"Reducinghopsgreatlyincreasespostplace-and-route(PAR)designperformance.
Allprogrammableelements,includingtheroutingresources,arecontrolledbyvaluesstoredinstaticstorageelements.
ThesevaluesareloadedintotheFPGAduringconfigurationandcanbereloadedtochangethefunctionsoftheprogrammableelements.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification7RVirtex-5FPGAFeaturesThissectionbrieflydescribesthefeaturesoftheVirtex-5familyofFPGAs.
Input/OutputBlocks(SelectIO)IOBsareprogrammableandcanbecategorizedasfollows:Programmablesingle-endedordifferential(LVDS)operationInputblockwithanoptionalsingledatarate(SDR)ordoubledatarate(DDR)registerOutputblockwithanoptionalSDRorDDRregisterBidirectionalblockPer-bitdeskewcircuitryDedicatedI/OandregionalclockingresourcesBuilt-indataserializer/deserializerTheIOBregistersareeitheredge-triggeredD-typeflip-flopsorlevel-sensitivelatches.
IOBssupportthefollowingsingle-endedstandards:LVTTLLVCMOS(3.
3V,2.
5V,1.
8V,1.
5V,and1.
2V)PCI(33and66MHz)PCI-XGTLandGTLPHSTL1.
5Vand1.
8V(ClassI,II,III,andIV)HSTL1.
2V(Class1)SSTL1.
8Vand2.
5V(ClassIandII)TheDigitallyControlledImpedance(DCI)I/Ofeaturecanbeconfiguredtoprovideon-chipterminationforeachsingle-endedI/OstandardandsomedifferentialI/Ostandards.
TheIOBelementsalsosupportthefollowingdifferentialsignalingI/Ostandards:LVDSandExtendedLVDS(2.
5Vonly)BLVDS(BusLVDS)ULVDSHypertransportDifferentialHSTL1.
5Vand1.
8V(ClassIandII)DifferentialSSTL1.
8Vand2.
5V(ClassIandII)RSDS(2.
5Vpoint-to-point)Twoadjacentpadsareusedforeachdifferentialpair.
TwoorfourIOBblocksconnecttooneswitchmatrixtoaccesstheroutingresources.
Per-bitdeskewcircuitryallowsforprogrammablesignaldelayinternaltotheFPGA.
Per-bitdeskewflexiblyprovidesfine-grainedincrementsofdelaytocarefullyproducearangeofsignaldelays.
Thisisespeciallyusefulforsynchronizingsignaledgesinsource-synchronousinterfaces.
GeneralpurposeI/Oinselectlocations(eightperbank)aredesignedtobe"regionalclockcapable"I/ObyaddingspecialhardwareconnectionsforI/Ointhesamelocality.
TheseregionalclockinputsaredistributedwithinalimitedregiontominimizeclockskewbetweenIOBs.
RegionalI/Oclockingsupplementstheglobalclockingresources.
Dataserializer/deserializercapabilityisaddedtoeveryI/Otosupportsource-synchronousinterfaces.
Aserial-to-parallelconverterwithassociatedclockdividerisincludedintheinputpath,andaparallel-to-serialconverterintheoutputpath.
Anin-depthguidetotheVirtex-5FPGAIOBisfoundintheVirtex-5FPGATri-ModeEthernetMACUserGuide.
ConfigurableLogicBlocks(CLBs)AVirtex-5FPGACLBresourceismadeupoftwoslices.
Eachsliceisequivalentandcontains:FourfunctiongeneratorsFourstorageelementsArithmeticlogicgatesLargemultiplexersFastcarrylook-aheadchainThefunctiongeneratorsareconfigurableas6-inputLUTsordual-output5-inputLUTs.
SLICEMsinsomeCLBscanbeconfiguredtooperateas32-bitshiftregisters(or16-bitx2shiftregisters)oras64-bitdistributedRAM.
Inaddition,thefourstorageelementscanbeconfiguredaseitheredge-triggeredD-typeflip-flopsorlevelsensitivelatches.
EachCLBhasinternalfastinterconnectandconnectstoaswitchmatrixtoaccessgeneralroutingresources.
TheVirtex-5FPGACLBsarefurtherdiscussedintheVirtex-5FPGAUserGuide.
BlockRAMThe36Kbittruedual-portRAMblockresourcesareprogrammablefrom32Kx1to512x72,invariousdepthandwidthconfigurations.
Inaddition,each36-Kbitblockcanalsobeconfiguredtooperateastwo,independent18-Kbitdual-portRAMblocks.
Eachportistotallysynchronousandindependent,offeringthree"read-during-write"modes.
BlockRAMiscascadabletoimplementlargeembeddedstorageblocks.
Additionally,back-endpipelineregisters,clockcontrolcircuitry,built-inFIFOsupport,ECC,andbytewriteenablefeaturesarealsoprovidedasoptions.
TheblockRAMfeatureinVirtex-5devicesisfurtherdiscussedintheVirtex-5FPGAUserGuide.
Virtex-5FamilyOverview8www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRGlobalClockingTheCMTsandglobal-clockmultiplexerbuffersprovideacompletesolutionfordesigninghigh-speedclocknetworks.
EachCMTcontainstwoDCMsandonePLL.
TheDCMsandPLLscanbeusedindependentlyorextensivelycascaded.
UptosixCMTblocksareavailable,providinguptoeighteentotalclockgeneratorelements.
EachDCMprovidesfamiliarclockgenerationcapability.
Togeneratedeskewedinternalorexternalclocks,eachDCMcanbeusedtoeliminateclockdistributiondelay.
TheDCMalsoprovides90°,180°,and270°phase-shiftedversionsoftheoutputclocks.
Fine-grainedphaseshiftingoffershigher-resolutionphaseadjustmentwithfractionoftheclockperiodincrements.
Flexiblefrequencysynthesisprovidesaclockoutputfrequencyequaltoafractionalorintegermultipleoftheinputclockfrequency.
ToaugmenttheDCMcapability,Virtex-5FPGACMTsalsocontainaPLL.
Thisblockprovidesreferenceclockjitterfilteringandfurtherfrequencysynthesisoptions.
Virtex-5deviceshave32global-clockMUXbuffers.
Theclocktreeisdesignedtobedifferential.
Differentialclockinghelpsreducejitteranddutycycledistortion.
DSP48ESlicesDSP48Esliceresourcescontaina25x18two'scomplementmultiplieranda48-bitadder/subtacter/accumulator.
EachDSP48Eslicealsocontainsextensivecascadecapabilitytoefficientlyimplementhigh-speedDSPalgorithms.
TheVirtex-5FPGADSP48EslicefeaturesarefurtherdiscussedinVirtex-5FPGAXtremeDSPDesignConsiderations.
RoutingResourcesAllcomponentsinVirtex-5devicesusethesameinterconnectschemeandthesameaccesstotheglobalroutingmatrix.
Inaddition,theCLB-to-CLBroutingisdesignedtoofferacompletesetofconnectivityinasfewhopsaspossible.
Timingmodelsareshared,greatlyimprovingthepredictabilityoftheperformanceforhigh-speeddesigns.
BoundaryScanBoundary-ScaninstructionsandassociateddataregisterssupportastandardmethodologyforaccessingandconfiguringVirtex-5devices,complyingwithIEEEstandards1149.
1and1532.
ConfigurationVirtex-5devicesareconfiguredbyloadingthebitstreamintointernalconfigurationmemoryusingoneofthefollowingmodes:Slave-serialmodeMaster-serialmodeSlaveSelectMAPmodeMasterSelectMAPmodeBoundary-Scanmode(IEEE-1532and-1149)SPImode(SerialPeripheralInterfacestandardFlash)BPI-up/BPI-downmodes(Byte-widePeripheralinterfacestandardx8orx16NORFlash)Inaddition,Virtex-5devicesalsosupportthefollowingconfigurationoptions:256-bitAESbitstreamdecryptionforIPprotectionMulti-bitstreammanagement(MBM)forcold/warmbootsupportParallelconfigurationbuswidthauto-detectionParalleldaisychainConfigurationCRCandECCsupportforthemostrobust,flexibledeviceintegritycheckingVirtex-5deviceconfigurationisfurtherdiscussedintheVirtex-5FPGAConfigurationGuide.
SystemMonitorFPGAsareanimportantbuildingblockinhighavailability/reliabilityinfrastructure.
Therefore,thereisneedtobettermonitortheon-chipphysicalenvironmentoftheFPGAanditsimmediatesurroundingswithinthesystem.
Forthefirsttime,theVirtex-5familySystemMonitorfacilitateseasiermonitoringoftheFPGAanditsexternalenvironment.
EverymemberoftheVirtex-5familycontainsaSystemMonitorblock.
TheSystemMonitorisbuiltarounda10-bit200kSPSADC(Analog-to-DigitalConverter).
ThisADCisusedtodigitizeanumberofon-chipsensorstoprovideinformationaboutthephysicalenvironmentwithintheFPGA.
On-chipsensorsincludeatemperaturesensorandpowersupplysensors.
Accesstotheexternalenvironmentisprovidedviaanumberofexternalanaloginputchannels.
Theseanaloginputsaregeneralpurposeandcanbeusedtodigitizeawidevarietyofvoltagesignaltypes.
Supportforunipolar,bipolar,andtruedifferentialinputschemesisprovided.
Thereisfullaccesstotheon-chipsensorsandexternalchannelsviatheJTAGTAP,allowingtheexistingJTAGinfrastructureonthePCboardtobeusedforanalogtestandadvanceddiagnosticsduringdevelopmentorafterdeploymentinthefield.
TheSystemMonitorisfullyoperationalafterpowerupandbeforeconfigurationoftheFPGA.
SystemMonitordoesnotrequireanexplicitinstantiationinadesigntogainaccesstoitsbasicfunctionality.
ThisallowstheSystemMonitortobeusedevenatalatestageinthedesigncycle.
TheVirtex-5FPGASystemMonitorisfurtherdiscussedintheVirtex-5FPGASystemMonitorUserGuide.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification9RVirtex-5LXT,SXT,TXT,andFXTPlatformFeaturesThissectionbrieflydescribesblocksavailableonlyinLXT,SXT,TXT,andFXTdevices.
Tri-Mode(10/100/1000Mb/s)EthernetMACsVirtex-5LXT,SXT,TXT,andFXTdevicescontainuptoeightembeddedEthernetMACs,twoperEthernetMACblock.
Theblockshavethefollowingcharacteristics:DesignedtotheIEEE802.
3-2002specificationUNH-compliancetestedRGMII/GMIIInterfacewithSelectIOorSGMIIinterfacewhenusedwithRocketIOtransceiversHalforfullduplexSupportsJumboframes1000Base-XPCS/PMA:WhenusedwithRocketIOGTPtransceiver,canprovidecomplete1000Base-Ximplementationon-chipDCR-busconnectiontomicroprocessorsIntegratedEndpointBlocksforPCIExpressVirtex-5LXT,SXT,TXT,andFXTdevicescontainuptofourintegratedEndpointblocks.
TheseblocksimplementTransactionLayer,DataLinkLayer,andPhysicalLayerfunctionstoprovidecompletePCIExpressEndpointfunctionalitywithminimalFPGAlogicutilization.
Theblockshavethefollowingcharacteristics:CompliantwiththePCIExpressBaseSpecification1.
1WorksinconjunctionwithRocketIOtransceiverstoprovidecompleteendpointfunctionality1,4,or8lanesupportperblockVirtex-5LXTandSXTPlatformFeaturesThissectionbrieflydescribesblocksavailableonlyinLXTandSXTdevices.
RocketIOGTPTransceivers4-24channelRocketIOGTPtransceiverscapableofrunning100Mb/sto3.
75Gb/s.
Fullclockanddatarecovery8/16-bitor10/20-bitdatapathsupportOptional8B/10BorFPGA-basedencode/decodeIntegratedFIFO/elasticbufferChannelbondingandclockcorrectionsupportEmbedded32-bitCRCgeneration/checkingIntegratedcomma-detectorA1/A2detectionProgrammablepre-emphasis(AKAtransmitterequalization)ProgrammabletransmitteroutputswingProgrammablereceiverequalizationProgrammablereceiverterminationEmbeddedsupportfor:OutofBand(OOB)signalling:SerialATABeaconing,electricalidle,andPCIExpressreceiverdetectionBuilt-inPRBSgenerator/checkerVirtex-5FPGARocketIOGTPtransceiversarefurtherdiscussedintheVirtex-5FPGARocketIOGTPTransceiverUserGuide.
Virtex-5FamilyOverview10www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRVirtex-5TXTandFXTPlatformFeaturesThissectiondescribesblocksonlyavailableinTXTandFXTdevices.
RocketIOGTXSerialTransceivers(TXT/FXT)8-48channelsRocketIOserialtransceiverscapableofrunning150Mb/sto6.
5Gb/sFullClockandDataRecovery8/16/32-bitor10/20/40-bitdatapathsupportOptional8B/10Bencoding,gearboxforprogrammable64B/66Bor64B/67Bencoding,orFPGA-basedencode/decodeIntegratedFIFO/ElasticBufferChannelbondingandclockcorrectionsupportDualembedded32-bitCRCgeneration/checkingIntegratedprogrammablecharacterdetectionProgrammablede-emphasis(AKAtransmitterequalization)ProgrammabletransmitteroutputswingsProgrammablereceiverequalizationProgrammablereceiverterminationEmbeddedsupportfor:SerialATA:OutofBand(OOB)signallingPCIExpress:Beaconing,electricalidle,andreceiverdetectionBuilt-inPRBSgenerator/checkerVirtex-5FPGARocketIOGTXtransceiversarefurtherdiscussedintheVirtex-5FPGARocketIOGTXTransceiverUserGuide.
OneorTwoPowerPC440ProcessorCores(FXTonly)SuperscalarRISCarchitecture32-bitBookEcompliant7-StageexecutionpipelineMultipleinstructionspercycleOut-of-orderexecutionIntegrated32KBLevel1InstructionCacheand32KBLevel1DataCache(64-waysetassociative)CoreConnectBusArchitectureCross-barconnectionforoptimizedprocessorbandwidthPLBSynchronizationLogic(Enablesnon-integerCPU-to-PLBclockratios)AuxiliaryProcessorUnit(APU)interfacewithanintegratedAPUcontrollerOptimizedFPGA-basedCoprocessorconnection-AutomaticdecodeofPowerPCfloating-pointinstructionsAllowscustominstructionsExtremelyefficientmicrocontroller-styleinterfacingThePowerPC440processorsarefurtherdiscussedintheEmbeddedProcessorBlockinVirtex-5FPGAsReferenceGuide.
IntellectualPropertyCoresXilinxoffersIPcoresforcommonlyusedcomplexfunctionsincludingDSP,businterfaces,processors,andprocessorperipherals.
UsingXilinxLogiCOREproductsandcoresfromthirdpartyAllianceCOREparticipants,customerscanshortendevelopmenttime,reducedesignrisk,andobtainsuperiorperformancefortheirdesigns.
Additionally,theCOREGeneratorsystemallowscustomerstoimplementIPcoresintoVirtex-5FPGAswithpredictableandrepeatableperformance.
Itoffersasimpleuserinterfacetogenerateparameter-basedcoresoptimizedforourFPGAs.
TheSystemGeneratorforDSPtoolallowssystemarchitectstoquicklymodelandimplementDSPfunctionsusinghandcraftedIPandfeaturesaninterfacetothird-partysystemlevelDSPdesigntools.
SystemGeneratorforDSPimplementsmanyofthehigh-performanceDSPcoressupportingVirtex-5FPGAsincludingtheXilinxForwardErrorCorrectionSolutionwithInterleaver/De-interleaver,Reed-Solomonencoder/decoders,andViterbidecoders.
Theseareidealforcreatinghighly-flexible,concatenatedcodecstosupportthecommunicationsmarket.
UsingVirtex-5FPGARocketIOtransceivers,industryleadingconnectivityandnetworkingIPcoresincludeleading-edgePCIExpress,SerialRapidIO,FibreChannel,and10GbEthernetcorescanbeimplemented.
TheXilinxSPI-4.
2IPcoreutilizestheVirtex-5FPGAChipSynctechnologytoimplementdynamicphasealignmentforhigh-performancesource-synchronousoperation.
XilinxalsoprovidesPCIcoresforadvancedsystem-synchronousoperation.
TheMicroBlaze32-bitprocessorcoreprovidestheindustry'sfastestsoftprocessingsolutionforbuildingcomplexsystemsforthenetworking,telecommunication,datacommunication,embedded,andconsumermarkets.
TheMicroBlazeprocessorfeaturesaRISCarchitecturewithHarvard-styleseparate32-bitinstructionanddatabusesrunningatfullspeedtoexecuteprogramsandaccessdatafrombothon-chipandexternalmemory.
AstandardsetofperipheralsarealsoCoreConnectenabledtoofferMicroBlazedesignerscompatibilityandreuse.
AllIPcoresforVirtex-5FPGAsarefoundontheXilinxIPCenterInternetportalpresentingthelatestintellectualpropertycoresandreferencedesignsusingSmartSearchforfasteraccess.
Virtex-5FPGALogiCOREEndpointBlockPlusWrapperforPCIExpressThisistherecommendedwrappertoconfiguretheintegratedEndpointblockforPCIExpressdeliveredthroughtheCOREGeneratorsystem.
Itprovidesmanyease-of-usefeaturesandoptimalconfigurationforEndpointapplicationsimplifyingthedesignprocessandreducingthetime-to-market.
Accesstothecore,includingbitstreamgenerationcapabilitycanbeobtainedthroughregistrationatnoextracharge.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification11RVirtex-5DeviceandPackageCombinationsandMaximumI/OsTable2:Virtex-5DeviceandPackageCombinationsandMaximumAvailableI/OsPackageFF323FFG323FFV323FF324FFG324FFV324FF676FFG676FFV676FF1153FFG1153FFV1153(1)FF1760FFG1760FFV1760(2)FF665FFG665FFV665FF1136FFG1136FFV1136(3)FF1156FFG1156FF1738FFG1738FFV1738(4)FF1759FFG1759Size(mm)19x1919x1927x2735x3542.
5x42.
527x2735x3535x3542.
5x42.
542.
5x42.
5DeviceGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OGTsI/OXC5VLX30N/A220N/A400XC5VLX50N/A220N/A440N/A560XC5VLX85N/A440N/A560XC5VLX110N/A440N/A800N/A800XC5VLX155N/A800N/A800XC5VLX220N/A800XC5VLX330N/A1,200XC5VLX20T4GTPs172XC5VLX30T4GTPs1728GTPs360XC5VLX50T8GTPs36012GTPs480XC5VLX85T12GTPs480XC5VLX110T16GTPs64016GTPs680XC5VLX155T16GTPs64016GTPs680XC5VLX220T16GTPs680XC5VLX330T24GTPs960XC5VSX35T8GTPs360XC5VSX50T8GTPs36012GTPs480XC5VSX95T16GTPs640XC5VSX240T24GTPs960XC5VTX150T40GTXs36040GTXs680XC5VTX240T48GTXs680XC5VFX30T8GTXs360XC5VFX70T8GTXs36016GTXs640XC5VFX100T16GTXs64016GTXs680XC5VFX130T20GTXs840XC5VFX200T24GTXs960Notes:1.
FFV1153packageisnotavailableintheLX155device.
2.
FFV1760packageisavailableintheLX110deviceonly.
3.
FFV1136packageisnotavailableintheLX155TandFX100Tdevices.
4.
FFV1738packageisavailableintheLX110Tdeviceonly.
Virtex-5FamilyOverview12www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRVirtex-5FPGAOrderingInformationVirtex-5FPGAorderinginformationshowninFigure1appliestoallpackagesincludingPb-Free.
X-RefTarget-Figure1Figure1:Virtex-5FPGAOrderingInformationExample:XC5VLX50T-1FFG665CDeviceTypeTemperatureRange:C=Commercial(TJ=0°Cto+85°C)I=Industrial(TJ=–40°Cto+100°C)NumberofPinsPackageTypeSpeedGrade(-1,-2,-3(1))Pb-FreeV=RoHS6/6G=RoHS6/6withexemption15DS100_01_071515Note:1)-3speedgradeisnotavailableinalldevicesVirtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification13RRevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.
DateVersionRevision04/14/061.
0InitialXilinxrelease.
05/12/061.
1FirstversionpostedtotheXilinxwebsite.
Minortypographicaleditsanddescriptionupdatestohighlightnewfeatures.
RemovedLUTutilizationbulletfrom"Virtex-5FPGALogic,"page3.
09/06/062.
0AddedLXTplatformtoentiredocument.
ThisincludesdescriptionsoftheRocketIOGTPtransceivers,theEthernetMACs,andthePCIExpressEndpointblock.
10/12/062.
1AddedLX85Tdevices.
AddedSystemMonitordescriptionsandfunctionality.
12/28/062.
2AddedLX220Tdevices.
RevisedtheTotalI/ObanksfortheLX330inTable1.
RevisedtheXC5VLX50T-FFG665exampleinFigure1.
Clarifiedsupportfor"DifferentialSSTL1.
8Vand2.
5V(ClassIandII),"page7.
02/02/073.
0AddedtheSXTplatformtoentiredocument.
05/23/073.
1RemovedsupportforIEEE1149.
609/04/073.
2Revisedmaximumlineratefrom3.
2Gb/sto3.
75Gb/sinentiredocument.
12/11/073.
3AddedLX20T,LX155T,andLX155devices.
12/17/073.
4AddedDisclaimer.
RevisedCMTsectiononpage3.
Clarified"Virtex-5FPGALogiCOREEndpointBlockPlusWrapperforPCIExpress,"page10.
03/31/084.
0AddedFXTplatformtoentiredocument.
Clarifiedinformationinthefollowingsections:"IntegratedEndpointBlockforPCIExpressCompliance"and"Tri-ModeEthernetMediaAccessController.
"ToavoidconfusionwithPLLfunctionality,removedPMCDreferencesin"GlobalClocking,"page8.
04/25/084.
1AddedXC5VSX240Ttoentiredocument.
05/07/084.
2UpdatedthroughoutdatasheetthattheRocketIOGTXtransceiversaredesignedtorunfrom150Mb/sto6.
5Gb/s.
ClarifiedPPC440MC_DDR2memorycontrolleronpage5.
06/18/084.
3RevisedEthernetMACcolumninTable1,page2andaddedNote5.
Alsoupdated"Tri-Mode(10/100/1000Mb/s)EthernetMACs,"page9.
09/23/084.
4AddedTXTplatformtoentiredocument.
RevisedRocketIOGTXtranscieverdatapathsupportonpage10.
02/6/095.
0ChangeddocumentclassificationtoProductSpecificationfromAdvanceProductSpecification.
08/21/155.
1UpdatedTable2andFigure1withRoHSpackageinformation.
Virtex-5FamilyOverview14www.
xilinx.
comDS100(v5.
1)August21,2015ProductSpecificationRDisclaimerTheinformationdisclosedtoyouhereunder(the"Materials")isprovidedsolelyfortheselectionanduseofXilinxproducts.
Tothemaximumextentpermittedbyapplicablelaw:(1)Materialsaremadeavailable"ASIS"andwithallfaults,XilinxherebyDISCLAIMSALLWARRANTIESANDCONDITIONS,EXPRESS,IMPLIED,ORSTATUTORY,INCLUDINGBUTNOTLIMITEDTOWARRANTIESOFMERCHANTABILITY,NON-INFRINGEMENT,ORFITNESSFORANYPARTICULARPURPOSE;and(2)Xilinxshallnotbeliable(whetherincontractortort,includingnegligence,orunderanyothertheoryofliability)foranylossordamageofanykindornaturerelatedto,arisingunder,orinconnectionwith,theMaterials(includingyouruseoftheMaterials),includingforanydirect,indirect,special,incidental,orconsequentiallossordamage(includinglossofdata,profits,goodwill,oranytypeoflossordamagesufferedasaresultofanyactionbroughtbyathirdparty)evenifsuchdamageorlosswasreasonablyforeseeableorXilinxhadbeenadvisedofthepossibilityofthesame.
XilinxassumesnoobligationtocorrectanyerrorscontainedintheMaterialsortonotifyyouofupdatestotheMaterialsortoproductspecifications.
Youmaynotreproduce,modify,distribute,orpubliclydisplaytheMaterialswithoutpriorwrittenconsent.
CertainproductsaresubjecttothetermsandconditionsofXilinx'slimitedwarranty,pleaserefertoXilinx'sTermsofSalewhichcanbeviewedathttp://www.
xilinx.
com/legal.
htm#tos;IPcoresmaybesubjecttowarrantyandsupporttermscontainedinalicenseissuedtoyoubyXilinx.
Xilinxproductsarenotdesignedorintendedtobefail-safeorforuseinanyapplicationrequiringfail-safeperformance;youassumesoleriskandliabilityforuseofXilinxproductsinsuchcriticalapplications,pleaserefertoXilinx'sTermsofSalewhichcanbeviewedathttp://www.
xilinx.
com/legal.
htm#tos.
Thisdocumentcontainspreliminaryinformationandissubjecttochangewithoutnotice.
Informationprovidedhereinrelatestoproductsand/orservicesnotyetavailableforsale,andprovidedsolelyforinformationpurposesandarenotintended,ortobeconstrued,asanofferforsaleoranattemptedcommercializationoftheproductsand/orservicesreferredtoherein.
AutomotiveApplicationsDisclaimerXILINXPRODUCTSARENOTDESIGNEDORINTENDEDTOBEFAIL-SAFE,ORFORUSEINANYAPPLICATIONREQUIRINGFAIL-SAFEPERFORMANCE,SUCHASAPPLICATIONSRELATEDTO:(I)THEDEPLOYMENTOFAIRBAGS,(II)CONTROLOFAVEHICLE,UNLESSTHEREISAFAIL-SAFEORREDUNDANCYFEATURE(WHICHDOESNOTINCLUDEUSEOFSOFTWAREINTHEXILINXDEVICETOIMPLEMENTTHEREDUNDANCY)ANDAWARNINGSIGNALUPONFAILURETOTHEOPERATOR,OR(III)USESTHATCOULDLEADTODEATHORPERSONALINJURY.
CUSTOMERASSUMESTHESOLERISKANDLIABILITYOFANYUSEOFXILINXPRODUCTSINSUCHAPPLICATIONS.
Virtex-5FamilyOverviewDS100(v5.
1)August21,2015www.
xilinx.
comProductSpecification15RVirtex-5FPGADocumentationCompleteandup-to-datedocumentationoftheVirtex-5familyofFPGAsisavailableontheXilinxwebsite.
InadditiontothemostrecentVirtex-5FamilyOverview,thefollowingfilesarealsoavailablefordownload:Virtex-5FPGADataSheet:DCandSwitchingCharacteristics(DS202)ThisdatasheetcontainstheDCandSwitchingCharacteristicspecificationsfortheVirtex-5family.
Virtex-5FPGAUserGuide(UG190)Thisguideincludeschapterson:ClockingResourcesClockManagementTechnology(CMT)Phase-LockedLoops(PLL)BlockRAMConfigurableLogicBlocks(CLBs)SelectIOResourcesSelectIOLogicResourcesAdvancedSelectIOLogicResourcesVirtex-5FPGAXtremeDSPDesignConsiderations(UG193)ThisguidedescribestheDSP48EsliceandincludesreferencedesignsforusingDSP48Emathfunctionsandvariousfilters.
Virtex-5FPGAConfigurationGuide(UG191)Thisall-encompassingconfigurationguideincludeschaptersonconfigurationinterfaces(serialandparallel),multi-bitstreammanagement,bitstreamencryption,Boundary-ScanandJTAGconfiguration,andreconfigurationtechniques.
Virtex-5FPGAPackagingandPinoutSpecification(UG195)Thisspecificationincludesthetablesfordevice/packagecombinationsandmaximumI/Os,pindefinitions,pinouttables,pinoutdiagrams,mechanicaldrawings,andthermalspecifications.
Virtex-5FPGAPCBDesigner'sGuide(UG203)ThisguideprovidesinformationonPCBdesignforVirtex-5devices,withafocusonstrategiesformakingdesigndecisionsatthePCBandinterfacelevel.
Virtex-5FPGASystemMonitorUserGuide(UG192)TheSystemMonitorfunctionalityisoutlinedinthisguide.
Virtex-5FPGARocketIOGTPTransceiverUserGuide(UG196)ThisguidedescribestheRocketIOGTPtransceiversavailableintheVirtex-5LXTandSXTplatforms.
Virtex-5FPGARocketIOGTXTransceiverUserGuide(UG198)ThisguidedescribestheRocketIOGTXtransceiversavailableintheVirtex-5TXTandFXTplatforms.
Virtex-5FPGATri-ModeEthernetMACUserGuide(UG194)ThisguidedescribesthededicatedTri-ModeEthernetMediaAccessControlleravailableintheVirtex-5LXT,SXT,TXT,andFXTplatforms.
Virtex-5FPGAIntegratedEndpointBlockforPCIExpressDesignsUserGuide(UG197)ThisguidedescribestheintegratedEndpointblocksintheVirtex-5LXT,SXT,TXT,andFXTplatformsthatarePCIExpresscompliant.
EmbeddedProcessorBlockinVirtex-5FPGAsReferenceGuide(UG200)ThisreferenceguideisadescriptionoftheembeddedprocessorblockavailableintheVirtex-5FXTplatform.
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