entirefastreport2

AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,intellectualpropertymattersandotherimportantdisclaimers.
PRODUCTIONDATA.
MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018MSP430F51x2,MSP430F51x1Mixed-SignalMicrocontrollers1DeviceOverview11.
1Features1LowSupply-VoltageRange:3.
6VDownto1.
8VUltra-LowPowerConsumption–ActiveMode(AM):180A/MHz–StandbyMode(LPM3WDTMode,3V):1.
1A–OffMode(LPM4RAMRetention,3V):0.
9A–ShutdownMode(LPM4.
5,3V):0.
25AWakeupFromStandbyModeinLessThan5s16-BitRISCArchitecture,ExtendedMemory,40-nsInstructionCycleTimeFlexiblePower-ManagementSystem–FullyIntegratedLDOWithProgrammableRegulatedCoreSupplyVoltage–SupplyVoltageSupervision,Monitoring,andBrownoutUnifiedClockSystem–FLLControlLoopforFrequencyStabilization–Low-PowerLow-FrequencyInternalClockSource(VLO)–Low-FrequencyTrimmedInternalReferenceSource(REFO)–32-kHzCrystals(XT1)–High-FrequencyCrystalsupto25MHz(XT1)HardwareMultiplierSupports32-BitOperations3-ChannelDMAUptoTwelve5-V-TolerantDigitalPush/PullI/OsWithupto20-mADriveStrength(1)16-BitTimerTD0WithThreeCapture/CompareRegistersandSupportofHigh-ResolutionMode(1)Fullfunctionalityinthe40-pinQFNpackageoptions.
Fortheavailablefeaturesofotherpackages,seeSignalDescriptions.
16-BitTimerTD1WithThreeCapture/CompareRegistersandSupportofHigh-ResolutionMode16-BitTimerTA0WithThreeCapture/CompareRegistersUniversalSerialCommunicationInterfaces(USCIs)(1)–USCI_A0Supports:–EnhancedUARTSupportsAutomaticBaud-RateDetection–IrDAEncoderandDecoder–SynchronousSPI–USCI_B0Supports:–I2C–SynchronousSPI10-Bit200-kspsAnalog-to-DigitalConverter(ADC)–InternalReference–Sample-and-Hold–AutoscanFeature–Upto8ExternalChannelsand2InternalChannels,IncludingTemperatureSensor(1)Upto16-ChannelOn-ChipComparatorIncludinganUltra-Low-PowerMode(1)SerialOnboardProgramming,NoExternalProgrammingVoltageNeededDeviceComparisonSummarizestheAvailableFamilyMembersAvailablein40-PinQFN(RSB),38-PinTSSOP(DA),and40-PinDie-SizedBGA(YFF)Packages1.
2ApplicationsAnalogandDigitalSensorSystemsLEDLightingDigitalPowerSuppliesMotorControlsRemoteControlsThermostats2MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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3DescriptionTheTIMSPfamilyofultra-low-powermicrocontrollersconsistsofseveraldevicesfeaturingdifferentsetsofperipheralstargetedforvariousapplications.
Thearchitecture,combinedwithfivelow-powermodes,isoptimizedtoachieveextendedbatterylifeinportablemeasurementapplications.
Thedevicefeaturesapowerful16-bitRISCCPU,16-bitregisters,andconstantgeneratorsthatcontributetomaximumcodeefficiency.
Thedigitallycontrolledoscillator(DCO)allowsthedevicestowakeupfromlow-powermodestoactivemodeinlessthan5s.
TheMSP430F51x2microcontrollersincludetwo16-bithigh-resolutiontimers,twoUSCIs(USCI_A0andUSCI_B0),a32-bithardwaremultiplier,ahigh-performance10-bitADC,anon-chipcomparator,a3-channelDMA,5-VtolerantI/Os,andupto29I/Opins.
TheMSP430F51x1microcontrollersincludetwo16-bithigh-resolutiontimers,twoUSCIs(USCI_A0andUSCI_B0),a32-bithardwaremultiplier,anon-chipcomparator,a3-channelDMA,5-VtolerantI/Os,andupto29I/Opins.
Typicalapplicationsforthesedevicesincludeanaloganddigitalsensorsystems,LEDlighting,digitalpowersupplies,motorcontrols,remotecontrols,thermostats,digitaltimers,andhand-heldmeters.
Forcompletemoduledescriptions,seetheMSP430F5xxandMSP430F6xxFamilyUser'sGuide.
(1)Forthemostcurrentpart,package,andorderinginformation,seethePackageOptionAddenduminSection8,orseetheTIwebsiteatwww.
ti.
com.
(2)Thedimensionsshownhereareapproximations.
Forthepackagedimensionswithtolerances,seetheMechanicalDatainSection8.
DeviceInformation(1)PARTNUMBERPACKAGEBODYSIZE(2)MSP430F5172IYFFDSBGA(40)SeeSection8MSP430F5172IRSBWQFN(40)5mm*5mmMSP430F5172IDATSSOP(38)12.
5mm*6.
2mm3MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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4FunctionalBlockDiagramsFigure1-1showsthefunctionalblockdiagramfortheMSP430F51x2devices.
Figure1-1.
FunctionalBlockDiagram,MSP430F51x2Figure1-2showsthefunctionalblockdiagramfortheMSP430F51x1devices.
Figure1-2.
FunctionalBlockDiagram,MSP430F51x14MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131TableofContentsCopyright2010–2018,TexasInstrumentsIncorporatedTableofContents1DeviceOverview11.
1Features11.
2Applications.
11.
3Description.
21.
4FunctionalBlockDiagrams.
32RevisionHistory53DeviceComparison63.
1RelatedProducts74TerminalConfigurationandFunctions.
84.
1PinDiagrams84.
2SignalDescriptions.
115Specifications145.
1AbsoluteMaximumRatings145.
2ESDRatings145.
3RecommendedOperatingConditions.
145.
4ActiveModeSupplyCurrentIntoVCCExcludingExternalCurrent.
165.
5Low-PowerModeSupplyCurrents(IntoVCC)ExcludingExternalCurrent.
165.
6ThermalResistanceCharacteristics175.
7Schmitt-TriggerInputs–General-PurposeI/O(P1.
0toP1.
5,P3.
2toP3.
7,andPJ.
0toPJ.
6)175.
8Schmitt-TriggerInputs–General-PurposeI/O(P1.
6andP1.
7,P2.
0toP2.
7,andP3.
0andP3.
1)175.
9Inputs–PortsP1andP2175.
10LeakageCurrent–General-PurposeI/O185.
11Outputs–PortsP1,P3,PJ(FullDriveStrength,P1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6)185.
12Outputs–PortsP1toP3(FullDriveStrength,P1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1)185.
13Outputs–PortsP1,P3,PJ(ReducedDriveStrength,P1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6).
195.
14Outputs–PortsP1toP3(ReducedDriveStrength,P1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1)195.
15OutputFrequency–PortsP1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6.
205.
16OutputFrequency–PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1.
205.
17TypicalCharacteristics–Outputs,ReducedDriveStrength(PxDS.
y=0),PortsP1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6.
215.
18TypicalCharacteristics–Outputs,FullDriveStrength(PxDS.
y=1),PortsP1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6.
225.
19TypicalCharacteristics–Outputs,ReducedDriveStrength(PxDS.
y=0),PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1.
235.
20TypicalCharacteristics–Outputs,FullDriveStrength(PxDS.
y=1),PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1.
255.
21CrystalOscillator,XT1,Low-FrequencyMode.
.
.
.
.
275.
22CrystalOscillator,XT1,High-FrequencyMode.
.
.
.
285.
23InternalVery-Low-PowerLow-FrequencyOscillator(VLO)295.
24InternalReference,Low-FrequencyOscillator(REFO)295.
25DCOFrequency.
305.
26PMM,BrownoutReset(BOR)315.
27PMM,CoreVoltage315.
28PMM,SVSHighSide325.
29PMM,SVMHighSide.
335.
30PMM,SVSLowSide.
335.
31PMM,SVMLowSide335.
32Wake-upTimesFromLow-PowerModes345.
33Timer_A345.
34USCI(UARTMode)345.
35USCI(SPIMasterMode)355.
36USCI(SPISlaveMode)375.
37USCI(I2CMode)395.
3810-BitADC,PowerSupplyandInputRangeConditions(MSP430F51x2DevicesOnly)405.
3910-BitADC,TimingParameters(MSP430F51x2DevicesOnly)405.
4010-BitADC,LinearityParameters(MSP430F51x2DevicesOnly)415.
41REF,ExternalReference(MSP430F51x2DevicesOnly)415.
42REF,Built-InReference(MSP430F51x2DevicesOnly)425.
43Comparator_B.
435.
44Timer_D,PowerSupplyandReferenceClock.
.
.
.
.
.
445.
45Timer_D,LocalClockGeneratorFrequency.
455.
46Timer_D,TrimmedClockFrequencies.
475.
47Timer_D,FrequencyMultiplicationMode475.
48Timer_D,InputCaptureandOutputCompareTiming485.
49FlashMemory495.
50JTAGandSpy-Bi-WireInterface.
496DetailedDescription506.
1CPU506.
2InstructionSet.
516.
3OperatingModes.
526.
4InterruptVectorAddresses.
536.
5MemoryOrganization546.
6Bootloader(BSL)546.
7FlashMemory556.
8RAM556.
9Peripherals556.
10Input/OutputDiagrams746.
11DeviceDescriptors917DeviceandDocumentationSupport977.
1GettingStartedandNextSteps.
977.
2DeviceNomenclature977.
3ToolsandSoftware997.
4DocumentationSupport.
1017.
5RelatedLinks1027.
6CommunityResources.
1027.
7Trademarks1027.
8ElectrostaticDischargeCaution1037.
9ExportControlNotice1035MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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comSLAS619R–AUGUST2010–REVISEDSEPTEMBER2018SubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131RevisionHistoryCopyright2010–2018,TexasInstrumentsIncorporated7.
10Glossary.
1038Mechanical,Packaging,andOrderableInformation.
1042RevisionHistoryChangesfromJuly20,2018toSeptember20,2018PageAddedtypicalconditionsstatementsatthebeginningofSection5,Specifications14UpdatedSection7.
4,DocumentationSupport.
1016MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131DeviceComparisonCopyright2010–2018,TexasInstrumentsIncorporated(1)Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddenduminSection8,orseetheTIwebsiteatwww.
ti.
com.
(2)Packagedrawings,thermaldata,andsymbolizationareavailableatwww.
ti.
com/packaging.
(3)EachnumberinthesequencerepresentsaninstantiationofTimer_AwithitsassociatednumberofcapturecompareregistersandPWMoutputgeneratorsavailable.
Forexample,anumbersequenceof3,5wouldrepresenttwoinstantiationsofTimer_A,thefirstinstantiationhaving3andthesecondinstantiationhaving5capturecompareregistersandPWMoutputgenerators,respectively.
(4)EachnumberinthesequencerepresentsaninstantiationofTimer_DwithitsassociatednumberofcapturecompareregistersandPWMoutputgeneratorsavailable.
Forexample,anumbersequenceof3,5wouldrepresenttwoinstantiationsofTimer_D,thefirstinstantiationhaving3andthesecondinstantiationhaving5capturecompareregistersandPWMoutputgenerators,respectively.
3DeviceComparisonTable3-1summarizestheavailablefamilymembers.
Table3-1.
DeviceComparison(1)(2)DEVICEFLASH(KB)SRAM(KB)Timer_A(3)Timer_D(4)USCIADC10_A(Ch)Comp_B(Ch)I/OsPACKAGECHANNELA:UART,IrDA,SPICHANNELB:SPI,I2CMSP430F517232233,3119ext,2int163140QFN40DSBGA8ext,2int152938TSSOPMSP430F515216233,3119ext,2int163140QFN40DSBGA8ext,2int152938TSSOPMSP430F51328133,3119ext,2int163140QFN40DSBGA8ext,2int152938TSSOPMSP430F517132233,311–163140QFN40DSBGA152938TSSOPMSP430F515116233,311–163140QFN40DSBGA152938TSSOPMSP430F51318133,311–163140QFN40DSBGA152938TSSOP7MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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1RelatedProductsForinformationaboutotherdevicesinthisfamilyofproductsorrelatedproducts,seethefollowinglinks.
TI16-bitand32-bitmicrocontrollersHigh-performance,low-powersolutionstoenabletheautonomousfutureProductsforMSP430ultra-low-powersensingandmeasurementmicrocontrollersOneplatform.
Oneecosystem.
Endlesspossibilities.
ProductsforMSP430ultra-low-powermicrocontrollersMCUsformetrology,monitoring,systemcontrol,andcommunicationsCompanionProductsforMSP430F5172Reviewproductsthatarefrequentlypurchasedorusedinconjunctionwiththisproduct.
ReferenceDesignsforMSP430F5172TIDesignsReferenceDesignLibraryisarobustreferencedesignlibrarythatspansanalog,embeddedprocessor,andconnectivity.
CreatedbyTIexpertstohelpyoujumpstartyoursystemdesign,allTIDesignsincludeschematicorblockdiagrams,BOMs,anddesignfilestospeedyourtimetomarket.
Searchanddownloaddesignsatti.
com/tidesigns.
8MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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1PinDiagramsFigure4-1showsthepinoutforthe40-pinRSBpackage.
Figure4-1.
40-PinRSBPackage(TopView)9MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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Figure4-2.
38-PinDAPackage(TopView)10MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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Forthepackagedimensions,seetheMechanicalDatainSection8.
Figure4-3.
40-PinYFFPackage(TopViewandBottomView)11MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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ThesecondarypinfunctionsAx(ADC10_Achannelx)availableonlyinMSP430F51x2devices.
(4)FordetailsonthePortMappingController,seeSection6.
9.
2.
4.
2SignalDescriptionsTable4-1describesthesignalsforalldeviceandpackagevariants.
Table4-1.
SignalDescriptionsTERMINALI/O(1)DESCRIPTIONNAMENO.
(2)RSBDAYFFP1.
0/PM_UCA0CLK/PM_UCB0STE/A0(3)/CB015B5I/OGeneral-purposedigitalI/Owithreconfigurableportmappingsecondaryfunction(4)Defaultmapping:Clocksignalinput–USCI_A0SPIslavemode;Clocksignaloutput–USCI_A0SPImastermodeDefaultmapping:Slavetransmitenable–USCI_B0SPImodeAnaloginputA0–10-bitADC(3)Comparator_BInput0P1.
1/PM_UCA0TXD/PM_UCA0SIMO/A1(3)/CB126B6I/OGeneral-purposedigitalI/ODefaultmapping:Transmitdata–USCI_A0UARTmodeDefaultmapping:Slavein,masterout–USCI_A0SPImodeAnaloginputA1–10-bitADC(3)Comparator_BInput1P1.
2/PM_UCA0RXD/PM_UCA0SOMI/A2(3)/CB237C5I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:Receivedata–USCI_A0UARTmodeDefaultmapping:Slaveout,masterin–USCI_A0SPImodeAnaloginputA2–10-bitADC(3)Comparator_BInput2P1.
3/PM_UCB0CLK/PM_UCA0STE/A3(3)/CB348C6I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:Clocksignalinput–USCI_B0SPIslavemode;Clocksignaloutput–USCI_B0SPImastermodeDefaultmapping:Slavetransmitenable–USCI_A0SPImodeAnaloginputA3–10-bitADC(3)Comparator_BInput3P1.
4/PM_UCB0SIMO/PM_UCB0SDA/A4(3)/CB459D5I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:Slavein,masterout–USCI_B0SPImodeDefaultmapping:I2Cdata–USCI_B0I2CmodeAnaloginputA4–10-bitADC(3)Comparator_BInput4P1.
5/PM_UCB0SOMI/PM_UCB0SCL/A5(3)/CB5610D6I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:Slaveout,masterin–USCI_B0SPImodeDefaultmapping:I2Cclock–USCI_B0I2CmodeAnaloginputA5–10-bitADC(3)Comparator_BInput5PJ.
0/SMCLK/TDO/CB6711E6I/OGeneral-purposedigitalI/OSMCLKclockoutputTestdataoutputportComparator_BInput6PJ.
1/MCLK/TDI/TCLK/CB7812E5I/OGeneral-purposedigitalI/OMCLKclockoutputTestdatainputortestclockinputComparator_BInput7PJ.
2/ADC10CLK/TMS/CB8913F6I/OGeneral-purposedigitalI/OADC10_AclockoutputTestmodeselectComparator_BInput8PJ.
3/ACLK/TCK/CB91014E4I/OGeneral-purposedigitalI/OACLKoutputportTestclockComparator_BInput9P1.
6/PM_TD0.
01115G6I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0CCR0compareoutput/captureinput12MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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SignalDescriptions(continued)TERMINALI/O(1)DESCRIPTIONNAMENO.
(2)RSBDAYFF(5)Whenthispinisconfiguredasreset,theinternalpullupresistorisenabledbydefault.
P1.
7/PM_TD0.
11216F5I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0CCR1compareoutput/captureinputP2.
0/PM_TD0.
21317F4I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0CCR2compareoutput/captureinputP2.
1/PM_TD1.
01418G5I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD1CCR0compareoutput/captureinputP2.
2/PM_TD1.
11519G4I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD1CCR1compareoutput/captureinputP2.
3/PM_TD1.
21620E3I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD1CCR2compareoutput/captureinputDVIO1721G35-VtolerantdigitalI/OpowersupplyDVSS1822G2DigitalgroundsupplyP2.
4/PM_TEC0CLR/PM_TEC0FLT2/PM_TD0.
01923F3I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0externalclearinputDefaultmapping:TD0faultinputchannel2(controlledbymoduleinputenable)Defaultmapping:TD0CCR0compareoutputP2.
5/PM_TEC0FLT0/PM_TD0.
12024G1I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0faultinputchannel0Defaultmapping:TD0CCR1compareoutputP2.
6/PM_TEC0FLT1/PM_TD0.
22125F2I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0faultinputchannel1Defaultmapping:TD0CCR2compareoutputP2.
7/PM_TEC1CLR/PM_TEC1FLT1/PM_TD1.
02226E2I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD1externalclearDefaultmapping:TD1faultinputchannel1(controlledbymoduleinputenable)Defaultmapping:TD1CCR0compareoutputP3.
0/PM_TEC1FLT2/PM_TD1.
12327F1I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD1faultinputchannel2Defaultmapping:TD1CCR1compareoutputP3.
1/PM_TEC1FLT0/PM_TD1.
22428E1I/O,DVIOGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD1faultinputchannel0Defaultmapping:TD1CCR2compareoutputVCORE2529D1RegulatedcorepowersupplyDVSS2630C1DigitalgroundsupplyDVCC2731B1DigitalpowersupplyPJ.
6/TD1CLK/TD0.
1/CB152832C2I/OGeneral-purposedigitalI/OTD1clockinputTD0CCR1compareoutputComparator_BInput15P3.
2/PM_TD0.
0/PM_SMCLK/CB142933B2I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0CCR0captureinputDefaultmapping:SMCLKoutputComparator_BInput14P3.
3/PM_TA0CLK/PM_CBOUT/CB133034A1I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TA0clockinputDefaultmapping:Comparator_BoutputComparator_BInput13P3.
4/PM_TD0CLK/PM_MCLK31–A2I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TD0clockinputDefaultmapping:MCLKoutputTEST/SBWTCK3235D2Testmodepin–selectdigitalI/OonJTAGpinsSpy-Bi-WireinputclockRST/NMI/SBWTDIO3336B3Resetinputactivelow(5)NonmaskableinterruptinputSpy-Bi-Wiredatainput/output13MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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SignalDescriptions(continued)TERMINALI/O(1)DESCRIPTIONNAMENO.
(2)RSBDAYFFP3.
5/PM_TA0.
2/A8(3)VEREF+/CB123437A3I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TA0CCR2compareoutput/captureinputAnaloginputA8–10-bitADC(3)PositiveterminalfortheADCreferencevoltageforanexternalappliedreferencevoltageComparator_BInput12P3.
6/PM_TA0.
1/A7(3)/VEREF-/CB113538A4I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TA0CCR1compareoutput/captureinputAnaloginputA7–10-bitADC(3)NegativeterminalfortheADCreferencevoltageforanexternalappliedreferencevoltageComparator_BInput11P3.
7/PM_TA0.
0/A6(3)/CB1036–B4I/OGeneral-purposedigitalI/OwithreconfigurableportmappingsecondaryfunctionDefaultmapping:TA0CCR0compareoutput/captureinputAnaloginputA6–10-bitADC(3)Comparator_BInput10AVCC371C3AnalogpowersupplyPJ.
4/XOUT382A5I/OGeneral-purposedigitalI/OOutputterminalofcrystaloscillatorPJ.
5/XIN393A6I/OGeneral-purposedigitalI/OInputterminalforcrystaloscillatorAVSS404C4AnaloggroundsupplyQFNpad–NANARecommendedtoconnecttoDVSSexternally14MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131SpecificationsCopyright2010–2018,TexasInstrumentsIncorporated(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditionsisnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)AllvoltagesreferencedtoVSS.
VCOREisforinternaldeviceusageonly.
NoexternalDCloadingorvoltageshouldbeapplied.
5SpecificationsAllgraphsinthissectionarefortypicalconditions,unlessotherwisenoted.
Typical(TYP)valuesarespecifiedatVCC=3.
3VandTA=25°C,unlessotherwisenoted.
5.
1AbsoluteMaximumRatings(1)overoperatingfree-airtemperaturerange(unlessotherwisenoted)MINMAXUNITVoltageVCCappliedatDVCCtoDVSS–0.
34.
1VVVoltageVIOappliedatVIOtoDVSS–0.
36.
1VVVoltageappliedtoanypin(excludingVCORE)(2)–0.
3VCC+0.
3VDiodecurrentatanydevicepin±2mAMaximumoperatingjunctiontemperature,TJ95°CStoragetemperature,Tstg–55150°C(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
Pinslistedas±1000Vmayactuallyhavehigherperformance.
(2)JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
Pinslistedas±250Vmayactuallyhavehigherperformance.
5.
2ESDRatingsVALUEUNITV(ESD)ElectrostaticdischargeHuman-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1)±1000VCharged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2)±250(1)TIrecommendspoweringAVCCandDVCCfromthesamesource.
Amaximumdifferenceof0.
3VbetweenV(AVCC)andV(DVCC)canbetoleratedduringpowerupandoperation.
(2)TheminimumsupplyvoltageisdefinedbythesupervisorSVSlevelswhenitisenabled.
SeetheSection5.
28thresholdparametersfortheexactvaluesandfurtherdetails.
(3)IfDVIOisnotsuppliedbythesamesourceasDVCC,TIrecommendspoweringAVCCandDVCCbeforepoweringDVIO.
AtDVCCandAVCCvoltageshigherthan1.
8V,themaximumdifferenceof0.
3VbetweenDVIOand(DVCCandAVCC)canbeexceeded.
DVIOmustbehigherthanorequaltoDVCC.
IncreasedcrosscurrentcanflowintoDVCCifDVIOislessthan(DVCC–0.
3V),withamaximumcurrentflowingwhenDVIOisequaltoDVCC/2.
ToavoidhighcurrentsintoDVCC,DVIOmustbehigherthanorequaltoDVCC,DVIOmustnotfloat,andDVIOmustbeturnedoffquickly.
TIrecommendspullingtheDVIOpinstolowbeforedisablingDVIO.
(4)Forbestcross-currentprevention,voltageappliedtoDVIOshouldnotbelowerthanDVCC.
However,ifDVIOisswitchedoffduringoperation,duetoapplicationrequirements,DVIOshouldbepulledtogroundtopreventafloatingvoltage.
(5)Acapacitortoleranceof±20%orbetterisrequired.
5.
3RecommendedOperatingConditionsMINNOMMAXUNITVCCSupplyvoltageduringprogramexecutionandflashprogrammingV(AVCC)=V(DVCC)=VCC(1)(2)PMMCOREVx=01.
83.
6VPMMCOREVx=0,12.
03.
6PMMCOREVx=0,1,22.
23.
6PMMCOREVx=0,1,2,32.
43.
6VIOSupplyvoltageofpinsP1.
6,P1.
7,P2.
0toP2.
7,P3.
0,andP3.
1suppliedbyVIO(3)(4)1.
85.
5VVSSSupplyvoltageV(AVSS)=V(DVSS)=VSS0VTAOperatingfree-airtemperature–4085°CTJOperatingjunctiontemperature–4085°CC(VCORE)RecommendedcapacitoratVCORE(5)470nFC(DVCC)/C(VCORE)CapacitorratioofDVCCtoVCORE1015MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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BoththehighandlowphaseofMCLKmustnotexceedthepulsedurationofthespecifiedmaximumfrequency.
(7)Modulesmayhaveadifferentmaximuminputclockspecification.
Seethespecificationoftherespectivemoduleinthisdatasheet.
fSYSTEMProcessorfrequency(maximumMCLKfrequency)(6)(7)(seeFigure5-1)PMMCOREVx=0,1.
8V≤VCC≤3.
6V(defaultcondition)012MHzPMMCOREVx=1,2.
0V≤VCC≤3.
6V016PMMCOREVx=2,2.
2V≤VCC≤3.
6V020PMMCOREVx=3,2.
4V≤VCC≤3.
6V025PINTInternalpowerdissipationVCC*I(DVCC)WPIOI/OpowerdissipationoftheI/OpinspoweredbyDVCC(VCC–VIOH)*IIOH+VIOL*IIOLWPIO5I/OpowerdissipationoftheI/OpinspoweredbyVIO(VIO–VIOH5)*IIOH5+VIOL5*IIOL5WPMAXMaximumallowedpowerdissipation,PMAX>PIO+PIO5+PINT(TJ–TA)/RθJAWFigure5-1.
FrequencyvsSupplyVoltage16MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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4ActiveModeSupplyCurrentIntoVCCExcludingExternalCurrentoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETEREXECUTIONMEMORYVCCPMMCOREVxFREQUENCY(fDCO=fMCLK=fSMCLK)UNIT1MHz8MHz12MHz20MHz25MHzTYPMAXTYPMAXTYPMAXTYPMAXTYPMAXIAM,FlashFlash3V00.
240.
271.
481.
60mA10.
261.
662.
482.
720.
281.
832.
724.
504.
830.
281.
832.
664.
405.
606.
15IAM,RAMRAM3V00.
170.
20.
890.
97mA10.
181.
001.
491.
6220.
201.
141.
682.
753.
030.
201.
201.
782.
923.
644.
0(1)Allinputsaretiedto0VortoVCC.
Outputsdonotsourceorsinkanycurrent.
DVIO=DVCC=AVCC.
(2)ThecurrentsarecharacterizedwithaMicroCrystalMS1V-T1KSMDcrystalwithaloadcapacitanceof12.
5pF.
Theinternalandexternalloadcapacitancearechosentocloselymatchtherequired9pF.
5.
5Low-PowerModeSupplyCurrents(IntoVCC)ExcludingExternalCurrentoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(2)PARAMETERVCCPMMCOREVx–40°C25°C60°C85°CUNITTYPMAXTYPMAXTYPMAXTYPMAXILPM0,1MHzLow-powermode02.
2V082908590879585100A3V388100851009010488104ILPM2Low-powermode22.
2V01012.
510121012.
512.
513A3V3911.
5111311151214ILPM3,XT1LFLow-powermode3,crystalmode2.
2V01.
7–1.
82.
02.
5–3.
56.
0A3V2.
0–2.
02.
23.
0–3.
76.
02.
2V11.
8–1.
9–2.
5–4.
0–3V2.
1–2.
2–2.
5–4.
0–2.
2V21.
8–2.
0–2.
5–4.
2–3V2.
0–2.
2–2.
8–4.
2–2.
2V31.
9–2.
02.
52.
9–4.
86.
53V2.
1–2.
22.
53.
0–5.
27.
0ILPM3,VLOLow-powermode3,VLOmode2.
2V01.
0–1.
01.
251.
6–3.
54.
5A3V1.
1–1.
21.
41.
5–3.
65.
02.
2V11.
0–1.
1–1.
8–3.
0–3V1.
3–1.
1–2.
0–3.
2–2.
2V21.
1–1.
1–1.
8–3.
1–3V1.
1–1.
2–2.
0–3.
2–2.
2V31.
1–1.
11.
41.
9–3.
55.
03V1.
1–1.
21.
52.
1–4.
05.
2ILPM4Low-powermode43V00.
8–0.
91.
31.
4–3.
54.
7A10.
8–1.
0–1.
4–3.
5–20.
8–1.
0–1.
5–3.
6–30.
9–1.
01.
31.
6–3.
65.
0ILPM4.
5Low-powermode4.
52.
2Vx0.
06–0.
200.
260.
33–0.
600.
9A3Vx0.
07–0.
250.
290.
37–0.
770.
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6ThermalResistanceCharacteristicsTHERMALMETRICVALUEUNITθJAJunction-to-ambientthermalresistance,stillairLow-Kboard(JESD51-3)QFN(RSB)87°C/WTSSOP(DA)109High-Kboard(JESD51-7)QFN(RSB)35TSSOP(DA)69θJCJunction-to-casethermalresistanceQFN(RSB)36°C/WTSSOP(DA)19(1)AlsoappliestoRSTpinwhenpulluporpulldownresistorisenabled.
5.
7Schmitt-TriggerInputs–General-PurposeI/O(P1.
0toP1.
5,P3.
2toP3.
7,andPJ.
0toPJ.
6)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITVIT+Positive-goinginputthresholdvoltage1.
8V0.
801.
40V3V1.
502.
10VIT–Negative-goinginputthresholdvoltage1.
8V0.
451.
00V3V0.
751.
65VhysInputvoltagehysteresis(VIT+–VIT–)1.
8V0.
30.
8V3V0.
41.
0RPullPulluporpulldownresistor(1)Forpullup:VIN=VSSForpulldown:VIN=VCC203550kCIInputcapacitanceVIN=VSSorVCC5pF5.
8Schmitt-TriggerInputs–General-PurposeI/O(P1.
6andP1.
7,P2.
0toP2.
7,andP3.
0andP3.
1)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVIOMINTYPMAXUNITVIT+Positive-goinginputthresholdvoltage1.
8V0.
801.
40V3V1.
202.
005V2.
102.
50VIT–Negative-goinginputthresholdvoltage1.
8V0.
450.
90V3V0.
751.
305V1.
101.
60VhysInputvoltagehysteresis(VIT+–VIT–)1.
8V0.
270.
45V3V0.
450.
655V0.
91.
2RPullPulluporpulldownresistorForpullup:VIN=VSSForpulldown:VIN=VCC203550kCIInputcapacitanceVIN=VSSorVCC5pF(1)Somedevicesmaycontainadditionalportswithinterrupts.
Seetheblockdiagramandterminalfunctiondescriptions.
(2)Anexternalsignalsetstheinterruptflageverytimetheminimuminterruptpulsedurationt(int)ismet.
Itmaybesetbytriggersignalsshorterthant(int).
5.
9Inputs–PortsP1andP2(1)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCorVIOMINMAXUNITt(int)Externalinterrupttiming(2)PortP1.
0toP1.
5,externaltriggerpulsedurationtosetinterruptflag1.
8Vto3.
6V20nsPortP1.
6andP1.
7andP2.
0toP2.
7,externaltriggerpulsedurationtosetinterruptflag1.
8Vto5V2518MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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(2)Theleakageofthedigitalportpinsismeasuredindividually.
Theportpinisselectedforinputandthepulluporpulldownresistorisdisabled.
5.
10LeakageCurrent–General-PurposeI/Ooverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITIlkg(Px.
y)High-impedanceleakagecurrentPortP1.
0toP1.
5,P3.
0toP3.
7,PJ.
0toPJ.
6See(1)(2)1.
8Vto3.
6V±1±50nAPortP1.
6andP1.
7,P2.
0toP2.
71.
8Vto5V±1±50(1)Themaximumtotalcurrent,I(OHmax)andI(OLmax),foralloutputscombinedshouldnotexceed±48mAtoholdthemaximumvoltagedropspecified.
(2)Themaximumtotalcurrent,I(OHmax)andI(OLmax),foralloutputscombinedshouldnotexceed±100mAtoholdthemaximumvoltagedropspecified.
5.
11Outputs–PortsP1,P3,PJ(FullDriveStrength,P1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINMAXUNITVOHHigh-leveloutputvoltageI(OHmax)=–3mA(1)1.
8VVCC–0.
25VCCVI(OHmax)=–10mA(2)VCC–0.
60VCCI(OHmax)=–5mA(1)3VVCC–0.
25VCCI(OHmax)=–15mA(2)VCC–0.
60VCCVOLLow-leveloutputvoltageI(OLmax)=3mA(1)1.
8VVSSVSS+0.
25VI(OLmax)=10mA(2)VSSVSS+0.
60I(OLmax)=5mA(1)3VVSSVSS+0.
25I(OLmax)=15mA(2)VSSVSS+0.
60(1)Themaximumtotalcurrent,I(OH5max)andI(OL5max),foralloutputscombinedshouldnotexceed±48mAtoholdthemaximumvoltagedropspecified.
(2)Themaximumtotalcurrent,I(OH5max)andI(OL5max),foralloutputscombinedshouldnotexceed±200mAtoholdthemaximumvoltagedropspecified.
5.
12Outputs–PortsP1toP3(FullDriveStrength,P1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVIOMINMAXUNITVOH5High-leveloutputvoltageI(OH5max)=–3mA(1)1.
8VVIO–0.
25VIOVI(OH5max)=–10mA(2)VIO–0.
60VIOI(OH5max)=–5mA(1)3VVIO–0.
25VIOI(OH5max)=–15mA(2)VIO–0.
60VIOI(OH5max)=–7mA(1)5VVIO–0.
25VIOI(OH5max)=–20mA(2)VIO–0.
60VIOVOL5Low-leveloutputvoltageI(OL5max)=3mA(1)1.
8VVSSVSS+0.
25VI(OL5max)=10mA(2)VSSVSS+0.
60I(OL5max)=5mA(1)3VVSSVSS+0.
25I(OL5max)=15mA(2)VSSVSS+0.
60I(OL5max)=7mA(1)5VVSSVSS+0.
25I(OL5max)=20mA(2)VSSVSS+0.
6019MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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(2)Themaximumtotalcurrent,I(OHmax)andI(OLmax),foralloutputscombined,shouldnotexceed±48mAtoholdthemaximumvoltagedropspecified.
(3)Themaximumtotalcurrent,I(OHmax)andI(OLmax),foralloutputscombined,shouldnotexceed±100mAtoholdthemaximumvoltagedropspecified.
5.
13Outputs–PortsP1,P3,PJ(ReducedDriveStrength,P1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)PARAMETERTESTCONDITIONSVCCMINMAXUNITVOHHigh-leveloutputvoltageI(OHmax)=–1mA(2)1.
8VVCC–0.
25VCCVI(OHmax)=–3mA(3)VCC–0.
60VCCI(OHmax)=–2mA(2)3VVCC–0.
25VCCI(OHmax)=–6mA(3)VCC–0.
60VCCVOLLow-leveloutputvoltageI(OLmax)=1mA(2)1.
8VVSSVSS+0.
25VI(OLmax)=3mA(3)VSSVSS+0.
60I(OLmax)=2mA(2)3VVSSVSS+0.
25I(OLmax)=6mA(3)VSSVSS+0.
60(1)SelectingreduceddrivestrengthmayreduceEMI.
(2)Themaximumtotalcurrent,I(OH5max)andI(OL5max),foralloutputscombined,shouldnotexceed±48mAtoholdthemaximumvoltagedropspecified.
(3)Themaximumtotalcurrent,I(OH5max)andI(OL5max),foralloutputscombined,shouldnotexceed±200mAtoholdthemaximumvoltagedropspecified.
5.
14Outputs–PortsP1toP3(ReducedDriveStrength,P1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)PARAMETERTESTCONDITIONSVIOMINMAXUNITVOH5High-leveloutputvoltageI(OH5max)=–1mA(2)1.
8VVIO–0.
25VIOVI(OH5max)=–3mA(3)VIO–0.
60VIOI(OH5max)=–2mA(2)3VVIO–0.
25VIOI(OH5max)=–6mA(3)VIO–0.
60VIOI(OH5max)=–4mA(2)5.
0VVIO–0.
25VIOI(OH5max)=–12mA(3)VIO–0.
60VIOVOL5Low-leveloutputvoltageI(OL5max)=1mA(2)1.
8VVSSVSS+0.
25VI(OL5max)=3mA(3)VSSVSS+0.
60I(OL5max)=2mA(2)3VVSSVSS+0.
25I(OL5max)=6mA(3)VSSVSS+0.
60I(OH5max)=4mA(2)5.
0VVSSVSS+0.
25I(OL5max)=12mA(3)VSSVSS+0.
6020MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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5kbetweenVCCandVSSisusedasload.
Theoutputisconnectedtothecentertapofthedivider.
(2)Theoutputvoltagereachesatleast10%and90%VCCatthespecifiedtogglefrequency.
5.
15OutputFrequency–PortsP1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINMAXUNITfPx.
yPortoutputfrequency(withload)PJ.
0/SMCLKCL=20pF,RL=1k(1)(2)VCC=1.
8V,PMMCOREVx=016MHzVCC=3V,PMMCOREVx=325fPort_CLKClockoutputfrequencyPJ.
3/ACLKPJ.
0/SMCLKPJ.
1/MCLKCL=20pF(2)VCC=1.
8V,PMMCOREVx=016MHzVCC=3V,PMMCOREVx=325(1)Aresistivedividerwith2*0.
5kbetweenVCCandVSSisusedasload.
Theoutputisconnectedtothecentertapofthedivider.
(2)Theoutputvoltagereachesatleast10%and90%VCCatthespecifiedtogglefrequency.
5.
16OutputFrequency–PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINMAXUNITfPx.
yPortoutputfrequency(withload)P1.
6portmapperSMCLKfromP3.
4,CL=20pF,RL=1k(1)(2)VCC=1.
8V,VIO=1.
8V,PMMCOREVx=016MHzVCC=3V,VIO=3V,PMMCOREVx=325VCC=3V,VIO=5V,PMMCOREVx=325fPort_CLKClockoutputfrequencyP1.
6portmapperSMCLKfromP3.
4,CL=20pF(2)VCC=1.
8V,VIO=1.
8V,PMMCOREVx=016MHzVCC=3V,VIO=3V,PMMCOREVx=325VCC=3V,VIO=5V,PMMCOREVx=32521MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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17TypicalCharacteristics–Outputs,ReducedDriveStrength(PxDS.
y=0),PortsP1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)Figure5-2.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-3.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-4.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltageFigure5-5.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltage22MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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18TypicalCharacteristics–Outputs,FullDriveStrength(PxDS.
y=1),PortsP1.
0toP1.
5,P3.
2toP3.
7,PJ.
0toPJ.
6overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)Figure5-6.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-7.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-8.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltageFigure5-9.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltage23MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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19TypicalCharacteristics–Outputs,ReducedDriveStrength(PxDS.
y=0),PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)Figure5-10.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-11.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-12.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-13.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltage24MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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y=0),PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1(continued)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)Figure5-14.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltageFigure5-15.
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20TypicalCharacteristics–Outputs,FullDriveStrength(PxDS.
y=1),PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)Figure5-16.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-17.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-18.
TypicalLow-LevelOutputCurrentvsLow-LevelOutputVoltageFigure5-19.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltage26MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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y=1),PortsP1.
6andP1.
7,P2.
0toP2.
7,P3.
0andP3.
1(continued)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)Figure5-20.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltageFigure5-21.
TypicalHigh-LevelOutputCurrentvsHigh-LevelOutputVoltage27MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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21CrystalOscillator,XT1,Low-FrequencyModeoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITIDVCC.
LFDifferentialXT1oscillatorcrystalcurrentconsumptionfromlowestdrivesetting,LFmodefOSC=32768Hz,XTS=0,XT1BYPASS=0,XT1DRIVEx=1,TA=25°C3V0.
075AfOSC=32768Hz,XTS=0,XT1BYPASS=0,XT1DRIVEx=2,TA=25°C0.
170fOSC=32768Hz,XTS=0,XT1BYPASS=0,XT1DRIVEx=3,TA=25°C0.
290fXT1,LF0XT1oscillatorcrystalfrequency,LFmodeXTS=0,XT1BYPASS=032768HzfXT1,LF,SWXT1oscillatorlogic-levelsquare-waveinputfrequency,LFmodeXTS=0,XT1BYPASS=11032.
76850kHzOALFOscillationallowanceforLFcrystalsXTS=0,XT1BYPASS=0,XT1DRIVEx=0,fXT1,LF=32768Hz,CL,eff=6pF210kXTS=0,XT1BYPASS=0,XT1DRIVEx=1,fXT1,LF=32768Hz,CL,eff=12pF300CL,effIntegratedeffectiveloadcapacitance,LFmodeXTS=0,XCAPx=01pFXTS=0,XCAPx=15.
5XTS=0,XCAPx=28.
5XTS=0,XCAPx=312.
0Dutycycle,LFmodeXTS=0,MeasuredatACLK,fXT1,LF=32768Hz30%70%fFault,LFOscillatorfaultfrequency,LFmodeXTS=01010000HztSTART,LFStart-uptime,LFmodefOSC=32768Hz,XTS=0,XT1BYPASS=0,XT1DRIVEx=0,TA=25°C,CL,eff=12pF3V1000msfOSC=32768Hz,XTS=0,XT1BYPASS=0,XT1DRIVEx=3,TA=25°C,CL,eff=12pF50028MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131SpecificationsCopyright2010–2018,TexasInstrumentsIncorporated(1)ToimproveEMIontheXT1oscillatorthefollowingguidelinesshouldbeobserved.
Keepthetracesbetweenthedeviceandthecrystalasshortaspossible.
Designagoodgroundplanearoundtheoscillatorpins.
PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT.
AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins.
UseassemblymaterialsandprocessesthatavoidanyparasiticloadontheoscillatorXINandXOUTpins.
Ifconformalcoatingisused,makesurethatitdoesnotinducecapacitiveorresistiveleakagebetweentheoscillatorpins.
(2)Maximumfrequencyofoperationoftheentiredevicecannotbeexceeded.
(3)WhenXT1BYPASSisset,theVLO,REFO,XT1circuitsareautomaticallypowereddown.
(4)Oscillationallowanceisbasedonasafetyfactorof5forrecommendedcrystals.
(5)Includesparasiticbondandpackagecapacitance(approximately2pFperpin).
BecausethePCBaddsadditionalcapacitance,verifythecorrectloadbymeasuringtheACLKfrequency.
Foracorrectsetup,theeffectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal.
(6)Requiresexternalcapacitorsatbothterminals.
Valuesarespecifiedbycrystalmanufacturers.
5.
22CrystalOscillator,XT1,High-FrequencyMode(1)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITIDVCC,HFDifferentialXT1oscillatorcrystalcurrentconsumptionfromlowestdrivesetting,HFmodefOSC=4MHz,XTS=1,XOSCOFF=0,XT1BYPASS=0,XT1DRIVEx=0,TA=25°C200AfOSC=12MHz,XTS=1,XOSCOFF=0,XT1BYPASS=0,XT1DRIVEx=1,TA=25°C3V260fOSC=20MHz,XTS=1,XOSCOFF=0,XT1BYPASS=0,XT1DRIVEx=2,TA=25°C325fOSC=32MHz,XTS=1,XOSCOFF=0,XT1BYPASS=0,XT1DRIVEx=3,TA=25°C450fXT1,HF0XT1oscillatorcrystalfrequency,HFmode0XTS=1,XT1BYPASS=0,XT1DRIVEx=0(2)48MHzfXT1,HF1XT1oscillatorcrystalfrequency,HFmode1XTS=1,XT1BYPASS=0,XT1DRIVEx=1(2)816MHzfXT1,HF2XT1oscillatorcrystalfrequency,HFmode2XTS=1,XT1BYPASS=0,XT1DRIVEx=2(2)1624MHzfXT1,HF3XT1oscillatorcrystalfrequency,HFmode3XTS=1,XT1BYPASS=0,XT1DRIVEx=3(2)2432MHzfXT1,HF,SWXT1oscillatorlogic-levelsquare-waveinputfrequency,HFmodeXTS=1,XT1BYPASS=1(3)(2)0.
732MHzOAHFOscillationallowanceforHFcrystals(4)XTS=1,XT1BYPASS=0,XT1DRIVEx=0,fXT1,HF=6MHz,CL,eff=15pF450ΩXTS=1,XT1BYPASS=0,XT1DRIVEx=1,fXT1,HF=12MHz,CL,eff=15pF320XTS=1,XT1BYPASS=0,XT1DRIVEx=2,fXT1,HF=20MHz,CL,eff=15pF200XTS=1,XT1BYPASS=0,XT1DRIVEx=3,fXT1,HF=32MHz,CL,eff=15pF200tSTART,HFStart-uptime,HFmodefOSC=6MHz,XTS=1,XT1BYPASS=0,XT1DRIVEx=0,TA=25°C,CL,eff=15pF3V0.
5msfOSC=20MHz,XTS=1,XT1BYPASS=0,XT1DRIVEx=2,TA=25°C,CL,eff=15pF0.
3CL,effIntegratedeffectiveloadcapacitance,HFmode(5)(6)XTS=11pF29MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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FrequenciesabovetheMAXspecificationdonotsetthefaultflag.
FrequenciesbetweentheMINandMAXspecificationsmightsettheflag.
(8)Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals.
Dutycycle,HFmodeXTS=1,MeasuredatACLK,fXT1,HF2=20MHz40%50%60%fFault,HFOscillatorfaultfrequency,HFmode(7)XTS=1(8)30300kHz(1)Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(85°C–(–40°C)).
Thecoefficientisnegative.
(2)Calculatedusingtheboxmethod:(MAX(1.
8Vto3.
6V)–MIN(1.
8Vto3.
6V))/MIN(1.
8Vto3.
6V)/(3.
6V–1.
8V).
Thecoefficientispositive.
5.
23InternalVery-Low-PowerLow-FrequencyOscillator(VLO)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITfVLOVLOfrequencyMeasuredatACLK1.
8Vto3.
6V69.
414kHzdfVLO/dTVLOfrequencytemperaturedriftMeasuredatACLK(1)1.
8Vto3.
6V0.
5%/°CdfVLO/dVCCVLOfrequencysupplyvoltagedriftMeasuredatACLK(2)1.
8Vto3.
6V4%/VDutycycleMeasuredatACLK1.
8Vto3.
6V40%50%60%(1)Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(85°C–(–40°C))(2)Calculatedusingtheboxmethod:(MAX(1.
8Vto3.
6V)–MIN(1.
8to3.
6V))/MIN(1.
8Vto3.
6V)/(3.
6V–1.
8V)5.
24InternalReference,Low-FrequencyOscillator(REFO)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITIREFOREFOoscillatorcurrentconsumptionTA=25°C1.
8Vto3.
6V3AfREFOREFOfrequencycalibratedMeasuredatACLK1.
8Vto3.
6V32768HzREFOabsolutetolerancecalibratedFulltemperaturerange1.
8Vto3.
6V±3.
5%TA=25°C3V±1.
5%dfREFO/dTREFOfrequencytemperaturedriftMeasuredatACLK(1)1.
8Vto3.
6V0.
01%/°CdfREFO/dVCCREFOfrequencysupplyvoltagedriftMeasuredatACLK(2)1.
8Vto3.
6V1.
0%/VDutycycleMeasuredatACLK1.
8Vto3.
6V40%50%60%tSTARTREFOstart-uptime40%/60%dutycycle1.
8Vto3.
6V25s30MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131SpecificationsCopyright2010–2018,TexasInstrumentsIncorporated(1)WhenselectingtheproperDCOfrequencyrange(DCORSELx),thetargetDCOfrequency,fDCO,shouldbesettoresidewithintherangeoffDCO(n,0),MAX≤fDCO≤fDCO(n,31),MIN,wherefDCO(n,0),MAXrepresentsthemaximumfrequencyspecifiedfortheDCOfrequency,rangen,tap0(DCOx=0)andfDCO(n,31),MINrepresentstheminimumfrequencyspecifiedfortheDCOfrequency,rangen,tap31(DCOx=31).
ThisensuresthatthetargetDCOfrequencyresideswithintherangeselected.
ItshouldalsobenotedthatiftheactualfDCOfrequencyfortheselectedrangecausestheFLLortheapplicationtoselecttap0or31,theDCOfaultflagissettoreportthattheselectedrangeisatitsminimumormaximumtapsetting.
5.
25DCOFrequencyoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-22)PARAMETERTESTCONDITIONSMINTYPMAXUNITfDCO(0,0)DCOfrequency(0,0)(1)DCORSELx=0,DCOx=0,MODx=00.
070.
20MHzfDCO(0,31)DCOfrequency(0,31)(1)DCORSELx=0,DCOx=31,MODx=00.
701.
70MHzfDCO(1,0)DCOfrequency(1,0)(1)DCORSELx=1,DCOx=0,MODx=00.
150.
38MHzfDCO(1,31)DCOfrequency(1,31)(1)DCORSELx=1,DCOx=31,MODx=01.
473.
45MHzfDCO(2,0)DCOfrequency(2,0)(1)DCORSELx=2,DCOx=0,MODx=00.
320.
75MHzfDCO(2,31)DCOfrequency(2,31)(1)DCORSELx=2,DCOx=31,MODx=03.
177.
38MHzfDCO(3,0)DCOfrequency(3,0)(1)DCORSELx=3,DCOx=0,MODx=00.
641.
51MHzfDCO(3,31)DCOfrequency(3,31)(1)DCORSELx=3,DCOx=31,MODx=06.
0714.
0MHzfDCO(4,0)DCOfrequency(4,0)(1)DCORSELx=4,DCOx=0,MODx=01.
33.
2MHzfDCO(4,31)DCOfrequency(4,31)(1)DCORSELx=4,DCOx=31,MODx=012.
328.
2MHzfDCO(5,0)DCOfrequency(5,0)(1)DCORSELx=5,DCOx=0,MODx=02.
56.
0MHzfDCO(5,31)DCOfrequency(5,31)(1)DCORSELx=5,DCOx=31,MODx=023.
754.
1MHzfDCO(6,0)DCOfrequency(6,0)(1)DCORSELx=6,DCOx=0,MODx=04.
610.
7MHzfDCO(6,31)DCOfrequency(6,31)(1)DCORSELx=6,DCOx=31,MODx=039.
088.
0MHzfDCO(7,0)DCOfrequency(7,0)(1)DCORSELx=7,DCOx=0,MODx=08.
519.
6MHzfDCO(7,31)DCOfrequency(7,31)(1)DCORSELx=7,DCOx=31,MODx=060135MHzSDCORSELFrequencystepbetweenrangeDCORSELandDCORSEL+1SRSEL=fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)1.
22.
4ratioSDCOFrequencystepbetweentapDCOandDCO+1SDCO=fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)1.
021.
12ratioDutycycleMeasuredatSMCLK40%50%60%dfDCO/dTDCOfrequencytemperaturedriftfDCO=1MHz,VCORE=1.
2V,2.
0V0.
1%/°CdfDCO/dVCOREDCOfrequencyvoltagedriftfDCO=1MHz1.
9%/VFigure5-22.
TypicalDCOFrequency31MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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26PMM,BrownoutReset(BOR)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITV(DVCC_BOR_IT-)BORHonvoltage,DVCCfallingleveldDVCC/dt5VV(DVCC_BOR_IT+)BORHoffvoltage,DVCCrisingleveldDVCC/dt50VV(DVCC_BOR_hys)BORHhysteresis40275mVV(VCORE_BOR_IT-)BORLonvoltage,VCOREfallinglevelDVCC=1.
8Vto3.
6V0.
690.
87VV(VCORE_BOR_IT+)BORLoffvoltage,VCORErisinglevelDVCC=1.
8Vto3.
6V0.
831.
05VV(VCORE_BOR_hys)BORLhysteresis60200mVtdBORBORLresetreleasetime2000stRESETPulsedurationrequiredatRST/NMIpintoacceptareset2s5.
27PMM,CoreVoltageoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITVCORE3(AM)Corevoltage,activemode,PMMCOREV=32.
4V≤DVCC≤3.
6V,0mA≤I(VCORE)≤25mA1.
90VVCORE2(AM)Corevoltage,activemode,PMMCOREV=22.
2V≤DVCC≤3.
6V,0mA≤I(VCORE)≤21mA1.
80VVCORE1(AM)Corevoltage,activemode,PMMCOREV=12.
0V≤DVCC≤3.
6V,0mA≤I(VCORE)≤17mA1.
60VVCORE0(AM)Corevoltage,activemode,PMMCOREV=01.
8V≤DVCC≤3.
6V,0mA≤I(VCORE)≤13mA1.
40VVCORE3(LPM)Corevoltage,activemode,PMMCOREV=32.
4V≤DVCC≤3.
6V,0mA≤I(VCORE)≤30A1.
94VVCORE2(LPM)Corevoltage,low-currentmode,PMMCOREV=22.
2V≤DVCC≤3.
6V,0A≤I(VCORE)≤30A1.
84VVCORE1(LPM)Corevoltage,low-currentmode,PMMCOREV=12.
0V≤DVCC≤3.
6V,0A≤I(VCORE)≤30A1.
64VVCORE0(LPM)Corevoltage,low-currentmode,PMMCOREV=01.
8V≤DVCC≤3.
6V,0A≤I(VCORE)≤30A1.
44V32MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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28PMM,SVSHighSideoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITI(SVSH)SVScurrentconsumptionSVSHE=0,DVCC=3.
6V0nASVSHE=1,DVCC=3.
6V,SVSHFP=0200SVSHE=1,DVCC=3.
6V,SVSHFP=12AV(SVSH_IT–)SVSHonvoltagelevelSVSHE=1,SVSHRVL=01.
591.
641.
69VSVSHE=1,SVSHRVL=11.
791.
841.
91SVSHE=1,SVSHRVL=21.
982.
042.
11SVSHE=1,SVSHRVL=32.
102.
162.
23V(SVSH_IT+)SVSHoffvoltagelevelSVSHE=1,SVSMHRRL=01.
621.
741.
81VSVSHE=1,SVSMHRRL=11.
881.
942.
01SVSHE=1,SVSMHRRL=22.
072.
142.
21SVSHE=1,SVSMHRRL=32.
202.
262.
33SVSHE=1,SVSMHRRL=42.
322.
402.
48SVSHE=1,SVSMHRRL=52.
562.
702.
84SVSHE=1,SVSMHRRL=62.
853.
003.
15SVSHE=1,SVSMHRRL=72.
853.
003.
15tpd(SVSH)SVSHpropagationdelaySVSHE=1,dVDVCC/dt=10mV/s,SVSHFP=12.
5sSVSHE=1,dVDVCC/dt=±1mV/s,SVSHFP=025t(SVSH)SVSHonoroffdelaytimeSVSHE=0→1,SVSHFP=112.
5sSVSHE=0→1,SVSHFP=0100dVDVCC/dtDVCCrisetime01000V/s33MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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29PMM,SVMHighSideoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITI(SVMH)SVMHcurrentconsumptionSVMHE=0,DVCC=3.
6V0nASVMHE=1,DVCC=3.
6V,SVMHFP=0200SVMHE=1,DVCC=3.
6V,SVMHFP=12.
0AV(SVMH)SVMHonoroffvoltagelevelSVMHE=1,SVSMHRRL=01.
651.
741.
86VSVMHE=1,SVSMHRRL=11.
851.
942.
02SVMHE=1,SVSMHRRL=22.
022.
142.
22SVMHE=1,SVSMHRRL=32.
182.
262.
35SVMHE=1,SVSMHRRL=42.
322.
402.
48SVMHE=1,SVSMHRRL=52.
562.
702.
84SVMHE=1,SVSMHRRL=62.
853.
003.
15SVMHE=1,SVSMHRRL=72.
853.
003.
15SVMHE=1,SVMHOVPE=13.
75tpd(SVMH)SVMHpropagationdelaySVMHE=1,dVDVCC/dt=10mV/s,SVMHFP=12.
5sSVMHE=1,dVDVCC/dt=1mV/s,SVMHFP=020st(SVMH)SVMHonoroffdelaytimeSVMHE=0→1,SVSHFP=112.
5sSVMHE=0→1,SVSHFP=01005.
30PMM,SVSLowSideoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITI(SVSL)SVSLcurrentconsumptionSVSLE=0,PMMCOREV=20nASVSLE=1,PMMCOREV=2,SVSLFP=0200SVSLE=1,PMMCOREV=2,SVSLFP=12.
0At(SVSL)SVSLonoroffdelaytimeSVSLE=1,dVCORE/dt=10mV/s,SVSLFP=16sSVSLE=1,dVCORE/dt=1mV/s,SVSLFP=050tpd(SVSL)SVSLpropagationdelaySVMHE=0→1,SVSLFP=112.
5sSVMHE=0→1,SVSLFP=01005.
31PMM,SVMLowSideoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITI(SVML)SVMLcurrentconsumptionSVMLE=0,PMMCOREV=20nASVMLE=1,PMMCOREV=2,SVMLFP=0200SVMLE=1,PMMCOREV=2,SVMLFP=12.
0Atpd(SVML)SVMLpropagationdelaySVMLE=1,dVCORE/dt=10mV/s,SVMLFP=12.
5sSVMLE=1,dVCORE/dt=1mV/s,SVMLFP=030t(SVML)SVMLonoroffdelaytimeSVMLE=0→1,SVSLFP=112.
5sSVMLE=0→1,SVSLFP=010034MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131SpecificationsCopyright2010–2018,TexasInstrumentsIncorporated(1)Thisvaluerepresentsthetimefromthewake-upeventtothefirstactiveedgeofMCLK.
Thewake-uptimedependsontheperformancemodeofthelow-sidesupervisor(SVSL)andlow-sidemonitor(SVML).
tWAKE-UP-FASTispossiblewithSVSLandSVMLinfullperformancemodeordisabled.
Forspecificregistersettings,seetheLow-SideSVSandSVMControlandPerformanceModeSelectionsectioninthePowerManagementModuleandSupplyVoltageSupervisorchapteroftheMSP430x5xxandMSP430x6xxFamilyUser'sGuide.
(2)Thisvaluerepresentsthetimefromthewake-upeventtothefirstactiveedgeofMCLK.
Thewake-uptimedependsontheperformancemodeofthelow-sidesupervisor(SVSL)andlow-sidemonitor(SVML).
tWAKE-UP-SLOWissetwithSVSLandSVMLinnormalmode(lowcurrentmode).
Forspecificregistersettings,seetheLow-SideSVSandSVMControlandPerformanceModeSelectionsectioninthePowerManagementModuleandSupplyVoltageSupervisorchapteroftheMSP430x5xxandMSP430x6xxFamilyUser'sGuide.
(3)Thewake-uptimesfromLPM0andLPM1toAMarenotspecified.
TheyareproportionaltoMCLKcycletimebutarenotaffectedbytheperformancemodesettingsasforLPM2,LPM3,andLPM4.
(4)Thisvaluerepresentsthetimefromthewake-upeventtotheresetvectorexecution.
5.
32Wake-upTimesFromLow-PowerModesoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITtFAST-WAKE-UPWake-uptimefromLPM2,LPM3,orLPM4toactivemode(1)PMMCOREVx=SVSMLRRLx=n(wheren=0,1,2,or3),SVSLFP=1fMCLK≥4MHz36.
5s1MHz50165stWAKE-UPLPM5Wake-uptimefromLPM4.
5toactivemode(4)23mstWAKE-UP-RESETWake-uptimefromRSTorBOReventtoactivemode(4)23ms5.
33Timer_Aoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINMAXUNITfTATimer_AinputclockfrequencyInternal:SMCLKorACLK,External:TACLK,Dutycycle=50%±10%1.
8V,3V25MHztTA,capTimer_AcapturetimingAllcaptureinputs,minimumpulsedurationrequiredforcapture.
1.
8V,3V20ns(1)TheDCOwake-uptimemustbeconsideredinLPM3andLPM4.
Thewake-uptimemustbeconsideredinLPMx.
5.
5.
34USCI(UARTMode)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITfUSCIUSCIinputclockfrequencyInternal:SMCLKorACLK,External:UCLK,Dutycycle=50%±10%fSYSTEMMHzfmax,BITCLKMaximumBITCLKclockfrequency(equalsbaudrateinMBaud)(1)1MHztτUARTreceivedeglitchtime2.
2V50150200ns3V5015020035MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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(2)SpecifiesthetimetodrivethenextvaliddatatotheSIMOoutputaftertheoutputchangingUCLKclockedge.
SeethetimingdiagramsinFigure5-23andFigure5-24.
(3)SpecifieshowlongdataontheSIMOoutputisvalidaftertheoutputchangingUCLKclockedge.
NegativevaluesindicatethatthedataontheSIMOoutputcanbecomeinvalidbeforetheoutputchangingclockedgeobservedonUCLK.
SeethetimingdiagramsinFigure5-23andFigure5-24.
5.
35USCI(SPIMasterMode)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(seeFigure5-23andFigure5-24)PARAMETERTESTCONDITIONSVCCMINMAXUNITfUSCIUSCIinputclockfrequencySMCLKorACLK,Dutycycle=50%±10%fSYSTEMMHztSU,MISOMIinputdatasetuptimePMMCOREV=01.
8V55ns3V38PMMCOREV=32.
4V303V25tHD,MISOMIinputdataholdtimePMMCOREV=01.
8V0ns3V0PMMCOREV=32.
4V03V0tVALID,MOSIMOoutputdatavalidtime(2)UCLKedgetoSIMOvalid,CL=20pF,PMMCOREV=01.
8V20ns3V18UCLKedgetoSIMOvalid,CL=20pF,PMMCOREV=32.
4V163V15tHD,MOSIMOoutputdataholdtime(3)CL=20pF,PMMCOREV=01.
8V–10ns3V–8CL=20pF,PMMCOREV=32.
4V–103V–836MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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SPIMasterMode,CKPH=0Figure5-24.
SPIMasterMode,CKPH=137MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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(2)SpecifiesthetimetodrivethenextvaliddatatotheSOMIoutputaftertheoutputchangingUCLKclockedge.
SeethetimingdiagramsinFigure5-25andFigure5-26.
(3)SpecifieshowlongdataontheSOMIoutputisvalidaftertheoutputchangingUCLKclockedge.
SeethetimingdiagramsinFigure5-25andFigure5-26.
5.
36USCI(SPISlaveMode)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(seeFigure5-25andFigure5-26)PARAMETERTESTCONDITIONSVCCMINMAXUNITtSTE,LEADSTEleadtime,STElowtoclockPMMCOREV=01.
8V11ns3V8PMMCOREV=32.
4V73V6tSTE,LAGSTElagtime,LastclocktoSTEhighPMMCOREV=01.
8V3ns3V3PMMCOREV=32.
4V33V3tSTE,ACCSTEaccesstime,STElowtoSOMIdataoutPMMCOREV=01.
8V66ns3V50PMMCOREV=32.
4V363V30tSTE,DISSTEdisabletime,STEhightoSOMIhighimpedancePMMCOREV=01.
8V30ns3V23PMMCOREV=32.
4V163V13tSU,SISIMOinputdatasetuptimePMMCOREV=01.
8V5ns3V5PMMCOREV=32.
4V23V2tHD,SISIMOinputdataholdtimePMMCOREV=01.
8V5ns3V5PMMCOREV=32.
4V53V5tVALID,SOSOMIoutputdatavalidtime(2)UCLKedgetoSOMIvalid,CL=20pF,PMMCOREV=01.
8V76ns3V60UCLKedgetoSOMIvalid,CL=20pF,PMMCOREV=32.
4V443V40tHD,SOSOMIoutputdataholdtime(3)CL=20pF,PMMCOREV=01.
8V18ns3V12CL=20pF,PMMCOREV=32.
4V103V838MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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SPISlaveMode,CKPH=0Figure5-26.
SPISlaveMode,CKPH=139MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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37USCI(I2CMode)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-27)PARAMETERTESTCONDITIONSVCCMINMAXUNITfUSCIUSCIinputclockfrequencyInternal:SMCLKorACLK,External:UCLK,Dutycycle=50%±10%fSYSTEMMHzfSCLSCLclockfrequency2.
2V,3V0400kHztHD,STAHoldtime(repeated)STARTfSCL≤100kHz2.
2V,3V4.
0sfSCL>100kHz0.
6tSU,STASetuptimeforarepeatedSTARTfSCL≤100kHz2.
2V,3V4.
7sfSCL>100kHz0.
6tHD,DATDataholdtime2.
2V,3V0nstSU,DATDatasetuptime2.
2V,3V250nstSU,STOSetuptimeforSTOPfSCL≤100kHz2.
2V,3V4.
0sfSCL>100kHz0.
6tSPPulsedurationofspikessuppressedbyinputfilter2.
2V50600ns3V50600Figure5-27.
I2CModeTiming40MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131SpecificationsCopyright2010–2018,TexasInstrumentsIncorporated(1)TheleakagecurrentisdefinedintheleakagecurrenttablewithP6.
x/Axparameter.
(2)TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeVR+toVR–forvalidconversionresults.
Theexternalreferencevoltagerequiresdecouplingcapacitors.
Twodecouplingcapacitors,10Fand100nF,shouldbeconnectedtoVEREFtodecouplethedynamiccurrentrequiredforanexternalreferencesourceifitisusedfortheADC10_A.
AlsoseetheMSP430x5xxandMSP430x6xxFamilyUser'sGuide.
5.
3810-BitADC,PowerSupplyandInputRangeConditions(MSP430F51x2DevicesOnly)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITAVCCAnalogsupplyvoltageAVCCandDVCCareconnectedtogether,AVSSandDVSSareconnectedtogether,V(AVSS)=V(DVSS)=0V1.
83.
6VV(Ax)Analoginputvoltagerange(2)AllADC10_Apins:P1.
0toP1.
5andP3.
6andP3.
7terminals0AVCCVIADC10_AOperatingsupplycurrentintoAVCCterminal,REFmoduleandreferencebufferofffADC10CLK=5MHz,ADC10ON=1,REFON=0,SHT0=0,SHT1=0,ADC10DIV=0,ADC10SREF=002.
2V6090A3V75100OperatingsupplycurrentintoAVCCterminal,REFmoduleon,referencebufferonfADC10CLK=5MHz,ADC10ON=1,REFON=1,SHT0=0,SHT1=0,ADC10DIV=0,ADC10SREF=013V113130OperatingsupplycurrentintoAVCCterminal,REFmoduleoff,referencebufferonfADC10CLK=5MHz,ADC10ON=1,REFON=0,SHT0=0,SHT1=0,ADC10DIV=0,ADC10SREF=10,VEREF=2.
5V3V105125OperatingsupplycurrentintoAVCCterminal,REFmoduleoff,referencebufferofffADC10CLK=5MHz,ADC10ON=1,REFON=0,SHT0=0,SHT1=0,ADC10DIV=0,ADC10SREF=11,VEREF=2.
5V3V7095CIInputcapacitanceOnlyoneterminalAxcanbeselectedatonetimefromthepadtotheADC10_Acapacitorarrayincludingwiringandpad2.
2V3.
5pFRIInputMUXONresistanceAVCC>2.
0V,0V≤VAx≤AVCC36k1.
8V5LSB.
Thereferenceandinputsignalarealreadysettled.
(3)ApproximatelyeightTau(τ)arerequiredforanerroroflessthan±0.
5LSB5.
3910-BitADC,TimingParameters(MSP430F51x2DevicesOnly)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITfADC10CLKForspecifiedperformanceofADC10_Alinearityparameters2.
2V,3V0.
4555.
5MHzfADC10OSCInternalADC10_Aoscillator(1)ADC10DIV=0,fADC10CLK=fADC10OSC2.
2V,3V4.
24.
85.
4MHztCONVERTConversiontimeREFON=0,Internaloscillator,12ADC10CLKcycles,10-bitmode,fADC10OSC=4MHzto5MHz2.
2V,3V2.
43.
0sExternalfADC10CLKfromACLK,MCLKorSMCLK,ADC10SSEL≠012*1/fADC10CLKtADC10ONTurnonsettlingtimeoftheADCSee(2)100nstSampleSamplingtimeRS=1000,RI=96k,CI=3.
5pF(3)1.
8V3sRS=1000,RI=36k,CI=3.
5pF(3)3V141MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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5.
4010-BitADC,LinearityParameters(MSP430F51x2DevicesOnly)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITEIIntegrallinearityerror1.
4V≤(VEREF+–VEREF-)≤1.
6V,CVEREF+=20pF±1.
0LSB1.
6V5Gainerror,internalreferenceSee(1)±1.
5%VREFETTotalunadjustederror,internalreferenceSee(1)±1.
5%VREF(1)TheexternalreferenceisusedduringADCconversiontochargeanddischargethecapacitancearray.
Theinputcapacitance,CI,isalsothedynamicloadforanexternalreferenceduringconversion.
Thedynamicimpedanceofthereferencesupplyshouldfollowtherecommendationsonanalog-sourceimpedancetoallowthechargetosettlefor10-bitaccuracy.
(2)Theaccuracylimitstheminimumpositiveexternalreferencevoltage.
Lowerreferencevoltagelevelsmaybeappliedwithreducedaccuracyrequirements.
(3)Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.
Higherreferencevoltagelevelsmaybeappliedwithreducedaccuracyrequirements.
(4)Theaccuracylimitsminimumexternaldifferentialreferencevoltage.
Lowerdifferentialreferencevoltagelevelsmaybeappliedwithreducedaccuracyrequirements.
(5)Twodecouplingcapacitors,10Fand100nF,shouldbeconnectedtoVEREFtodecouplethedynamiccurrentrequiredforanexternalreferencesourceifitisusedfortheADC10_A.
AlsoseetheMSP430x5xxandMSP430x6xxFamilyUser'sGuide.
5.
41REF,ExternalReference(MSP430F51x2DevicesOnly)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITVEREF+PositiveexternalreferencevoltageinputVEREF+>VEREF-(2)1.
4AVCCVVEREF-NegativeexternalreferencevoltageinputVEREF+>VEREF-(3)01.
2VVEREF+–VEREF-DifferentialexternalreferencevoltageinputVEREF+>VEREF-(4)1.
4AVCCVI(VEREF+),I(VEREF-)Staticinputcurrent1.
4V≤VEREF+≤V(AVCC),VEREF-=0V,fADC10CLK=5MHz,ADC10SHTx=0x0001,Conversionrate200ksps2.
2V,3V±8.
5±26A1.
4V≤VEREF+≤V(AVCC),VEREF-=0V,fADC10CLK=5MHZ,ADC10SHTX=0x1000,Conversionrate20ksps2.
2V,3V±1C(VEREF+/-)CapacitanceatVEREF+andVEREF-terminalsSee(5)10F42MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131SpecificationsCopyright2010–2018,TexasInstrumentsIncorporated(1)TheleakagecurrentisdefinedintheleakagecurrenttablewithP6.
x/Axparameter.
(2)TheinternalreferencecurrentissuppliedthroughtheAVCCterminal.
ConsumptionisindependentoftheADC10ONcontrolbit,unlessaconversionisactive.
TheREFONbitenablestosettlethebuilt-inreferencebeforestartinganA/Dconversion.
(3)Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)).
(4)ThesensorcurrentISENSORisconsumedif(ADC10ON=1andREFON=1)or(ADC10ON=1andINCH=0Ahandsamplesignalishigh).
WhenREFON=1,ISENSORisalreadyincludedinIREF+.
(5)Thetemperaturesensoroffsetcanbeasmuchas±20°C.
TIrecommendsasingle-pointcalibrationtominimizetheoffseterrorofthebuilt-intemperaturesensor.
(6)Thetypicalequivalentimpedanceofthesensoris51k.
Thesampletimerequiredincludesthesensor-ontimetSENSOR(on).
(7)Theon-timetVMID(on)isincludedinthesamplingtimetVMID(sample);noadditionalontimeisneeded.
(8)TheconditionisthattheerrorinaconversionstartedaftertREFONislessthan±0.
5LSB.
5.
42REF,Built-InReference(MSP430F51x2DevicesOnly)overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITVREF+Positivebuilt-inreferencevoltageREFVSEL={2}for2.
5V,REFON=13V2.
51±1.
5%VREFVSEL={1}for2.
0V,REFON=13V1.
99±1.
5%REFVSEL={0}for1.
5V,REFON=12.
2V,3V1.
5±1.
5%AVCC(min)AVCCminimumvoltage,Positivebuilt-inreferenceactiveREFVSEL={0}for1.
5V1.
8VREFVSEL={1}for2.
0V2.
3REFVSEL={2}for2.
5V2.
8IREF+OperatingsupplycurrentintoAVCCterminal(2)fADC10CLK=5MHz,REFON=1,REFBURST=0,REFVSEL={0}for1.
5V3V15.
519AfADC10CLK=5MHz,REFON=1,REFBURST=0,REFVSEL={1}for2.
0V3V1824fADC10CLK=5MHz,REFON=1,REFBURST=0,REFVSEL={2}for2.
5V3V2130TCREF+Temperaturecoefficientofbuilt-inreference(3)REFVSEL={0,1,2},REFON=13050ppm/°CISENSOROperatingsupplycurrentintoAVCCterminal(4)REFON=1,INCH=0Ah,ADC10ON=1,TA=30°C2.
2V150180A3V150190VSENSORSee(5)REFON=1,INCH=0Ah,ADC10ON=1,TA=30°C2.
2V765mV3V765VMIDAVCCdivideratchannel11ADC10ON=1,INCH=0Bh,VMID≈0.
5*VAVCC2.
2V1.
061.
11.
14V3V1.
461.
51.
54tSENSOR(sample)Sampletimerequiredifchannel10isselected(6)ADC10ON=1,INCH=0Ah,Errorofconversionresult≤1LSB30stVMID(sample)Sampletimerequiredifchannel11isselected(7)ADC10ON=1,INCH=0Bh,Errorofconversionresult≤1LSB1sPSRR_DCPowersupplyrejectionratio(DC)AVCC=AVCC(min)toAVCC(max),TA=25°C,REFVSEL={0,1,2},REFON=1120300V/VPSRR_ACPowersupplyrejectionratio(AC)AVCC=AVCC(min)toAVCC(max),TA=25°C,f=1kHz,ΔVpp=100mV,REFVSEL={0,1,2},REFON=16.
4mV/VtSETTLESettlingtimeofreferencevoltage(8)AVCC=AVCC(min)toAVCC(max),REFVSEL={0,1,2},REFON=0→1TA=–40°Cto85°C23125sTA=25°C2350TA=85°C162543MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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43Comparator_Boverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITVCCSupplyvoltage1.
83.
6VIAVCC_COMPComparatoroperatingsupplycurrentintoAVCC,ExcludesreferenceresistorladderCBPWRMD=00,CBON=1,CBRSx=001.
8V38A2.
2V31383V3239CBPWRMD=01,CBON=1,CBRSx=002.
2V,3V1017CBPWRMD=10,CBON=1,CBRSx=002.
2V,3V0.
20.
85VREFReferencevoltagelevelCBREFLx=01,CBREFACC=0≥1.
8V1.
421.
441.
46VCBREFLx=10,CBREFACC=0≥2.
2V1.
891.
921.
95CBREFLx=11,CBREFACC=0≥3.
0V2.
352.
392.
43IAVCC_REFQuiescentcurrentofresistorladderintoAVCC,IncludingREFmodulecurrentCBREFACC=1,CBREFLx=01,CBRSx=10,REFON=0,CBON=02.
2V,3V1017ACBREFACC=0,CBREFLx=01,CBRSx=10,REFON=0,CBON=02.
2V,3V3340VICCommonmodeinputrange0VCC–1VVOFFSETInputoffsetvoltageCBPWRMD=00±20mVCBPWRMD=01,10±10CINInputcapacitance5pFRSINSeriesinputresistanceOn(switchclosed)34kOff(switchopened)50MtPDPropagationdelay,responsetimeCBPWRMD=00,CBF=0450nsCBPWRMD=01,CBF=0600CBPWRMD=10,CBF=050stPD,filterPropagationdelaywithfilteractiveCBPWRMD=00,CBON=1,CBF=1,CBFDLY=000.
350.
61.
5sCBPWRMD=00,CBON=1,CBF=1,CBFDLY=010.
61.
01.
8CBPWRMD=00,CBON=1,CBF=1,CBFDLY=101.
01.
83.
4CBPWRMD=00,CBON=1,CBF=1,CBFDLY=111.
83.
46.
5tEN_CMPComparatorenabletimeCBON=0→1,CBPWRMD=00or0112sCBON=0→1,CBPWRMD=10100tEN_REFResistorreferenceenabletimeCBON=0toCBON=11.
01.
5sTCCB_REFTemperaturecoefficientreferenceofVCB_REF50ppm/°CVCB_REFReferencevoltageforagiventapVIN=referenceintoresistorladder,n=0to31VIN*(n+0.
5)/32VIN*(n+1)/32VIN*(n+1.
5)/32V44MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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x/Axparameter.
5.
44Timer_D,PowerSupplyandReferenceClockoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)PARAMETERTESTCONDITIONSVCCMINTYPMAXUNITDVCCDigitalsupplyvoltageV(DVSS)=0V1.
83.
6VfREF,DCOTimer_DinputreferenceclockfrequencyPMMCOREVx=01.
8V≤VCC≤3.
6V812.
0MHzPMMCOREVx=12.
0V≤VCC≤3.
6V816.
0PMMCOREVx=22.
2V≤VCC≤3.
6V820.
0PMMCOREVx=32.
4V≤VCC≤3.
6V825.
5I(64MHz)I(DVCC)at64-MHzTimer_Dclock,clockgeneratoronlyfreference=8MHz,MCx=0,TDHREGEN=1,TDHMx=0,TDHCLKCR=0253320AI(128MHz)I(DVCC)at128-MHzTimer_Dclock,clockgeneratoronlyfreference=16MHz,MCx=0,TDHREGEN=1,TDHMx=0,TDHCLKCR=0285360AI(200MHz)I(DVCC)at200-MHzTimer_Dclock,clockgeneratoronlyfreference=25MHz,MCx=0,TDHREGEN=1,TDHMx=0,TDHCLKCR=1280345AI(256MHz)I(DVCC)at256-MHzTimer_Dclock,clockgeneratoronlyfreference=16MHz,MCx=0,TDHREGEN=1,TDHMx=1,TDHCLKCR=1265330AI(0,16,64)I(DVCC)TDHCLKRx=0,TDHCLKSRx=16,TDHCLKTRIM=642.
2V244A3.
0V295325I(1,16,64)I(DVCC)TDHCLKRx=1,TDHCLKSRx=16,TDHCLKTRIM=642.
2V282A3.
0V300400I(2,16,64)I(DVCC)TDHCLKRx=2,TDHCLKSRx=16,TDHCLKTRIM=642.
2V358A3.
0V41447045MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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45Timer_D,LocalClockGeneratorFrequencyoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITfHRCG(0,0,64)HRCGfrequency(0,0,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=0,TDHCLKTRIM=64395673MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=0,TDHCLKTRIM=6478112146fHRCG(0,7,64)HRCGfrequency(0,7,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=7,TDHCLKTRIM=64466686MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=7,TDHCLKTRIM=6492132172fHRCG(0,15,64)HRCGfrequency(0,15,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=15,TDHCLKTRIM=645578101MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=15,TDHCLKTRIM=64110156202fHRCG(0,23,64)HRCGfrequency(0,23,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=23,TDHCLKTRIM=646187113MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=23,TDHCLKTRIM=64122174226fHRCG(0,31,0)HRCGfrequency(0,31,0)TDHREGEN=0,TDHMx=0,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=31,TDHCLKTRIM=0365673MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=31,TDHCLKTRIM=072112146fHRCG(0,31,64)HRCGfrequency(0,31,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=31,TDHCLKTRIM=646898128MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=31,TDHCLKTRIM=64136196256fHRCG(0,31,127)HRCGfrequency(0,31,127)TDHREGEN=0,TDHMx=0,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=31,TDHCLKTRIM=12797138180MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=1,TDHCLKRx=0,TDHCLKSRx=31,TDHCLKTRIM=127196176360fHRCG(1,0,64)HRCGfrequency(1,0,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=0,TDHCLKTRIM=6471101131MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=0,TDHCLKTRIM=64142202262fHRCG(1,7,64)HRCGfrequency(1,7,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=7,TDHCLKTRIM=6484120156MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=7,TDHCLKTRIM=64168240312fHRCG(1,15,64)HRCGfrequency(1,15,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=15,TDHCLKTRIM=6497139182MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=15,TDHCLKTRIM=64196278364fHRCG(1,23,64)HRCGfrequency(1,23,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=23,TDHCLKTRIM=64108154200MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=23,TDHCLKTRIM=64216308400fHRCG(1,31,0)HRCGfrequency(1,31,0)TDHREGEN=0,TDHMx=0,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=31,TDHCLKTRIM=06897126MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=31,TDHCLKTRIM=0136194252fHRCG(1,31,64)HRCGfrequency(1,31,64)TDHREGEN=0,TDHMx=0,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=31,TDHCLKTRIM=64123175227MHzTDHREGEN=0,TDHMx=1,TDHCLKCR=0,TDHCLKRx=1,TDHCLKSRx=31,TDHCLKTRIM=6424635045446MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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16fHRCG=8,16,or25MHz,TDHREGEN=10dfHRCG/dVDVCCHRCGfrequencyvoltagedriftfHRCG=8,16,or25MHz,TDHREGEN=005%/VfHRCG=8,16,or25MHz,TDHREGEN=10tSETTLESettlingtimeTDHEN=0→1,TDHFW=0359sSettlingtime,fastwake-upTDHEN=0→1,TDHFW=11.
55.
46Timer_D,TrimmedClockFrequenciesoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITFrequencytoleranceduringtrimming–0.
5%+0.
5%fTRIM(64MHz)TDHMx=0,TDHREGEN=0,TDHCLKCR=0,TDHxCTL1=TDHxCTL1_64TA=25°C,VCC=1.
8V636465MHzfTRIM(128MHz)TDHMx=0,TDHREGEN=0,TDHCLKCR=1,TDHxCTL1=TDHxCTL1_128TA=25°C,VCC=2.
0V126128130MHzfTRIM(200MHz)TDHMx=0,TDHREGEN=0,TDHCLKCR=1,TDHxCTL1=TDHxCTL1_200TA=25°C,VCC=2.
4V197200203MHzfTRIM(256MHz)TDHMx=1,TDHREGEN=0,TDHCLKCR=1,TDHxCTL1=TDHxCTL1_256TA=25°C,VCC=2.
2V250256262MHz5.
47Timer_D,FrequencyMultiplicationModeoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITExternalfrequencytolerance0%E(TDHREGEN=1,64)freference=8MHz,TDHMx=0,TDHREGEN=1,TDHCLKCR=0,TDHCLKRx=0TA=25°C,VCC=1.
8V–1%+1%E(TDHREGEN=1,128)freference=16MHz,TDHMx=0,TDHREGEN=1,TDHCLKCR=1,TDHCLKRx=0TA=25°C,VCC=2.
0V–1%+1%E(TDHREGEN=1,200)freference=25MHz,TDHMx=0,TDHREGEN=1,TDHCLKCR=1,TDHCLKRx=0TA=25°C,VCC=2.
4V–1%+1%E(TDHREGEN=1,256)freference=16MHz,TDHMx=1,TDHREGEN=1,TDHCLKCR=1,TDHCLKRx=0TA=25°C,VCC=2.
2V–1%+1%48MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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48Timer_D,InputCaptureandOutputCompareTimingoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITtTD,capTimer_Dinputcapturetiming,minimumpulsedurationtotriggerinputcaptureeventfMAX=262MHz4nstTD0,cap,matchingTimer0_Dinputcapturetiming,matchingbetweeninputcapturechannelsP1.
6toP1.
7andP2.
0fMAX=262MHz12LSBTimer0_Dinputcapturetiming,matchingbetweeninputcapturechannels.
P2.
4toP2.
5andP2.
6fMAX=262MHz34tTD1,cap,matchingTimer1_Dinputcapturetiming,matchingbetweeninputcapturechannelsP2.
1toP2.
2andP2.
3fMAX=262MHz23LSBTimer1_Dinputcapturetiming,matchingbetweeninputcapturechannels.
P2.
7toP3.
0andP3.
1fMAX=262MHz24tTD01,cap,matchingTimer0_DandTimer1_Dinputcapturetiming,matchingbetweeninputcapturechannels.
Timer0_Disthehigh-resolutionclockgeneratorsource.
fMAX=262MHz48LSBtTD0,comp,matchingTimer0_Doutputcomparetiming,matchingbetweenoutputcapturecomparechannelsforpinsP1.
6,P1.
7,andP2.
0Risingedges,fMAX=262MHz4nsFallingedges,fMAX=262MHz4Risingandfallingedges,fMAX=262MHz8tTD1,comp,matchingTimer1_Doutputcomparetiming,matchingbetweenoutputcapturecomparechannelsforpinsP2.
1,P2.
2,andP2.
3Risingedges,fMAX=262MHz4nsFallingedges,fMAX=262MHz4Risingandfallingedges,fMAX=262MHz8tTD01,comp,matchingTimer0_DandTimer1_Doutputcomparetiming,matchingbetweenoutputcomparechannels.
Timer0_Disthehigh-resolutionclockgeneratorsourceAlledges,fMAX=262MHz8LSB49MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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Thisparameterappliestoallprogrammingmethods:individualwordorbytewriteandblockwritemodes.
(2)Thesevaluesarehardwiredintothestatemachineoftheflashcontroller.
5.
49FlashMemoryoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERTJMINTYPMAXUNITDVCC(PGM/ERASE)Programanderasesupplyvoltage1.
83.
6VIPGMSupplycurrentfromDVCCduringprogram35mAIERASESupplycurrentfromDVCCduringerase26.
5mAIMERASE,IBANKSupplycurrentfromDVCCduringmasseraseorbankerase26.
5mAtCPTCumulativeprogramtime(1)16msProgramanderaseendurance104105cyclestRetentionDataretentionduration25°C100yearstWordWordorbyteprogramtime(2)6485stBlock,0Blockprogramtimeforfirstbyteorword(2)4965stBlock,1–(N–1)Blockprogramtimeforeachadditionalbyteorword,exceptforlastbyteorword(2)3749stBlock,NBlockprogramtimeforlastbyteorword(2)5573stMassEraseMasserasetime(2)2332mstSegEraseSegmenterasetime(2)2332msfMCLK,MGRMCLKfrequencyinmarginalreadmode(FCLK4.
MGR0=1orFCTL4.
MGR1=1)01MHz(1)ToolsthataccesstheSpy-Bi-WireinterfacemustwaitfortheminimumtSBW,EntimeafterpullingtheTEST/SBWTCKpinhighbeforeapplyingthefirstSBWTCKclockedge.
(2)fTCKmayberestrictedtomeetthetimingrequirementsofthemoduleselected.
5.
50JTAGandSpy-Bi-WireInterfaceoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)PARAMETERVCCMINTYPMAXUNITfSBWSpy-Bi-Wireinputfrequency2.
2V,3V020MHztSBW,LowSpy-Bi-Wirelowclockpulseduration2.
2V,3V0.
02515stSBW,EnSpy-Bi-Wireenabletime(TESThightoacceptanceoffirstclockedge)(1)2.
2V,3V1stSBW,RstSpy-Bi-Wirereturntonormaloperationtime15100sfTCKTCKinputfrequency,4-wireJTAG(2)2.
2V05MHz3V010RinternalInternalpulldownresistanceonTEST2.
2V,3V456080k50MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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1CPUTheMSP430CPUhasa16-bitRISCarchitecturethatishighlytransparenttotheapplication.
Alloperations,otherthanprogram-flowinstructions,areperformedasregisteroperationsinconjunctionwithsevenaddressingmodesforsourceoperandandfouraddressingmodesfordestinationoperand.
TheCPUisintegratedwith16registersthatprovidereducedinstructionexecutiontime.
Theregister-to-registeroperationexecutiontimeisonecycleoftheCPUclock.
Fouroftheregisters,R0toR3,arededicatedasprogramcounter,stackpointer,statusregister,andconstantgenerator,respectively.
Theremainingregistersaregeneral-purposeregisters(seeFigure6-1).
PeripheralsareconnectedtotheCPUusingdata,address,andcontrolbuses.
Peripheralscanbemanagedwithallinstructions.
Figure6-1.
IntegratedCPURegisters51MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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2InstructionSetTheinstructionsetconsistsoftheoriginal51instructionswiththreeformatsandsevenaddressmodesandadditionalinstructionsfortheexpandedaddressrange.
Eachinstructioncanoperateonwordandbytedata.
Table6-1listsexamplesofthethreetypesofinstructionformats;Table6-2liststheaddressmodes.
Table6-1.
InstructionWordFormatsFORMATEXAMPLEOPERATIONDualoperands,source-destinationADDR4,R5R4+R5→R5Singleoperands,destinationonlyCALLR8PC→(TOS),R8→PCRelativejump,un/conditionalJNEJump-on-equalbit=0(1)S=source,D=destinationTable6-2.
AddressModeDescriptionsADDRESSMODES(1)D(1)SYNTAXEXAMPLEOPERATIONRegister++MOVRs,RdMOVR10,R11R10→R11Indexed++MOVX(Rn),Y(Rm)MOV2(R5),6(R6)M(2+R5)→M(6+R6)Symbolic(PCrelative)++MOVEDE,TONIM(EDE)→M(TONI)Absolute++MOV&MEM,&TCDATM(MEM)→M(TCDAT)Indirect+MOV@Rn,Y(Rm)MOV@R10,Tab(R6)M(R10)→M(Tab+R6)Indirectautoincrement+MOV@Rn+,RmMOV@R10+,R11M(R10)→R11R10+2→R10Immediate+MOV#X,TONIMOV#45,TONI#45→M(TONI)52MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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3OperatingModesTheMSP430hasoneactivemodeandsixsoftware-selectablelow-powermodesofoperation.
Aninterrupteventcanwakeupthedevicefromanyofthefivelow-powermodes,servicetherequest,andrestorebacktothelow-powermodeonreturnfromtheinterruptprogram.
Softwarecanconfigurethefollowingoperatingmodes:Activemode(AM)–AllclocksareactiveLow-powermode0(LPM0)–CPUisdisabled–ACLKandSMCLKremainactive–MCLKisdisabled–FLLloopcontrolremainsactiveLow-powermode1(LPM1)–CPUisdisabled–FLLloopcontrolisdisabled–ACLKandSMCLKremainactive–MCLKisdisabledLow-powermode2(LPM2)–CPUisdisabled–MCLK,FLLloopcontrol,andDCOCLKaredisabled–DCgeneratoroftheDCOremainsenabled–ACLKremainsactiveLow-powermode3(LPM3)–CPUisdisabled–MCLK,FLLloopcontrol,andDCOCLKaredisabled–DCgeneratoroftheDCOisdisabled–ACLKremainsactiveLow-powermode4(LPM4)–CPUisdisabled–ACLKisdisabled–MCLK,FLLloopcontrol,andDCOCLKaredisabled–DCgeneratoroftheDCOisdisabled–Crystaloscillatorisstopped–CompletedataretentionLow-powermode5(LPM4.
5)–Internalregulatordisabled–Nodataretention–Wake-upinputfromRST/NMI,P1,andP253MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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(Non)maskable:theindividualinterruptenablebitcandisableaninterruptevent,butthegeneralinterruptenablebitcannotdisableit.
(3)Interruptflagsareinthemodule.
(4)Reservedinterruptvectorsataddressesarenotusedinthisdeviceandcanbeusedforregularprogramcodeifnecessary.
Tomaintaincompatibilitywithotherdevices,TIrecommendsreservingtheselocations.
6.
4InterruptVectorAddressesTheinterruptvectorsandthepower-upstartaddressareintheaddressrange0FFFFhto0FF80h(seeTable6-3).
Thevectorcontainsthe16-bitaddressoftheappropriateinterrupt-handlerinstructionsequence.
Table6-3.
InterruptSources,Flags,andVectorsINTERRUPTSOURCEINTERRUPTFLAGSYSTEMINTERRUPTWORDADDRESSPRIORITYSystemResetPowerupExternalresetWatchdogtime-out,keyviolationFlashmemorykeyviolationWDTIFG,KEYV(SYSRSTIV)(1)(2)Reset0FFFEh63,highestSystemNMIPMMVacantmemoryaccessJTAGmailboxSVMLIFG,SVMHIFG,DLYLIFG,DLYHIFG,VLRLIFG,VLRHIFG,VMAIFG,JMBNIFG,JMBOUTIFG(SYSSNIV)(1)(Non)maskable0FFFCh62UserNMINMIOscillatorfaultFlashmemoryaccessviolationNMIIFG,OFIFG,ACCVIFG(SYSUNIV)(1)(2)(Non)maskable0FFFAh61Comp_BCBIIFG,CBIFG(CBIV)(1)(3)Maskable0FFF8h60TEC0TEC0FLTIFG,TEC0EXCLRIFG,TEC0AXCLRIFG(1)(3)Maskable0FFF6h59TD0TD0CCR0CCIFG0(3)Maskable0FFF4h58TD0TD0CCR1CCIFG1,.
.
.
TD0CCR2CCIFG2,TD0IFG,TD0HFLIFG,TD0HFHIFG,TD0HLKIFG,TD0HUNLKIFG(TD0IV)(1)(3)Maskable0FFF2h57WatchdogTimer_AintervaltimermodeWDTIFGMaskable0FFF0h56USCI_A0receiveortransmitUCA0RXIFG,UCA0TXIFG(UCA0IV)(1)(3)Maskable0FFEEh55USCI_B0receiveortransmitUCB0RXIFG,UCB0TXIFG,I2CStatusInterruptFlags(UCB0IV)(1)(3)Maskable0FFECh54ADC10_A(MSP430F51x2only)ADC10IFG0,ADC10INIFG,ADC10LOIFG,ADC10HIIFG,ADC10TOVIFG,ADC10OVIFG(ADC10IV)(1)(3)Maskable0FFEAh53TA0TA0CCR0CCIFG0(3)Maskable0FFE8h52TA0TA0CCR1CCIFG1.
.
.
TA0CCR2CCIFG2,TA0IFG(TA0IV)(1)(3)Maskable0FFE6h51DMADMA0IFG,DMA1IFG,DMA2IFG(DMAIV)(1)(3)Maskable0FFE4h50TEC1TEC1FLTIFG,TEC1EXCLRIFG,TEC1AXCLRIFG(1)(3)Maskable0FFE249TD1TD1CCR0CCIFG0(3)Maskable0FFE0h48TD1TD1CCR1CCIFG1.
.
.
TD1CCR2CCIFG2,TD1IFG,TD1HFLIFG,TD1HFHIFG,TD1HLKIFG,TD1HUNLKIFG(TD1IV)(1)(3)Maskable0FFDEh47I/OportP1P1IFG.
0toP1IFG.
7(P1IV)(1)(3)Maskable0FFDCh46I/OportP2P2IFG.
0toP2IFG.
7(P2IV)(1)(3)Maskable0FFDAh45ReservedReserved(4)0FFD8h440FF80h0,lowest54MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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5MemoryOrganizationTable6-4summarizesthememorymapofalldevices.
Table6-4.
MemoryOrganizationMSP430F5132,MSP430F5131MSP430F5152,MSP430F5151MSP430F5172,MSP430F5171MemoryMain:interruptvectorMain:codememorySizeFlashFlash8KB00FFFFh–00FF80h00FFFFh–00E000h16KB00FFFFh–00FF80h00FFFFh–00C000h32KB00FFFFh–00FF80h00FFFFh–008000hRAMSize1KB2KB2KBSector0001FFFh–001C00h0023FFh–001C00h0023FFh–001C00hInformationmemory(Flash)Size512Byte512Byte512ByteInfoA128B0019FFh–001980h128B0019FFh–001980h128B0019FFh–001980hInfoB128B00197Fh–001900h128B00197Fh–001900h128B00197Fh–001900hInfoC128B0018FFh–001880h128B0018FFh–001880h128B0018FFh–001880hInfoD128B00187Fh–001800h128B00187Fh–001800h128B00187Fh–001800hBootloader(BSL)memorySize2K2KB2KBBSL3512B0017FFh–001600h512B0017FFh–001600h512B0017FFh–001600hBSL2512B0015FFh–001400h512B0015FFh–001400h512B0015FFh–001400hBSL1512B0013FFh–001200h512B0013FFh–001200h512B0013FFh–001200hBSL0512B0011FFh–001000h512B0011FFh–001000h512B0011FFh–001000hPeripheralsSizeFlash4KB000FFFh–000000h4KB000FFFh–000000h4KB000FFFh–000000h6.
6Bootloader(BSL)TheBSLletsusersprogramtheflashmemoryorRAMusingaUARTserialinterface.
AccesstothedevicememorybytheBSLisprotectedbyuser-definedpassword.
AbootloadersecuritykeyisprovidedtodisabletheBSLcompletelyortodisabletheerasureoftheflashifaninvalidpasswordissupplied.
ForcompletedescriptionofthefeaturesoftheBSLanditsimplementation,seeMSP430ProgrammingWiththeBootloader(BSL).
Table6-5liststhepinsrequiredforBSLaccess.
Table6-5.
BSLFunctionsBSLFUNCTIONDESCRIPTION40-PINQFNRSBPACKAGE38-PINTSSOPDAPACKAGE40-PINDSBGAYFFPACKAGERST/NMI/SBWTDIOEntrysequencesignalEntrysequencesignalEntrysequencesignalTEST/SBWTCKEntrysequencesignalEntrysequencesignalEntrysequencesignalDatatransmitP3.
7-36P3.
5-37P3.
7-B4DatareceiveP3.
6-35P3.
6-38P3.
6-A4VCCPowersupplyPowersupplyPowersupplyVSSGroundsupplyGroundsupplyGroundsupply55MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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7FlashMemoryTheflashmemorycanbeprogrammedthroughtheJTAGport,Spy-Bi-Wire(SBW),theBSL,orinsystembytheCPU.
TheCPUcanperformsingle-byte,single-word,andlong-wordwritestotheflashmemory.
Featuresoftheflashmemoryinclude:Flashmemoryhasnsegmentsofmainmemoryandfoursegmentsofinformationmemory(AtoD)of128byteseach.
Eachsegmentinmainmemoryis512bytesinsize.
Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased.
SegmentsAtoDcanbeerasedindividually,orasagroupwithsegments0ton.
SegmentsAtoDarealsocalledinformationmemory.
SegmentAcanbelockedseparately.
6.
8RAMTheRAMismadeupofnsectors.
Eachsectorcanbecompletelypowereddowntosaveleakage;however,alldataislost.
FeaturesoftheRAMinclude:RAMhasnsectors.
ThesizeofasectorcanbefoundinSection6.
5.
Eachsector0toncanbecompletedisabled;however,dataretentionislost.
Eachsector0tonautomaticallyenterslow-powerretentionmodewhenpossible.
6.
9PeripheralsPeripheralsareconnectedtotheCPUthroughdata,address,andcontrolbuses.
Theperipheralscanbemangedusingallinstructions.
Forcompletemoduledescriptions,seetheMSP430x5xxandMSP430x6xxFamilyUser'sGuide.
6.
9.
1DigitalI/OUptothree8-bitI/Oportsareimplemented.
PortPJcontainssevenindividualI/Opins,commontoalldevices.
AllindividualI/Obitsareindependentlyprogrammable.
Anycombinationofinput,output,andinterruptconditionsispossible.
Programmablepulluporpulldownonallports.
Programmabledrivestrengthonallports.
All8bitsofportsP1andP2supportedge-selectableinterruptinput.
Readandwriteaccesstoport-controlregistersissupportedbyallinstructions.
Portscanbeaccessedbyte-wise.
P1andP2canalsobeaccessedword-wise(PA).
TheinputandoutputvoltagelevelsofthepinssuppliedbyDVIO(seeTable4-1)aredefinedbythevoltagesuppliedbyDVIO(upto5V).
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Theportmappingregistersareonly5bitswide,andtheupperbitsareignored,whichresultsinareadoutvalueof31.
6.
9.
2PortMappingControllerTheportmappingcontrollerallowstheflexibleandreconfigurablemappingofdigitalfunctionstoPortP1,PortP2,andPortP3(seeTable6-6).
Table6-6.
PortMappingMnemonicsandFunctionsVALUEPxMAPyMNEMONICINPUTPINFUNCTIONOUTPUTPINFUNCTION0PM_NONENoneDVSS1PM_UCA0CLKUSCI_A0clockinput/output(directioncontrolledbyUSCI)PM_UCB0STEUSCI_B0SPIslavetransmitenable(directioncontrolledbyUSCI)2PM_UCA0TXDUSCI_A0UARTTXD(DirectioncontrolledbyUSCI–output)PM_UCA0SIMOUSCI_A0SPIslaveinmasterout(directioncontrolledbyUSCI)3PM_UCB0SOMIUSCI_B0SPIslaveoutmasterin(directioncontrolledbyUSCI)PM_UCB0SCLUSCI_B0I2Cclock(opendrainanddirectioncontrolledbyUSCI)4PM_UCA0RXDUSCI_A0UARTRXD(DirectioncontrolledbyUSCI–input)PM_UCA0SOMIUSCI_A0SPIslaveoutmasterin(directioncontrolledbyUSCI)5PM_UCB0SIMOUSCI_B0SPIslaveinmasterout(directioncontrolledbyUSCI)PM_UCB0SDAUSCI_B0I2Cdata(opendrainanddirectioncontrolledbyUSCI)6PM_UCB0CLKUSCI_B0clockinput/output(directioncontrolledbyUSCI)PM_UCA0STEUSCI_A0SPIslavetransmitenable(directioncontrolledbyUSCI)7PM_TD0.
0TD0inputcapturechannel0TD0outputcomparechannel08PM_TD0.
1TD0inputcapturechannel1TD0outputcomparechannel19PM_TD0.
2TD0inputcapturechannel2TD0outputcomparechannel210PM_TD1.
0TD1inputcapturechannel0TD1outputcomparechannel011PM_TD1.
1TD1inputcapturechannel1TD1outputcomparechannel112PM_TD1.
2TD1inputcapturechannel2TD1outputcomparechannel213PM_CLR1TD0.
0TD0externalclearinputTD0outputcomparechannel0PM_FLT1_2TD0.
0TD0faultinputchannel214PM_FLT1_0TD0.
1TD0faultinputchannel0TD0outputcomparechannel115PM_FLT1_1TD0.
2TD0faultinputchannel1TD0outputcomparechannel216PM_CLR2TD1.
0TD1externalclearinput(controlledbymoduleinputenable)TD1outputcomparechannel0PM_FLT2_1TD1.
0TD1faultinputchannel1(controlledbymoduleinputenable)17PM_FLT2_2TD1.
1TD1faultinputchannel2TD1outputcomparechannel118PM_FLT2_0TD1.
2TD1faultinputchannel0TD1outputcomparechannel219PM_TD0.
0SMCLKTD0inputcapturechannel0SMCLKoutput20PM_TA0CLKCBOUTTA0inputclockComparator_Boutput21PM_TD0CLKMCLKTD0inputclockMCLKoutput22PM_TA0_0TA0inputcapturechannel0TA0outputcomparechannel023PM_TA0_1TA0inputcapturechannel1TA0outputcomparechannel124PM_TA0_2TA0inputcapturechannel2TA0outputcomparechannel225PM_DMAE0SMCLKDMAE0inputSMCLKoutput26PM_DMAE1MCLKDMAE1inputMCLKoutput27PM_DMAE2SVMDMAE2inputSVMoutput28PM_TD0OUTHTD03-stateinputADC10CLK29PM_TD1OUTHTD13-stateinputACLK30ReservedNoneDVSS31(0FFh)(1)PM_ANALOGDisablestheoutputdriverandtheinputSchmitt-triggertopreventparasiticcrosscurrentswhenapplyinganalogsignals.
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Table6-7.
DefaultMappingPINPxMAPyMNEMONICINPUTPINFUNCTIONOUTPUTPINFUNCTIONP1.
0/PM_UCA0CLK/PM_UCB0STE/A0/CB0PM_UCA0CLKPM_UCB0STEUSCI_A0clockinput/output(directioncontrolledbyUSCI)USCI_B0SPIslavetransmitenable(directioncontrolledbyUSCI)P1.
1/PM_UCA0TXD/PM_UCA0SIMO/A1/CB1PM_UCA0TXDPM_UCA0SIMOUSCI_A0UARTTXD(DirectioncontrolledbyUSCI–output)USCI_A0SPIslaveinmasterout(directioncontrolledbyUSCI)P1.
2/PM_UCA0RXD/PM_UCA0SOMI/A2/CB2PM_UCA0RXDPM_UCA0SOMIUSCI_A0UARTRXD(DirectioncontrolledbyUSCI–input)USCI_A0SPIslaveoutmasterin(directioncontrolledbyUSCI)P1.
3/PM_UCB0CLK/PM_UCA0STE/A3/CB3PM_UCB0CLKPM_UCA0STEUSCI_B0clockinput/output(directioncontrolledbyUSCI)USCI_A0SPIslavetransmitenable(directioncontrolledbyUSCI)P1.
4/PM_UCB0SIMO/PM_UCB0SDA/A4/CB4PM_UCB0SIMOPM_UCB0SDAUSCI_B0SPIslaveinmasterout(directioncontrolledbyUSCI)USCI_B0I2Cdata(opendrainanddirectioncontrolledbyUSCI)P1.
5/PM_UCB0SOMI/PM_UCB0SCL/A5/CB5PM_UCB0SOMIPM_UCB0SCLUSCI_B0SPIslaveoutmasterin(directioncontrolledbyUSCI)USCI_B0I2Cclock(opendrainanddirectioncontrolledbyUSCI)P1.
6/PM_TD0.
0PM_TD0.
0TD0inputcapturechannel0TD0outputcomparechannel0P1.
7/PM_TD0.
1PM_TD0.
1TD0inputcapturechannel1TD0outputcomparechannel1P2.
0/PM_TD0.
2PM_TD0.
2TD0inputcapturechannel2TD0outputcomparechannel2P2.
1/PM_TD1.
0PM_TD1.
0TD1inputcapturechannel0TD1outputcomparechannel0P2.
2/PM_TD1.
1PM_TD1.
1TD1inputcapturechannel1TD1outputcomparechannel1P2.
3/PM_TD1.
2PM_TD1.
2TD1inputcapturechannel2TD1outputcomparechannel2P2.
4/PM_TEC0CLR/PM_TEC0FLT2/PM_TD0.
0PM_CLR1TD0.
0PM_FLT1_2TD0.
0TD0externalclearinput(controlledbymoduleinputenable)TD0faultinputchannel2(controlledbymoduleinputenable)TD0outputcomparechannel0P2.
5/PM_TEC0FLT0/PM_TD0.
1PM_FLT1_0TD0.
1TD0faultinputchannel0TD0outputcomparechannel1P2.
6/PM_TEC0FLT1/PM_TD0.
2PM_FLT1_1TD0.
2TD0faultinputchannel1TD0outputcomparechannel2P2.
7/PM_TEC1CLR/PM_TEC1FLT1/PM_TD1.
0PM_CLR2TD1.
0PM_FLT2_1TD1.
0TD1externalclearinput(controlledbymoduleinputenable)TD1faultinputchannel1(controlledbymoduleinputenable)TD1outputcomparechannel0P3.
0/PM_TEC1FLT2/PM_TD1.
1PM_FLT2_2TD1.
1TD1faultinputchannel2TD1outputcomparechannel1P3.
1/PM_TEC1FLT0/PM_TD1.
2PM_FLT2_0TD1.
2TD1faultinputchannel0TD1outputcomparechannel2P3.
2/PM_TD0.
0/PM_SMCLK/CB14PM_TD0.
0SMCLKTD0inputcapturechannel0SMCLKoutputP3.
3/PM_TA0CLK/PM_CBOUT/CB13PM_TA0CLKCBOUTTA0inputclockComparator_BoutputP3.
4/PM_TD0CLK/PM_MCLKPM_TD0CLKMCLKTD0inputclockMCLKoutputP3.
5/PM_TA0.
2/VEREF+/CB12PM_TA3_2TA0inputcapturechannel0TA0outputcomparechannel0P3.
6/PM_TA0.
1/A7VEREF-/CB11PM_TA3_1TA0inputcapturechannel1TA0outputcomparechannel1P3.
7/PM_TA0.
0/A6/CB10PM_TA3_0TA0inputcapturechannel2TA0outputcomparechannel258MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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9.
3OscillatorandSystemClockTheclocksystem(UnifiedClockSystem[UCS])moduleincludessupportfora32-kHzwatchcrystaloscillatorandhigh-frequencycrystaloscillator,aninternalvery-low-powerlow-frequencyoscillator(VLO),aninternaltrimmedlow-frequencyoscillator(REFO),andanintegratedinternaldigitallycontrolledoscillator(DCO).
TheUCSmoduleisdesignedtomeettherequirementsofbothlowsystemcostandlowpowerconsumption.
TheUCSmodulefeaturesdigitalfrequencylockedloop(FLL)hardwarethat,inconjunctionwithadigitalmodulator,stabilizestheDCOfrequencytoaprogrammablemultipleofthewatchcrystalfrequency.
TheinternalDCOprovidesafastturnonclocksourceandstabilizesinlessthan5s.
TheUCSmoduleprovidesthefollowingclocksignals:Auxiliaryclock(ACLK),sourcedfroma32-kHzwatchcrystalorhigh-frequencycrystal(XT1),theinternallow-frequencyoscillator(VLO),thetrimmedlow-frequencyoscillator(REFO),ortheinternaldigitally-controlledoscillatorDCO.
Mainclock(MCLK),thesystemclockusedbytheCPU.
MCLKcanbesourcedbysamesourcesavailabletoACLK.
Sub-Mainclock(SMCLK),thesubsystemclockusedbytheperipheralmodules.
SMCLKcanbesourcedbysamesourcesavailabletoACLK.
ACLK/n,thebufferedoutputofACLK,ACLK/2,ACLK/4,ACLK/8,ACLK/16,ACLK/32.
6.
9.
4Power-ManagementModule(PMM)ThePMMincludesanintegratedvoltageregulatorthatsuppliesthecorevoltagetothedeviceandcontainsprogrammableoutputlevelstoprovideforpoweroptimization.
ThePMMalsoincludessupplyvoltagesupervisor(SVS)andsupplyvoltagemonitoring(SVM)circuitry,andbrownoutprotection.
Thebrownoutcircuitprovidestheproperinternalresetsignaltothedeviceduringpoweronandpoweroff.
TheSVSandSVMcircuitrydetectsifthesupplyvoltagedropsbelowauser-selectablelevelandsupportsbothsupplyvoltagesupervision(thedeviceisautomaticallyreset)andsupplyvoltagemonitoring(thedeviceisnotautomaticallyreset).
SVSandSVMcircuitryisavailableontheprimarysupplyandcoresupply.
6.
9.
5HardwareMultiplierThemultiplicationoperationissupportedbyadedicatedperipheralmodule.
Themoduleperformsoperationswith32-,24-,16-,and8-bitoperands.
Themodulesupportssignedandunsignedmultiplicationaswellassignedandunsignedmultiplyandaccumulateoperations.
6.
9.
6WatchdogTimer(WDT_A)Theprimaryfunctionofthewatchdogtimer(WDT_A)moduleistoperformacontrolledsystemrestartafterasoftwareproblemoccurs.
Iftheselectedtimeintervalexpires,asystemresetisgenerated.
Ifthewatchdogfunctionisnotneededinanapplication,themodulecanbeconfiguredasanintervaltimerandcangenerateinterruptsatselectedtimeintervals.
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9.
7SystemModule(SYS)TheSYSmodulehandlesmanyofthesystemfunctionswithinthedevice.
Theseincludepower-onresetandpower-upclearhandling,NMIsourceselectionandmanagement,resetinterruptvectorgenerators,bootloaderentrymechanisms,andconfigurationmanagement(devicedescriptors)(seeTable6-8).
ItalsoincludesadataexchangemechanismusingJTAGthatiscalledaJTAGmailboxandthatcanbeusedintheapplication.
Table6-8.
SystemModuleInterruptVectorRegistersINTERRUPTVECTORREGISTERINTERRUPTEVENTWORDADDRESSOFFSETPRIORITYSYSRSTIV,SystemResetNointerruptpending019Eh00hBrownout(BOR)02hHighestRST/NMI(POR)04hPMMSWBOR(BOR)06hLPM5wake-up(BOR)08hSecurityviolation(BOR)0AhSVSL(POR)0ChSVSH(POR)0EhSVML_OVP(POR)10hSVMH_OVP(POR)12hPMMSWPOR(POR)14hWDTtime-out(PUC)16hWDTkeyviolation(PUC)18hKEYVflashkeyviolation(PUC)1AhReserved1ChPeripheralareafetch(PUC)1EhPMMkeyviolation(PUC)20hReserved22hto3EhLowestSYSSNIV,SystemNMINointerruptpending019Ch00hSVMLIFG02hHighestSVMHIFG04hDLYLIFG06hDLYHIFG08hVMAIFG0AhJMBINIFG0ChJMBOUTIFG0EhVLRLIFG10hVLRHIFG12hReserved14hto1EhLowestSYSUNIV,UserNMINointerruptpending019Ah00hNMIIFG02hHighestOFIFG04hACCVIFG06hReserved08hto1EhLowest60MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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9.
8DMAControllerTheDMAcontrollerallowsmovementofdatafromonememoryaddresstoanotherwithoutCPUintervention.
Forexample,theDMAcontrollercanbeusedtomovedatafromtheADC10_AconversionmemorytoRAM.
UsingtheDMAcontrollercanincreasethethroughputofperipheralmodules.
TheDMAcontrollerreducessystempowerconsumptionbyallowingtheCPUtoremaininsleepmode,withouthavingtowaketomovedatatoorfromaperipheral.
Table6-9liststhetriggersthatcanbeassignedtostartaDMAtransfer.
(1)ReservedDMAtriggersmaybeusedbyotherdevicesinthefamily.
ReservedDMAtriggersdonotcauseanyDMAtriggereventwhenselected.
Table6-9.
DMATriggerAssignments(1)TRIGGERCHANNEL0120DMAREQDMAREQDMAREQ1TA0CCR0CCIFGTA0CCR0CCIFGTA0CCR0CCIFG2TA0CCR2CCIFGTA0CCR2CCIFGTA0CCR2CCIFG3TD0CCR0CCIFGTD0CCR0CCIFGTD0CCR0CCIFG4TD0CCR2CCIFGTD0CCR2CCIFGTD0CCR2CCIFG5TD1CCR0CCIFGTD1CCR0CCIFGTD1CCR0CCIFG6TD1CCR2CCIFGTD1CCR2CCIFGTD1CCR2CCIFG7ReservedReservedReserved8ReservedReservedReserved9ReservedReservedReserved10ReservedReservedReserved11ReservedReservedReserved12ReservedReservedReserved13ReservedReservedReserved14ReservedReservedReserved15ReservedReservedReserved16UCA0RXIFGUCA0RXIFGUCA0RXIFG17UCA0TXIFGUCA0TXIFGUCA0TXIFG18UCB0RXIFGUCB0RXIFGUCB0RXIFG19UCB0TXIFGUCB0TXIFGUCB0TXIFG20ReservedReservedReserved21ReservedReservedReserved22ReservedReservedReserved23ReservedReservedReserved24ADC10IFG0ADC10IFG0ADC10IFG025ReservedReservedReserved26ReservedReservedReserved27ReservedReservedReserved28ReservedReservedReserved29MPYreadyMPYreadyMPYready30DMA2IFGDMA0IFGDMA1IFG31DMAE0DMAE0DMAE061MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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6.
9.
9UniversalSerialCommunicationInterface(USCI)TheUSCImodulesareusedforserialdatacommunication.
TheUSCImodulesupportssynchronouscommunicationprotocolssuchasSPI(3-or4-pin)andI2C,andasynchronouscommunicationprotocolssuchasUART,enhancedUARTwithautomaticbaudratedetection,andIrDA.
EachUSCImodulecontainstwomodules,AandB.
TheUSCI_AxmoduleprovidessupportforSPI(3-or4-pin),UART,enhancedUART,orIrDA.
TheUSCI_BxmoduleprovidessupportforSPI(3-or4-pin)orI2C.
6.
9.
10TA0TA0isa16-bittimer/counterwiththreecapture/compareregisters.
TA0cansupportmultiplecapture/compares,PWMoutputs,andintervaltiming(seeTable6-10).
TA0alsohasextensiveinterruptcapabilities.
Interruptsmaybegeneratedfromthecounteronoverflowconditionsandfromeachofthecapture/compareregisters.
Table6-10.
TA0SignalConnectionsINPUTPINNUMBERDEVICEINPUTSIGNALMODULEINPUTSIGNALMODULEBLOCKMODULEOUTPUTSIGNALDEVICEOUTPUTSIGNALOUTPUTPINNUMBERRSB(40-PINQFN)DA(38-PINTSSOP)YFF(40-PINDSBGA)RSB(40-PINQFN)DA(38-PINTSSOP)YFF(40-PINDSBGA)P3.
3-30P3.
3-34P3.
3-G6TA0CLKTACLKTimerNANA–––ACLK(internal)ACLKACLKACLKACLK–––SMCLK(internal)SMCLKSMCLKSMCLKSMCLK–––P3.
3-30P3.
3-34P3.
3-G6TA0CLKTACLK–––P3.
7-36–P3.
7-G4TA0.
0CCI0ACCR0TA0TA0.
0P3.
7-36–P3.
7-G4–––CBOUTCCI0B––––––VSSGND––––––VCCVCC–––P3.
6-35–P3.
6-G3TA0.
1CCI1ACCR1TA1TA0.
1P3.
6-35P3.
6-38P3.
6-G3–––ACLKCCI1BADC10_A(1)(internal)ADC10SHSx=001bADC10_A(1)(internal)ADC10SHSx=001bADC10_A(1)(internal)ADC10SHSx=001b–––VSSGND––––––VCCVCC–––P3.
5-34P3.
5-37P3.
5-F3TA0.
2CCI2ACCR2TA2TA0.
2P3.
5-34P3.
5-37P3.
5-F3–––VSSCCI2B––––––VSSGND––––––VCCVCC–––62MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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6forTD0.
0,P1.
7forTD0.
1,andP2.
0forTD0.
2areoptimizedformatching.
(2)TheADC10_AtriggerisavailableonMSP430F51x2devices.
6.
9.
11TD0TD0isa16-bittimer/counterwiththreecapture/compareregisterssupportingupto256-MHz(4-ns)resolution.
TD0cansupportmultiplecapture/compares,PWMoutputs,andintervaltiming(seeTable6-11).
TD0alsohasextensiveinterruptcapabilities.
Interruptsmaybegeneratedfromthecounteronoverflowconditionsandfromeachofthecapture/compareregisters.
ExternalfaultinputsaswellasaexternaltimercounterclearissupportedalongwithinterruptflagsfromtheTEC0module.
Table6-11.
TD0SignalConnectionsINPUTPINNUMBERDEVICEINPUTSIGNALMODULEINPUTSIGNALMODULEBLOCKMODULEOUTPUTSIGNALDEVICEOUTPUTSIGNALOUTPUTPINNUMBERRSB(40-PINQFN)DA(38-PINTSSOP)YFF(40-PINDSBGA)RSB(40-PINQFN)DA(38-PINTSSOP)YFF(40-PINDSBGA)P3.
4-31–P3.
4-G5TD0CLKTDCLKTimerNANA–––ACLK(internal)ACLK(internal)ACLK(internal)ACLKACLK–––SMCLK(internal)SMCLK(internal)SMCLK(internal)SMCLKSMCLK–––P3.
4-31–P3.
4-G5TD0CLKTDCLK–––––––CLK0–––P2.
4-19P2.
4-23P2.
4-B4TEC0CLRTECXCLR–––P1.
6-11(1)P1.
6-15(1)P1.
6-A1(1)TD0.
0CCI0ACCR0TD0TD0P1.
6-11(1)P1.
6-15(1)P1.
6-A1(1)P3.
2-29P3.
2-33P3.
2-F5TD0.
0CCI0BP2.
4-19P2.
4-23P2.
4-B4–––VSSGNDADC10_A(internal)ADC10SHSx=010b(2)ADC10_A(internal)ADC10SHSx=010b(2)ADC10_A(internal)ADC10SHSx=010b(2)–––VCCVCC–––P2.
5-20P2.
5-24P2.
5-A6TEC0FLT0TECXFLT0––P1.
7-12(1)P1.
7-16(1)P1.
7-B2(1)TD0.
1CCI1ACCR1TD1TD1P1.
7-12(1)P1.
7-16(1)P1.
7-B2(1)CBOUT(internal)CBOUT(internal)CBOUT(internal)TD0.
1CCI1BPJ.
6-28PJ.
6-32PJ.
6-E5–––VSSGNDP2.
5-20P2.
5-24P2.
5-A6–––VCCVCCADC10_A(internal)ADC10SHSx=011b(2)ADC10_A(internal)ADC10SHSx=011b(2)ADC10_A(internal)ADC10SHSx=011b(2)P2.
6-21P2.
6-20P2.
6-B5TEC0FLT1TECXFLT1––P2.
0-13(1)P2.
0-17(1)P2.
0-B3(1)TD0.
2CCI2ACCR2TD2TD2P2.
0-13(1)P2.
0-17(1)P2.
0-B3(1)ACLK(internal)ACLK(internal)ACLK(internal)TD0.
2CCI2BP2.
6-21P2.
6-25P2.
6-B5–––VSSGND––––––VCCVCC–––P2.
4-19P2.
4-23P2.
4-B4TEC0FLT2TECXFLT2–––63MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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1forTD1.
0,P2.
2forTD1.
1,andP2.
3forTD1.
2areoptimizedformatching.
6.
9.
12TD1TD1isa16-bittimer/counterwiththreecapture/compareregisterssupportingupto256-MHz(4-ns)resolution.
TD1cansupportmultiplecapture/compares,PWMoutputs,andintervaltiming(seeTable6-12).
TD1alsohasextensiveinterruptcapabilities.
Interruptsmaybegeneratedfromthecounteronoverflowconditionsandfromeachofthecapture/compareregisters.
ExternalfaultinputsaswellasaexternaltimercounterclearissupportedalongwithinterruptflagsfromtheTEC0module.
Table6-12.
TD1SignalConnectionsINPUTPINNUMBERDEVICEINPUTSIGNALMODULEINPUTSIGNALMODULEBLOCKMODULEOUTPUTSIGNALDEVICEOUTPUTSIGNALOUTPUTPINNUMBERRSB(40-PINQFN)DA(38-PINTSSOP)YFF(40-PINDSBGA)RSB(40-PINQFN)DA(38-PINTSSOP)YFF(40-PINDSBGA)PJ.
6-28PJ.
6-32PJ.
6-E5TD1CLKTDCLKTimerNANA–––ACLK(internal)ACLK(internal)ACLK(internal)ACLKACLK–––SMCLK(internal)SMCLKSMCLKSMCLKSMCLK–––PJ.
6-28PJ.
6-32PJ.
6-E5TD1CLKTDCLK––––––fromTD0(internal)CLK0P2.
7-22P2.
7-26P2.
7-C5TEC1CLRTECxCLR–––P2.
1-14(1)P2.
1-18(1)P2.
1-A2TD1.
0CCI0ACCR0TD0TD0P2.
1-14(1)P2.
1-18(1)P2.
1-A2(1)–––TD1.
0CCI0BP2.
7-22P2.
7-26P2.
7-C5–––VSSGND––––––VCCVCC–––P3.
1-24P3.
1-28P3.
1-C6TEC1FLT0TECXFLT0–––P2.
2-15(1)P2.
2-19(1)P2.
2-A3TD1.
1CCI1ACCR1TD1TD1P2.
2-15(1)P2.
2-19(1)P2.
2-A3(1)CBOUT(internal)CBOUT(internal)CBOUT(internal)TD1.
1CCI1BP3.
0-23P3.
0-27P3.
0-B6–––VSSGND––––––VCCVCC–––P2.
7-22P2.
7-26P2.
7-C5TEC1FLT1TECXFLT1–––P2.
3-16(1)P2.
3-20(1)P2.
3-C4TD1.
2CCI2ACCR2TD2TD2P2.
3-16(1)P2.
3-20(1)P2.
3-C4(1)ACLK(internal)ACLK(internal)ACLK(internal)TD1.
2CCI2BP3.
1-24P3.
1-28P3.
1-C6–––VSSGND––––––VCCVCC–––P3.
0-23P3.
0-27P3.
0-B6TEC1FLT2TECXFLT2–––64MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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9.
13Comparator_BTheprimaryfunctionoftheComparator_Bmoduleistosupportprecisionslopeanalog-to-digitalconversions,batteryvoltagesupervision,andmonitoringofexternalanalogsignals.
6.
9.
14ADC10_A(MSP430F51x2Only)TheADC10_Amodulesupportsfast10-bitanalog-to-digitalconversions.
Themoduleimplementsa10-bitSARcore,sampleselectcontrol,referencegenerator,andaconversionresultbuffer.
AwindowcomparatorwithlowerandupperlimitsallowsCPU-independentresultmonitoringwiththreewindowcomparatorinterruptflags.
6.
9.
15CRC16TheCRC16moduleproducesasignaturebasedonasequenceofentereddatavaluesandcanbeusedfordatacheckingpurposes.
TheCRC16modulesignatureisbasedontheCRC-CCITTstandard.
6.
9.
16Reference(REF)ModuleVoltageReferenceTheREFisresponsibleforgenerationofallcriticalreferencevoltagesthatcanbeusedbythevariousanalogperipheralsinthedevice.
6.
9.
17EmbeddedEmulationModule(EEM)(SVersion)TheEEMsupportsreal-timein-systemdebugging.
TheSversionoftheEEMhasthefollowingfeatures:ThreehardwaretriggersorbreakpointsonmemoryaccessOnehardwaretriggerorbreakpointonCPUregisterwriteaccessUptofourhardwaretriggerscanbecombinedtoformcomplextriggersorbreakpointsOnecyclecounterClockcontrolonmodulelevel65MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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9.
18PeripheralFileMapTable6-13liststhebaseaddressandoffsetrangefortheregistersofallperipherals.
Table6-13.
PeripheralsMODULENAMEBASEADDRESSOFFSETADDRESSRANGESpecialFunctions(seeTable6-14)0100h000h–01FhPMM(seeTable6-15)0120h000h–010hFlashControl(seeTable6-16)0140h000h–00FhCRC16(seeTable6-17)0150h000h–007hRAMControl(seeTable6-18)0158h000h–001hWatchdog(seeTable6-19)015Ch000h–001hUCS(seeTable6-20)0160h000h–01FhSYS(seeTable6-21)0180h000h–01FhSharedReference(seeTable6-22)01B0h000h–001hPortMappingControl(seeTable6-23)01C0h000h–007hPortMappingPortP1(seeTable6-24)01C8h000h–007hPortMappingPortP2(seeTable6-25)01D0h000h–007hPortMappingPortP3(seeTable6-26)01D8h000h–007hPortP1,P2(seeTable6-27)0200h000h–01FhPortP3(seeTable6-28)0220h000h–01FhPortPJ(seeTable6-29)0320h000h–01FhTA0(seeTable6-30)03C0h000h–03Fh32-BitHardwareMultiplier(seeTable6-31)04C0h000h–02FhDMAGeneralControl(seeTable6-32)0500h000h–00FhDMAChannel0(seeTable6-33)0500h010h–00AhDMAChannel1(seeTable6-34)0500h020h–00AhDMAChannel2(seeTable6-35)0500h030h–00AhUSCI_A0(seeTable6-36)05C0h000h–01FhUSCI_B0(seeTable6-36)05E0h000h–01FhADC10_A(seeTable6-38)(MSP430F51x2only)0740h000h–01FhComparator_B(seeTable6-39)08C0h000h–00FhTD0(seeTable6-40)0B00h000h–03FhTEC0(seeTable6-42)0C00h000h–007hTD1(seeTable6-41)0B40h000h–03FhTEC1(seeTable6-43)0C20h000h–007h66MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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SpecialFunctionRegisters(BaseAddress:0100h)REGISTERDESCRIPTIONREGISTEROFFSETSFRinterruptenableSFRIE100hSFRinterruptflagSFRIFG102hSFRresetpincontrolSFRRPCR04hTable6-15.
PMMRegisters(BaseAddress:0120h)REGISTERDESCRIPTIONREGISTEROFFSETPMMcontrol0PMMCTL000hPMMcontrol1PMMCTL102hSVShigh-sidecontrolSVSMHCTL04hSVSlow-sidecontrolSVSMLCTL06hPMMinterruptflagsPMMIFG0ChPMMinterruptenablePMMIE0EhPMMpowermode5controlPM5CTL010hTable6-16.
FlashControlRegisters(BaseAddress:0140h)REGISTERDESCRIPTIONREGISTEROFFSETFlashcontrol1FCTL100hFlashcontrol3FCTL304hFlashcontrol4FCTL406hTable6-17.
CRC16Registers(BaseAddress:0150h)REGISTERDESCRIPTIONREGISTEROFFSETCRCdatainputCRC16DI00hCRCresultCRC16INIRES04hTable6-18.
RAMControlRegisters(BaseAddress:0158h)REGISTERDESCRIPTIONREGISTEROFFSETRAMcontrol0RCCTL000hTable6-19.
WatchdogRegisters(BaseAddress:015Ch)REGISTERDESCRIPTIONREGISTEROFFSETWatchdogtimercontrolWDTCTL00hTable6-20.
UCSRegisters(BaseAddress:0160h)REGISTERDESCRIPTIONREGISTEROFFSETUCScontrol0UCSCTL000hUCScontrol1UCSCTL102hUCScontrol2UCSCTL204hUCScontrol3UCSCTL306hUCScontrol4UCSCTL408hUCScontrol5UCSCTL50AhUCScontrol6UCSCTL60ChUCScontrol7UCSCTL70EhUCScontrol8UCSCTL810h67MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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SYSRegisters(BaseAddress:0180h)REGISTERDESCRIPTIONREGISTEROFFSETSystemcontrolSYSCTL00hBootloaderconfigurationareaSYSBSLC02hJTAGmailboxcontrolSYSJMBC06hJTAGmailboxinput0SYSJMBI008hJTAGmailboxinput1SYSJMBI10AhJTAGmailboxoutput0SYSJMBO00ChJTAGmailboxoutput1SYSJMBO10EhBuserrorvectorgeneratorSYSBERRIV18hUserNMIvectorgeneratorSYSUNIV1AhSystemNMIvectorgeneratorSYSSNIV1ChResetvectorgeneratorSYSRSTIV1EhTable6-22.
SharedReferenceRegisters(BaseAddress:01B0h)REGISTERDESCRIPTIONREGISTEROFFSETSharedreferencecontrolREFCTL00hTable6-23.
PortMappingControl(BaseAddress:01C0h)REGISTERDESCRIPTIONREGISTEROFFSETPortmappingpasswordPMAPPWD00hPortmappingcontrolPMAPCTL02hTable6-24.
PortMappingforPortP1(BaseAddress:01C8h)REGISTERDESCRIPTIONREGISTEROFFSETPortP1.
0mappingP1MAP000hPortP1.
1mappingP1MAP101hPortP1.
2mappingP1MAP202hPortP1.
3mappingP1MAP303hPortP1.
4mappingP1MAP404hPortP1.
5mappingP1MAP505hPortP1.
6mappingP1MAP606hPortP1.
7mappingP1MAP707hTable6-25.
PortMappingforPortP2(BaseAddress:01D0h)REGISTERDESCRIPTIONREGISTEROFFSETPortP2.
0mappingP2MAP000hPortP2.
1mappingP2MAP201hPortP2.
2mappingP2MAP202hPortP2.
3mappingP2MAP303hPortP2.
4mappingP2MAP404hPortP2.
5mappingP2MAP505hPortP2.
6mappingP2MAP606hPortP2.
7mappingP2MAP707h68MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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PortMappingforPortP3(BaseAddress:01D8h)REGISTERDESCRIPTIONREGISTEROFFSETPortP3.
0mappingP3MAP000hPortP3.
1mappingP3MAP101hPortP3.
2mappingP3MAP202hPortP3.
3mappingP3MAP303hPortP3.
4mappingP3MAP404hPortP3.
5mappingP3MAP505hPortP3.
6mappingP3MAP606hPortP3.
7mappingP3MAP707hTable6-27.
PortRegistersPortP1,P2(BaseAddresses:0200h)REGISTERDESCRIPTIONREGISTEROFFSETPortP1inputP1IN00hPortP1outputP1OUT02hPortP1directionP1DIR04hPortP1resistorenableP1REN06hPortP1drivestrengthP1DS08hPortP1selectionP1SEL0AhPortP1interruptvectorwordP1IV0EhPortP1interruptedgeselectP1IES18hPortP1interruptenableP1IE1AhPortP1interruptflagP1IFG1ChPortP2inputP2IN01hPortP2outputP2OUT03hPortP2directionP2DIR05hPortP2resistorenableP2REN07hPortP2drivestrengthP2DS09hPortP2selectionP2SEL0BhPortP2interruptvectorwordP2IV1EhPortP2interruptedgeselectP2IES19hPortP2interruptenableP2IE1BhPortP2interruptflagP2IFG1DhTable6-28.
PortRegistersP3(BaseAddresses:0220h)REGISTERDESCRIPTIONREGISTEROFFSETPortP3inputP3IN00hPortP3outputP3OUT02hPortP3directionP3DIR04hPortP3resistorenableP3REN06hPortP3drivestrengthP3DS08hPortP3selectionP3SEL0Ah69MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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PortRegistersPJ(BaseAddresses:0320h)REGISTERDESCRIPTIONREGISTEROFFSETPortPJinputPJIN00hPortPJoutputPJOUT02hPortPJdirectionPJDIR04hPortPJresistorenablePJREN06hPortPJdrivestrengthPJDS08hPortPJselectionPJSEL0AhTable6-30.
TA0Registers(BaseAddress:03C0h)REGISTERDESCRIPTIONREGISTEROFFSETTA0controlTA0CTL00hCapture/comparecontrol0TA0CCTL002hCapture/comparecontrol1TA0CCTL104hCapture/comparecontrol2TA0CCTL206hTA0counterTA0R10hCapture/compare0TA0CCR012hCapture/compare1TA0CCR114hCapture/compare2TA0CCR216hTA0expansion0TA0EX020hTA0interruptvectorTA0IV2EhTable6-31.
32-BitHardwareMultiplierRegisters(BaseAddress:04C0h)REGISTERDESCRIPTIONREGISTEROFFSET16-bitoperand1–multiplyMPY00h16-bitoperand1–signedmultiplyMPYS02h16-bitoperand1–multiplyaccumulateMAC04h16-bitoperand1–signedmultiplyaccumulateMACS06h16-bitoperand2OP208h16*16resultlowwordRESLO0Ah16*16resulthighwordRESHI0Ch16*16sumextensionregisterSUMEXT0Eh32-bitoperand1–multiplylowwordMPY32L10h32-bitoperand1–multiplyhighwordMPY32H12h32-bitoperand1–signedmultiplylowwordMPYS32L14h32-bitoperand1–signedmultiplyhighwordMPYS32H16h32-bitoperand1–multiplyaccumulatelowwordMAC32L18h32-bitoperand1–multiplyaccumulatehighwordMAC32H1Ah32-bitoperand1–signedmultiplyaccumulatelowwordMACS32L1Ch32-bitoperand1–signedmultiplyaccumulatehighwordMACS32H1Eh32-bitoperand2–lowwordOP2L20h32-bitoperand2–highwordOP2H22h32*32result0–leastsignificantwordRES024h32*32result1RES126h32*32result2RES228h32*32result3–mostsignificantwordRES32AhMPY32control0MPY32CTL02Ch70MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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DMAGeneralControl(BaseAddress:0500h)REGISTERDESCRIPTIONREGISTEROFFSETDMAmodulecontrol0DMACTL000hDMAmodulecontrol1DMACTL102hDMAmodulecontrol2DMACTL204hDMAmodulecontrol3DMACTL306hDMAmodulecontrol4DMACTL408hDMAinterruptvectorDMAIV0EhTable6-33.
DMAChannel0(BaseAddress:0510h)REGISTERDESCRIPTIONREGISTEROFFSETDMAchannel0controlDMA0CTL00hDMAchannel0sourceaddresslowDMA0SAL02hDMAchannel0sourceaddresshighDMA0SAH04hDMAchannel0destinationaddresslowDMA0DAL06hDMAchannel0destinationaddresshighDMA0DAH08hDMAchannel0transfersizeDMA0SZ0AhTable6-34.
DMAChannel1(BaseAddress:0520h)REGISTERDESCRIPTIONREGISTEROFFSETDMAchannel1controlDMA1CTL00hDMAchannel1sourceaddresslowDMA1SAL02hDMAchannel1sourceaddresshighDMA1SAH04hDMAchannel1destinationaddresslowDMA1DAL06hDMAchannel1destinationaddresshighDMA1DAH08hDMAchannel1transfersizeDMA1SZ0AhTable6-35.
DMAChannel2(BaseAddress:0530h)REGISTERDESCRIPTIONREGISTEROFFSETDMAchannel2controlDMA2CTL00hDMAchannel2sourceaddresslowDMA2SAL02hDMAchannel2sourceaddresshighDMA2SAH04hDMAchannel2destinationaddresslowDMA2DAL06hDMAchannel2destinationaddresshighDMA2DAH08hDMAchannel2transfersizeDMA2SZ0Ah71MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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USCI0_ARegisters(BaseAddress:05C0h)REGISTERDESCRIPTIONREGISTEROFFSETUSCIcontrol0UCA0CTL001hUSCIcontrol1UCA0CTL100hUSCIbaudrate0UCA0BR006hUSCIbaudrate1UCA0BR107hUSCImodulationcontrolUCA0MCTL08hUSCIstatusUCA0STAT0AhUSCIreceivebufferUCA0RXBUF0ChUSCItransmitbufferUCA0TXBUF0EhUSCILINcontrolUCA0ABCTL10hUSCIIrDAtransmitcontrolUCA0IRTCTL12hUSCIIrDAreceivecontrolUCA0IRRCTL13hUSCIinterruptenableUCA0IE1ChUSCIinterruptflagsUCA0IFG1DhUSCIinterruptvectorwordUCA0IV1EhTable6-37.
USCI0_BRegisters(BaseAddress:05E0h)REGISTERDESCRIPTIONREGISTEROFFSETUSCIsynchronouscontrol0UCB0CTL000hUSCIsynchronouscontrol1UCB0CTL101hUSCIsynchronousbitrate0UCB0BR006hUSCIsynchronousbitrate1UCB0BR107hUSCIsynchronousstatusUCB0STAT0AhUSCIsynchronousreceivebufferUCB0RXBUF0ChUSCIsynchronoustransmitbufferUCB0TXBUF0EhUSCII2CownaddressUCB0I2COA10hUSCII2CslaveaddressUCB0I2CSA12hUSCIinterruptenableUCB0IE1ChUSCIinterruptflagsUCB0IFG1DhUSCIinterruptvectorwordUCB0IV1EhTable6-38.
ADC10_ARegisters(MSP430F51x2DevicesOnly)(BaseAddress:0740h)REGISTERDESCRIPTIONREGISTEROFFSETADC10_Acontrol0ADC10CTL000hADC10_Acontrol1ADC10CTL102hADC10_Acontrol2ADC10CTL204hADC10_AwindowcomparatorlowthresholdADC10LO06hADC10_AwindowcomparatorhighthresholdADC10HI08hADC10_Amemorycontrolregister0ADC10MCTL00AhADC10_AconversionmemoryregisterADC10MEM012hADC10_AinterruptenableADC10IE1AhADC10_AinterruptflagsADC10IGH1ChADC10_AinterruptvectorwordADC10IV1Eh72MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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Comparator_BRegisters(BaseAddress:08C0h)REGISTERDESCRIPTIONREGISTEROFFSETComparator_Bcontrol0CBCTL000hComparator_Bcontrol1CBCTL102hComparator_Bcontrol2CBCTL204hComparator_Bcontrol3CBCTL306hComparator_BinterruptCBINT0ChComparator_BinterruptvectorwordCBIV0EhTable6-40.
TD0Registers(BaseAddress:0B00h)REGISTERDESCRIPTIONREGISTEROFFSETTD0control0TD0CTL000hTD0control1TD0CTL102hTD0control2TD0CTL204hTD0counterTD0R06hCapture/comparecontrol0TD0CCTL008hCapture/compare0TD0CCR00AhCapture/comparelatch0TD0CL00ChCapture/comparecontrol1TD0CCTL10EhCapture/compare1TD0CCR110hCapture/comparelatch1TD0CL112hCapture/comparecontrol2TD0CCTL214hCapture/compare2TD0CCR216hCapture/comparelatch2TD0CL218hTD0high-resolutioncontrol0TD0HCTL038hTD0high-resolutioncontrol1TD0HCTL13AhTD0high-resolutioninterruptTD0HINT3ChTD0interruptvectorTD0IV3EhTable6-41.
TD1Registers(BaseAddress:0B40h)REGISTERDESCRIPTIONREGISTEROFFSETTD1control0TD1CTL000hTD1control1TD1CTL102hTD1control2TD1CTL204hTD1counterTD1R06hCapture/comparecontrol0TD1CCTL008hCapture/compare0TD1CCR00AhCapture/comparelatch0TD1CL00ChCapture/comparecontrol1TD1CCTL10EhCapture/compare1TD1CCR110hCapture/comparelatch1TD1CL112hCapture/comparecontrol2TD1CCTL214hCapture/compare2TD1CCR216hCapture/comparelatch2TD1CL218hTD1high-resolutioncontrol0TD1HCTL038hTD1high-resolutioncontrol1TD1HCTL13AhTD1high-resolutioninterruptTD1HINT3ChTD1interruptvectorTD1IV3Eh73MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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TEC0Registers(BaseAddress:0C00h)REGISTERDESCRIPTIONREGISTEROFFSETTimereventcontrol0externalcontrol0TEC0CTL000hTimereventcontrol0externalcontrolTEC0CTL102hTimereventcontrol0externalcontrolTEC0CTL204hTimereventcontrol0statusTEC0STA06hTimereventcontrol0externalinterruptTEC0XINT08hTimereventcontrol0externalinterruptvectorTEC0IV0AhTable6-43.
TEC1Registers(BaseAddress:0C20h)REGISTERDESCRIPTIONREGISTEROFFSETTimereventcontrol1externalcontrol0TEC1CTL000hTimereventcontrol1externalcontrolTEC1CTL102hTimereventcontrol1externalcontrolTEC1CTL204hTimereventcontrol1statusTEC1STA06hTimereventcontrol1externalinterruptTEC1XINT08hTimereventcontrol1externalinterruptvectorTEC1IV0Ah74MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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10Input/OutputDiagrams6.
10.
1PortP1(P1.
0toP1.
5)Input/OutputWithSchmittTriggerFigure6-2showstheportdiagram.
Table6-44summarizestheselectionofthepinfunction.
Figure6-2.
PortP1(P1.
0toP1.
5)Diagram75MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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(3)UCA0CLKfunctiontakesprecedenceoverUCB0STEfunction.
IfthepinisrequiredasUCA0CLKinputoroutput,USCI_B0isforcedto3-wireSPImodeif4-wireSPImodeisselected.
(4)MSP430F51x2deviceonly(5)IftheI2Cfunctionalityisselected,theoutputdrivesonlythelogical0toVSSlevel.
Table6-44.
PortP1(P1.
0toP1.
5)PinFunctionsPINNAME(P1.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)P1DIR.
xP1SEL.
xP1MAP.
xCBPD.
yP1.
0/0P1.
x(I/O)I:0;O:10X0PM_UCA0CLK/PM_UCB0STE/UCA0CLK/UCB0STE(2)(3)01default0A0/A0(4)X131INCHx=0XCB0CB0XXX1(y=0)P1.
1/1P1.
x(I/O)I:0;O:10X0PM_UCA0TXD/PM_UCA0SIMO/PM_UCA0TXD/PM_UCA0SIMO(2)01default0A1/A1(4)X131INCHx=1XCB1CB1XXX1(y=1)P1.
2/2P1.
x(I/O)I:0;O:10X0PM_UCA0RXD/PM_UCA0SOMI/PM_UCA0RXD/PM_UCA0SOMI(2)01default0A2/A2(4)X131INCHx=2XCB2CB2XXX1(y=2)P1.
3/3P1.
x(I/O)I:0;O:10X0PM_UCB0CLK/PM_UCA0STE/UCB0CLK/UCA0STE(2)01default0A3/A3(4)X131INCHx=3XCB3CB3XXX1(y=3)P1.
4/4P1.
x(I/O)I:0;O:10X0PM_UCB0SIMO/PM_UCB0SDA/PM_UCB0SIMO/PM_UCB0SDA(2)(5)01default0A4/A4(4)X131INCHx=4XCB4CB4XXX1(y=4)P1.
5/5P1.
x(I/O)I:0;O:10X0PM_UCB0SOMI/PM_UCB0SCL/PM_UCB0SOMI/PM_UCB0SCL(2)(5)01default0A5/A5(4)X131INCHx=5XCB5CB5XXX1(y=5)76MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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10.
2PortP1(P1.
6toP1.
7)Input/OutputWithSchmittTriggerFigure6-3showstheportdiagram.
Table6-45summarizestheselectionofthepinfunction.
Figure6-3.
PortP1(P1.
6andP1.
7)DiagramTable6-45.
PortP1(P1.
6andP1.
7)PinFunctionsPINNAME(P1.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)P1DIR.
xP1SEL.
xP1MAP.
xP1.
6/6P1.
x(I/O)I:0;O:10XPM_TD0.
0TD0.
CCI0A01defaultTD0.
TA011defaultP1.
7/7P1.
x(I/O)I:0;O:10XPM_TD0.
1TD0.
CCI1A01defaultTD0.
TA111default77MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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10.
3PortP2(P2.
0toP2.
7)Input/OutputWithSchmittTriggerFigure6-4showstheportdiagram.
Table6-46summarizestheselectionofthepinfunction.
Figure6-4.
PortP2(P2.
0toP2.
7)Diagram78MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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PortP2(P2.
0toP2.
7)PinFunctionsPINNAME(P2.
x)xFUNCTIONCONTROLBITSORSIGNALSP2DIR.
xP2SEL.
xP2MAP.
xP2.
0/0P2.
x(I/O)I:0;O:10XPM_TD0.
2TD0.
CCI2A01defaultTD0.
TA211defaultP2.
1/1P2.
x(I/O)I:0;O:10XPM_TD1.
0TD1.
CCI0A01defaultTD1.
TA011defaultP2.
2/2P2.
x(I/O)I:0;O:10XPM_TD1.
1TD1.
CCI1A01defaultTD1.
TA111defaultP2.
3/3P2.
x(I/O)I:0;O:100PM_TD1.
2TD1.
CCI2A01defaultTD1.
TA211defaultP2.
4/4P2.
x(I/O)I:0;O:10XPM_TEC0CLR/TD0.
TECEXTCLR,controlledbyenablesignalsintheTEC0module01defaultPM_TEC0FLT2/TD0.
TECXFLT2,controlledbyenablesignalsintheTEC0module01defaultPM_TD0.
0TD0.
TA011defaultP2.
5/5P2.
x(I/O)I:0;O:10xPM_TEC0FLT0/TD0.
TECXFLT0,controlledbyenablesignalsintheTEC0module01defaultPM_TD0.
1TD0.
TA111defaultP2.
6/6P2.
x(I/O)I:0;O:10XPM_TEC0FLT1/TD0.
TECXFLT1,controlledbyenablesignalsintheTEC0module01defaultPM_TD0.
2TD0.
TA211defaultP2.
7/7P2.
x(I/O)I:0;O:10XPM_TEC1CLR/TD1.
TECEXTCLR,controlledbyenablesignalsintheTEC1module01defaultPM_TEC1FLT1/TD1.
TECXFLT1,controlledbyenablesignalsintheTEC1module01defaultPM_TD1.
0TD1.
TA011default79MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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10.
4PortP3(P3.
0andP3.
1)Input/OutputWithSchmittTriggerFigure6-5showstheportdiagram.
Table6-47summarizestheselectionofthepinfunction.
Figure6-5.
PortP3(P3.
0andP3.
1)DiagramTable6-47.
PortP3(P3.
0andP3.
1)PinFunctionsPINNAME(P3.
x)xFUNCTIONCONTROLBITSORSIGNALSP3DIR.
xP3SEL.
xP3MAP.
xP3.
0/0P3.
x(I/O)I:0;O:10XPM_TEC1FLT2/TD1.
TECXFLT2,controlledbyenablesignalsintheTEC1module01defaultPM_TD1.
1TD1.
TA111defaultP3.
1/1P3.
x(I/O)I:0;O:10XPM_TEC1FLT0/TD1.
TECXFLT0,controlledbyenablesignalsintheTEC1module01defaultPM_TD1.
2TD1.
TA211default80MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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10.
5PortP3(P3.
2andP3.
3)Input/OutputWithSchmittTriggerFigure6-6showstheportdiagram.
Table6-48summarizestheselectionofthepinfunction.
Figure6-6.
PortP3(P3.
2andP3.
3)DiagramTable6-48.
PortP3(P3.
2andP3.
3)PinFunctionsPINNAME(P3.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)P3DIR.
xP3SEL.
xP3MAP.
xCBPD.
yP3.
2/2P3.
x(I/O)I:0;O:10X0PM_TD0.
0/TD0.
CCI0A01default0PM_SMCLK/SMCLKoutput11default0CB14CB14XXX1(y=14)P3.
3/3P3.
x(I/O)I:0;O:10X0PM_TA0CLK/TA0.
TA0CLK01default0PM_CBOUT/CBOUT11default0CB13CB13XXX1(y=13)81MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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10.
6PortP3(P3.
4)Input/OutputWithSchmittTriggerFigure6-7showstheportdiagram.
Table6-49summarizestheselectionofthepinfunction.
Figure6-7.
PortP3(P3.
4)DiagramTable6-49.
PortP3(P3.
4)PinFunctionsPINNAME(P3.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)P3DIR.
xP3SEL.
xP3MAP.
xP3.
4/4P3.
x(I/O)I:0;O:10X0PM_TD0CLK/TD0clockinput01default0PM_MCLKMCLKoutput11default082MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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6.
10.
7PortP3(P3.
5)Input/OutputWithSchmittTriggerFigure6-8showstheportdiagram.
Table6-50summarizestheselectionofthepinfunction.
Figure6-8.
PortP3(P3.
5)DiagramTable6-50.
PortP3(P3.
5)PinFunctionsPINNAME(P3.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)P3DIR.
xP3SEL.
xP3MAP.
xCBPD.
yP3.
5/5P3.
x(I/O)I:0;O:10X0PM_TA0.
2/TA0.
CCI2A01default0TA0.
TA211default0VEREF+/VEREF+(2)X131XA8/A8(2)X1INCHx=8XCB12CB12XXX1(y=12)83MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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(3)MSP430F51x2devicesonly.
6.
10.
8PortP3(P3.
6)Input/OutputWithSchmittTriggerFigure6-9showstheportdiagram.
Table6-51summarizestheselectionofthepinfunction.
Figure6-9.
PortP3(P3.
6)DiagramTable6-51.
PortP3(P3.
6)PinFunctionsPINNAME(P3.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)P3DIR.
xP3SEL.
xP3MAP.
xCBPD.
yP3.
6/6P3.
x(I/O)(2)I:0;O:10X0PM_TA0.
1/TA0.
CCR001default0TA0.
TA111default0VEREF-/VEREF-(3)X131XA7/A7(3)X131INCHx=7XCB11CB11XX01(y=11)84MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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6.
10.
9PortP3(P3.
7)Input/OutputWithSchmittTriggerFigure6-10showstheportdiagram.
Table6-52summarizestheselectionofthepinfunction.
Figure6-10.
PortP3(P3.
7)DiagramTable6-52.
PortP3(P3.
7)PinFunctionsPINNAME(P3.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)P3DIR.
xP3SEL.
2P3MAP.
xCBPD.
yP3.
7/7P3.
x(I/O)(1)I:0;O:10X0PM_TA0.
0/TA0.
CCR001default0TA0.
TA011default0A6/A6(2)X131INCHx=6XCB10CB10XX01(y=10)85MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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10.
10PortJ(PJ.
0)JTAGPinTDO,Input/OutputWithSchmittTriggerorOutputFigure6-11showstheportdiagram.
Table6-53summarizestheselectionofthepinfunction.
Figure6-11.
PortPJ(PJ.
0)Diagram86MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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10.
11PortJ(PJ.
1toPJ.
3)JTAGPinsTMS,TCK,TDI/TCLK,Input/OutputWithSchmittTriggerorOutputFigure6-12showstheportdiagram.
Table6-53summarizestheselectionofthepinfunction.
Figure6-12.
PortPJ(PJ.
1toPJ.
3)Diagram87MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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(4)InJTAGmode,pullupsareactivatedautomaticallyonTMS,TCK,andTDI/TCLK.
PJREN.
xaredon'tcare.
(5)MSP430F51x2deviceonly.
Table6-53.
PortPJ(PJ.
0toPJ.
3)PinFunctionsPINNAME(PJ.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)PJDIR.
xPJSEL.
xJTAGMODECBPD.
yPJ.
0/0PJ.
x(I/O)(2)I:0;O:1000SMCLK/SMCLK1100TDO/TDO(3)XX1XCB6CB6XX01(y=6)PJ.
1/1PJ.
x(I/O)(2)I:0;O:1000MCLK/MCLK1100TDI/TCLK/TDI/TCLK(3)(4)XX1XCB7CB70X01(y=7)PJ.
2/2PJ.
x(I/O)(2)I:0;O:1000ADC10CLK/ADC10CLK(See(5))1100TMS/TMS(3)(4)XX1XCB8CB8XX01(y=8)PJ.
3/3PJ.
x(I/O)(2)I:0;O:1000ACLK/ACLK1100TCK/TCK(3)(4)XX1XCB9CB9XX01(y=9)88MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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10.
12PortJ(PJ.
4)Input/OutputWithSchmittTriggerFigure6-13showstheportdiagram.
Table6-54summarizestheselectionofthepinfunction.
Figure6-13.
PortPJ(PJ.
4)Diagram89MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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5causesthegeneral-purposeI/Otobedisabledincrystalmode.
Whenusingbypassmode,PJ.
4canbeusedasgeneral-purposeI/O.
(3)SettingPJSEL.
5causesthegeneral-purposeI/Otobedisabled.
PendingthesettingofXT1BYPASS,PJ.
5isconfiguredforcrystalmodeorbypassmode.
6.
10.
13PortJ(PJ.
5)Input/OutputWithSchmittTriggerFigure6-14showstheportdiagram.
Table6-54summarizestheselectionofthepinfunction.
Figure6-14.
PortPJ(PJ.
5)DiagramTable6-54.
PortPJ(PJ.
4andPJ.
5)PinFunctionsPINNAME(PJ.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)PJDIR.
xPJSEL.
4PJSEL.
5XT1BYPASSPJ.
4/4PJ.
4(I/O)I:0;O:100X11XOUTXOUTcrystalmode(2)XX10PJ.
5/5PJ.
5(I/O)(2)I:0;O:1X0xXINXINcrystalmode(3)XX10XINbypassmode(3)XX1190MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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10.
14PortJ(PJ.
6)Input/OutputWithSchmittTriggerFigure6-15showstheportdiagram.
Table6-55summarizestheselectionofthepinfunction.
Figure6-15.
PortPJ(PJ.
6)DiagramTable6-55.
PortPJ(PJ.
6)PinFunctionsPINNAME(PJ.
x)xFUNCTIONCONTROLBITSORSIGNALS(1)PJDIR.
xPJSEL.
xCBPD.
yPJ.
6/6PJ.
x(I/O)I:0;O:100TD1CLK/TD1clockinput010TD0.
1/TD0.
TA1110CB15CB15XX1(y=15)91MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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11DeviceDescriptorsTable6-56andTable6-57listthecompletecontentsofthedevicedescriptortag-length-value(TLV)structurefortheMSP430F51x2andMSP430F51x1devices,respectively.
Table6-56.
MSP430F51x2DeviceDescriptorTable(1)DESCRIPTIONADDRESSSIZE(bytes)VALUEF5172F5152F5132RSB,YFFDARSBDARSBDAInfoBlockInfolength0x1A0010x060x060x060x060x060x06CRClength0x1A0110x060x060x060x060x060x06CRCvalue0x1A022PerunitPerunitPerunitPerunitPerunitPerunitDeviceID0x1A0410x300x300x2C0x2C0x280x28DeviceID0x1A0510x800x800x800x800x800x80Hardwarerevision0x1A0610x300300x300x300x300x30Firmwarerevision0x1A0710x100x100x100x100x100x10DieRecordDierecordtag0x1A0810x08080x08080x0808Dierecordlength0x1A0910x0A0A0x0A0A0x0A0ALot/waferID0x1A0A4PerunitPerunitPerunitPerunitPerunitPerunitDieXposition0x1A0Eh2PerunitPerunitPerunitPerunitPerunitPerunitDieYposition0x1A102PerunitPerunitPerunitPerunitPerunitPerunitTestresults0x1A122PerunitPerunitPerunitPerunitPerunitPerunitADC10CalibrationADC10calibrationtag0x1A1410x130x130x130x130x130x13ADC10calibrationlength0x1A1510x100x100x100x100x100x10ADCgainfactor0x1A162PerunitPerunitPerunitPerunitPerunitPerunitADCoffset0x1A182PerunitPerunitPerunitPerunitPerunitPerunitADC1.
5-VreferenceTemperaturesensor30°C0x1A1A2PerunitPerunitPerunitPerunitPerunitPerunitADC1.
5-VreferenceTemperaturesensor85°C0x1A1C2PerunitPerunitPerunitPerunitPerunitPerunitADC2.
0-VreferenceTemperaturesensor30°C0x1A1Eh2PerunitPerunitPerunitPerunitPerunitPerunitADC2.
0-VreferenceTemperaturesensor85°C0x1A202PerunitPerunitPerunitPerunitPerunitPerunitADC2.
5-VreferenceTemperaturesensor30°C0x1A222PerunitPerunitPerunitPerunitPerunitPerunitADC2.
5-VreferenceTemperaturesensor85°C0x1A242PerunitPerunitPerunitPerunitPerunitPerunitREFUserCalibrationREFtag0x1A2610x120x120x120x120x120x12REFlength0x1A2710x060x060x060x060x060x06REF1.
5-Vreference0x1A2820xFF0xFF0xFF0xFF0xFF0xFFREF2.
0-Vreference0x1A2A20xFF0xFF0xFF0xFF0xFF0xFFREF2.
5-Vreference0x1A2C20xFF0xFF0xFF0xFF0xFF0xFFTimer_D0CalibrationTimer_Dtag0x1A2E10x150x150x150x150x150x15Timer_Dlength0x1A2F10x080x080x080x080x080x08Timer_D64-MHzfrequency0x1A302PerunitPerunitPerunitPerunitPerunitPerunitTimer_D128-MHzfrequency0x1A322PerunitPerunitPerunitPerunitPerunitPerunitTimer_D200-MHzfrequency0x1A342PerunitPerunitPerunitPerunitPerunitPerunitTimer_D256-MHzfrequency0x1A362PerunitPerunitPerunitPerunitPerunitPerunitTimer_D1CalibrationTimer_Dtag0x1A3810x150x150x150x150x150x15Timer_Dlength0x1A3910x080x080x080x080x080x08Timer_D64-MHzfrequency0x1A3A2PerunitPerunitPerunitPerunitPerunitPerunitTimer_D128-MHzfrequency0x1A3C2PerunitPerunitPerunitPerunitPerunitPerunitTimer_D200-MHzfrequency0x1A3E2PerunitPerunitPerunitPerunitPerunitPerunitTimer_D256-MHzfrequency0x1A402PerunitPerunitPerunitPerunitPerunitPerunit92MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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MSP430F51x2DeviceDescriptorTable(1)(continued)DESCRIPTIONADDRESSSIZE(bytes)VALUEF5172F5152F5132RSB,YFFDARSBDARSBDAPeripheralDescriptorPeripheraldescriptortag0x1A4210x020x020x020x020x020x02Peripheraldescriptorlength0x1A4310x530x530x530x530x530x53BSLmemory0x1A4420x8A080x8A080x8A080x8A080x8A080x8A08Informationmemory0x1A4620x860C0x860C0x860C0x860C0x860C0x860CRAM0x1A4820x2A0E0x2A0E0x2A0E0x2A0E0x280E0x280EMainmemory0x1A4A20x92400x92400x90600x90600x8E700x8E70Delimiter0x1A4C10x000x000x000x000x000x00Peripheralcount0x1A4D10x1C0x1C0x1B0x1B0x1B0x1BMSP430CPUXV20x1A4E20x23000x23000x23000x23000x23000x2300SBW0x1A5020x0F000x0F000x0F000x0F000x0F000x0F00EEM-S0x1A5220x03000x03000x03000x03000x03000x0300TIBSL0x1A5420xFC000xFC000xFC000xFC000xFC000xFC00SFR0x1A5620x41100x41100x41100x41100x41100x4110PMM0x1A5820x30020x30020x30020x30020x30020x3002FCTL0x1A5A20x38020x38020x38020x38020x38020x3802CRC160x1A5C20x3C010x3C010x3C010x3C010x3C010x3C01CRC16_RB0x1A5E20x3D000x3D000x3D000x3D000x3D000x3D00RAMCTL0x1A6020x44000x44000x44000x44000x44000x4400WDT_A0x1A6220x40000x40000x40000x40000x40000x4000UCS0x1A6420x48010x48010x48010x48010x48010x4801SYS0x1A6620x42020x42020x42020x42020x42020x4202SharedREF0x1A6820xA0030xA0030xA0030xA0030xA0030xA003PortMapping0x1A6A20x10010x10010x10010x10010x10010x1001Port1/20x1A6C20x51040x51040x51040x51040x51040x5104Port3/40x1A6E20x52020x52020x52020x52020x52020x5202PortJ0x1A7020x5F100x5F100x5F100x5F100x5F100x5F10TA00x1A7220x610A0x610A0x610A0x610A0x610A0x610AMPY320x1A7420x85100x85100x85100x85100x85100x8510DMAwith3channels0x1A7620x47040x47040x47040x47040x47040x4704USCI_A0/B00x1A7820x900C0x900C0x900C0x900C0x900C0x900CADC10_A0x1A7A20xD3180xD3180xD3180xD3180xD3180xD318COMP_B0x1A7C20xA8180xA8180x1A9190xA8180x1A9190xA818TIMER_D00x1A7E20xD6240xD6240xD6240xD6240xD6240xD624TIMER_D10x1A8020x6D040x6D040x6D040x6D040x6D040x6D04TEC_00x1A8220x700C0x700C0x700C0x700C0x700C0x700CTEC_10x1A8420x70020x70020x70020x70020x70020x700293MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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MSP430F51x2DeviceDescriptorTable(1)(continued)DESCRIPTIONADDRESSSIZE(bytes)VALUEF5172F5152F5132RSB,YFFDARSBDARSBDAInterruptsCOMP_B0x1A8610xA80xA80xA80xA80xA80xA8TEC_00x1A8710x6D0x6D0x6D0x6D0x6D0x6DTIMER_D00x1A8810x620x620x620x620x620x62TIMER_D00x1A8910x630x630x630x630x630x63WDTIFG0x1A8A10x400x400x400x400x400x40USCI_A00x1A8B10x900x900x900x900x900x90USCI_B00x1A8C10x910x910x910x910x910x91ADC10_A0x1A8D10xD00xD00xD00xD00xD00xD0TA0.
CCIFG00x1A8E10x600x600x600x600x600x60TA0.
CCIFG1.
.
40x1A8F10x610x610x610x610x610x61DMA0x1A9010x460x460x460x460x460x46TEC_10x1A9110x6E0x6E0x6E0x6E0x6E0x6ETIMER_D10x1A9210x640x640x640x640x640x64TIMER_D10x1A9310x650x650x650x650x650x65PortP10x1A9410x500x500x500x500x500x50PortP20x1A9510x510x510x510x510x510x51Delimiter0x1A9610x000x000x000x000x000x00EmptyUnusedmemory0x1A97-0x1AB90xFF0xFF0xFF0xFF0xFF0xFF(1)NA=NotapplicableTable6-57.
MSP430F51x1DeviceDescriptorTable(1)DESCRIPTIONADDRESSSIZE(bytes)VALUEF5171F5151F5131RSBDARSBDARSBDAInfoBlockInfolength0x1A0010x060x060x060x060x060x06CRClength0x1A0110x060x060x060x060x060x06CRCvalue0x1A022PerunitPerunitPerunitPerunitPerunitPerunitDeviceID0x1A0410x2E0x2E0x2A0x2A0x260x26DeviceID0x1A0510x800x800x800x800x800x80Hardwarerevision0x1A0610x300x300x300x300x300x30Firmwarerevision0x1A0710x100x100x100x100x100x10DieRecordDierecordtag0x1A0810x08080x08080x0808Dierecordlength0x1A0910x0A0A0x0A0A0x0A0ALot/waferID0x1A0A4PerunitPerunitPerunitPerunitPerunitPerunitDieXposition0x1A0Eh2PerunitPerunitPerunitPerunitPerunitPerunitDieYposition0x1A102PerunitPerunitPerunitPerunitPerunitPerunitTestresults0x1A122PerunitPerunitPerunitPerunitPerunitPerunit94MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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MSP430F51x1DeviceDescriptorTable(1)(continued)DESCRIPTIONADDRESSSIZE(bytes)VALUEF5171F5151F5131RSBDARSBDARSBDAADC10CalibrationADC10calibrationtag0x1A1410x050x050x050x050x050x05ADC10calibrationlength0x1A1510x100x100x100x100x100x10ADCgainfactor0x1A162PerunitPerunitPerunitPerunitPerunitPerunitADCoffset0x1A182PerunitPerunitPerunitPerunitPerunitPerunitADC1.
5-VreferenceTemperaturesensor30°C0x1A1A2PerunitPerunitPerunitPerunitPerunitPerunitADC1.
5-VreferenceTemperaturesensor85°C0x1A1C2PerunitPerunitPerunitPerunitPerunitPerunitADC2.
0-VreferenceTemperaturesensor30°C0x1A1Eh2PerunitPerunitPerunitPerunitPerunitPerunitADC2.
0-VreferenceTemperaturesensor85°C0x1A202PerunitPerunitPerunitPerunitPerunitPerunitADC2.
5-VreferenceTemperaturesensor30°C0x1A222PerunitPerunitPerunitPerunitPerunitPerunitADC2.
5-VreferenceTemperaturesensor85°C0x1A242PerunitPerunitPerunitPerunitPerunitPerunitREFUserCalibrationREFtag0x1A2610x120x120x120x120x120x12REFlength0x1A2710x060x060x060x060x060x06REF1.
5-Vreference0x1A2820xFF0xFF0xFF0xFF0xFF0xFFREF2.
0-Vreference0x1A2A20xFF0xFF0xFF0xFF0xFF0xFFREF2.
5-Vreference0x1A2C20xFF0xFF0xFF0xFF0xFF0xFFTimer_D0CalibrationTimer_Dtag0x1A2E10x150x150x150x150x150x15Timer_Dlength0x1A2F10x080x080x080x080x080x08Timer_D64-MHzfrequency0x1A302PerunitPerunitPerunitPerunitPerunitPerunitTimer_D128-MHzfrequency0x1A322PerunitPerunitPerunitPerunitPerunitPerunitTimer_D200-MHzfrequency0x1A342PerunitPerunitPerunitPerunitPerunitPerunitTimer_D256-MHzfrequency0x1A362PerunitPerunitPerunitPerunitPerunitPerunitTimer_D1CalibrationTimer_Dtag0x1A3810x150x150x150x150x150x15Timer_Dlength0x1A3910x080x080x080x080x080x08Timer_D64-MHzfrequency0x1A3A2PerunitPerunitPerunitPerunitPerunitPerunitTimer_D128-MHzfrequency0x1A3C2PerunitPerunitPerunitPerunitPerunitPerunitTimer_D200-MHzfrequency0x1A3E2PerunitPerunitPerunitPerunitPerunitPerunitTimer_D256-MHzfrequency0x1A402PerunitPerunitPerunitPerunitPerunitPerunit95MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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MSP430F51x1DeviceDescriptorTable(1)(continued)DESCRIPTIONADDRESSSIZE(bytes)VALUEF5171F5151F5131RSBDARSBDARSBDAPeripheralDescriptorPeripheraldescriptortag0x1A4210x020x020x020x020x020x02Peripheraldescriptorlength0x1A4310x510x510x510x510x510x51BSLmemory0x1A4420x8A080x8A080x8A080x8A080x8A080x8A08Informationmemory0x1A4620x860C0x860C0x860C0x860C0x860C0x860CRAM0x1A4820x2A0E0x2A0E0x2A0E0x2A0E0x280E0x280EMainmemory0x1A4A20x92400x92400x90600x90600x8E700x8E70Delimiter0x1A4C10x000x000x000x000x000x00Peripheralcount0x1A4D10x1B0x1B0x1B0x1B0x1B0x1BMSP430CPUXV20x1A4E20x23000x23000x23000x23000x23000x2300SBW0x1A5020x0F000x0F000x0F000x0F000x0F000x0F00EEM-S0x1A5220x03000x03000x03000x03000x03000x0300TIBSL0x1A5420xFC000xFC000xFC000xFC000xFC000xFC00SFR0x1A5620x41100x41100x41100x41100x41100x4110PMM0x1A5820x30020x30020x30020x30020x30020x3002FCTL0x1A5A20x38020x38020x38020x38020x38020x3802CRC160x1A5C20x3C010x3C010x3C010x3C010x3C010x3C01CRC16_RB0x1A5E20x3D000x3D000x3D000x3D000x3D000x3D00RAMCTL0x1A6020x44000x44000x44000x44000x44000x4400WDT_A0x1A6220x40000x40000x40000x40000x40000x4000UCS0x1A6420x48010x48010x48010x48010x48010x4801SYS0x1A6620x42020x42020x42020x42020x42020x4202SharedREF0x1A6820xA0030xA0030xA0030xA0030xA0030xA003PortMapping0x1A6A20x10010x10010x10010x10010x10010x1001Port1/20x1A6C20x51040x51040x51040x51040x51040x5104Port3/40x1A6E20x52020x52020x52020x52020x52020x5202PortJ0x1A7020x5F100x5F100x5F100x5F100x5F100x5F10TA00x1A7220x610A0x610A0x610A0x610A0x610A0x610AMPY320x1A7420x85100x85100x85100x85100x85100x8510DMAwith3channels0x1A7620x47040x47040x47040x47040x47040x4704USCI_A0/B00x1A7820x900C0x900C0x900C0x900C0x900C0x900CCOMP_B0x1A7A20xA8300xA8300xA8300xA8300xA8300xA830TIMER_D00x1A7C20xD6240xD6240xD6240xD6240xD6240xD624TIMER_D10x1A7E20x6D040x6D040x6D040x6D040x6D040x6D04TEC_00x1A8020x700C0x700C0x700C0x700C0x700C0x700CTEC_10x1A8220x70020x70020x70020x70020x70020x700296MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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MSP430F51x1DeviceDescriptorTable(1)(continued)DESCRIPTIONADDRESSSIZE(bytes)VALUEF5171F5151F5131RSBDARSBDARSBDAInterruptsCOMP_B0x1A8310xA80xA80xA80xA80xA80xA8TEC_00x1A8410x6D0x6D0x6D0x6D0x6D0x6DTIMER_D00x1A8510x620x620x620x620x620x62TIMER_D00x1A8610x630x630x630x630x630x63WDTIFG0x1A8710x400x400x400x400x400x40USCI_A00x1A8810x900x900x900x900x900x90USCI_B00x1A8910x910x910x910x910x910x91ADC10_A0x1A8A10xD00xD00xD00xD00xD00xD0TA0.
CCIFG00x1A8B10x600x600x600x600x600x60TA0.
CCIFG1.
.
40x1A8C10x610x610x610x610x610x61DMA0x1A8D10x460x460x460x460x460x46TEC_10x1A8E10x6E0x6E0x6E0x6E0x6E0x6ETIMER_D10x1A8F10x640x640x640x640x640x64TIMER_D10x1A9010x650x650x650x650x650x65PortP10x1A9110x500x500x500x500x500x50PortP20x1A9210x510x510x510x510x510x51Delimiter0x1A9310x000x000x000x000x000x00EmptyUnusedMemory0x1A94–0x1AB90xFF0xFF0xFF0xFF0xFF0xFF97MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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1GettingStartedandNextStepsFormoreinformationontheMSP430familyofdevicesandthetoolsandlibrariesthatareavailabletohelpwithyourdevelopment,visittheMSP430ultra-low-powersensing&measurementMCUsoverview.
7.
2DeviceNomenclatureTodesignatethestagesintheproductdevelopmentcycle,TIassignsprefixestothepartnumbersofallMSPMCUdevices.
EachMSPMCUcommercialfamilymemberhasoneoftwoprefixes:MSPorXMS.
Theseprefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes(XMS)throughfullyqualifiedproductiondevices(MSP).
XMS–Experimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectricalspecificationsMSP–FullyqualifiedproductiondeviceXMSdevicesareshippedagainstthefollowingdisclaimer:"Developmentalproductisintendedforinternalevaluationpurposes.
"MSPdeviceshavebeencharacterizedfully,andthequalityandreliabilityofthedevicehavebeendemonstratedfully.
TI'sstandardwarrantyapplies.
Predictionsshowthatprototypedevices(XMS)haveagreaterfailureratethanthestandardproductiondevices.
TIrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheirexpectedend-usefailureratestillisundefined.
Onlyqualifiedproductiondevicesaretobeused.
TIdevicenomenclaturealsoincludesasuffixwiththedevicefamilyname.
Thissuffixindicatesthetemperaturerange,packagetype,anddistributionformat.
Figure7-1providesalegendforreadingthecompletedevicename.
98MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131DeviceandDocumentationSupportCopyright2010–2018,TexasInstrumentsIncorporatedFigure7-1.
DeviceNomenclature99MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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3ToolsandSoftwareAllMSPmicrocontrollersaresupportedbyawidevarietyofsoftwareandhardwaredevelopmenttools.
ToolsareavailablefromTIandvariousthirdparties.
SeethemallatMSP430Ultra-Low-PowerMCUs–Tools&software.
Table7-1liststhedebugfeaturesoftheseMCUs.
SeetheCodeComposerStudioIDEforMSP430User'sGuidefordetailsontheavailablefeatures.
Table7-1.
HardwareDebugFeaturesMSP430ARCHITECTURE4-WIREJTAG2-WIREJTAGBREAK-POINTS(N)RANGEBREAK-POINTSCLOCKCONTROLSTATESEQUENCERTRACEBUFFERLPMx.
5DEBUGGINGSUPPORTMSP430Xv2YesYes3YesYesNoNoNoDesignKitsandEvaluationModulesMSP43040-PinPackageBoardandUSBProgrammerTheMSP-FET430U40isabundlefeaturingastandalone40-pinZIFsockettargetboardwhichisusedtoprogramanddebugtheMSP430MCUin-systemthroughtheJTAGinterfaceortheSpyBi-Wire(2-wireJTAG)protocolandtheMSP-FETFlashEmulationTool.
MSP43040-PinTargetDevelopmentBoardforMSP430F5xMCUsTheMSP-TS430RSB40isastand-alone40-pinZIFsockettargetboardthatisusedtoprogramanddebugtheMSP430MCUin-systemthroughtheJTAGinterfaceortheSpyBi-Wire(2-wireJTAG)protocol.
SoftwareMSP430WareSoftwareMSP430Waresoftwareisacollectionofcodeexamples,datasheets,andotherdesignresourcesforallMSP430devicesdeliveredinaconvenientpackage.
InadditiontoprovidingacompletecollectionofexistingMSP430designresources,MSP430Waresoftwarealsoincludesahigh-levelAPIcalledMSPDriverLibrary.
ThislibrarymakesiteasytoprogramMSP430hardware.
MSP430WaresoftwareisavailableasacomponentofCodeComposerStudioIDEorasastand-alonepackage.
MSP430F51x2,MSP430F51x1CodeExamplesCCodeexamplesareavailableforeveryMSPdevicethatconfigureseachoftheintegratedperipheralsforvariousapplicationneeds.
MSPDriverLibraryDriverLibrary'sabstractedAPIkeepsyouabovethebitsandbytesoftheMSP430hardwarebyprovidingeasy-to-usefunctioncalls.
ThoroughdocumentationisdeliveredthroughahelpfulAPIGuide,whichincludesdetailsoneachfunctioncallandtherecognizedparameters.
DeveloperscanuseDriverLibraryfunctionstowritecompleteprojectswithminimaloverhead.
MSPEnergyTraceTechnologyEnergyTracetechnologyforMSP430microcontrollersisanenergy-basedcodeanalysistoolthatmeasuresanddisplaystheapplication'senergyprofileandhelpstooptimizeitforultra-low-powerconsumption.
ULP(Ultra-LowPower)AdvisorULPAdvisorsoftwareisatoolforguidingdeveloperstowritemoreefficientcodetofullyutilizetheuniqueultra-lowpowerfeaturesofMSPandMSP432microcontrollers.
Aimedatbothexperiencedandnewmicrocontrollerdevelopers,ULPAdvisorchecksyourcodeagainstathoroughULPchecklisttosqueezeeverylastnanoampoutofyourapplication.
Atbuildtime,ULPAdvisorwillprovidenotificationsandremarkstohighlightareasofyourcodethatcanbefurtheroptimizedforlowerpower.
IEC60730SoftwarePackageTheIEC60730MSP430softwarepackagewasdevelopedtobeusefulinassistingcustomersincomplyingwithIEC60730-1:2010(AutomaticElectricalControlsforHouseholdandSimilarUse–Part1:GeneralRequirements)foruptoClassBproducts,whichincludeshomeappliances,arcdetectors,powerconverters,powertools,e-bikes,andmanyothers.
TheIEC60730MSP430softwarepackagecanbeembeddedincustomerapplicationsrunningonMSP430stohelpsimplifythecustomer'scertificationeffortsoffunctionalsafety-compliantconsumerdevicestoIEC60730-1:2010ClassB.
100MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
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Theseroutinesaretypicallyusedincomputationallyintensivereal-timeapplicationswhereoptimalexecutionspeed,highaccuracy,andultra-lowenergyarecritical.
ByusingtheIQmathandQmathlibraries,itispossibletoachieveexecutionspeedsconsiderablyfasterandenergyconsumptionconsiderablylowerthanequivalentcodewrittenusingfloating-pointmath.
FloatingPointMathLibraryforMSP430Continuingtoinnovateinthelowpowerandlowcostmicrocontrollerspace,TIbringsyouMSPMATHLIB.
Leveragingtheintelligentperipheralsofourdevices,thisfloatingpointmathlibraryofscalarfunctionsbringsyouupto26xbetterperformance.
Mathlibiseasytointegrateintoyourdesigns.
ThislibraryisfreeandisintegratedinbothCodeComposerStudioandIARIDEs.
Readtheuser'sguideforanindepthlookatthemathlibraryandrelevantbenchmarks.
DevelopmentToolsCodeComposerStudioIntegratedDevelopmentEnvironmentforMSPMicrocontrollersCodeComposerStudioisanintegrateddevelopmentenvironment(IDE)thatsupportsallMSPmicrocontrollerdevices.
CodeComposerStudiocomprisesasuiteofembeddedsoftwareutilitiesusedtodevelopanddebugembeddedapplications.
ItincludesanoptimizingC/C++compiler,sourcecodeeditor,projectbuildenvironment,debugger,profiler,andmanyotherfeatures.
TheintuitiveIDEprovidesasingleuserinterfacetakingyouthrougheachstepoftheapplicationdevelopmentflow.
Familiarutilitiesandinterfacesallowuserstogetstartedfasterthaneverbefore.
CodeComposerStudiocombinestheadvantagesoftheEclipsesoftwareframeworkwithadvancedembeddeddebugcapabilitiesfromTIresultinginacompellingfeature-richdevelopmentenvironmentforembeddeddevelopers.
WhenusingCCSwithanMSPMCU,auniqueandpowerfulsetofpluginsandembeddedsoftwareutilitiesaremadeavailabletofullyleveragetheMSPmicrocontroller.
Command-LineProgrammerMSPFlasherisanopen-sourceshell-basedinterfaceforprogrammingMSPmicrocontrollersthroughaFETprogrammeroreZ430usingJTAGorSpy-Bi-Wire(SBW)communication.
MSPFlashercandownloadbinaryfiles(.
txtor.
hex)filesdirectlytotheMSPmicrocontrollerwithoutanIDE.
MSPMCUProgrammerandDebuggerTheMSP-FETisapowerfulemulationdevelopmenttool–oftencalledadebugprobe–whichallowsuserstoquicklybeginapplicationdevelopmentonMSPlow-powermicrocontrollers(MCU).
CreatingMCUsoftwareusuallyrequiresdownloadingtheresultingbinaryprogramtotheMSPdeviceforvalidationanddebugging.
TheMSP-FETprovidesadebugcommunicationpathwaybetweenahostcomputerandthetargetMSP.
Furthermore,theMSP-FETalsoprovidesaBackchannelUARTconnectionbetweenthecomputer'sUSBinterfaceandtheMSPUART.
ThisaffordstheMSPprogrammeraconvenientmethodforcommunicatingseriallybetweentheMSPandaterminalrunningonthecomputer.
Italsosupportsloadingprograms(oftencalledfirmware)totheMSPtargetusingtheBSL(bootloader)throughtheUARTandI2Ccommunicationprotocols.
MSP-GANGProductionProgrammerTheMSPGangProgrammerisanMSP430orMSP432deviceprogrammerthatcanprogramuptoeightidenticalMSP430orMSP432FlashorFRAMdevicesatthesametime.
TheMSPGangProgrammerconnectstoahostPCusingastandardRS-232orUSBconnectionandprovidesflexibleprogrammingoptionsthatallowtheusertofullycustomizetheprocess.
TheMSPGangProgrammerisprovidedwithanexpansionboard,calledtheGangSplitter,thatimplementstheinterconnectionsbetweentheMSPGangProgrammerandmultipletargetdevices.
Eightcablesareprovidedthatconnecttheexpansionboardtoeighttargetdevices(throughJTAGorSpy-Bi-Wireconnectors).
TheprogrammingcanbedonewithaPCorasastand-alonedevice.
APC-sidegraphicaluserinterfaceisalsoavailableandisDLL-based.
101MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
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4DocumentationSupportThefollowingdocumentsdescribetheMSP430F51x2andMSP430F51x1devices.
CopiesofthesedocumentsareavailableontheInternetatwww.
ti.
com.
ReceivingNotificationofDocumentUpdatesToreceivenotificationofdocumentationupdates—includingsiliconerrata—gototheproductfolderforyourdeviceonti.
com(forlinkstotheproductfolder,seeSection7.
5).
Intheupperrightcorner,clickthe"Alertme"button.
Thisregistersyoutoreceiveaweeklydigestofproductinformationthathaschanged(ifany).
Forchangedetails,checktherevisionhistoryofanyreviseddocument.
ErrataMSP430F5172DeviceErratasheetDescribestheknownexceptionstothefunctionalspecificationsforallsiliconrevisionsofthedevice.
MSP430F5152DeviceErratasheetDescribestheknownexceptionstothefunctionalspecificationsforallsiliconrevisionsofthedevice.
MSP430F5132DeviceErratasheetDescribestheknownexceptionstothefunctionalspecificationsforallsiliconrevisionsofthedevice.
MSP430F5171DeviceErratasheetDescribestheknownexceptionstothefunctionalspecificationsforallsiliconrevisionsofthedevice.
MSP430F5151DeviceErratasheetDescribestheknownexceptionstothefunctionalspecificationsforallsiliconrevisionsofthedevice.
MSP430F5131DeviceErratasheetDescribestheknownexceptionstothefunctionalspecificationsforallsiliconrevisionsofthedevice.
User'sGuidesMSP430F5xxandMSP430F6xxFamilyUser'sGuideDetailedinformationonthemodulesandperipheralsavailableinthisdevicefamily.
MSP430FlashDeviceBootloader(BSL)User'sGuideTheMSP430bootloader(BSL)letsuserscommunicatewithembeddedmemoryintheMSP430microcontrollerduringtheprototypingphase,finalproduction,andinservice.
Boththeprogrammablememory(flashmemory)andthedatamemory(RAM)canbemodifiedasrequired.
Donotconfusethebootloaderwiththebootstraploaderprogramsfoundinsomedigitalsignalprocessors(DSPs)thatautomaticallyloadprogramcode(anddata)fromexternalmemorytotheinternalmemoryoftheDSP.
MSP430ProgrammingWiththeJTAGInterfaceThisdocumentdescribesthefunctionsthatarerequiredtoerase,program,andverifythememorymoduleoftheMSP430flash-basedandFRAM-basedmicrocontrollerfamiliesusingtheJTAGcommunicationport.
Inaddition,itdescribeshowtoprogramtheJTAGaccesssecurityfusethatisavailableonallMSP430devices.
Thisdocumentdescribesdeviceaccessusingboththestandard4-wireJTAGinterfaceandthe2-wireJTAGinterface,whichisalsoreferredtoasSpy-Bi-Wire(SBW).
MSP430HardwareToolsUser'sGuideThismanualdescribesthehardwareoftheTIMSP-FET430FlashEmulationTool(FET).
TheFETistheprogramdevelopmenttoolfortheMSP430ultra-low-powermicrocontroller.
Bothavailableinterfacetypes,theparallelportinterfaceandtheUSBinterface,aredescribed.
ApplicationReportsMSP43032-kHzCrystalOscillatorsSelectionoftherightcrystal,correctloadcircuit,andproperboardlayoutareimportantforastablecrystaloscillator.
ThisapplicationreportsummarizescrystaloscillatorfunctionandexplainstheparameterstoselectthecorrectcrystalforMSP430ultra-low-poweroperation.
Inaddition,hintsandexamplesforcorrectboardlayoutaregiven.
Thedocumentalsocontainsdetailedinformationonthepossibleoscillatorteststoensurestableoscillatoroperationinmassproduction.
102MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
ti.
comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131DeviceandDocumentationSupportCopyright2010–2018,TexasInstrumentsIncorporatedMSP430System-LevelESDConsiderationsSystem-LevelESDhasbecomeincreasinglydemandingwithsilicontechnologyscalingtowardslowervoltagesandtheneedfordesigningcost-effectiveandultra-low-powercomponents.
ThisapplicationreportaddressesthreedifferentESDtopicstohelpboarddesignersandOEMsunderstandanddesignrobustsystem-leveldesigns:(1)Component-levelESDtestingandsystem-levelESDtesting,theirdifferencesandwhycomponent-levelESDratingdoesnotensuresystem-levelrobustness.
(2)Generaldesignguidelinesforsystem-levelESDprotectionatdifferentlevelsincludingenclosures,cables,PCBlayout,andon-boardESDprotectiondevices.
(3)IntroductiontoSystemEfficientESDDesign(SEED),aco-designmethodologyofon-boardandon-chipESDprotectiontoachievesystem-levelESDrobustness,withexamplesimulationsandtestresults.
Afewreal-worldsystem-levelESDprotectiondesignexamplesandtheirresultsarealsodiscussed.
7.
5RelatedLinksTable7-2listsquickaccesslinks.
Categoriesincludetechnicaldocuments,supportandcommunityresources,toolsandsoftware,andquickaccesstosampleorbuy.
Table7-2.
RelatedLinksPARTSPRODUCTFOLDERORDERNOWTECHNICALDOCUMENTSTOOLS&SOFTWARESUPPORT&COMMUNITYMSP430F5172ClickhereClickhereClickhereClickhereClickhereMSP430F5152ClickhereClickhereClickhereClickhereClickhereMSP430F5132ClickhereClickhereClickhereClickhereClickhereMSP430F5171ClickhereClickhereClickhereClickhereClickhereMSP430F5151ClickhereClickhereClickhereClickhereClickhereMSP430F5131ClickhereClickhereClickhereClickhereClickhere7.
6CommunityResourcesThefollowinglinksconnecttoTIcommunityresources.
Linkedcontentsareprovided"ASIS"bytherespectivecontributors.
TheydonotconstituteTIspecificationsanddonotnecessarilyreflectTI'sviews;seeTI'sTermsofUse.
TIE2ECommunityTI'sEngineer-to-Engineer(E2E)Community.
Createdtofostercollaborationamongengineers.
Ate2e.
ti.
com,youcanaskquestions,shareknowledge,exploreideas,andhelpsolveproblemswithfellowengineers.
TIEmbeddedProcessorsWikiTexasInstrumentsEmbeddedProcessorsWiki.
EstablishedtohelpdevelopersgetstartedwithembeddedprocessorsfromTexasInstrumentsandtofosterinnovationandgrowthofgeneralknowledgeaboutthehardwareandsoftwaresurroundingthesedevices.
7.
7TrademarksMSP430,MSP430Ware,CodeComposerStudio,EnergyTrace,ULPAdvisor,E2EaretrademarksofTexasInstruments.
Allothertrademarksarethepropertyoftheirrespectiveowners.
103MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131www.
ti.
comSLAS619R–AUGUST2010–REVISEDSEPTEMBER2018SubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131DeviceandDocumentationSupportCopyright2010–2018,TexasInstrumentsIncorporated7.
8ElectrostaticDischargeCautionThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
7.
9ExportControlNoticeRecipientagreestonotknowinglyexportorre-export,directlyorindirectly,anyproductortechnicaldata(asdefinedbytheU.
S.
,EU,andotherExportAdministrationRegulations)includingsoftware,oranycontrolledproductrestrictedbyotherapplicablenationalregulations,receivedfromdisclosingpartyundernondisclosureobligations(ifany),oranydirectproductofsuchtechnology,toanydestinationtowhichsuchexportorre-exportisrestrictedorprohibitedbyU.
S.
orotherapplicablelaws,withoutobtainingpriorauthorizationfromU.
S.
DepartmentofCommerceandothercompetentGovernmentauthoritiestotheextentrequiredbythoselaws.
7.
10GlossaryTIGlossaryThisglossarylistsandexplainsterms,acronyms,anddefinitions.
104MSP430F5172,MSP430F5152,MSP430F5132MSP430F5171,MSP430F5151,MSP430F5131SLAS619R–AUGUST2010–REVISEDSEPTEMBER2018www.
ti.
comSubmitDocumentationFeedbackProductFolderLinks:MSP430F5172MSP430F5152MSP430F5132MSP430F5171MSP430F5151MSP430F5131Mechanical,Packaging,andOrderableInformationCopyright2010–2018,TexasInstrumentsIncorporated8Mechanical,Packaging,andOrderableInformationThefollowingpagesincludemechanical,packaging,andorderableinformation.
Thisinformationisthemostcurrentdataavailableforthedesignateddevices.
Thisdataissubjecttochangewithoutnoticeandrevisionofthisdocument.
Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation.
PACKAGEOPTIONADDENDUMwww.
ti.
com21-Feb-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesMSP430F5131IDAACTIVETSSOPDA3840Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5131MSP430F5131IDARACTIVETSSOPDA382000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5131MSP430F5131IRSBRACTIVEWQFNRSB403000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5131MSP430F5131IRSBTACTIVEWQFNRSB40250Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5131MSP430F5131IYFFRACTIVEDSBGAYFF403000Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5131MSP430F5131IYFFTACTIVEDSBGAYFF40250Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5131MSP430F5132IDAACTIVETSSOPDA3840Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5132MSP430F5132IDARACTIVETSSOPDA382000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5132MSP430F5132IRSBRACTIVEWQFNRSB403000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5132MSP430F5132IRSBTACTIVEWQFNRSB40250Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5132MSP430F5132IYFFRACTIVEDSBGAYFF403000Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5132MSP430F5132IYFFTACTIVEDSBGAYFF40250Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5132MSP430F5151IDAACTIVETSSOPDA3840Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5151MSP430F5151IRSBRACTIVEWQFNRSB403000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5151MSP430F5151IRSBTACTIVEWQFNRSB40250Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5151MSP430F5151IYFFRACTIVEDSBGAYFF403000Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5151MSP430F5151IYFFTACTIVEDSBGAYFF40250Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5151PACKAGEOPTIONADDENDUMwww.
ti.
com21-Feb-2020Addendum-Page2OrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesMSP430F5152IDAACTIVETSSOPDA3840Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5152MSP430F5152IDARACTIVETSSOPDA382000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5152MSP430F5152IRSBRACTIVEWQFNRSB403000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5152MSP430F5152IRSBTACTIVEWQFNRSB40250Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5152MSP430F5152IYFFRACTIVEDSBGAYFF403000Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5152MSP430F5152IYFFTACTIVEDSBGAYFF40250Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5152MSP430F5171IDAACTIVETSSOPDA3840Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5171MSP430F5171IDARACTIVETSSOPDA382000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5171MSP430F5171IRSBRACTIVEWQFNRSB403000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5171MSP430F5171IRSBTACTIVEWQFNRSB40250Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5171MSP430F5171IYFFRACTIVEDSBGAYFF403000Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5171MSP430F5171IYFFTACTIVEDSBGAYFF40250Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5171MSP430F5172IDAACTIVETSSOPDA3840Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5172MSP430F5172IDARACTIVETSSOPDA382000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5172MSP430F5172IRSBRACTIVEWQFNRSB403000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5172MSP430F5172IRSBTACTIVEWQFNRSB40250Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85M430F5172MSP430F5172IYFFRACTIVEDSBGAYFF403000Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5172MSP430F5172IYFFTACTIVEDSBGAYFF40250Green(RoHS&noSb/Br)SNAGCULevel-1-260C-UNLIM-40to85M430F5172PACKAGEOPTIONADDENDUMwww.
ti.
com21-Feb-2020Addendum-Page3(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantMSP430F5131IDARTSSOPDA382000330.
024.
48.
613.
01.
812.
024.
0Q1MSP430F5131IRSBRWQFNRSB403000330.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5131IRSBTWQFNRSB40250180.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5131IYFFRDSBGAYFF403000180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5131IYFFTDSBGAYFF40250180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5132IDARTSSOPDA382000330.
024.
48.
613.
01.
812.
024.
0Q1MSP430F5132IRSBRWQFNRSB403000330.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5132IRSBTWQFNRSB40250180.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5132IYFFRDSBGAYFF403000180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5132IYFFTDSBGAYFF40250180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5151IRSBRWQFNRSB403000330.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5151IRSBTWQFNRSB40250180.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5151IYFFRDSBGAYFF403000180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5151IYFFTDSBGAYFF40250180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5152IDARTSSOPDA382000330.
024.
48.
613.
01.
812.
024.
0Q1MSP430F5152IRSBRWQFNRSB403000330.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5152IRSBTWQFNRSB40250180.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5152IYFFRDSBGAYFF403000180.
08.
42.
863.
160.
694.
08.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com1-Jan-2020PackMaterials-Page1DevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantMSP430F5152IYFFTDSBGAYFF40250180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5171IDARTSSOPDA382000330.
024.
48.
613.
01.
812.
024.
0Q1MSP430F5171IRSBRWQFNRSB403000330.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5171IRSBTWQFNRSB40250180.
012.
45.
35.
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0Q2MSP430F5171IYFFRDSBGAYFF403000180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5171IYFFTDSBGAYFF40250180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5172IDARTSSOPDA382000330.
024.
48.
613.
01.
812.
024.
0Q1MSP430F5172IRSBRWQFNRSB403000330.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5172IRSBTWQFNRSB40250180.
012.
45.
35.
31.
18.
012.
0Q2MSP430F5172IYFFRDSBGAYFF403000180.
08.
42.
863.
160.
694.
08.
0Q1MSP430F5172IYFFTDSBGAYFF40250180.
08.
42.
863.
160.
694.
08.
0Q1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)MSP430F5131IDARTSSOPDA382000350.
0350.
043.
0MSP430F5131IRSBRWQFNRSB403000367.
0367.
035.
0MSP430F5131IRSBTWQFNRSB40250210.
0185.
035.
0MSP430F5131IYFFRDSBGAYFF403000182.
0182.
020.
0MSP430F5131IYFFTDSBGAYFF40250182.
0182.
020.
0MSP430F5132IDARTSSOPDA382000350.
0350.
043.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com1-Jan-2020PackMaterials-Page2DevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)MSP430F5132IRSBRWQFNRSB403000367.
0367.
035.
0MSP430F5132IRSBTWQFNRSB40250210.
0185.
035.
0MSP430F5132IYFFRDSBGAYFF403000182.
0182.
020.
0MSP430F5132IYFFTDSBGAYFF40250182.
0182.
020.
0MSP430F5151IRSBRWQFNRSB403000367.
0367.
035.
0MSP430F5151IRSBTWQFNRSB40250210.
0185.
035.
0MSP430F5151IYFFRDSBGAYFF403000182.
0182.
020.
0MSP430F5151IYFFTDSBGAYFF40250182.
0182.
020.
0MSP430F5152IDARTSSOPDA382000350.
0350.
043.
0MSP430F5152IRSBRWQFNRSB403000367.
0367.
035.
0MSP430F5152IRSBTWQFNRSB40250210.
0185.
035.
0MSP430F5152IYFFRDSBGAYFF403000182.
0182.
020.
0MSP430F5152IYFFTDSBGAYFF40250182.
0182.
020.
0MSP430F5171IDARTSSOPDA382000350.
0350.
043.
0MSP430F5171IRSBRWQFNRSB403000367.
0367.
035.
0MSP430F5171IRSBTWQFNRSB40250210.
0185.
035.
0MSP430F5171IYFFRDSBGAYFF403000182.
0182.
020.
0MSP430F5171IYFFTDSBGAYFF40250182.
0182.
020.
0MSP430F5172IDARTSSOPDA382000350.
0350.
043.
0MSP430F5172IRSBRWQFNRSB403000367.
0367.
035.
0MSP430F5172IRSBTWQFNRSB40250210.
0185.
035.
0MSP430F5172IYFFRDSBGAYFF403000182.
0182.
020.
0MSP430F5172IYFFTDSBGAYFF40250182.
0182.
020.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com1-Jan-2020PackMaterials-Page3www.
ti.
comPACKAGEOUTLINEC5.
154.
855.
154.
850.
80.
70.
050.
002X3.
636X0.
42X3.
640X0.
50.
340X0.
250.
153.
50.
1(0.
2)TYPWQFN-0.
8mmmaxheightRSB0040BPLASTICQUADFLATPACK-NOLEAD4219094/A11/20180.
08C0.
1CAB0.
05NOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
PIN1INDEXAREASEATINGPLANEPIN1IDSYMMEXPOSEDTHERMALPADSYMM11011202130314041SCALE3.
000ABwww.
ti.
comEXAMPLEBOARDLAYOUT36X(0.
4)(R0.
05)TYP0.
05MAXALLAROUND0.
05MINALLAROUND40X(0.
6)40X(0.
2)(4.
8)(4.
8)(3.
5)(0.
2)TYPVIA(0.
6)TYP(0.
9)TYP(0.
6)TYP(0.
9)TYPWQFN-0.
8mmmaxheightRSB0040BPLASTICQUADFLATPACK-NOLEAD4219094/A11/2018NOTES:(continued)4.
Thispackageisdesignedtobesolderedtoathermalpadontheboard.
Formoreinformation,seeTexasInstrumentsliteraturenumberSLUA271(www.
ti.
com/lit/slua271).
5.
Viasareoptionaldependingonapplication,refertodevicedatasheet.
Ifanyviasareimplemented,refertotheirlocationsshownonthisview.
Itisrecommendedthatviasunderpastebefilled,pluggedortented.
SYMMSYMMLANDPATTERNEXAMPLEEXPOSEDMETALSHOWNSCALE:20XSEESOLDERMASKDETAIL11011202130314041METALEDGESOLDERMASKOPENINGEXPOSEDMETALMETALUNDERSOLDERMASKSOLDERMASKOPENINGEXPOSEDMETALNONSOLDERMASKDEFINED(PREFERRED)SOLDERMASKDEFINEDSOLDERMASKDETAILSwww.
ti.
comEXAMPLESTENCILDESIGN40X(0.
6)40X(0.
2)36X(0.
4)(4.
8)(4.
8)9X(1)(R0.
05)TYP(1.
2)TYP(1.
2)TYPWQFN-0.
8mmmaxheightRSB0040BPLASTICQUADFLATPACK-NOLEAD4219094/A11/2018NOTES:(continued)6.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
SOLDERPASTEEXAMPLEBASEDON0.
125MMTHICKSTENCILSCALE:20XEXPOSEDPAD4173%PRINTEDSOLDERCOVERAGEBYAREAUNDERPACKAGESYMMSYMM11011202130314041METALTYPD:Max=E:Max=3.
09mm,Min=2.
79mm,Min=3.
03mm2.
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