Delayipower

ipower  时间:2021-01-11  阅读:()
REV.
0AD1833AInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
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O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781/329-4700www.
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comFax:781/326-87032003AnalogDevices,Inc.
Allrightsreserved.
Multichannel,24-Bit,192kHz,-DACFEATURES5VStereoAudioSystemwith3.
3VTolerantDigitalInterfaceSupports96kHzSampleRateson6Channelsand192kHzon2ChannelsSupports16-/20-/24-BitWordLengthsMultibit-ModulatorswithPerfectDifferentialLinearityRestorationforReducedIdleTonesandNoiseFloorDataDirectedScramblingDACs—LeastSensitivetoJitterDifferentialOutputforOptimumPerformanceDACsSignal-to-NoiseandDynamicRange:110dB–94dBTHD+N—6-ChannelMode–95dBTHD+N—2-ChannelModeOn-ChipVolumeControlperChannelwith1024-StepLinearScaleSoftwareControllableClicklessMuteDigitalDe-emphasisProcessingSupports256fS,512fS,and768fSMasterClockModesPower-DownModePlusSoftPower-DownModeFlexibleSerialDataPortwithRight-Justified,Left-Justified,I2SCompatible,andDSPSerialPortModesSupportsPackedDataModeandTDMMode48-LeadLQFPPlasticPackageAPPLICATIONSDVDVideoandAudioPlayersHomeTheaterSystemsAutomotiveAudioSystemsSet-TopBoxesDigitalAudioEffectsProcessorsFUNCTIONALBLOCKDIAGRAMAGNDDGNDFILTRFILTDMCLKCDATACLATCHCCLKOUTLP1OUTLN1OUTLP2OUTLN2OUTLP3OUTLN3OUTRP3OUTRN3OUTRP2OUTRN2OUTRP1OUTRN1ZEROFLAGSDVDD1DVDD2AVDDRESETSOUTAD1833ASPIPORTDATAPORTL/RCLKBCLKSDIN1SDIN2SDIN3INTERPOLATORDACINTERPOLATORDACINTERPOLATORDACINTERPOLATORDACINTERPOLATORDACFILTERENGINEINTERPOLATORDACGENERALDESCRIPTIONTheAD1833Aisacomplete,highperformance,single-chip,multichannel,digitalaudioplaybacksystem.
Itfeaturessixaudioplaybackchannels,eachcomprisingahighperformancedigitalinterpolationfilter,amultibitS-DmodulatorfeaturingAnalogDevices'patentedtechnology,andacontinuous-timevoltage-outanalogDACsection.
Otherfeaturesincludeanon-chipclicklessattenuatorandmutecapabilityforeachchannel,programmedthroughanSPIcompatibleserialcontrolport.
TheAD1833AisfullycompatiblewithallknownDVDformats,accommodatingwordlengthsofupto24bitsatsampleratesof48kHzand96kHzonallsixchannelswhilesupportinga192kHzsamplerateontwochannels.
ItalsoprovidestheRedbookstan-dard50ms/15msdigitalde-emphasisfiltersatsampleratesof32kHz,44.
1kHz,and48kHz.
TheAD1833AhasaveryflexibleserialdatainputportthatallowsgluelessinterconnectiontoavarietyofADCs,DSPchips,AES/EBUreceivers,andsamplerateconverters.
Itcanbecon-figuredinright-justified,left-justified,I2S,orDSPserialportcompatiblemodes.
TheAD1833AacceptsserialaudiodatainMSBfirst,twoscomplementformat.
TheAD1833Acanbeoperatedfromasingle5Vpowersupply;italsofeaturesaseparatesupplypinforitsdigitalinterfacethatallowsittobeinterfacedtodevicesusing3.
3Vpowersupplies.
TheAD1833Aisfabricatedonasinglemonolithicintegratedcircuitandishousedina48-leadLQFPpackageforoperationfrom–40∞Cto+85∞C.
AD1833A*PRODUCTPAGEQUICKLINKSLastContentUpdate:02/23/2017COMPARABLEPARTSViewaparametricsearchofcomparableparts.
DOCUMENTATIONApplicationNotesAN-214:GroundRulesforHighSpeedCircuitsDataSheetAD1833A:Multi-Channel,24-bit,192kHz,Sigma-DeltaDACDataSheetDESIGNRESOURCESAD1833AMaterialDeclarationPCN-PDNInformationQualityAndReliabilitySymbolsandFootprintsDISCUSSIONSViewallAD1833AEngineerZoneDiscussions.
SAMPLEANDBUYVisittheproductpagetoseepricingoptions.
TECHNICALSUPPORTSubmitatechnicalquestionorfindyourregionalsupportnumber.
DOCUMENTFEEDBACKSubmitfeedbackforthisdatasheet.
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REV.
0–2–AD1833A–SPECIFICATIONSParameterMinTypMaxUnitTestConditionsANALOGPERFORMANCEDIGITAL-TO-ANALOGCONVERTERSDynamicRange(20Hzto20kHz,–60dBFSInput)withA-WeightedFilterAD1833AA106.
5110.
0dBAD1833AA110.
5dBfS=96kHzAD1833AC107.
0dBTotalHarmonicDistortion+Noise–95–89dBTwochannelsactive–94dBSixchannelsactive–95dB96kHz,twochannelsactive–94dB96kHz,sixchannelsactiveSNR110dBInterchannelIsolation108dBDCAccuracyGainError±3%InterchannelGainMismatch0.
2%GainDrift80ppm/∞CInterchannelCrosstalk(EIAJMethod)–120dBInterchannelPhaseDeviation±0.
1DegreesVolumeControlStepSize(1023LinearSteps)0.
098%VolumeControlRange(MaxAttenuation)+63.
5(0.
098)dB(%)MuteAttenuation–63.
5(0.
098)dB(%)De-emphasisGainError±0.
1dBFull-ScaleOutputVoltageatEachPin(Single-Ended)1(2.
8)Vrms(Vp-p)OutputResistanceMeasuredDifferentially150WCommon-ModeOutputVolts2.
2VDACINTERPOLATIONFILTER—8Mode(48kHz)PassBand21.
768kHzPass-BandRipple±0.
01dBStopBand24kHzStop-BandAttenuation70dBGroupDelay510msDACINTERPOLATIONFILTER—4Mode(96kHz)PassBand37.
7kHzPass-BandRipple±0.
03dBStopBand55.
034kHzStop-BandAttenuation70dBGroupDelay160msDACINTERPOLATIONFILTER—2Mode(192kHz)PassBand89.
954kHzPass-BandRipple±1dBStopBand104.
85kHzStop-BandAttenuation70dBGroupDelay140msTESTCONDITIONS,UNLESSOTHERWISENOTED*SupplyVoltages(AVDD,DVDDX)5VAmbientTemperature25∞CInputClock12.
288MHz,(8Mode)InputSignalNominally1kHz,0dBFS(Full-Scale)InputSampleRate48kHzMeasurementBandwidth20Hzto20kHzWordWidth24BitsLoadCapacitance100pFLoadImpedance10kW*Performanceisidenticalforallchannels(exceptfortheInterchannelGainMismatchandInterchannelPhaseDeviationspecifications).
REV.
0–3–AD1833AParameterMinTypMaxUnitTestConditionsDIGITALI/OInputVoltageHI2.
4VInputVoltageLO0.
8VOutputVoltageHIDVDD2–0.
4VOutputVoltageLO0.
4VPOWERSUPPLIESSupplyVoltage(AVDDandDVDD1)4.
555.
5VSupplyVoltage(DVDD2)3.
3DVDD1VSupplyCurrentIANALOG38.
542mASupplyCurrentIDIGITAL4248mAActive2mAPower-DownPowerSupplyRejectionRatio1kHz300mVp-pSignalatAnalogSupplyPins–60dB20kHz300mVp-pSignalatAnalogSupplyPins–50dBSpecificationssubjecttochangewithoutnotice.
DIGITALTIMINGParameterMinMaxUnitCommentsMASTERCLOCKANDRESETtMLMCLKLO(AllModes)*15ns24MHzclock,clockdoublerbypassedtMHMCLKHI(AllModes)*15ns24MHzclock,clockdoublerbypassedtPDRPD/RSTLO20nsSPIPORTtCCHCCLKHIPulsewidth20nstCCLCCLKLOPulsewidth20nstCCPCCLKPeriod80nstCDSCDATASetupTime10nsToCCLKrisingtCDHCDATAHoldTime10nsFromCCLKrisingtCLSCLATCHSetup10nsToCCLKrisingtCLHCLATCHHold10nsFromCCLKrisingDACSERIALPORTtDBHBCLKHI15nstDBLBCLKLO15nstDLSL/RCLKSetup10nsToBCLKrisingtDLHL/RCLKHold10nsFromBCLKrisingtDDSSDATASetup10nsToBCLKrisingtDDHSDATAHold15nsFromBCLKrisingTDMMODEMASTERtTMBDBCLKTDMDelay20nsFromMCLKrisingtTMFSDFSTDMDelay10nsFromBCLKTDMrisingtTMDDSSDIN1Setup15nsToBCLKTDMfallingtTMDDHSDIN1Hold15nsFromBCLKTDMfallingTDMMODESLAVEfTSBBCLKTDMFrequency256fStTSBCHBCLKTDMHigh20nstTSBCLBCLKTDMLow20nstTSFSFSTDMSetup10nsToBCLKTDMfallingtTSFHFSTDMHold10nsFromBCLKTDMfallingtTSDDSSDIN1Setup15nsToBCLKTDMfallingtTSDDHSDIN1Hold15nsFromBCLKTDMfallingAUXILIARYINTERFACEtAXLRDL/RCLKDelay10nsFromBCLKfallingtAXDDDataDelay10nsFromBCLKfallingtAXBDAUXBCLKDelay20nsFromMCLKrising*MCLKsymmetrymustbebetterthan60:40or40:60.
Specificationssubjecttochangewithoutnotice.
(Guaranteedover–40Cto+85C,AVDD=DVDD=5V10%)REV.
0–4–AD1833AMCLKtMHPD/RSTtMLtPDRFigure1.
MCLKandRESETTimingCLATCHCCLKCIND0D15D14D8tCCHtCCLD9tCDStCDHtCLStCLHtCCPFigure2.
SPIPortTimingBCLKL/RCLKSDATALEFT-JUSTIFIEDMODESDATARIGHT-JUSTIFIEDMODELSBSDATAI2SMODEMSBMSB-1MSBMSBtDBHtDBLtDLStDDStDDHtDDStDLHtDDHtDDStDDStDDHtDDHFigure3.
SerialPortTimingMSBtTMBDtTMFSDtTMDDStTMDDHMCLKBCLKTDMFSTDMSDIN1tTSBCLtTSBCHtTSDDHtTSDDStTSFStTSFHFigure4.
TDMMasterandSlaveModeTimingREV.
0AD1833A–5–ABSOLUTEMAXIMUMRATINGS*(TA=25∞C,unlessotherwisenoted.
)AVDD,DVDDXtoAGND,DGND0.
3Vto+6.
5VAGNDtoDGND0.
3Vto+0.
3VDigitalI/OVoltagetoDGND0.
3VtoDVDD2+0.
3VAnalogI/OVoltagetoAGND0.
3VtoAVDD+0.
3VOperatingTemperatureRangeIndustrial(AVersion)40∞Cto+85∞CStorageTemperatureRange65∞Cto+150∞CMaximumJunctionTemperature150∞CLQFP,qJAThermalImpedance91∞C/WLeadTemperature,SolderingVaporPhase(60sec)215∞CInfrared(15sec)220∞C*StressesabovethoselistedunderAbsoluteMaximumRatingsmaycauseperma-nentdamagetothedevice.
Thisisastressratingonly;functionaloperationofthedeviceattheseoranyotherconditionsabovethoselistedintheoperationalsectionsofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
Onlyoneabsolutemaximumratingmaybeappliedatanyonetime.
MSBMCLKAUXBCLKAUXL/RCLKAUXDATAtAXDDtAXLRDtAXBDFigure5.
AuxiliaryInterfaceTimingORDERINGGUIDEModelTemperatureRangePackageDescriptionPackageOptionAD1833AAST–40∞Cto+85∞CLowProfileQuadFlatPackageST-48AD1833ACST–40∞Cto+85∞CLowProfileQuadFlatPackageST-48EVAL-AD1833AEBEvaluationBoardAD1833AAST-REEL–40∞Cto+85∞CLowProfileQuadFlatPackageST-48AD1833ACST-REEL–40∞Cto+85∞CLowProfileQuadFlatPackageST-48CAUTIONESD(electrostaticdischarge)sensitivedevice.
Electrostaticchargesashighas4000Vreadilyaccumulateonthehumanbodyandtestequipmentandcandischargewithoutdetection.
AlthoughtheAD1833AfeaturesproprietaryESDprotectioncircuitry,permanentdamagemayoccurondevicessubjectedtohighenergyelectrostaticdischarges.
Therefore,properESDprecautionsarerecommendedtoavoidperformancedegradationorlossoffunctionality.
REV.
0AD1833A–6–PINCONFIGURATION363534333231302928272625131415161718192021222324123456789101112484746454439383743424140PIN1IDENTIFIERTOPVIEW(NottoScale)OUTRP1OUTRN1AVDDAVDDAGNDAGNDAGNDOUTLP1OUTLN1AVDDAVDDAGNDAGNDAGNDDGNDDVDD1ZEROAZERO3RDGNDDVDD2RESETZERO1LAD1833AZERO3LZERO1ROUTLN2OUTLP2OUTLN3OUTLP3AVDDFILTDFILTRAGNDOUTRP3OUTRN3OUTRP2OUTRN2ZERO2RCLATCHCDATACCLKL/RCLKBCLKMCLKSDIN1SDIN2SDIN3SOUTZERO2LPINFUNCTIONDESCRIPTIONSPinNo.
MnemonicIN/OUTDescription1OUTLP1ODAC1LeftChannelPositiveOutput.
2OUTLN1ODAC1LeftChannelNegativeOutput.
3,4,33,34,44AVDDAnalogSupply.
5,6,7,30,31,32,41AGNDAnalogGround.
8,29DGNDDigitalGround.
9DVDD1DigitalSupplytoCoreLogic.
10ZEROAOFlagtoIndicateZeroInputonAllChannels.
11ZERO3ROFlagtoIndicateZeroInputonChannel3Right.
12ZERO3LOFlagtoIndicateZeroInputonChannel3Left.
13ZERO2ROFlagtoIndicateZeroInputonChannel2Right.
14CLATCHILatchInputforControlData(SPIPort).
15CDATAISerialControlDataInput(SPIPort).
16CCLKIClockInputforControlData(SPIPort).
17L/RCLKI/OLeft/RightClockforDACDataInput;FSTDMInputinTDMSlaveMode;FSTDMOutputinTDMMasterMode.
18BCLKI/OBitClockforDACDataInput;BCLKTDMInputinTDMSlaveMode;BCLKTDMOutputinTDMMasterMode.
19MCLKIMasterClockInput.
20SDIN1IDataInputforChannel1Left/Right(DataStreamInputinTDMandPackedModes).
21SDIN2I/ODataInputforChannel2Left/Right(L/RCLKOutputtoAuxiliaryDACinTDMMode).
22SDIN3I/ODataInputforChannel3Left/Right(BCLKOutputtoAuxiliaryDACinTDMMode).
23SOUTOAuxiliaryI2SOutput(AvailableinTDMMode).
24ZERO2LOFlagtoIndicateZeroInputonChannel2Left.
25ZERO1ROFlagtoIndicateZeroInputonChannel1Right.
26ZERO1LOFlagtoIndicateZeroInputonChannel1Left.
27RESETIPower-DownandResetControl.
28DVDD2PowerSupplytoOutputInterfaceLogic.
35OUTRN1ODAC1RightChannelNegativeOutput.
36OUTRP1ODAC1RightChannelPositiveOutput.
37OUTRN2ODAC2RightChannelNegativeOutput.
38OUTRP2ODAC2RightChannelPositiveOutput.
39OUTRN3ODAC3RightChannelNegativeOutput.
REV.
0AD1833A–7–DEFINITIONOFTERMSDynamicRangeTheratioofafull-scaleinputsignaltotheintegratedinputnoiseinthepassband(20Hzto20kHz),expressedindecibels.
Dynamicrangeismeasuredwitha–60dBinputsignalandisequalto(S/[THD+N])+60dB.
Notethatspuriousharmonicsarebelowthenoisewitha–60dBinput,sothenoiselevelestablishesthedynamicrange.
ThedynamicrangeisspecifiedwithandwithoutanA-Weightfilterapplied.
Signalto(TotalHarmonicDistortion+Noise)[S/(THD+N)]Theratiooftheroot-mean-square(rms)valueofthefundamentalinputsignaltothermssumofallotherspectralcomponentsinthepassband,expressedindecibels.
PassBandTheregionofthefrequencyspectrumunaffectedbytheattenuationofthedigitaldecimator'sfilter.
Pass-BandRippleThepeak-to-peakvariationinamplituderesponsefromequal-amplitudeinputsignalfrequencieswithinthepassband,expressedindecibels.
StopBandTheregionofthefrequencyspectrumattenuatedbythedigitaldecimator'sfiltertothedegreespecifiedbystop-bandattenuation.
GainErrorWithanearfull-scaleinput,theratioofactualoutputtoexpectedoutput,expressedasapercentage.
InterchannelGainMismatchWithidenticalnearfull-scaleinputs,theratioofoutputsofthetwostereochannels,expressedindecibels.
GainDriftChangeinresponsetoanearlyfull-scaleinputwithachangeintemperature,expressedasparts-per-million(ppm/∞C).
Crosstalk(EIAJMethod)Ratioofresponseononechannelwithagroundedinputtoafull-scale1kHzsinewaveinputontheotherchannel,expressedindecibels.
PowerSupplyRejectionWithnoanaloginput,signalpresentattheoutputwhena300mVp-psignalisappliedtothepowersupplypins,expressedindecibelsoffullscale.
GroupDelayIntuitively,thetimeintervalrequiredforaninputpulsetoappearattheconverter'soutput,expressedinms.
Moreprecisely,thederivativeofradianphasewithrespecttotheradianfrequencyatagivenfrequency.
GroupDelayVariationThedifferenceingroupdelaysatdifferentinputfrequencies.
Specifiedasthedifferencebetweenthelargestandthesmallestgroupdelaysinthepassband,expressedinms.
PINFUNCTIONDESCRIPTIONS(continued)PinNo.
MnemonicIN/OUTDescription40OUTRP3ODAC3RightChannelPositiveOutput.
42FILTRReference/FilterCapacitorConnection.
Recommend0.
1mF/10mFdecoupletoanalogground.
43FILTDFilterCapacitorConnection.
Recommend0.
1mF/10mFdecoupletoanalogground.
45OUTLP3ODAC3LeftChannelPositiveOutput.
46OUTLN3ODAC3LeftChannelNegativeOutput.
47OUTLP2ODAC2LeftChannelPositiveOutput.
48OUTLN2ODAC2LeftChannelNegativeOutput.
REV.
0AD1833A–8–0.
01000.
20.
40.
60.
81.
01.
21.
41.
61.
82.
00.
0080.
0060.
0040.
0020–0.
002–0.
004–0.
006–0.
008–0.
010dBHz104TPC1.
Pass-BandResponse,8Mode102.
002.
052.
102.
152.
202.
252.
302.
352.
402.
452.
500–10–20–30dBHz104–40–50–60–70–80–90–100TPC2.
TransitionBandResponse,8Mode00.
51.
52.
02.
53.
00–20–40–60–80–100–120–140–160dBHz1051.
0TPC3.
CompleteResponse,8Mode–TypicalPerformanceCharacteristics0.
1000.
51.
01.
52.
02.
53.
03.
50.
080.
060.
040.
020–0.
02–0.
04–0.
06–0.
08–0.
10dBHz104TPC4.
Pass-BandResponse,4Mode0.
500.
51.
01.
52.
02.
53.
03.
54.
00.
40.
30.
20.
10–0.
1–0.
2–0.
3–0.
4–0.
5dBHz104TPC5.
40kHzPass-BandResponse,4Mode104.
04.
24.
44.
64.
85.
05.
25.
45.
65.
86.
00–10–20–30dBHz104–40–50–60–70–80–90–100TPC6.
TransitionBandResponse,4ModeREV.
0AD1833A–9–00.
51.
52.
00–20–40–60–80–100–120–140–160dBHz1051.
02.
53.
0TPC7.
CompleteResponse,4Mode2.
00123456781.
50.
50–0.
5–1.
0–1.
5–2.
0dBHz1041.
0TPC8.
80kHzPass-BandResponse,2Mode100.
800.
850.
900.
951.
001.
051.
101.
151.
200–10–20–30dBHz105–40–50–60–70–80–90–100TPC9.
TransitionBandResponse,2Mode00.
51.
52.
00–20–40–60–80–100–120–140–160dBHz1051.
0TPC10.
CompleteResponse,2ModeREV.
0AD1833A–10–FUNCTIONALDESCRIPTIONDeviceArchitectureTheAD1833Aisasix-channelaudioDACfeaturingmultibitsigma-delta(S-D)technology.
TheAD1833Afeaturesthreestereoconverters(providingsixchannels);eachstereochanneliscon-trolledbyacommonbit-clock(BCLK)andsynchronizationsignal(L/RCLK).
GeneralOverviewTheAD1833AisdesignedtorunwithaninternalMCLK(IMCLK)of24.
576MHzandamodulatorrateof6.
144MHz(i.
e.
,IMCLK/4).
FromthisIMCLKfrequency,sampleratesof48kHzand96kHzcanbeachievedonsixchannelsor192kHzcanbeachievedontwochannels.
Theinternalclockshouldneverberunatahigherfrequencybutmaybereducedtoachievelowersamplingrates,i.
e.
,forasamplerateof44.
1kHz,theappro-priateinternalMCLKis22.
5792MHz.
ThemodulatorratescalesinproportionwiththeMCLKscaling.
InterpolatorTheinterpolatorconsistsofasmanyasthreestagesofsampleratedoublingandhalf-bandfilteringfollowedbya16-samplezeroorderhold(ZOH).
Thesampleratedoublingisachievedbyzerostuffingtheinputsamples,andadigitalhalf-bandfilterisusedtoremoveanyimagesabovethebandofinterestandtobringthezerosamplestotheircorrectvalues.
TheinterpolatoroutputmustalwaysbeatarateofIMCLK/64.
Dependingontheinterpolationratesselected,one,two,orallthreestagesofdoublingmaybeswitchedin.
ThisallowsforthreedifferentsamplerateinputsforanygivenIMCLK.
ForanIMCLKof24.
576MHz,allthreedoublingstagesareusedwitha48kHzinputsamplerate;witha96kHzinputsamplerate,onlytwodoublingstagesareused;andwitha192kHzinputsamplerate,onlyonedoublingstageisused.
Ineachcase,theinputsamplefrequencyisincreasedto384kHz(IMCLK/64).
TheZOHholdstheinterpolatorsamplesforupsamplingbythemodulator.
Thisisdoneatarate16timestheinterpolatoroutputsamplerate.
ModulatorThemodulatorisa6-bit,secondorderimplementationandusesdatascramblingtechniquestoachieveperfectlinearity.
Themodu-latorsamplestheoutputoftheinterpolatorstage(s)atarateof(IMCLK/4).
OPERATINGFEATURESSPIRegisterDefinitionsTheSPIportallowsflexiblecontrolofthedevice'sprogrammablefunctions.
Itisorganizedaroundnineregisters:sixindividualchannelvolumeregistersandthreecontrolregisters.
EachwriteoperationtotheAD1833ASPIcontrolportrequires16bitsofserialdatainMSB-firstformat.
Thefourmostsignificantbitsareusedtoselectoneofnineregisters(sevenregisteraddressesarereserved),andthebottom10bitsarewrittentothatregister.
Thisallowsawritetooneofthenineregistersinasingle16-bittransaction.
TheSPICCLKsignalisusedtoclockinthedata.
Theincomingdatashouldchangeonthefallingedgeofthissignalandremainvalidduringtherisingedge.
Attheendofthe16CCLKperiods,theCLATCHsignalshouldrisetolatchthedatainternallyintotheAD1833A(seeFigure2).
Theserialinterfaceformatusedonthecontrolportusesa16-bitserialword,asshowninTableI.
The16-bitwordisdividedintoseveralfields:Bits15through12definetheregisteraddress,Bits11and10arereservedandmustbeprogrammedto0,andBits9through0arethedatafield(whichhasspecificdefinitions,dependingontheregisterselected).
TableI.
ControlPortMapRegisterAddressReserved1DataField15214131211109876543210NOTES1Mustbeprogrammedtozero.
2Bit15=MSB.
Bit15Bit14Bit13Bit12RegisterFunction0000DACControl10001DACControl20010DACVolume10011DACVolume20100DACVolume30101DACVolume40110DACVolume50111DACVolume61000DACControl31001Reserved1010Reserved1011Reserved1100Reserved1101Reserved1110Reserved1111ReservedREV.
0AD1833A–11–DACWordWidthTheAD1833Awillacceptinputdatainthreeseparateword-lengths—16bits,20bits,and24bits.
ThewordlengthmaybeselectedbywritingtoControlBits4and3inDACControlRegister1(seeTableV).
TableV.
WordLengthSettingsBit4Bit3WordLength0024Bits0120Bits1016Bits11ReservedPower-DownControlTheAD1833AcanbepowereddownbywritingtoControlBit2inDACControlRegister1(seeTableVI).
TableVI.
Power-DownControlBit2Power-DownSetting0NormalOperation1Power-DownModeInterpolatorModeTheAD1833A'sDACinterpolatorscanbeoperatedinoneofthreemodes—8,4,or2—thencorrespondto48kHz,96kHz,and192kHzmodes,respectively(forIMCLK=24.
576MHz).
TheinterpolatormodemaybeselectedbywritingtoControlBits1and0inDACControlRegister1(seeTableVII).
TableVII.
InterpolatorModeSettingsBit1Bit0InterpolatorMode008x(48kHz)*012x(192kHz)*104x(96kHz)*11Reserved*ForIMCLK=24.
576MHz.
DACCONTROLREGISTER1De-emphasisTheAD1833Ahasabuilt-inde-emphasisfilterthatcanbeusedtodecodeCDsthathavebeenencodedwiththestandardRedbook50ms/15msemphasisresponsecurve.
Threecurvesareavailable,oneeachfor32kHz,44.
1kHz,and48kHzsamplingrates.
ThefiltersmaybeselectedbywritingtoControlBits9and8inDACControlRegister1(seeTableIII).
TableIII.
De-emphasisSettingsBit9Bit8De-emphasis00Disabled0144.
1kHz1032kHz1148kHzDataSerialInterfaceModeTheAD1833A'sserialdatainterfaceisdesignedtoacceptdatainawiderangeofpopularformatsincludingI2S,right-justified(RJ),left-justified(LJ),andflexibleDSPmodes.
TheL/RCLKpinactsasthewordclock(orframesync)toindicatesampleintervalboundaries.
TheBCLKdefinestheserialdataratewhilethedataisinputontheSDIN1–SDIN3pins.
TheserialmodesettingsmaybeselectedbywritingtoControlBits7through5intheDACControlRegister1(seeTableIV).
TableIV.
DataSerialInterfaceModeSettingsBit7Bit6Bit5SerialMode000I2S001RightJustify010DSP011LeftJustify100PackedMode1(256)101PackedMode2(128)110TDMMode111ReservedTableII.
DACControlRegister1FunctionData-WordPower-DownInterpolatorAddressReserved1De-emphasisSerialModeWidthRESETMode15–1211109–87–54–321–000000000=None000=I2S00=24Bits0=Normal00=8(48kHz)201=44.
1kHz001=RJ01=20Bits1=PWRDWN01=2(192kHz)210=32.
0kHz010=DSP10=16Bits10=4(96kHz)211=48.
0kHz011=LJ11=Reserved11=Reserved100=PackMode1(256)101=PackMode2(128)110=TDMMode111=ReservedNOTES1Mustbeprogrammedtozero.
2ForIMCLK=24.
576MHz.
REV.
0AD1833A–12–TableX.
DACControlRegister3FunctionStereoReplicateAddressReserved*Reserved*(192kHz)MCLKSelectZeroDetectReserved*TDMMode15–1211109–654–321010000000=Normal00=IMCLK=MCLK20=ActiveHigh00=Master1=Replicate01=IMCLK=MCLK11=ActiveLow1=Slave10=IMCLK=MCLK2/3*Mustbeprogrammedtozero.
DACCONTROLREGISTER2DACControlRegister2containsindividualchannelmutecontrolsforeachofthesixDACs.
Defaultoperation(bit=0)ismutingoff.
Bits9through6ofControlRegister2arereservedandshouldbeprogrammedtozero(seeTableVIII).
DACCONTROLREGISTER3StereoReplicateTheAD1833AallowsthestereoinformationonChannel1(SDIN1—Left1andRight1)tobecopiedtoChannels2and3(Left/Right2andLeft/Right3).
ThesesignalscanbeusedinanexternalsummingamplifiertoincreasepotentialsignalSNR.
StereoreplicatemodecanbeenabledbywritingtocontrolBit5(seeTableXI).
Notethatreplicationisnotreflectedinthezeroflagstatus.
TableXI.
StereoReplicateBit5StereoMode0Normal1Channel1DataReplicatedonChannels2and3TableVIII.
DACControlRegister2FunctionAddressReserved*Reserved*MuteControl15–1211109–65432100001000Channel6Channel5Channel4Channel3Channel2Channel10=MuteOff0=MuteOff0=MuteOff0=MuteOff0=MuteOff0=MuteOff1=MuteOn1=MuteOn1=MuteOn1=MuteOn1=MuteOn1=MuteOn*Mustbeprogrammedtozero.
TableIX.
MutingControlBit5Bit4Bit3Bit2Bit1Bit0MutingXXXXX1MuteChannel1XXXX1XMuteChannel2XXX1XXMuteChannel3XX1XXXMuteChannel4X1XXXXMuteChannel51XXXXXMuteChannel6REV.
0AD1833A–13–MCLKSelectTheAD1833AallowsthematchingofavailableexternalMCLKfrequenciestotherequiredinternalMCLKrate.
TheMCLKmodificationfactorcanbeselectedfrom2,1,or2/3bywritingtoBit4andBit3ofControlRegister3.
Internally,theAD1833ArequiresanMCLKof24.
576MHzforsampleratesof48kHz,96kHz,and192kHz.
Inthecaseof48kHzdatawithanMCLKof256fS,aclockdoublerisused,whereaswithanMCLKof768fS,adivide-by-3block(3)isfirstimplementedfollowedbyaclockdoubler.
WithanMCLKof512fS,theMCLKispassedthroughunmodified(seeTableXII).
TableXII.
MCLKSettingsBit4Bit3ModificationFactor00MCLK2Internally01MCLK1Internally10MCLK2/3Internally11ReservedChannelZeroStatusTheAD1833Aprovidesindividuallogicoutputstatusindicatorswhenzerodataissenttoachannelfor1024ormoreconsecutivesampleperiodsinallmodesexceptright-justified.
ThereisalsoTableXIV.
MCLKvs.
SampleRateSelectionSamplingRateInterpolatorModeInternalMCLKSuitableExternalMCLKFrequencies(MHz)fS(kHz)RequiredRequired(MHz)MCLK2MCLK1MCLK2/332864416.
384819216.
38424.
576128244.
1888.
2422.
579211.
289622.
579233.
8688176.
4248896424.
57612.
28824.
57636.
8641922TableXV.
VolumeControlRegistersAddressReserved*VolumeControl15–1211109–0001000Channel1VolumeControl(OUTL1)0011Channel2VolumeControl(OUTR1)0100Channel3VolumeControl(OUTL2)0101Channel4VolumeControl(OUTR2)0110Channel5VolumeControl(OUTL3)0111Channel6VolumeControl(OUTR3)*Mustbeprogrammedtozero.
aglobalzeroflagthatindicatesallchannelscontainzerodata.
ThepolarityofthezerosignalisprogrammablebywritingtoControlBit2(seeTableXIII).
Inright-justifiedmode,thesixindividualchannelflagsarebestusedasthreestereozeroflagsbycombiningpairsofthemthroughsuitablelogicgates.
Then,whenboththeleftandrightinputsarezerofor1024clockcycles,i.
e.
,astereozeroinputfor1024sampleperiods,thecombinedresultofthetwoindividualflagswillbecomeactive,indicat-ingastereozero.
TableXIII.
ZeroDetectBit2ChannelZeroStatus0ActiveHigh1ActiveLowDACVolumeControlRegistersTheAD1833Ahassixvolumecontrolregisters,oneforeachofthesixDACchannels.
VolumecontrolisexercisedbywritingtotherelevantregisterassociatedwitheachDAC.
ThissettingisusedtoattenuatetheDACoutput.
Full-scalesetting(all1s)isequivalenttozeroattenuation(seeTableXV).
REV.
0AD1833A–14–I2STimingI2StimingusesanL/RCLKtodefinewhenthedatabeingtrans-mittedisfortheleftchannelandwhenitisfortherightchannel.
TheL/RCLKislowfortheleftchannelandhighfortherightchannel.
Abitclockrunningat64fSisusedtoclockinthedata.
Thereisadelayof1bitclockfromthetimetheL/RCLKsignalchangesstatetothefirstbitofdataontheSDINxlines.
ThedataiswrittenMSBfirstandisvalidontherisingedgeofthebitclock.
Left-JustifiedTimingLeft-justified(LJ)timingusesanL/RCLKtodefinewhenthedatabeingtransmittedisfortheleftchannelandwhenitisfortherightchannel.
TheL/RCLKishighfortheleftchannelandlowfortherightchannel.
Abitclockrunningat64fSisusedLEFTCHANNELRIGHTCHANNELLSB+1LSBMSBL/RCLKINPUTBCLKINPUTSDATAINPUTLSB+2MSB–2MSB–1MSBLSB+1LSBLSB+2MSB–2MSB–1MSBFigure6.
I2STimingDiagramLEFTCHANNELRIGHTCHANNELLSB+1LSBL/RCLKINPUTBCLKINPUTSDATAINPUTLSB+2MSB–2MSB–1MSBLSB+1LSBLSB+2MSB–2MSB–1MSBMSB–1MSBFigure7.
Left-JustifiedTimingDiagramLEFTCHANNELRIGHTCHANNELLSB+1LSBL/RCLKINPUTBCLKINPUTSDATAINPUTLSB+2MSB–2MSB–1LSBMSBLSB+1LSBLSB+2MSB–2MSB–1MSBFigure8.
Right-JustifiedTimingDiagramtoclockinthedata.
ThefirstbitofdataappearsontheSDINxlineswhentheL/RCLKtoggles.
ThedataiswrittenMSBfirstandisvalidontherisingedgeofthebitclock.
Right-JustifiedTimingRight-justified(RJ)timingusesanL/RCLKtodefinewhenthedatabeingtransmittedisfortheleftchannelandwhenitisfortherightchannel.
TheL/RCLKishighfortheleftchannelandlowfortherightchannel.
Abitclockrunningat64fSisusedtoclockinthedata.
ThefirstbitofdataappearsontheSDINx8-bitclockperiods(for24-bitdata)afterL/RCLKtoggles.
InRJmode,theLSBofdataisalwaysclockedbythelastbitclockbeforeL/RCLKtransitions.
ThedataiswrittenMSBfirstandisvalidontherisingedgeofthebitclock.
REV.
0AD1833A–15–TDMModeTiming—InterfacingtoaSHARCInTDMmode,theAD1833Acanbethemasterorslave,depend-ingonBit0inControlRegister3.
Inmastermode,itgeneratesaframesyncsignal(FSTDM)onitsL/RCLKpinandabitclock(BCLKTDM)onitsBCLKpin,whereasinslavemodeitexpectsthesesignalstobeprovided.
ThesesignalsareusedtocontrolthedatatransmissionfromtheSHARC.
ThebitclockmustrunatafrequencyofIMCLK/2andtheinterpolationmodemustbesetto8,whichlimitsTDMmodetofrequenciesof48kHzorless.
Inthismode,alldataiswrittenontherisingedgeofthebitclockandreadonthefallingedgeofthebitclock.
Theframestartswithaframesyncattherisingedgeofthebitclock.
TheSHARCthenstartsoutputtingdataonthenextrisingedgeofthebitclock.
Eachchannelisgivena32-bitclockslot,andthedataisleft-justifiedanduses16,20,or24ofthe32bits.
Anenlargeddiagramdetailingthisisprovided(seeFigure9).
ThedataissentfromtheSHARCtotheAD1833AontheSDIN1pinandprovidedinthefollowingorder:MSBfirst—InternalDACL0,InternalDACL1,InternalDACL2,AUXDACL0,InternalDACR0,InternalDACR1,InternalDACR2,andAUXDACR0.
ThedataiswrittenontherisingedgeofthebitclockandreadbytheAD1833Aonthefallingedgeofthebitclock.
TheleftandrightdatadestinedfortheauxiliaryDACissentinstandardI2SformatinthenextframeusingtheSDIN2,SDIN3,andSOUTpinsastheL/RCLK,BCLK,andSDATApins,respectively,forcommunicatingwiththeauxiliaryDAC.
DSPModeTimingDSPmodetimingusestherisingedgeoftheframesyncsignalontheL/RCLKpintodenotethestartofthetransmissionofadata-word.
Notethatforbothleftandrightchannels,arisingedgeisused;thereforeinthismode,thereisnowaytodeterminewhichdataisintendedfortheleftchannelandwhichisintendedfortheright.
TheDSPwritesdataontherisingedgeofBCLKandtheAD1833Areadsitonthefallingedge.
TheDSPraisestheframesyncsignalontherisingedgeofBCLKandthenproceedstotransmitdata,MSBfirst,onthenextrisingedgeofBCLK.
Thedatalengthcanbe16,20,or24bits.
TheframesyncsignalcanbebroughtlowanytimeatoraftertheMSBistransmitted,butmustbebroughtlowatleastoneBCLKperiodbeforethestartofthenextchanneltransmission.
INTERNALDACL0INTERNALDACL1INTERNALDACL2AUXILIARYDACL0INTERNALDACR0INTERNALDACR1INTERNALDACR2AUXILIARYDACR0FSTDMBCLKTDMMSB24-BITDATA20-BITDATA16-BITDATABCLKTDMMSB–1MSB–2MSB–3MSB–4LSB+8LSB+7LSB+6LSB+5LSB+4LSB+3LSB+2LSB+1LSBMSBMSB–1MSB–2MSB–3MSB–4LSB+4LSB+3LSB+2LSB+1LSBMSBMSB–1MSB–2MSB–3MSB–4LSBFigure9.
TDMModeTimingL/RCLKBCLKSDATAMSBMSB–1MSB–2MSB–4MSB–5MSB–6MSBMSB–1MSB–2MSB–3MSB–4MSB–5MSB–6MSB32BCLKs32BCLKsMSB–3Figure10.
DSPModeTimingREV.
0AD1833A–16–PackedMode128InPackedMode128,allsixdatachannelsarepackedintoonesampleintervalononedatapin.
TheBCLKrunsat128fS;therefore,thereare128BCLKperiodsineachsampleinterval.
Eachsampleintervalisbrokenintoeighttimeslots:sixslotsof20BCLKandtwoof4BCLK.
Inthismode,thedatalengthisrestrictedtoamaximumof20bits.
Thethreeleftchannelsarewrittenfirst,MSBfirst,andthedataiswrittenonthefallingedgeofBCLK.
Afterthethreeleftchannelsarewritten,thereisaspaceoffourBCLK,andthenthethreerightchannelsarewrit-ten.
TheL/RCLKdefinestheleftandrightdatatransmission;itishighforthethreeleftchannelsandlowforthethreerightchannels.
PackedMode256InPackedMode256,allsixdatachannelsarepackedintoonesampleintervalononedatapin.
TheBCLKrunsat256fS;therefore,thereare256BCLKperiodsineachsampleinterval,andeachsampleintervalisbrokenintoeighttimeslotsof32BCLKeach.
Thedatalengthcanbe16,20,or24bits.
Thethreeleftchannelsarewrittenfirst,MSBfirst,andthedataiswrittenonthefallingedgeofBCLKwithaoneBCLKperioddelayfromthestartoftheslot.
Afterthethreeleftchannelsarewritten,thereisaspaceof32BCLK,andthenthethreerightchannelsarewritten.
TheL/RCLKdefinestheleftandrightdatatransmission;itislowforthethreeleftchannelsandhighforthethreerightchannels.
SLOT1LEFT0SLOT2LEFT1SLOT3LEFT2BLANKSLOT4SCLKSLOT4RIGHT0SLOT5RIGHT1SLOT6RIGHT2BLANKSLOT4SCLKDATA20-BITDATA16-BITDATABCLKBCLKMSB–1MSB–2MSB–3MSB–4MSB–1MSB–2MSB–3MSB–4LSB+4LSB+3LSB+2LSB+1MSBLSBLSBMSBL/RCLKFigure11.
PackedMode128SLOT1LEFT0SLOT2LEFT1SLOT3LEFT2SLOT4RIGHT0SLOT5RIGHT1SLOT6RIGHT220-BITDATA24-BITDATA16-BITDATABCLKMSB–1MSB–2MSB–3MSB–4MSB–1MSB–2MSB–3MSB–4LSB+8LSB+7LSB+6LSB+5LSB+4LSB+3LSB+2LSB+1LSB+4LSB+3LSB+2LSB+1MSBLSBLSBLSBMSBMSB–1MSB–2MSB–3MSB–4MSBDATABCLKL/RCLKFigure12.
PackedMode256REV.
0AD1833A–17–204060800–20–40–60–80–100–120–140100120kHzdBR0Figure16.
DynamicRangefor37kHz@–60dBFS,110dB,TriangularDitheredInput204060800–20–40–60–80–100–120–140100120kHzdBR0Figure17.
Input0dBFS@37kHz,BW20Hzto120kHz,SR96kHz,THD+N–95dBFS24680–20–40–60–80–100–120–1401012kHzdBV0–16014161820Figure18.
NoiseFloorforZeroInput,SR48kHz,SNR110dBFSA-Weighted3.
81k270pFNPO11k68pFNPO11kVOUT–5.
62kVOUT+560pFNPO1.
50k5.
62k150pFNPOOP2756042.
2nFNPOVFILTOUT567100pFNPOFigure13.
SuggestedOutputFilterSchematic2468101214160–20–40–60–80–100–120–1401820kHzdBR0Figure14.
DynamicRangefor1kHz@–60dBFS,110dB,TriangularDitheredInput2468101214160–20–40–60–80–100–120–1401820kHzdBR0Figure15.
Input0dBFS@1kHz,BW20Hzto20kHz,SR48kHz,THD+N–95dBFSREV.
0AD1833A–18––90–80–70–60–30–40–50–60–70–80–90–50–40dBFSdBR–100–100–30–20–100–20–110–120Figure20.
THD+NRatiovs.
InputAmplitude,Input1kHz,SR48kHz,24-Bit–90–80–70–60–70–80–90–100–50–40dBFSdBR–100–30–20–100–60–110–120Figure19.
THD+NAmplitudevs.
InputAmplitude,Input1kHz,SR48kHz,24-BitREV.
0AD1833A–19–CLATCHCDATACCLKL/RCLKBCLKSDIN1SDIN2SDIN3SOUTMCLKOUTLP1OUTLN1OUTLP2OUTLN2OUTLP3OUTLN3OUTRP1OUTRN1OUTRP2OUTRN2OUTRP3OUTRN3FILTRFILTDDGND1DGND2GNDDVDD1DVDD2AVDD1AVDD2AVDDAVDDAVDDAD1833A0.
1F+++0.
1F10F0.
1F10F0.
1F10FAVDD5V5V++0.
1F10F0.
1F10F0.
1F10F0.
1F10F++CLATCHCDATACCLKL1+L1–L2+L2–L3+L3–R1+R1–R2+R2–R3+R3–1247484546363538374039424314151617182021222319GNDGNDGNDGNDGNDGND+10F0.
1F+10FRXPRXNFILTAGNDDGNDSDATAFSYNCSCKMCKM0M1M2M3CUCBLVERFERFCO/EOCA/E1CB/E2CC/F0CD/F1CE/F2SELCS12/FCKDIR-CS8414SHLD1SHLD1SHLD1SHLD1DVDDOUTU5TORX17310nF10nF47nF1k75RO5V10k0.
1FL50.
1F10F26111219232418171141528256543227161382120109VA+VD+56241PALDVDDAVDD730631532412983DVDD–INTF22792843333444Figure21.
ExampleDigitalInterfaceREV.
0C02336–0–5/03(0)AD1833A–20–OUTLINEDIMENSIONS48-LeadLowProfileQuadFlatPackage[LQFP]1.
4mmThick(ST-48)DimensionsshowninmillimetersTOPVIEW(PINSDOWN)1121325243637480.
270.
220.
170.
50BSC7.
00BSCSEATINGPLANE1.
60MAX0.
750.
600.
45VIEWA73.
500.
200.
091.
451.
401.
350.
150.
050.
08MAXCOPLANARITYVIEWAROTATED90CCWPIN1INDICATOR9.
00BSCCOMPLIANTTOJEDECSTANDARDSMS-026BBCSEATINGPLANE

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