GPHY3gp.com

ExarCorporation48720KatoRoad,FremontCA,94538(510)668-7000FAX(510)668-7017www.
exar.
comEXSTOR-1XRS10L210SERIALATAII:PORTSELECTORDECEMBER2008REV.
1.
04FEATURESGENERALFEATURESThreeindependent3/1.
5GbpsSATAports.
Connects2hostportsto1deviceport.
Supports3/1.
5Gbpsratedetection/speednegotiation.
Supportspowerdownmodes-Active,partial,slumberandpowerdown.
AdvancedfeaturesconfigurablethroughMDIObus.
PORTMULTIPLIER/SELECTORLOGICFEATURESLowlatencyarchitecture.
SupportsOOBsignalingforSATAapplications.
InternalOOBdetectorsforCOMRESET/COMINITandCOMWAKE.
HIGHSPEEDI/OFEATURESHighspeedoutputswithprogrammablepre-emphasistodrivelonginterconnects.
Selectablehighspeedinputequalizationforoptimumreception.
CompliantwithSATAGen-2i&Gen-2mspecification.
Enablesreliabledatatransmissionover1meterofFR-4and4metersormoreofunequalizedcoppercable.
Supportsspreadspectrumclocking(SSC)toreduceEMI.
PHYSICALFEATURESCMOS0.
13MicronTechnologySingle1.
2VPowerSupply-40°Cto85°CIndustrialTemperatureRangeNoheatsinkorairflowrequired64-QFNand100-PinLQFPPackage1.
0INTRODUCTIONTheXRS10L210isaSerialATAIIPortSelectorat3.
0Gbpsand1.
5Gbps.
ItprovidesafailoverpathfromtwoindependenthoststoasingleSATAdriveandoffersaleadingsolutionforpropagationofhighdatarateSerialATAproductsinawidevarietyofapplications.
TheintegrationofSerialATAPHYlinks,avarietyofdigitallogiccapabilities,rateadjustFIFOs,integratedlow-costclockoscillatorsupport,testandloopbackfeaturesisachievedinalowcostandlowerpowerimplementation.
Theportselectorfunctionisusedwhendualhosts,suchasI/Ocontrollers,mustaccesssingle-portdiskdrivesinhighavailabilitystoragesubsystemswhereredundancyandloadsharingareimportant.
TheoutputsfromtheI/OcontrollersaremultiplexedtoaSerialATAdrivethroughtheportselectorblockoftheXRS10L210.
Active/passiveportselectorinXRS10L210allowstwodifferenthostportstoconnecttothesametargetinordertocreatearedundantpathtothattarget.
IncombinationwithRAID,theXRS10L210allowssystemproviderstobuildfullyredundantsolutions.
Thisavoidsthepresenceofasinglepointoffailure,andenablesafail-overpathinthecaseofhostfailure.
TheXRS10L210includesenhancedfeaturessuchasstaggeredHDDspin-up,powermanagementcontrol,hotplugcapabilityandsupportforlegacysoftware.
TheXRS10L210actsasaretimer,maintainingindependentsignalingdomainsbetweenthedrives,hostsandtheexternalinterconnect.
Thehigh-speedserialinputfeature:selectableequalizationadjustmentandthehigh-speedserialoutputfeature:programmablepre-emphasiscanbeusedtocompensateforISI(Inter-SymbolInterference)andincreasemaximumcabledistances.
XRS10L210meetstightjitterbudgetsinSATAapplications.
Exar'sserialI/Otechnologyenablesreliabledatatransmissionover1meterofFR-4and4metersofunequalizedcoppercable.
Hostanddriveportspeedscanbemixedandmatched,baseduponinherentdataratenegotiationpresentintheSATAIIspecifications.
TheMDIObusallowssimpleconfigurationoftheXRS10L210whenneeded.
Receiveequalization,transmitamplitudeandpre-emphasisandSSCcontrolareallconfigurableviathe2-wireMDIOinterface.
Tosummarize,theportselectorfunctionalityintheXRS10L210allowsreplacementforexpensiveFibreChanneldriveswithcosteffectiveandhighcapacitySATAdrivesinenterpriseclassapplicationswithoutcompromisingonredundancyorperformance.
EXSTOR-1XRS10L2102SERIALATAII:PORTSELECTORREV.
1.
04STANDARDSCOMPLIANCETheXRS10L210iscompliantwiththefollowingindustryspecifications:SerialATA,Revision1.
0aSerialATAII:ExtensionstoSerialATA1.
0a,Revision1.
2SerialATAIIPHYElectricalSpecifications,Revision1.
0SerialATAII:PortSelector,Revision1.
0SerialATAII:Revision2.
6APPLICATIONSSerialATAEnclosuresOtherSerialATAlinkreplicatorapplicationsBuffersforexternallyconnectedlinksHighdensitystorageboxesRAIDSubsystemsAPPLICATIONEXAMPLETheXRS10L210isideallysuitedforusewithinanexternaldriveenclosureasameansofprovidingredundanthostaccesstoensuresystemavailabilityandreliability.
ThisapplicationisshowninFigure1.
TheXRS10L210canbeusedinacombinedSASandSATAstoragesystem.
ThemuxisrequiredinActive/ActiveorActive/Passivefailoversystems.
Inenterprisestorageapplications,FibreChannelandSASdrivesareknownforadualportarchitecturewherecommandscanbesenttoeitherportbydifferenthostsorthesamehost.
ThedualporteddriveallowstwodifferentRAIDcontrollerstoaccessthesamedrive.
Themajoradvantageofthisarchitectureisthatitprovidessystemswithfail-overcapability.
ThesestoragesystemsallowcomponentsofthesystemstobechangedorservicedwhiletheIOisrunning.
SATAdrivesarebeingdeployedintheenterprisesystemswheretheylackdualportcapability.
ThelackofdualportSATAdrivescanbecompensatedforbyusingtheXRS10l210inwhichsingleportSATAdrivescanbeconvertedintodualporteddrives.
OtherapplicationsfortheXRS10L210areindualportedSAS/STPexpanders,NASservers,highavailability,highdensitystoragesub-systemsandtapeemulationmarketwhereSATAdrivesareusedasthestoragemedia.
FIGURE1.
SYSTEMBLOCKDIAGRAMFORXRS10L210INADRIVEENCLOSUREAPPLICATIONSASEXPANDERSASEXPANDERSASXRT10L210SATASASXRT10L210SATAEXSTOR-1XRS10L2103REV.
1.
04SERIALATAII:PORTSELECTORNOTE:1)64PinQFNPinoutPRELIMINARYFIGURE2.
PINOUTOFTHEXRS10L210-64PINQFN(NOTE1)VSSVSS123456789101112131415164847464544434241403938373635343364XRS10L21064-pinQFNTCKTMSTDOTDITRSTPORTSELMDCVSSMDIOVDDVSSVDDVSSVDDCLKSTNCLKSTPVSSVDDSCANMODEVSSAXODXOGVDDACMUREFPCMUREFNVSSARBIASVDDAANTESTPWRDNBVSS17181920212223242526272829303132636261605958575655545352515049VSSVDDAVSSAVSSSORPSORNVDDSOTPSOTNVSSDRACTRESETBHBACTPS_SIDEBAND_BVSSVDDSITN0VSSVSSASIRN0VDDSITP0SIRP0VDDAVSSSIRP1VDDSIRN1SITP1SITN1TMODEEXSTOR-1XRS10L2104SERIALATAII:PORTSELECTORREV.
1.
04FIGURE3.
PINOUTOFTHEXRS10L210-100PINLQFPXRS10L210TRSTPORTSELMDCVSSMDIOVSSNCNCVDDNCNCVSSNCNCVSSNCNCVDDNCNCVSSVSSVDDCLKSTNCLKSTPVDDARBIASVSSACMU_REFNCMU_REFPVDDAXOGXODVSSASCANMODENCNCVDDNCNCNCNCNCVSSNCNCVDDNCNCVSSRESETBDRACTNCNCNCVSSSOTNSOTPVDDSORNSORPVSSVSSAVDDAVSSNCNCVDDNCNCVSSVDDVSSPWRDNBANTESTHBACTPS_SIDEBAND_BVSSVDDVSSSITN1SITP1VDDSIRN1SIRP1VSSVDDAVSSAVSSSIRP0SIRN0VDDSITP0SITN0VSSTCKTMSVDDTDOTDI757473727170696867666564636261605958575655545352517677787980818283848586878889909192939495969798991001234567891011121314151617181920212223242550494847464544434241403938373635343332313029282726EXSTOR-1XRS10L2105REV.
1.
04SERIALATAII:PORTSELECTOR2.
0PINDESCRIPTIONSTABLE1:XRS10L210PINDESCRIPTIONSPINNAMELQFP100PINNUMBERQFN64PINNUMBER(NOTE1)I/OTYPEDESCRIPTIONDATAINTERFACESOTP/SOTN68,6940.
41OCMLACCoupledSerialATAOutputTransmitters.
Theseportscom-municatefromtheXRS10L210todownstreamdevicesSORP/SORN65,6637,38ISerialATAInputReceivers.
TheseportsreceivesignalsfromdownstreamdevicesSITP0/SITN093,9463,64OSerialATAOutputTransmitters.
Theseportscom-municatefromtheXRS10L210toupstreamhosts.
SITP1/SITN182,8152,51SIRP0/SIRN090,9160,61ISerialATAInputReceivers.
Theseportsreceivesignalsfromupstreamhosts.
SIRP1/SIRN185,8455,54CLOCKINTERFACECMU_REFP/CMU_REFN46,4725,26ICMLACCoupledReferenceclockinputXOD43220AnalogCrystaloscillatoroutputXOG4423IAnalogCrystaloscillatorinput,1.
26VmaxMDIOINTERFACESIGNALSMDC38ILVCMOSMDIOclockinput,+3.
3VLVCMOSMDIO510I/OLVCMOSMDIOdataport,+3.
3VLVCMOS.
OpendrainJTAGINTERFACESIGNALSTCK962ILVCMOSJTAGtestclock,+3.
3VLVCMOSTDI1005IJTAGtestdatain,+3.
3VLVCMOSTDO994OJTAGtestdataout,+3.
3VLVCMOS.
OpendrainIfusedtodaisychainJTAGdevices,pullupexter-nallyusing3.
3KOhmresistor.
TMS973IJTAGmodeselect,+3.
3VLVCMOSTRST16IJTAGtestreset,+3.
3VLVCMOS.
Pulllowexter-nallyusing3.
3KOhmresistorfornormaloperationofthedevice.
GENERALCONTROLANDCONFIGURATIONSIGNALS(CMOS)RBIAS4928IAnalogConnectionpointforcalibrationterminationresis-tor.
RESETB7545ILVCMOSActivelowresetpin,+3.
3VLVCMOS.
EXSTOR-1XRS10L2106SERIALATAII:PORTSELECTORREV.
1.
04PWRDNB5231ILVCMOSActivelowpowerdownsignalforchip,+3.
3VLVC-MOS.
DRACT7444OLVCMOSDriveactivityportforexternalLED.
ActiveLow,3.
3VLVCMOS,opendrainHBACT7646OLVCMOS0=Host0selected(status)1=Nohostselected(status)0-1-0-1Toggle=Host1selected(1secstayateachstate)3.
3VLVCMOSPS_SIDEBAND_B7747ILVCMOS+3.
3VLVCMOSPleaserefertoTable2,"HostPortSelec-tion,"onpage8PORTSEL27ILVCMOSPortselectorexternalinputpinwhenthismodeissetintheregister.
Lowselectshostport0,other-wiseport1.
+3.
3VLVCMOSTESTPINANTEST5130OAnalogAnalogtestpinCLKSTN/CLKSTP24,2516,17OCMLACCoupledOutputclocktestpinRESERVEDPINSNC7,8,10,11,13,14,16,17,19,20,27,28,30,31,33,34,35,36,37,39,40,56,57,59,60,71,72NoConnect-Donotconnectthispinduringoper-ationaluse.
SCANMODE4120ILVCMOSForfactoryuseonly,connecttoground.
TMODE7343Forfactoryuseonly,leavefloating.
Donotcon-nectthispinduringoperationaluse.
POWERANDGROUNDSIGNALSTABLE1:XRS10L210PINDESCRIPTIONSPINNAMELQFP100PINNUMBERQFN64PINNUMBER(NOTE1)I/OTYPEDESCRIPTIONEXSTOR-1XRS10L2107REV.
1.
04SERIALATAII:PORTSELECTORVDD9,18,23,29,38,54,58,67,79,83,92,9811,13,15,19,39,49,53,62I1.
2Vsupply.
VDDA45,50,62,8724,29,34,57I1.
2VAnalogsupply.
VSS4,6,12,15,21,22,26,32,53,55,61,64,70,78,80,86,89,951,9,12,14,18,32,33,36,42,48,50,56,59IGround.
VSSA42,48,63,8821,27,35,58IAnalogGround.
TABLE1:XRS10L210PINDESCRIPTIONSPINNAMELQFP100PINNUMBERQFN64PINNUMBER(NOTE1)I/OTYPEDESCRIPTIONEXSTOR-1XRS10L2108SERIALATAII:PORTSELECTORREV.
1.
04TABLE2:HOSTPORTSELECTIONHARDWAREPINSREGISTERSETTINGS-REGISTER0.
009ACOMMENTSPS_SIDEBAND_BPIN77PORTSELPIN2P_SEL_MTHDBIT0P_SIDE_MTHDBIT1P_HOST_SELBIT23.
3VLVCMOS0Selectshostport0=Hostport01=Hostport1x0xHostportisselectedbyhard-warePORTSELpinxSelectshostport0=Hostport01=Hostport110xHostportisselectedbyhard-warePORTSELpin0xx1Selectshostport0=Hostport01=Hostport1Hostportisselectedbyregister0x0.
009Abit2xx11Selectshostport0=Hostport01=Hostport1Hostportisselectedbyregister0x0.
009Abit21x0xxHostportisselectedbyprotocolbasedselectionEXSTOR-1XRS10L2109REV.
1.
04SERIALATAII:PORTSELECTOR3.
0FUNCTIONALDESCRIPTIONAtop-levelviewoftheXRS10L210isshowninFigure4outliningtheinterfacestothedeviceandtherequiredsupportcomponents.
Thedatapathcanbeseenatthetopofthedevice.
Thisincludesthetwooutputtransmitandinputreceivepathsatthetopleft,providingtheupstreaminterfacetothehost,andthetwooutputtransmitandinputreceivepathsatthetopright,providingthedownstreaminterfacetothetargetdevices.
Theclocking,control,andconfigurationinterfacesareshownbelowthedottedline.
TheXRS10L210incorporatesidenticalinstantiationsofadual-channelSerialATAII3GbpsPHYmacro.
Thiscommonbuildingblockprovidesauniformimplementationwithcommoncharacteristicsandacommonregistermap,butprovidesafunctionalimplementationofindependentPHYblocks.
DigitallogicimplementationsofSerialATAlinklayerblocksalongwithportselectorandportmultiplierlogicprovidetheremainderofthedatapathwithintheXRS10L210.
Inaddition,managementandcontrolinterfacesincludinganMDIOinterfaceforregistercontrol,aJTAGinterfaceforboundaryscanpurposes,andaresistorcalibrationcircuitcompletethedevice.
AblockdiagramoftheXRS10L210isshowninFigure5.
FIGURE4.
XRS10L210INTERFACESFIGURE5.
XRS10L210BLOCKDIAGRAMSIT_P/N[1:0]SIR_P/N[1:0]DRACTHBACTRESETBPWRDNBMDCMDIORBIASSOT_P/NSOR_P/NCMU_REF_P/NXODXOGTCKTDITDOTMSTRSTSerialATAUpstreamInterfacetoHBAsControlandStatusInterfaceConfigurationInterfaceSerialATADownstreamInterfacetoDevicesReferenceClockCrystalOscillatorI/OJTAGInterfaceVDDACalibrationResistor49.
9±0.
5%PS_SIDEBAND_BPORTSELSATAII3GPHYSIT0SIR0PORTSELECTORSATAII3GPHYSIT1SIR1SATAIILINKLAYERRATEADJUSTFIFOSATAIILINKLAYERSATAII3GPHYSORSOTEXSTOR-1XRS10L21010SERIALATAII:PORTSELECTORREV.
1.
043.
1OutOfBandFeatureEachSerialATAlinkprovidesfullsupportforthethreeOutOfBand(OOB)signalssupportedbySerialATA:COMRESET,COMINITandCOMWAKE.
ThesesequencesmustbeseparatedbyidleperiodsasshowninFigure6.
Thesequencesarecomprisedof106.
7nsburstsofactivitythatareinterleavedwithvaryinglengthstretchesofelectricalidle.
Thisalternatingsequencemustberepeatedfourtimestoberecognized.
AnexampleOOBsequenceandtheresultingburstandidlewidthsareshowninFigure7.
IfthesequenceofburstWidthandidleWidthcountsfallswithintherangespecifiedintheMDIOregistersforfourconsecutiveburst/idlesequences,thenthelinkwillassertCOMINITorCOMWAKE.
ThisOOBsignalwillremainassertedforaslongasthecorrespondingsequenceontheinputpinscontinues.
FIGURE6.
COMWAKEANDCOMRESET/COMINITSEQUENCESFIGURE7.
EXAMPLEOOBSEQUENCECOMWAKECOMRESETCOMINIT106.
7ns106.
7ns320nsrxdP,rxdNsquelchClock151515COMINT=(MaxBurstWidth≥burstWidth≥MinBurstWidth)&&(MaxInitWidth≥idleWidth≥MinInitWidth)COMWAKE=(MaxBurstWidth≥burstWidth≥MinBurstWidth)&&(MaxWakeWidth≥idleWidthMinWakeWidth)171717idleWidthburstWidthEXSTOR-1XRS10L21011REV.
1.
04SERIALATAII:PORTSELECTOR3.
2PowerDownModesEachSerialATAlinkwithintheXRS10L210featuresindependentsupportfor3powermodesviaMDIOinterface,asfollows:Active:Allpartsofthelinkareactive.
Allpower-downsignalsarede-asserted.
Partial:Inpartialmode,theinputandoutputpipelinesareshutdown,butthePLLandtheOOBgenerationcircuitsareactive.
Slumber:Inslumbermode,thePLLisalsoshutdown,savingadditionalpowerbutaddinglatencyonexit.
3.
3SpeedNegotiationTheXRS10L210willautomaticallyperformspeednegotiationwiththehostanddevicesinordertoverifywhetherthesecondgenerationSerialATA3.
0GbpsdatarateisavailableorwhetherthesystemwillneedtofallbackuponthefirstgenerationSerialATA1.
5Gbpsdatarate.
Speednegotiationisperformedonanindependentbasisbyeachofthedual-channelmacros.
Speednegotiationisdoneindependentlyonallhostanddeviceportsbydefault.
MDIOconfigurationcanrequestacommonnegotiatedspeedonthehostanddeviceportsifsuchaspeedexists.
Toperformspeednegotiationwithadownstreamdevice,theXRS10L210willfirstperformaCOMRESET/COMINIThandshakewiththedeviceandthenperformsacalibrate/COMWAKEhandshake.
FollowingreceiptofthedeviceCOMWAKEsignal,theXRS10L210willcontinuallysendoutaD10.
2signalwhileawaitingreceiptofthedeviceALIGNprimitive.
DependingonthespeedoftheALIGNprimitive,theXRS10L210willbeabletodeterminethePHYgenerationofthedevice,andprovidetheappropriate1.
5Gbpsor3.
0GbpsALIGNprimitiveinreturntothedevice,thuscompletingspeednegotiation.
ThisprocessisoutlinedinFigure8.
Forspeednegotiationwithanupstreamhost,aftertheCOMRESET/COMINITandCOMWAKEhandshakeiscomplete,theXRS10L210willinitiallysendoutanALIGNprimitiveatthe2ndgeneration3.
0Gbpsdatarate.
Ifnoconfirming3.
0GbpsALIGNprimitiveisreceivedfromthehost,theXRS10L210willthenstepdownandattemptnegotiationatthelower1.
5Gbpsdatarate.
3.
4PortselectorImplementationTheXRS10L210providesfullsupportfortheSerialATAIIPortSelectorspecification.
ASerialATAPortSelectorisamechanismthatallowstwodifferenthostportstoconnecttothesamedeviceinordertocreatearedundantpathtothatdevice.
Onlyonehostconnectiontothedeviceisactiveatatime.
FIGURE8.
SERIALATASPEEDNEGOTIATIONEXSTOR-1XRS10L21012SERIALATAII:PORTSELECTORREV.
1.
04ThetwohostportsareresponsibleforcoordinationofaccesstotheXRS10L210byoneoftwoseparatemeans:protocol-basedportselectionorsidebandportselection.
Eachmethodisdescribedindetailinthenexttwosections.
3.
4.
1ProtocolBasedPortSelectionProtocol-basedportselectionmakesuseofasequenceofSerialATAOOBsignalstoselecttheactivehostport.
TheportselectionsignalisbasedonapatternofCOMRESETOOBsignalstransmittedfromthehosttotheXRS10L210.
TheportselectionsignaliscomposedofaseriesofCOMRESETsignalswiththetimingfromoneCOMRESETsignaltothenextasshowninTable3andFigure9.
TheXRS10L210selectstheport,ifinactive,onthede-assertionofCOMRESETafterreceivingtwocompleteback-to-backsequenceswiththisdefinedinter-burstspacing.
ThiscanalsobeidentifiedastwosequencesoftwoCOMRESETintervalscomprisingatotaloffiveCOMRESETburstswithfourinter-burstdelays.
Onceaportisdesignatedasactive,receptionofadditionalCOMRESETsignalsispropagateddirectlytothedevice,eveniftheCOMRESETsignalsconstituteaportselectionsignal.
Notethatwhenprotocolbasedselectionmodehasbeenenabled,followingtheinitialhardwarereset,asingleCOMRESETburstwillselecttheactivehostport.
Afterthisintialhostportselection,onlyCOMRESETOOBobservingtheprotocoltiminggivenbelowwillchangetheactivehost.
3.
4.
2SidebandBasedPortSelectionTheXRS10L210alsofeaturessupportforasidebandportselectionmechanism.
ThisisimplementedusingacombinationoftheMDIOregistersettingsanddevicepinsincludingPS_SIDEBAND_BandPORTSEL.
RefertoTable2forsidebandportselectionsettings.
TABLE3:PORTSELECTORSIGNALINTER-RESETTIMINGREQUIREMENTSNOMINALMIN.
MAXUNITSCOMMENTST12.
01.
62.
4msInter-resetassertiondelayforfirsteventoftheselectionsequenceT28.
07.
68.
4msInter-resetassertiondelayforsecondeventoftheselectionsequenceFIGURE9.
PORTSELECTIONSIGNAL-TRANSMITTEDCOMRESETSIGNALSEXSTOR-1XRS10L21013REV.
1.
04SERIALATAII:PORTSELECTOR3.
5ClockingTheXRS10L210allowstheuseofeitheranexternalreferenceclockorofalowcostcrystaloscillatortoactasareferenceclock.
Separatedeviceinputsareavailableforeachapproach,withfullratereferenceclockinputsprovidedonpinsCMU_REFPandCMU_REFN,andcrystaloscillatorinputsprovidedonpinsXODandXOG.
SupporteddataratesandtheirappropriatePLLdividefactorsareoutlinedinTable4.
NOTE:*Alllinkstartwith3.
0Gbps,thennegotiatedownto1.
5GbpsforSATAGeneration1devices.
3.
5.
1SpreadSpectrumClockingTheXRS10L210providesfullsupportforreceiptandgenerationofsignalsthathavebeenconfiguredforSpreadSpectrumClocking(SSC)support.
Thespreadtechniqueisimplementedbydown-spreadingthedatarateby0.
5%asameansofreducingEMI.
Generationofthedown-spreadclockisperformedwithintheXRS10L210.
AnexampleoftheresultantspectralfundamentalfrequencybeforeandafterSSCcanbeseeninFigure10.
TABLE4:PLLDIVIDEFACTORSMODESYSCLK/REF/FBDINCLKRXCLKSERIALCLOCKDATARATESATAGen.
225MHz160300MHz1.
5GHz3.
0GbpsSATAGen.
250MHz130300MHz1.
5GHz3.
0GbpsSATAGen.
275MHz120300MHz1.
5GHz3.
0GbpsSATAGen.
2100MHz230300MHz1.
5GHz3.
0GbpsSATAGen.
2150MHz110300MHz1.
5GHz3.
0GbpsFIGURE10.
SPREADSPECTRUMCLOCKINGEXSTOR-1XRS10L21014SERIALATAII:PORTSELECTORREV.
1.
044.
0ELECTRICALSPECIFICATIONSThissectioncontainstheelectricalspecificationsfortheXRS10L210.
4.
1SerialATASpecificationsTheXRS10L210electricaltransmitandreceivespecificationsareoutlinedinthissection.
TheXRS10L210isfullycomplianttotheSerialATAIIspecificationforGen2i,Gen2x,Gen2m,Gen1i,Gen1xandGen1mvariationsat3.
0and1.
5Gbps.
4.
1.
1SerialATATransmitterAsimplifiedversionoftheoutputcircuitandtestfixtureforeachofthe3SerialATAtransmitoutputpairsontheXRS10L210isshowninFigure11.
TheoutputdifferentialpairisterminatedtothesupplyVDD.
ThecircuitisdesignedtobeACcoupled.
TheXRS10L210SerialATAoutputsincludeasimpleone-tapequalizer,thatisusefulindrivinglongerprintedcircuittracesandisarequiredcomponentinsecondgenerationSerialATAPHYs.
Thisequalizerpre-emphasizestheoutputsignalwheneverthereisadatatransition.
Theamountofpre-emphasiscanvarybetween0and45.
5%,andisconfiguredviaMDIOregistersettings.
Notethatpre-emphasisdoesn'tincreasetheoverallswing,butinsteadreducestheoutputamplitudewhenthereisnotransition.
FIGURE11.
SERIALATAEQUIVALENTOUTPUTCIRCUITEXSTOR-1XRS10L21015REV.
1.
04SERIALATAII:PORTSELECTORTheoverallswinglevelcanalsobemodifiedviaMDIOregistersettings.
TheXRS10L210transmitmaskisshowninFigure13.
FIGURE12.
EFFECTSOFTRANSMITPRE-EMPHASISFIGURE13.
TRANSMITEYEMASKFORSERIALATAOUTPUTEXSTOR-1XRS10L21016SERIALATAII:PORTSELECTORREV.
1.
044.
1.
2SerialATAReceiverAnequivalentcircuitfortheXRS10L210SerialATAinputsisshowninFigure14.
ThedevicereceivermaskisshowninFigure15.
ThiscircuitisdesignedtobeACcoupled.
Theterminationresistorsarenotconnectedduringpower-upFIGURE14.
SERIALATAEQUIVALENTINPUTCIRCUITFIGURE15.
RECEIVEEYEMASKFORSERIALATAINPUTEXSTOR-1XRS10L21017REV.
1.
04SERIALATAII:PORTSELECTORNOTES:1.
Thisvalueincludes0.
5%downspreadSpreadSpectrumclocking,plus350ppmtolerancearoundthecenterfrequency.
2.
Thisismeasuredatthepackageballanddoesnotincludeanyboardorconnectorloss.
3.
Thisvaluecanbeaslowas5duringpoweron.
TABLE5:SERIALATALINKSPECIFICATIONSNAMEDESCRIPTIONMIN.
NOMMAXUNITStBIT,XSBitTime670-333psJXR1InputJitterToleranceMaskatsignalcrossover0.
32--UIJXR1,DJDeterministicjittertoleranceatsignalcrossover0.
18--UIJXT1Outputjittermaskatsignalcrossover--0.
15UIJXT1,DJDeterministicoutputjitteratsignalcrossover--0.
07UItR/tFInputsignalrise/falltimes(20%-80%)0.
2-0.
46UItQR/tQFOutputsignalrise/falltimes(20%-80%)0.
2-0.
41UItTOL,RX1RXtosysclockfrequencyoffsettolerance-53500350ppmVINInputswing,differentialpeak-peak175-1600mVVSW2Outputswing,differentialpeak-peak800-1200mVVIN,IDLENoswingdetectionthreshold65120155mVRIN,DIFFDifferentialmodeinputresistance85100115RIN,CM3Commonmodeinputresistance405060RIN,OFFCommonmodeinputresistance,nopower200--kRIN,XSOutputterminationresistance405060S11,IN,DIFFDifferentialinputreturnloss,50MHz-1.
5GHz12--dBS11,IN,CMCommonmodeinputreturnloss50MHz-1.
5GHz6--dBS22,OUT,DIFFDifferentialoutputreturnloss50MHz-1.
5GHz12--dBS22,OUT,CMCommonmodeoutputreturnloss50MHz-1.
5GHz6--dBtS,REGSetuptimeforregisterport1.
5--nstH,REGHoldtimeforregisterport1.
5--nstQ,REGClocktoQtimeforregisterport0-2nstCYC,REGRegisterportclockcycletime10--nstHI,REGRregisterportclockhightime4--nstLO,REGRegisterportclocklowtime4--nstRF,REGRegisterportinputrise/falltime--0.
5nsEXSTOR-1XRS10L21018SERIALATAII:PORTSELECTORREV.
1.
044.
2CMOSInterfaceACandDCspecificationsfortheCMOSinputsandoutputsarelistedinTable6.
Sinceallthesesignalsareasynchronous,therearenosetuporholdtimesdefined.
TheCMOSpinsaredefinedintheGeneralControlandConfigurationportionofTable1inSection3,"PinDescriptions".
NOTE:.
1.
Thisvalueismeasureddrivingaloadof20pF.
NOTE:.
2.
Thisvalueismeasuredat2.
5VDC.
4.
3MDIOInterfaceTheManagementDataInput/Output(MDIO)portcomplieswithClause45oftheIEEE802.
3aespecification.
ArepresentativeMDIOdriver/receiverisshowninFigure16.
MDIOusesanopendraindriverwithapullupresistor.
TABLE6:CMOSI/OSPECIFICATIONSNAMEDESCRIPTIONMINNOMMAXUNITStDR/tDF,CMOSCMOSinputsignalrise/falltimes(20%-80%)0.
2-5nstQR/tQF,CMOS1CMOSoutputsignalrise/falltimes(20%-80%)0.
2-5nsVIL,CMOSCMOSinputlowvoltage-0.
300.
8VVIH,CMOSCMOSinputhighvoltage1.
73.
33.
6VVOL,CMOSCMOSoutputlowvoltage-0.
300.
4VVPULLUPOpenDrainPull-upVoltage2.
33.
6VIOL,CMOSOutputcurrentforVOL=0.
4V10-20mAdIOL/dt,CMOSOutputcurrentrateofchange-10-10mA/nsLI,CMOSCMOSI/Oinductance--8nHCI,CMOSCMOSI/Ocapacitance--5pFILEAKAGE2CMOSI/OLeakageCurrent150uAEXSTOR-1XRS10L21019REV.
1.
04SERIALATAII:PORTSELECTORRepresentativeMDIOReadandWritewaveformsareshowninFigure17.
TheXRS10L210samplesMDIOontherisingedgeofMDCforinputanddrivesMDIOaftertherisingedgeofMDCforoutput.
Notethatsetup,hold,andoutputtimingsaredefinedfromthemaximumVILandminimumVIHlevels.
ValuesforMDIOparametersareshowninTable7FIGURE16.
REPRESENTATIVEMDIOCIRCUITFIGURE17.
MDIOINPUTANDOUTPUTWAVEFORMSOpenDrainDriverTootherMDIODevicesPin2.
5V/3.
3VEXSTOR-1XRS10L21020SERIALATAII:PORTSELECTORREV.
1.
04NOTES:1.
MeasuredfromminimumMDIOVIHtomaximumMDCVILforMDIOrisingedge.
MeasuredfrommaximumMDIOVILtomaximumMDCVILforMDIOfallingedge.
2.
MeasuredfromminimumMDCVIHtomaximumMDIOVILforMDIOrisingedge.
MeasuredfromminimumMDCVIHtominimumMDIOVIHforMDIOfallingedge.
3.
MeasuredfromminimumMDCVIHtomaximumMDIOVILforMDIOrisingedgeandMDCrisingedge.
MeasuredfromminimumMDCVIHtominimumMDIOVIHforMDIOfallingedgeandMDCrisingedge.
MeasuredfrommaximumMDCVILtomaximumMDIOVILforMDIOrisingedgeandMDCfallingedge.
MeasuredfrommaximumMDCVILtominimumMDIOVIHforMDIOfallingedgeandMDCfallingedge.
4.
Measureddrivingaloadof470pF.
TABLE7:MDIODCANDACCHARACTERISTICSNAMEDESCRIPTIONMINNOMMAXUNITStCYCLE,MDIOMDCcycletime400--nstLOW,MDCMDClowtime160--nstHIGH,MDCMDChightime160--nstS,MDIO1MDIOinputtoMDCsetuptime10--nstH,MDIO2MDCtoMDIOinputholdtime10--nstQ,MDIO3MDCtoMDIOoutputtime0-150nstDR/tDF,MDIOMDIOinputsignalrise/falltimes(20%-80%)0.
2-100nstQR/tQF,MDIO4MDIOoutputsignalrise/falltimes(20%-80%)0.
2-80nsVIL,MDIOMDIOinputlowvoltage-0.
300.
8VVIH,MDIOMDIOinputhighvoltage1.
73.
33.
6VVOL,MDIO4MDIOoutputlowvoltage-0.
300.
4VVPULLUPOpenDrainPull-upVoltage2.
33.
6VIOL,MDIOMDIOOutputcurrentforVOL=0.
4V10-20mAdIOL/dt,MDIOMDIOOutputcurrentrateofchange-10-10mA/nsLI,MDIOMDIOinputinductance--8nHCI,MDIOMDIOinputcapacitance--5pFTABLE8:OPERATINGCONDITIONSNameDescriptionMinNomMaxUnitsTAAmbienttemperatureunderbias-402585°CVDDCorepowersupplyvoltage1.
141.
21.
26VIDDCorepowersupplycurrent-300400mAEXSTOR-1XRS10L21021REV.
1.
04SERIALATAII:PORTSELECTORVESD1Electrostaticdischargetolerance,HumanBodyModel-AnypinwithrespecttoanyotherpinexceptVDDApins(pins14,34,45,50,62,and87)-14001400VVESD2Electrostaticdischargetolerance,HumanBodyModel-AnypinwithrespecttoVDDApins(pins14,34,45,50,62,and87)-300300VVESD3Electrostaticdischargetolerance,HumanBodyModel-HighspeedIOpins(65,66,68,69,81,82,84,85,90,91,93,94)withrespecttoVSSandVSSApinswhenACcoupledtoVDDApins.
-20002000VθJAJunction-to-ambientthermalresistance38.
50C/WTABLE8:OPERATINGCONDITIONSNameDescriptionMinNomMaxUnitsEXSTOR-1XRS10L21022SERIALATAII:PORTSELECTORREV.
1.
045.
0REGISTERDESCRIPTIONSTheXRS10L210providesavarietyofregistersforthepurposeofdeviceconfiguration,testingandmonitoring.
TheseregistersareaccessedthroughtheMDIOinterface,outlinedin"Section4.
3,MDIOInterface"onpage18.
Operationalregistersavailabletothecustomeraregivenbelow.
Notethatallotheraddressspaceshouldbeleftunmodifiedinordertoensureproperbehaviourofthedevice.
5.
1RegisterOverviewTheXRS10L210portaddressishardwiredto0;thisfieldshouldbesetto0inallpackets.
TheXRS10L210containstwoidenticalinstantiationsofadualSerialATAPHYmacro.
Acommonsetofregistersexistswithineachofthesemacros,andareoutlinedin"Section5.
2,MacroRegisters"onpage23.
MDIOdevicedesignations1-2areusedforeachofthesemacrosasshowninTable9.
RegistersrelatingtotheXRS10L210asawholeareoutlinedin"Section5.
3,XRS10L210DeviceGenericRegisters"onpage28andmakeuseofMDIOdevice0.
TheXRS10L210registersarearrangedas8-bitfieldswith8-bitaddresses.
Thesearemappedintothe16-bitMDIOaddressanddatafieldsbysettingthemostsignificantbyteofeachtobe0.
Anexamplemappingfromamacroaddress/datacombinationtoanMDIOaddress&datacombinationisshowninTable10.
NOTE:Theunusedupper3bitsinFBDIVarealsosetto0duringMDIOwritesandareundefinedduringMDIOreads.
Inthedescriptionofeachregisterfield,thereisanentrydescribingitsread/writestatus.
Thismayfallintooneofthefollowingcategories:RW-registerfieldisread/writeRO-registerfieldisreadonlyLL-LatchingLow-UsedwithbitsthatmonitorsomestateinternaltotheXRS10L210.
Whentheconditionforthebittogolowisreached,thebitstayslowuntilthenexttimeitisread.
Onceitisread,itsvaluerevertstothecur-rentstateoftheconditionitmonitors.
LH-LatchingHigh-Whentheconditionforthebittogohighisreached,thebitstayshighuntilthenexttimeitisread.
Onceitisread,itsvaluerevertstothecurrentstateoftheconditionitmonitors.
SC-WhenanSCbitisset,someactionisinitiated;oncetheactioniscomplete,thebitiscleared.
TABLE9:MDIODEVICEDESIGNATIONSMDIODEVICEDESIGNATIONMACRORELEVANTPINS0XRS10L210DeviceGenericRegistersN/A1SerialATAInputMacroSI0,SI12SerialATAOutputMacro0SOTABLE10:MDIOADDRESSINGMACROADDRESSMACRODATAMDIOADDRESSMDIODATA0x40abcde0x004000000000000abcdeEXSTOR-1XRS10L21023REV.
1.
04SERIALATAII:PORTSELECTOR5.
2MacroRegistersTheregistersoutlinedinthissectionarecommontoeachofthetwoSerialATAdualPHYmacrosasdescribedintheprevioussection.
Assuch,eachlistedregisterispresentineachofthe1,and2MDIOregisterspaces,andwillperformthestatedfunctiononthespecifiedSerialATAlane.
TheregisterswithineachdualPHYmacroaresplitintothefollowingsections:Transmit/Receivelane0registers:Addressrange000*****Transmit/Receivelane1registers:Addressrange001*****PLLregisters:Addressrange010*****Biasgeneratorregisters:Addressrange011*****TABLE11:TRANSMIT/RECEIVELANEREGISTERS(MDIODEVICE1,2)ADDRESSHEXBIT(S)NAMER/WDEFAULTDESCRPTIONN.
0000N.
00207ReservedRW0DONOTMODIFY6SATAPCIEXB_G1RW0Txoutputswingboosterbit(Gen1)0=boostswingby15%1=nominalswing5:1ReservedRW00001DONOTMODIFY0SATAPCIEXB_G2RW0Txoutputswingboosterbit(Gen2)0=boostswingby15%1=nominalswingN.
0001N.
00217:3ReservedRW00000DONOTMODIFY2:0Transmit_Eq0[2:0]Transmit_Eq1[2:0]RW011Transmitpre-emphasiscontrol000=0%transmitpreemphasis001=6.
5%transmitpreemphasis010=13%transmitpreemphasis011=19.
5%transmitpreemphasis100=26%transmitpreemphasis101=32.
5%transmitpreemphasis110=39%transmitpreemphasis111=45.
5%transmitpreemphasisEXSTOR-1XRS10L21024SERIALATAII:PORTSELECTORREV.
1.
04N.
0002N.
00227:67:6mscProg0[1:0]mscProg1[1:0]RW01Receiveequalizationcontrol–boostat1.
5GHz00=Lowestboostlevel01=2ndboostlevel10=3rdboostlevel11=Highestboostlevel5:35:3Beacon_Swing0[2:0]Beacon_Swing1[2:0]RW100TransmitswingsizeforOOBSignals000=800mV001=700mV010=600mV011=500mV100=400mV101=300mV110=200mV111=0mV2:02:0Output_Swing0[2:0]Output_Swing1[2:0]RW100Transmitswingsizeinnormaloperation000=800mV001=700mV010=600mV011=500mV100=400mV101=300mV110=200mV111=0mVN.
0003N.
00237enEqBRW0Enablereceiveequalization0=enableequalization1=disableequalization6:0ReservedRW0010000DONOTMODIFYN.
0015N.
00357ReservedRO-Reserved6:4sysclk25divsel0[2:0]sysclk25divsel1[2:0]RW000Dividerselectionforsysclk->sysclk25000=divideby1(sysclkis25MHz)001=divideby2(sysclkis50MHz)010=divideby3(sysclkis75MHz)011=divideby4(sysclkis100MHz)100=divideby5(sysclkis125MHz)101=divideby6(sysclkis150MHz)110=divideby10(sysclkis250MHz)111=divideby12(sysclkis300MHz)3:0ReservedRW0101DONOTMODIFYTABLE11:TRANSMIT/RECEIVELANEREGISTERS(MDIODEVICE1,2)ADDRESSHEXBIT(S)NAMER/WDEFAULTDESCRPTIONEXSTOR-1XRS10L21025REV.
1.
04SERIALATAII:PORTSELECTORN.
0018N.
00387:3ReservedRW00100DONOTMODIFY2:0txbiasbuffsela0[2:0]txbiasbuffsela1[2:0]RW100TxPredriverswingsizeinnormaloperation000=800mV001=700mV010=600mV011=500mV100=400mV(satadefault)101=300mVTABLE11:TRANSMIT/RECEIVELANEREGISTERS(MDIODEVICE1,2)ADDRESSHEXBIT(S)NAMER/WDEFAULTDESCRPTIONEXSTOR-1XRS10L21026SERIALATAII:PORTSELECTORREV.
1.
04TABLE12:PLLCONFIGURATION(MDIODEVICE1,2)ADDRESSHEXBIT(S)NAMETYPEDEFAULTDESCRIPTIONN.
00407:6ReservedRO-Reserved5:0FBDIV[5:0]RW101101Dividevalueforfeedbackclock110000=divideby5100000=divideby10100001=divideby15100010=divideby20100011=divideby25100101=divideby30100111=divideby50101101=divideby60(defaultfor25MHzRef))Other-reservedN.
00417:6ReservedRO-Reserved5:0REFDIV[5:0]RW010000Dividevaluesforsystemclock010000=divideby1(defaultfor25MHzRef))000000=divideby2000001=divideby3000010=divideby4000011=divideby5000101=divideby6000110=divideby8000111=divideby10001101=divideby12001110=divideby16001111=divideby20Others-reservedN.
00447:6ReservedRO-Reserved5:0SSCMaxRW00000Maximumvalueforspread(setto45,0x2DwhenSSCBypassissetto'0')EXSTOR-1XRS10L21027REV.
1.
04SERIALATAII:PORTSELECTORNOTE:1)InordertoenableSSCgeneration,setregisterN.
0044to0x2D,N.
0045to0x14andthenresetthePLLbywritingregister0.
0004to0x0then0xF.
N.
0045NOTE17:5RO-Reserved4SSCmodeRW0Selectspositionofspreadinginterpolator0=Interpolatorinfeedbackpath1=Interpolatorinfeedforwardpath(Setto'1'whenSSCBypass='0')3ReservedRW0DONOTMODIFY2SSCInvertRW0InvertingSSCprofile-SettingfordownspreadperSATAspecSetto'0'whenSSCmode='0'Setto'1'whenSSCmode='1'1ReservedRW0DONOTMODIFY0SSCBypassRW1Bypassthesawgeneratorandpulsedensitymodu-latorandgetincrementfromSSCMax(setSSCMaxto45[0x2D]whenSSCBypassissetto0)TABLE13:POWERDOWNREGISTERS(MDIODEVICES1,2)ADDRESSHEXBIT(S)NAMETYPERESETVALUEDESCRIPTION1.
00802.
00807:6SIpwrdnDetB[1:0]SO01pwrdnDetB[1:0]RW11PowersdownthesignaldetectorandCOM*circuits1=normaloperation0=powerdown5:4SIpwrdnRxB[1:0]SO01pwrdnRxB[1:0]RW11PowersdownthereceiversandCDR1=normaloperation0=powerdown3:2SIpwrdnTxDrvB[1:0]SO01pwrdnTxDrvB[1:0]RW11Powersdownthetransmitter1=normaloperation0=powerdown1:0SIpwrdnTxB[1:0]SO01pwrdnTxB[1:0]RW11Powersdownthetransmitpipesandclock1=normaloperation0=powerdown1.
00812.
00817:2ReservedRO-Reserved1SIpwrdnBiasGenSO01pwrdnBiasGenRW0Powersdownthebandgap.
1=powerdown0=normaloperation0SIpwrdnPLLBSO01pwrdnPLLBRW1PowersdownthePLL1=normaloperation0=powerdownTABLE12:PLLCONFIGURATION(MDIODEVICE1,2)ADDRESSHEXBIT(S)NAMETYPEDEFAULTDESCRIPTIONEXSTOR-1XRS10L21028SERIALATAII:PORTSELECTORREV.
1.
045.
3XRS10L210DeviceGenericRegistersThissectionoutlinesgenericregistersrelatingtotheXRS10L210asawhole.
TheseregistersareaccessedthroughMDIOdevice0.
TABLE14:BIASGENERATORCONFIGURATION(MDIODEVICE1,2)ADDRESSHEXBIT(S)NAMETYPERESETVALUEDESCRIPTIONN.
00647:4pr100Tx[3:0]RW0x0Transmitpre-drivercurrentbias1010=50uA0010=75uA0000=100uA0001=125uA1100=150uA0111=175uA1111=200uA3:0Reserved[3:0]RW0x0DONOTMODIFYN.
00657:4ReservedRW0x0DONOTMODIFY3:0prcal100Tx[3:0]RW0x0Transmitdrivercurrentbias1010=50uA0010=75uA0000=100uA0001=125uA1100=150uA0111=175uA1111=200uATABLE15:RESETCONTROLSIGNALSADDRESSHEXBIT(S)NAMETYPERESETVALUEDESCRIPTION0.
00043:0resetPLLB_reg[3:0]RW0x0FResetsthePLLportionofthemacros0x00=PLLreset0x0F=clearsPLLreset0.
00307:0revision_id[7:0]R/O0x01DeiviceRevisionID0.
00317:0device_id[15:8]R/O0x83DeviceIDMSB0.
00327:0device_id[7:0R/O0x07DeviceIDLSBEXSTOR-1XRS10L21029REV.
1.
04SERIALATAII:PORTSELECTORTABLE16:SATAPORTSELECTORREGISTERSADDRESSHEXBIT(S)NAMETYPERESETVALUEDESCRIPTION0.
009A7:3ReservedRW00100DONOTMODIFY2p_host_selRW0Sidebandportselection1=SelectHostport10=SelectHostport01p_side_mthdRW01=p_host_selbasedsidebandselection0=externalpinbasedsidebandselection0p_sel_mthdRW0PleaserefertoTable2,"HostPortSelection,"onpage8TABLE17:PORTMULTIPLIERSATASTANDARDREGISTERSREGISTERBIT(S)NAMETYPEDEFAULTVALUEDESCRIPTIONGSCR(0)ProductIdentifier31-16DeviceIDR/O0x8307DeviceIDallocatedbythevendor.
15-0VendorIDR/O0x13A8VendorIDallocatedbythePCI-SIGofthevendorthatproducedthePortMultiplier.
GSCR(1)RevisionInformation31-16ReservedR/O0x000031-16Reserved15-8REV_LEVR/O0x0115-8RevisionlevelofthePortMultiplier.
7:4ReservedR/O0x07-4Reserved3PM_1,2R/O11=SupportsPortMultiplierspecification1.
2.
2PM_1.
1R/O11=SupportsPortMultiplierspecification1.
1.
1PM_1.
0R/O11=SupportsPortMultiplierspecification1.
0.
0ReservedR/O0ReservedGSCR(2)PortInformation7:4ReservedR/O0x0Reserved3-0DEV_FAN_OUT_PORTSR/O0x1Numberofexposeddevicefan-outports.
EXSTOR-1XRS10L21030SERIALATAII:PORTSELECTORREV.
1.
04GSCR(32)ErrorInformation31-15ReservedR/O0x014ReservedR/O0Unused13ReservedR/O0Unused12ReservedR/O0Unused11ReservedR/O0Unused10ReservedR/O0Unused9ReservedR/O0Unused8ReservedR/O0Unused7ReservedR/O0Unused6ReservedR/O0Unused5ReservedR/O0Unused4ReservedR/O0Unused3OR_PORT-3R/O0ORofselectablebitsinPort3PSCR[1](SError)2OR_PORT-2R/O0ORofselectablebitsinPort2PSCR[1](SError)1OR_PORT-1R/O0ORofselectablebitsinPort1PSCR[1](SError)0OR_PORT-0R/O0ORofselectablebitsinPort0PSCR[1](SError)GSCR(33)ErrorInfor-mationBitEnable31-0ERR_INFO_ENR/O0x400FFFFIfset,bitisenabledforuseinGSCR[32]GSCR(64)PortMulti-plierRevi-sion1.
XFeaturesSupport31-5ReservedR/O0x0Reserved4PHY_EVENTR/O01=SupportsPhyeventcounters3ASYNCR/O11=Supportsasynchronousnotification2SSCR/O01=SupportsdynamicSSCtransmitenable1PMREQPR/O11=SupportsissuingPMREQPtohost0BISTR/O01=SupportsBISTGSCR(96)PortMulti-plierRevi-sion1.
XFeaturesEnable31-4ReservedR/O0x0Reserved3ASYNC_ENR/W01=Asynchronousnotificationenabled2SSC_ENR/W01=DynamicSSCtransmitisenabled1PMREQP_ENR/W01=IssuingPMREQPtohostisenabled0BIST_ENR/W01=BISTsupportisenabledTABLE17:PORTMULTIPLIERSATASTANDARDREGISTERSREGISTERBIT(S)NAMETYPEDEFAULTVALUEDESCRIPTIONEXSTOR-1XRS10L21031REV.
1.
04SERIALATAII:PORTSELECTORTABLE18:SATASTANDARDREGISTERS-DEVICEPORT(0TO1)-STATUSANDCONTROLNOTE:RegistersdesignatedasWCarewriteclear.
InordertoclearaparticularbitorbitfieldwithinaWCdesignatedregister,writea'1'tothatbitorbitfield.
REGISTERBIT(S)NAMETYPEDEFAULTVALUEDESCRIPTIONPSCR(0)(SStatus)31-12ReservedR/O0x0Reserved11-8IPMR/O0x0TheIPMvalueindicatesthecurrentinterfacepowerman-agementstate0000b=Devicenotpresentorcommunicationnotestab-lished0001b=Interfaceinactivestate0010b=InterfaceinPartialpowermanagementstate0110b=InterfaceinSlumberpowermanagementstateAllothervaluesreserved7-4SPDR/O0x0TheSPDvalueindicatesthenegotiatedinterfacecommuni-cationspeedestablished0000b=Nonegotiatedspeed(devicenotpresentorcom-municationnotestablished)0001b=Generation1communicationratenegotiated0010b=Generation2communicationratenegotiatedAllothervaluesreserved3-0DETR/O0x0TheDETvalueindicatestheinterfacedevicedetectionandPhystate.
0000b=NodevicedetectedandPhycommunicationnotestablished0001b=DevicepresencedetectedbutPhycommunicationnotestablished0011b=DevicepresencedetectedandPhycommunicationestablished0100b=PhyinofflinemodeasaresultoftheinterfacebeingdisabledorrunninginaBISTloopbackmodeAllothervaluesreservedPSCR(1)(SError)31-16DIAGR/WC0x40Seedescriptionbelow15-0ERRR/WC0x0SeedescriptionbelowPSCR(2)(SControl)31-19ReservedR/O0x0ReservedAllreservedfieldsshallbeclearedtozero.
20-16ReservedR/W0x0ReservedAllreservedfieldsshallbeclearedtozero15-12SPMR/W0x0Seedescriptionbelow11-8IPMR/W0x0Seedescriptionbelow7-4SPDR/W0x0Seedescriptionbelow3-0DETR/W0x4SeedescriptionbelowEXSTOR-1XRS10L21032SERIALATAII:PORTSELECTORREV.
1.
04SErrorregisterSCR(1)-TheSerialATAinterfaceErrorregister-SError-isa32-bitregisterthatconveyssupplementalInterfaceerrorinformationtocomplementtheerrorinformationavailableintheShadowRegisterBlockErrorregister.
TheregisterrepresentsallthedetectederrorsaccumulatedsincethelasttimetheSErrorregisterwascleared(whetherrecoveredbytheinterfaceofnot).
SetbitsintheerrorregisterareexplicitlyclearedbyawriteoperationtotheSErrorregister,oraresetoperation.
Thevaluewrittentoclearseterrorbitsshallhave1'sencodedinthebitpositionscorrespondingtothebitsthataretobecleared.
HostsoftwareshouldcleartheInterfaceSErrorregisteratappropriatecheckpointsinordertobestisolateerrorconditionsandthecommandstheyimpact.
Bits[31:16]DIAGTheDIAGfieldcontainsdiagnosticerrorinformationforusebydiagnosticsoftwareinvalidatingcorrectoperationorisolatingfailuremodes.
Thefieldisbitsignificantasdefinedinthefollowingfigure.
APortSelectorpresencedetected:ThisbitissettoonewhenCOMWAKEisreceivedwhilethehostisinstateHP2:HR_AwaitCOMINIT.
Onpower-upresetthisbitisclearedtozero.
Thebitisclearedtozerowhenthehostwritesaonetothisbitlocation.
B10bto8bDecodeerror:Whensettoaone,thisbitindicatesthatoneormore10bto8bdecodingerrorsoccurredsincethebitwaslastclearedtozero.
CCRCError:Whensettoone,thisbitindicatesthatoneormoreCRCerrorsoccurredwiththeLinklayersincethebitwaslastclearedtozero.
DDisparityError:Whensettoone,thisbitindicatesthatincorrectdisparitywasdetectedoneormoretimessincethelasttimethebitwasclearedtozero.
FUnrecognizedFIStype:Whensettoone,thisbitindicatesthatsincethebitwaslastclearedoneormoreFISeswerereceivedbytheTransportlayerwithgoodCRC,buthadatypefieldthatwasnotrecognized.
IPhyInternalError:Whensettoone,thisbitindicatesthatthePhydetectedsomeinternalerrorsincethelasttimethisbitwasclearedtozero.
NPHYRDYchange:Whensettoone,thisbitindicatesthatthePHYRDYsignalchangedstatesincethelasttimethisbitwasclearedtozero.
HHandshakeerror:Whensettoone,thisbitindicatesthatoneormoreR_ERRPhandshakeresponsewasreceivedinresponsetoframetransmission.
SucherrorsmaybetheresultofaCRCerrordetectedbytherecipient,adisparityor10b/8bdecodingerror,orothererrorconditionleadingtoanegativehandshakeonatransmittedframe.
RReservedbitforfutureuse:Shallbeclearedtozero.
SLinkSequenceError:Whensettoone,thisbitindicatesthatoneormoreLinkstatemachineerrorconditionswasencounteredsincethelasttimethisbitwasclearedtozero.
TheLinklayerstatemachinedefinestheconditionsunderwhichthelinklayerdetectsanerroneoustransition.
TTransportstatetransitionerror:Whensettoone,thisbitindicatesthatanerrorhasoccurredinthetransitionfromonestatetoanotherwithintheTransportlayersincethelasttimethisbitwasclearedtozero.
WCOMWAKEDetected:WhensettoonethisbitindicatesthataCOMWAKEsignalwasdetectedbythePhysincethelasttimethisbitwasclearedtozero.
XExchanged:Whensettoonethisbitindicatesthatdevicepresencehaschangedsincethelasttimethisbitwasclearedtozero.
Themeansbywhichtheimplementationdeterminesthatthedevicepresencehaschangedisvendorspecific.
ThisbitmaybesettooneanytimeaPhyresetinitializationsequenceoccursasdeterminedbyreceptionoftheCOMINITsignalwhetherinresponsetoanewdevicebeinginserted,inresponsetoaCOMRESEThavingbeenissued,orinresponsetopower-up.
DIAGRRRRAXFTSHCDBWINEXSTOR-1XRS10L21033REV.
1.
04SERIALATAII:PORTSELECTORBits[15:0]ERRTheERRfieldcontainserrorinformationforusebyhostsoftwareindeterminingtheappropriateresponsetotheerrorcondition.
Thefieldisbitsignificantasdefinedinthefollowingfigure.
CNon-recoveredpersistentcommunicationordataintegrityerror:Acommunicationerrorthatwasnotrecoveredoccurredthatisexpectedtobepersistent.
Sincetheerrorconditionisexpectedtobepersistenttheoperationneednotberetriedbyhostsoftware.
Persistentcommunicationserrorsmayarisefromfaultyinterconnectwiththedevice,fromadevicethathasbeenremovedorhasfailed,oranumberofothercauses.
EInternalerror:Thehostbusadapterexperiencedaninternalerrorthatcausedtheoperationtofailandmayhaveputthehostbusadapterintoanerrorstate.
Hostsoftwareshouldresettheinterfacebeforere-tryingtheoperation.
Iftheconditionpersists,thehostbusadaptermaysufferfromadesignissuerenderingitincompatiblewiththeattacheddevice.
IRecovereddataintegrityerror:Adataintegrityerroroccurredthatwasrecoveredbytheinterfacethrougharetryoperationorotherrecoveryaction.
Thismayarisefromanoiseburstinthetransmission,avoltagesupplyvariation,orfromothercauses.
Noactionisrequiredbyhostsoftwaresincetheoperationultimatelysucceeded,however,hostsoftwaremayelecttotracksuchrecoverederrorsinordertogaugeoverallcommunicationsintegrityandpotentiallystepdownthenegotiatedcommunicationspeed.
MRecoveredcommunicationserror:Communicationsbetweenthedeviceandhostwastemporarilylostbutwasre-established.
Thismayarisefromadevicetemporarilybeingremoved,fromatemporarylossofPhysynchronization,orfromothercausesandmaybederivedfromthePHYRDYnsignalbetweenthePhyandLinklayers.
Noactionisrequiredbythehostsoftwaresincetheoperationultimatelysucceeded,however,hostsoftwaremayelecttotracksuchrecoverederrorsinordertogaugeoverallcommunicationsintegrityandpotentiallystepdownthenegotiatedcommunicationspeed.
PProtocolerror:AviolationoftheSerialATAprotocolwasdetected.
ThismayarisefrominvalidorpoorlyformedFISesbeingreceived,frominvalidstatetransitions,orfromothercauses.
Hostsoftwareshouldresettheinterfaceandretrythecorrespondingoperation.
Ifsuchanerrorpersists,theattacheddevicemayhaveadesignissuerenderingitincompatiblewiththehostbusadapter.
RReservedbitforfutureuse:Shallbeclearedtozero.
TNon-recoveredtransientdataintegrityerror:Adataintegrityerroroccurredthatwasnotrecoveredbytheinterface.
Sincetheerrorconditionisnotexpectedtobepersistenttheoperationshouldberetriedbyhostsoftware.
SControlregisterSCR(2)TheSerialATAinterfaceControlregister-SControl-isa32-bitread-writeregisterthatprovidestheinterfacebywhichsoftwarecontrolsSerialATAinterfacecapabilities.
WritestotheSControlregisterresultinanactionbeingtakenbythehostadapterorinterface.
Readsfromtheregisterreturnthelastvaluewrittentoit.
Bits[19:16]PMPThePortMultiplierPort(PMP)fieldrepresentsthe4-bitvaluetobeplacedinthePMPortfieldofalltransmittedFISes.
Thisfieldis'0000'uponpower-up.
ThisfieldisoptionalandanHBAimplementationmaychoosetoignorethisfieldiftheFIStobetransmittedisconstructedviaanalternativemethod.
Bits[15:12]SPMTheSelectPowerManagement(SPM)fieldisusedtoselectapowermanagementstate.
Anon-zerovaluewrittentothisfieldshallcausethepowermanagementstatespecifiedtobeinitiated.
Avaluewrittentothisfieldistreatedasaone-shot.
Thisfieldshallbereadas0000b.
s0000b=NopowermanagementstatetransitionrequestedERRRRRREPCTRRRRRRMIEXSTOR-1XRS10L21034SERIALATAII:PORTSELECTORREV.
1.
04s0001b=TransitiontothePartialpowermanagementstateinitiateds0010b=TransitiontotheSlumberpowermanagementstateinitiateds0100b=TransitiontotheactivepowermanagementstateinitiatedsAllothervaluesreservedBits[11:8]IPMTheIPMfieldrepresentstheenabledinterfacepowermanagementstatesthatmaybeinvokedviatheSerialATAinterfacepowermanagementcapabilitiess0000b=Nointerfacepowermanagementstaterestrictionss0001b=TransitionstothePartialpowermanagementstatedisableds0010b=TransitionstotheSlumberpowermanagementstatedisableds0011b=TransitionstoboththePartialandSlumberpowermanagementstatesdisabledsAllothervaluesreservedBits[7:4]SPDTheSPDfieldrepresentsthehighestallowedcommunicationspeedtheinterfaceisallowedtonegotiatewheninterfacecommunicationspeedisestablisheds0000b=Nospeednegotiationrestrictionss0001b=LimitspeednegotiationtoaratenotgreaterthanGen1communicationrates0010b=LimitspeednegotiationtoaratenotgreaterthanGen2communicationratesAllothervaluesreservedBits[3:0]DETTheDETfieldcontrolsthehostadapterdevicedetectionandinterfaceinitialization.
s0000b=Nodevicedetectionorinitializationactionrequesteds0001b=Performinterfacecommunicationinitializationsequencetoestablishcommunication.
Thisisfunctionallyequivalenttoahardresetandresultsintheinterfacebeingresetandcommunicationsreinitialized.
UponawritetotheSControlregisterthatsetstheDETfieldto0001b,thehostinterfaceshalltransitiontotheHP1:HR_ResetstateandshallremaininthatstateuntiltheDETfieldissettoavalueotherthan0001b,byasubsequentwritetotheSControlregister.
s0100b=DisabletheSerialATAinterfaceandputPhyinofflinemode.
sAllothervaluesreservedPRODUCTORDERINGINFORMATIONPRODUCTNUMBERPACKAGETYPEOPERATINGTEMPERATURERANGEXRS10L210IV-F100PinLQFP(LeadFree)-40°Cto+85°CXRS10L210IV100PinLQFP-40°Cto+85°CXRS10L210IL-F64PinQFN(LeadFree)-40°Cto+85°CXRS10L210IL64PinQFN-40°Cto+85°CEXSTOR-1XRS10L21035REV.
1.
04SERIALATAII:PORTSELECTOR100LEADLOW-PROFILEQUADFLATPACK(14X14X1.
4mmLQFP,1.
0mmFORM)NOTE:ThecontroldimensionisinmillimetersINCHESMILLIMETERSSYMBOLMINMAXMINMAXA0.
0550.
0631.
401.
60A10.
0020.
0060.
050.
15A20.
0530.
0571.
351.
45B0.
0100.
0140.
170.
27C0.
0040.
0080.
090.
20D0.
6220.
63815.
8016.
20D10.
3900.
55513.
9014.
10e0.
0197BSC0.
50BSCL0.
0180.
0300.
450.
75α0°7°0°7°β7°typ7°typ7551502612576100DD1DD1BeA2αA1ASeatingPlaneLCβEXSTOR-1XRS10L21036SERIALATAII:PORTSELECTORREV.
1.
0464LEADQUADFLATNOLEAD(9mmx9mmx0.
9mm,0.
50pitchQFN,SmallThermalPad)Rev.
1.
00Note:Thecontroldimensionisinmillimeter.
MINMAXMINMAXA0.
0310.
0390.
801.
00A10.
0000.
0020.
000.
05A30.
0060.
0100.
150.
25D0.
3500.
3588.
909.
10D20.
1870.
1994.
755.
05b0.
0070.
0120.
180.
30e0.
0197BSC0.
50BSCL0.
0140.
0180.
350.
45k0.
008-0.
20-SYMBOLINCHESMILLIMETERSNote:CenterthermalpadshouldbeconnectedtoPCBGroundPlane.
37NOTICEEXARCorporationreservestherighttomakechangestotheproductscontainedinthispublicationinordertoimprovedesign,performanceorreliability.
EXARCorporationassumesnoresponsibilityfortheuseofanycircuitsdescribedherein,conveysnolicenseunderanypatentorotherright,andmakesnorepresentationthatthecircuitsarefreeofpatentinfringement.
Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmayvarydependinguponauser'sspecificapplication.
Whiletheinformationinthispublicationhasbeencarefullychecked;noresponsibility,however,isassumedforinaccuracies.
EXARCorporationdoesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.
ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporationreceives,inwriting,assurancestoitssatisfactionthat:(a)theriskofinjuryordamagehasbeenminimized;(b)theuserassumesallsuchrisks;(c)potentialliabilityofEXARCorporationisadequatelyprotectedunderthecircumstances.
Copyright2007EXARCorporationDatasheetDecember2008.
Reproduction,inpartorwhole,withoutthepriorwrittenconsentofEXARCorporationisprohibited.
EXSTOR-1XRS10L210REV.
1.
04SERIALATAII:PORTSELECTORREVISIONSREV#DATEDESCRIPTIONOFCHANGES1.
00January2008Released.
1.
01March2008Revisedtooperationalregisters.
1.
02August2008.
UpdatedESDData1.
03September2008Added64QFNPackage.
1.
04December2008Pin-outcorrectionfor64QFNPackage