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ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013ADC122S051/ADC122S051Q2Channel,200kspsto500ksps12-BitA/DConverterCheckforSamples:ADC122S0511FEATURESDESCRIPTIONTheADC122S051/ADC122S051Qisalow-power,2SpecifiedOveraRangeofSampleRates.
two-channelCMOS12-bitanalog-to-digitalconverterTwoInputChannelswithahigh-speedserialinterface.
UnliketheVariablePowerManagementconventionalpracticeofspecifyingperformanceatasinglesamplerateonly,theSinglePowerSupplywith2.
7V-5.
25VRangeADC122S051/ADC122S051QisfullyspecifiedoveraTestedperAEC-Q100andQualifiedforsampleraterangeof200kspsto500ksps.
TheAutomotiveApplicationsconverterisbasedonasuccessive-approximationMeetsAEC-Q100-011C2CDMClassificationregisterarchitecturewithaninternaltrack-and-holdcircuit.
ItcanbeconfiguredtoacceptoneortwoinputsignalsatinputsIN1andIN2.
APPLICATIONSPortableSystemsTheoutputserialdataisstraightbinary,andiscompatiblewithseveralstandards,suchasSPI,RemoteDataAcquisitionQSPI,MICROWIRE,andmanycommonDSPInstrumentationandControlSystemsserialinterfaces.
TheADC122S051/ADC122S051QoperateswithaKEYSPECIFICATIONSsinglesupplythatcanrangefrom+2.
7Vto+5.
25V.
DNL:+0.
7/0.
4LSB(typ)Normalpowerconsumptionusinga+3Vor+5Vsupplyis3.
0mWand10mW,respectively.
TheINL:±0.
50LSB(typ)power-downfeaturereducesthepowerconsumptionSNR:72.
5dB(typ)tojust0.
14Wusinga+3Vsupply,or0.
32WusingPowerConsumption:a+5Vsupply.
–3VSupply:3.
0mW(typ)TheADC122S051/ADC122S051Qispackagedinan–5VSupply:10mW(typ)8-leadVSSOPpackage.
Operationovertheindustrialtemperaturerangeof40°Cto+85°Cisspecified.
Table1.
Pin-CompatibleAlternativesbyResolutionandSpeed(1)ResolutionSpecifiedforSampleRateRangeof:50to200ksps200to500ksps500kspsto1Msps12-bitADC122S021ADC122S051ADC122S10110-bitADC102S021ADC102S051ADC102S1018-bitADC082S021ADC082S051ADC082S101(1)Alldevicesarefullypinandfunctioncompatible.
ConnectionDiagram1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2004–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
ADC122S051SNAS257E–NOVEMBER2004–REVISEDMARCH2013www.
ti.
comBlockDiagramPINDESCRIPTIONSandEQUIVALENTCIRCUITSPinNo.
SymbolDescriptionANALOGI/O5,4IN1andIN2Analoginputs.
Thesesignalscanrangefrom0VtoVA.
DIGITALI/O8SCLKDigitalclockinput.
Thisclockdirectlycontrolstheconversionandreadoutprocesses.
Digitaldataoutput.
Theoutputsamplesareclockedoutofthispinonfallingedgesofthe7DOUTSCLKpin.
Digitaldatainput.
TheADC122S051/ADC122S051Q'sControlRegisterisloadedthrough6DINthispinonrisingedgesoftheSCLKpin.
Chipselect.
OnthefallingedgeofCS,aconversionprocessbegins.
Conversionscontinue1CSaslongasCSisheldlow.
POWERSUPPLYPositivesupplypin.
Thispinshouldbeconnectedtoaquiet+2.
7Vto+5.
25Vsourceand2VAbypassedtoGNDwitha1Fcapacitoranda0.
1Fmonolithiccapacitorlocatedwithin1cmofthepowerpin.
3GNDThegroundreturnforthedie.
Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
2SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013AbsoluteMaximumRatings(1)(2)(3)AnalogSupplyVoltageVA0.
3Vto6.
5VVoltageonAnyPintoGND0.
3VtoVA+0.
3VInputCurrentatAnyPin(4)±10mAPackageInputCurrent(4)±20mAPowerConsumptionatTA=25°CSee(5)ESDSusceptibility(6)HumanBodyModel2500VMachineModel250VChargedDeviceModel500VJunctionTemperature+150°CStorageTemperature65°Cto+150°C(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
(3)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
(4)Whentheinputvoltageatanypinexceedsthepowersupply(thatis,VINVA),thecurrentatthatpinshouldbelimitedto10mA.
The20mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof10mAtotwo.
TheAbsoluteMaximumRatingspecificationdoesnotapplytotheVApin.
ThecurrentintotheVApinislimitedbytheAnalogSupplyVoltagespecification.
(5)Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150°C.
ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDMAX=(TJmaxTA)/θJA.
Thevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(e.
g.
wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed).
Obviously,suchconditionsshouldalwaysbeavoided.
(6)Humanbodymodelis100pFcapacitordischargedthrougha1.
5kresistor.
Machinemodelis220pFdischargedthroughzeroohmsOperatingRatings(1)(2)OperatingTemperatureRange40°C≤TA≤+85°CVASupplyVoltage+2.
7Vto+5.
25VDigitalInputPinsVoltageRange0.
3VtoVAClockFrequency50kHzto16MHzAnalogInputVoltage0VtoVA(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
PackageThermalResistance(1)PackageθJA8-leadVSSOP250°C/W(1)SolderingprocessmustcomplywithReflowTemperatureProfilespecifications.
Refertowww.
ti.
com/packaging.
Reflowtemperatureprofilesaredifferentforlead-freeandnon-lead-freepackages.
Copyright2004–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:ADC122S051ADC122S051SNAS257E–NOVEMBER2004–REVISEDMARCH2013www.
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comADC122S051/ADC122S051QConverterElectricalCharacteristics(1)(2)ThefollowingspecificationsapplyforVA=+2.
7Vto5.
25V,GND=0V,fSCLK=3.
2MHzto8MHz,fSAMPLE=200kspsto500ksps,CL=35pFunlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(3)STATICCONVERTERCHARACTERISTICSResolutionwithNoMissingCodes12BitsINLIntegralNon-Linearity±0.
5±1.
1LSB(max)+0.
71.
3LSB(max)DNLDifferentialNon-Linearity0.
41.
0LSB(min)VOFFOffsetError+0.
3±1.
3LSB(max)OEMChanneltoChannelOffsetErrorMatch±0.
1±1.
0LSB(max)FSEFullScaleError0.
5±1.
5LSB(max)ChanneltoChannelFull-ScaleErrorFSEM+0.
01±1.
0LSB(max)MatchDYNAMICCONVERTERCHARACTERISTICSVA=+2.
7to5.
25VSINADSignal-to-NoisePlusDistortionRatio7269.
2dB(min)fIN=40.
2kHz,0.
02dBFSVA=+2.
7to5.
25VSNRSignal-to-NoiseRatio72.
570.
6dB(min)fIN=40.
2kHz,0.
02dBFSVA=+2.
7to5.
25VTHDTotalHarmonicDistortion8475dB(max)fIN=40.
2kHz,0.
02dBFSVA=+2.
7to5.
25VSFDRSpurious-FreeDynamicRange8676dB(min)fIN=40.
2kHz,0.
02dBFSENOBEffectiveNumberofBitsVA=+2.
7to5.
25V11.
711.
2Bits(min)VA=+5.
25VChannel-to-ChannelCrosstalk86dBfIN=40.
2kHzIntermodulationDistortion,SecondVA=+5.
25V,87dBOrderTermsfa=40.
161kHz,fb=41.
015kHzIMDIntermodulationDistortion,ThirdOrderVA=+5.
25V88dBTermsfa=40.
161kHz,fb=41.
015kHzVA=+5V11MHzFPBW-3dBFullPowerBandwidthVA=+3V8MHzANALOGINPUTCHARACTERISTICSVINInputRange0toVAVIDCLDCLeakageCurrent±0.
02±1A(max)TrackMode33pFCINAInputCapacitanceHoldMode3pFDIGITALINPUTCHARACTERISTICSVA=+5.
25V2.
4V(min)VIHInputHighVoltageVA=+3.
6V2.
1V(min)VILInputLowVoltage0.
8V(max)IINInputCurrentVIN=0VorVIN=VA±0.
02±10A(max)CINDDigitalInputCapacitance24pF(max)DIGITALOUTPUTCHARACTERISTICSISOURCE=200AVA0.
03VA0.
5V(min)VOHOutputHighVoltageISOURCE=1mAVA0.
10VISINK=200A0.
020.
4V(max)VOLOutputLowVoltageISINK=1mA0.
1V(1)Min/maxspecificationlimitsarespecifiedbydesign,test,orstatisticalanalysis.
(2)PPAP(ProductionPartApprovalProcess)documentationofthedevicetechnology,processandqualificationisavailablefromTexasInstrumentsuponrequest.
(3)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
4SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013ADC122S051/ADC122S051QConverterElectricalCharacteristics(1)(2)(continued)ThefollowingspecificationsapplyforVA=+2.
7Vto5.
25V,GND=0V,fSCLK=3.
2MHzto8MHz,fSAMPLE=200kspsto500ksps,CL=35pFunlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(3)IOZH,IOZLTRI-STATELeakageCurrent0.
005±1A(max)COUTTRI-STATEOutputCapacitance24pF(max)OutputCodingStraight(Natural)BinaryPOWERSUPPLYCHARACTERISTICS(CL=10pF)2.
7V(min)VAAnalogSupplyVoltage5.
25V(max)VA=+5.
25V,1.
92.
4mA(max)fSAMPLE=500ksps,fIN=40kHzSupplyCurrent,NormalMode(Operational,CSlow)VA=+3.
6V,0.
841.
2mA(max)fSAMPLE=500ksps,fIN=40kHzIAVA=+5.
25V,60nAfSAMPLE=0kspsSupplyCurrent,Shutdown(CShigh)VA=+3.
6V,38nAfSAMPLE=0kspsVA=+5.
25V1012.
6mW(max)PowerConsumption,NormalMode(Operational,CSlow)VA=+3.
6V3.
04.
3mW(max)PDVA=+5.
25V0.
32WPowerConsumption,Shutdown(CShigh)VA=+3.
6V0.
14WACELECTRICALCHARACTERISTICS3.
2MHz(min)fSCLKMaximumClockFrequencySee(4)8MHz(max)200ksps(min)fSSampleRateSee(4)500ksps(max)tCONVConversionTime13SCLKcycles30%(min)DCSCLKDutyCyclefSCLK=8MHz5070%(max)tACQTrack/HoldAcquisitionTimeFull-ScaleStepInput3SCLKcyclesThroughputTimeAcquisitionTime+ConversionTime16SCLKcycles(4)Thisisthefrequencyrangeoverwhichtheelectricalperformanceisspecified.
ThedeviceisfunctionaloverawiderrangewhichisspecifiedunderOperatingRatings.
Copyright2004–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:ADC122S051ADC122S051SNAS257E–NOVEMBER2004–REVISEDMARCH2013www.
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comADC122S051/ADC122S051QTimingSpecifications(1)ThefollowingspecificationsapplyforVA=+2.
7Vto5.
25V,GND=0V,fSCLK=3.
2MHzto8MHz,fSAMPLE=200kspsto500ksps,CL=35pF,BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(2)VA=+3.
0V3.
5tCSUSetupTimeSCLKHightoCSFallingEdgeSee(3)10ns(min)VA=+5.
0V0.
5VA=+3.
0V+4.
5tCLHHoldtimeSCLKLowtoCSFallingEdgeSee(3)10ns(min)VA=+5.
0V+1.
5VA=+3.
0V+4tENDelayfromCSUntilDOUTactive30ns(max)VA=+5.
0V+2VA=+3.
0V+14.
5tACCDataAccessTimeafterSCLKFallingEdge30ns(max)VA=+5.
0V+13tSUDataSetupTimePriortoSCLKRisingEdge+310ns(min)tHDataValidSCLKHoldTime+310ns(min)0.
3xtCHSCLKHighPulseWidth0.
5xtSCLKns(min)tSCLK0.
3xtCLSCLKLowPulseWidth0.
5xtSCLKns(min)tSCLKVA=+3.
0V1.
8OutputFallingVA=+5.
0V1.
3tDISCSRisingEdgetoDOUTHigh-Impedance20ns(max)VA=+3.
0V1.
0OutputRisingVA=+5.
0V1.
0(1)PPAP(ProductionPartApprovalProcess)documentationofthedevicetechnology,processandqualificationisavailablefromTexasInstrumentsuponrequest.
(2)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
(3)ClockmaybeeitherhighorlowwhenCSisassertedaslongassetupandholdtimestCSUandtCLHarestrictlyobserved.
TimingDiagramsFigure1.
OperationalTimingDiagram6SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013Figure2.
TimingTestCircuitFigure3.
SerialTimingDiagramFigure4.
SCLKandCSTimingParametersSpecificationDefinitionsACQUISITIONTIMEisthetimerequiredtoacquiretheinputvoltage.
Thatis,itistimerequiredfortheholdcapacitortochargeuptotheinputvoltage.
APERTUREDELAYisthetimebetweenthefourthfallingSCLKedgeofaconversionandthetimewhentheinputsignalisacquiredorheldforconversion.
CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword.
CROSSTALKisthecouplingofenergyfromonechannelintotheotherchannel,ortheamountofsignalenergyfromoneanaloginputthatappearsatthemeasuredanaloginput.
DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB.
DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.
ThespecificationherereferstotheSCLK.
Copyright2004–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:ADC122S051ADC122S051SNAS257E–NOVEMBER2004–REVISEDMARCH2013www.
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comEFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.
ENOBisdefinedas(SINAD1.
76)/6.
02andsaysthattheconverterisequivalenttoaperfectADCofthis(ENOB)numberofbits.
FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput.
FULLSCALEERROR(FSE)isameasureofhowfarthelastcodetransitionisfromtheideal1LSBbelowVREF+andisdefinedas:VFSE=Vmax+1.
5LSB–VREF+(1)whereVmaxisthevoltageatwhichthetransitiontothemaximumcodeoccurs.
FSEcanbeexpressedinVolts,LSBorpercentoffullscalerange.
GAINERRORisthedeviationofthelastcodetransition(111.
.
.
110)to(111.
.
.
111)fromtheideal(VREF1.
5LSB),afteradjustingforoffseterror.
INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(LSBbelowthefirstcodetransition)throughpositivefullscale(LSBabovethelastcodetransition).
Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue.
INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalspectralcomponentsasaresultoftwosinusoidalfrequenciesbeingappliedtotheADCinputatthesametime.
Itisdefinedastheratioofthepowerinthesecondandthirdorderintermodulationproductstothesumofthepowerinbothoftheoriginalfrequencies.
IMDisusuallyexpressedindB.
MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.
Thesecodescannotbereachedwithanyinputvalue.
TheADC122S051/ADC122S051Qisensurednottohaveanymissingcodes.
OFFSETERRORisthedeviationofthefirstcodetransition(000.
.
.
000)to(000.
.
.
001)fromtheideal(i.
e.
GND+0.
5LSB).
SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignalattheconverteroutputtothermsvalueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,notincludingd.
c.
orharmonicsincludedintheTHDspecification.
SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherspectralcomponentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.
c.
SPURIOUSFREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthedesiredsignalamplitudetotheamplitudeofthepeakspuriousspectralcomponent,whereaspuriousspectralcomponentisanysignalpresentintheoutputspectrumthatisnotpresentattheinputandmayormaynotbeaharmonic.
8SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013TOTALHARMONICDISTORTION(THD)istheratio,expressedindBordBc,ofthermstotalofthefirstfiveharmoniccomponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.
THDiscalculatedas(2)whereAf1istheRMSpoweroftheinputfrequencyattheoutputandAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies.
AccurateTHDmeasurementrequiresaspectrallypuresinewave(monotone)attheADCinput.
THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwosuccessiveconversion.
Itistheacquisitiontimeplustheconversionandreadouttimes.
InthecaseoftheADC122S051/ADC122S051Q,thisis16SCLKperiods.
Copyright2004–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:ADC122S051ADC122S051SNAS257E–NOVEMBER2004–REVISEDMARCH2013www.
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comTypicalPerformanceCharacteristicsTA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.
2MHzto8MHz,fIN=40.
2kHzunlessotherwisestated.
DNL-VA=3.
0VINL-VA=3.
0VFigure5.
Figure6.
DNL-VA=5.
0VINL-VA=5.
0VFigure7.
Figure8.
DNLvs.
SupplyINLvs.
SupplyFigure9.
Figure10.
10SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.
2MHzto8MHz,fIN=40.
2kHzunlessotherwisestated.
DNLvs.
ClockFrequencyINLvs.
ClockFrequencyFigure11.
Figure12.
DNLvs.
ClockDutyCycleINLvs.
ClockDutyCycleFigure13.
Figure14.
DNLvs.
TemperatureINLvs.
TemperatureFigure15.
Figure16.
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comTypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.
2MHzto8MHz,fIN=40.
2kHzunlessotherwisestated.
SNRvs.
SupplyTHDvs.
SupplyFigure17.
Figure18.
SNRvs.
ClockFrequencyTHDvs.
ClockFrequencyFigure19.
Figure20.
SNRvs.
ClockDutyCycleTHDvs.
ClockDutyCycleFigure21.
Figure22.
12SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.
2MHzto8MHz,fIN=40.
2kHzunlessotherwisestated.
SNRvs.
InputFrequencyTHDvs.
InputFrequencyFigure23.
Figure24.
SNRvs.
TemperatureTHDvs.
TemperatureFigure25.
Figure26.
SFDRvs.
SupplySINADvs.
SupplyFigure27.
Figure28.
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comTypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.
2MHzto8MHz,fIN=40.
2kHzunlessotherwisestated.
SFDRvs.
ClockFrequencySINADvs.
ClockFrequencyFigure29.
Figure30.
SFDRvs.
ClockDutyCycleSINADvs.
ClockDutyCycleFigure31.
Figure32.
SFDRvs.
InputFrequencySINADvs.
InputFrequencyFigure33.
Figure34.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013TypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.
2MHzto8MHz,fIN=40.
2kHzunlessotherwisestated.
SFDRvs.
TemperatureSINADvs.
TemperatureFigure35.
Figure36.
ENOBvs.
SupplyENOBvs.
ClockFrequencyFigure37.
Figure38.
ENOBvs.
ClockDutyCycleENOBvs.
InputFrequencyFigure39.
Figure40.
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comTypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.
2MHzto8MHz,fIN=40.
2kHzunlessotherwisestated.
ENOBvs.
TemperatureSpectralResponse-3V,200kspsFigure41.
Figure42.
SpectralResponse-5V,200kspsSpectralResponse-3V,500kspsFigure43.
Figure44.
SpectralResponse-5V,500kspsPowerConsumptionvs.
ThroughputFigure45.
Figure46.
16SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013APPLICATIONSINFORMATIONADC122S051/ADC122S051QOPERATIONFortherestofthisdocument,theADC122S051/ADC122S051QwillbereferredtoastheADC122S051.
TheADC122S051isasuccessive-approximationanalog-to-digitalconverterdesignedaroundacharge-redistributiondigital-to-analogconverter.
SimplifiedschematicsoftheADC122S051inbothtrackandholdmodesareshowninFigure47andFigure48,respectively.
InFigure47,theADC122S051isintrackmode:switchSW1connectsthesamplingcapacitortooneoftwoanaloginputchannelsthroughthemultiplexer,andSW2balancesthecomparatorinputs.
TheADC122S051isinthisstateforthefirstthreeSCLKcyclesafterCSisbroughtlow.
Figure48showstheADC122S051inholdmode:switchSW1connectsthesamplingcapacitortoground,maintainingthesampledvoltage,andswitchSW2unbalancesthecomparator.
Thecontrollogictheninstructsthecharge-redistributionDACtoaddfixedamountsofchargetothesamplingcapacitoruntilthecomparatorisbalanced.
Whenthecomparatorisbalanced,thedigitalwordsuppliedtotheDACisthedigitalrepresentationoftheanaloginputvoltage.
TheADC122S051isinthisstateforthefourththroughsixteenthSCLKcyclesafterCSisbroughtlow.
ThetimewhenCSislowisconsideredaserialframe.
Eachoftheseframesshouldcontainanintegermultipleof16SCLKcycles,duringwhichtimeaconversionisperformedandclockedoutattheDOUTpinanddataisclockedintotheDINpintoindicatethemultiplexeraddressforthenextconversion.
Figure47.
ADC122S051inTrackModeFigure48.
ADC122S051inHoldModeUSINGTHEADC122S051AnADC122S051timingdiagramandaserialinterfacetimingdiagramfortheADC122S051areshownintheTimingDiagramssection.
CSischipselect,whichinitiatesconversionsandframestheserialdatatransfers.
SCLK(serialclock)controlsboththeconversionprocessandthetimingofserialdata.
DOUTistheserialdataoutputpin,whereaconversionresultissentasaserialdatastream,MSBfirst.
DatatobewrittentotheADC122S051'sControlRegisterisplacedatDIN,theserialdatainputpin.
NewdataiswrittentoDINwitheachconversion.
AserialframeisinitiatedonthefallingedgeofCSandendsontherisingedgeofCS.
Eachframemustcontainanintegermultipleof16risingSCLKedges.
TheADCoutputdata(DOUT)isinahighimpedancestatewhenCSishighandisactivewhenCSislow.
Thus,CSactsasanoutputenable.
Additionally,thedevicegoesintoapowerdownstatewhenCSishighandalsobetweencontinuousconversioncycles.
Copyright2004–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:ADC122S051ADC122S051SNAS257E–NOVEMBER2004–REVISEDMARCH2013www.
ti.
comDuringthefirst3cyclesofSCLK,theADCisinthetrackmode,acquiringtheinputvoltage.
Forthenext13SCLKcyclestheconversionisaccomplishedandthedataisclockedout,MSBfirst,startingonthe5thclock.
Iftherearemorethanoneconversioninaframe,theADCwillre-enterthetrackmodeonthefallingedgeofSCLKaftertheN*16thrisingedgeofSCLK,andre-enterthehold/convertmodeontheN*16+4thfallingedgeofSCLK,where"N"isaninteger.
WhenCSisbroughthigh,SCLKisinternallygatedoff.
IfSCLKisstoppedinthelowstatewhileCSishigh,thesubsequentfallofCSwillgenerateafallingedgeoftheinternalversionofSCLK,puttingtheADCintothetrackmode.
ThisisseenbytheADCasthefirstfallingedgeofSCLK.
IfSCLKisstoppedwithSCLKhigh,theADCentersthetrackmodeonthefirstfallingedgeofSCLKafterthefallingedgeofCS.
Duringeachconversion,dataisclockedintotheADCatDINonthefirst8risingedgesofSCLKafterthefallofCS.
Foreachconversion,itisnecessarytoclockinthedataindicatingtheinputthatisselectedfortheconversionafterthecurrentone.
SeeTable2,Table3,andTable4.
IfCSandSCLKgolowwithinthetimesdefinedbytCSUandtCLH,therisingedgeofSCLKthatbeginsclockingdatainatDINmaybeoneclockcyclelaterthanexpected.
Itis,therefore,besttostrictlyobservetheminimumtCSUandtCLHtimesgivenintheTimingSpecifications.
Therearenopower-updelaysordummyconversionsrequiredwiththeADC122S051.
TheADCisabletosampleandconvertaninputtofullconversionimmediatelyfollowingpowerup.
Thefirstconversionresultafterpower-upwillbethatofIN1.
Table2.
ControlRegisterBitsBit7(MSB)Bit6Bit5Bit4Bit3Bit2Bit1Bit0DONTCDONTCADD2ADD1ADD0DONTCDONTCDONTCTable3.
ControlRegisterBitDescriptionsBit#:Symbol:Description7-6,2-0DONTCDon'tcare.
Thevalueofthesebitsdonotaffectthedevice.
3ADD0Thesethreebitsdeterminewhichinputchannelwillbesampledandconvertedinthenexttrack/holdcycle.
ThemappingbetweencodesandchannelsisshowninTable4.
4ADD15ADD2Table4.
InputChannelSelectionADD2ADD1ADD0InputChannelx00IN1(Default)x01IN2x1xNotallowed.
TheoutputsignalattheDOUTpinisindeterminateifADD1ishigh.
ADC122S051TRANSFERFUNCTIONTheoutputformatoftheADC122S051isstraightbinary.
CodetransitionsoccurmidwaybetweensuccessiveintegerLSBvalues.
TheLSBwidthfortheADC122S051isVA/4096.
TheidealtransfercharacteristicisshowninFigure49.
Thetransitionfromanoutputcodeof000000000000toacodeof000000000001isat1/2LSB,oravoltageofVA/8192.
OthercodetransitionsoccuratstepsofoneLSB.
18SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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comSNAS257E–NOVEMBER2004–REVISEDMARCH2013Figure49.
IdealTransferCharacteristicTYPICALAPPLICATIONCIRCUITAtypicalapplicationoftheADC122S051isshowninFigure50.
Powerisprovided,inthisexample,bytheTILP2950low-dropoutvoltageregulator,availableinavarietyoffixedandadjustableoutputvoltages.
ThepowersupplypinisbypassedwithacapacitornetworklocatedclosetotheADC122S051.
BecausethereferencefortheADC122S051isthesupplyvoltage,anynoiseonthesupplywilldegradedevicenoiseperformance.
Tokeepnoiseoffthesupply,useadedicatedlinearregulatorforthisdevice,orprovidesufficientdecouplingfromothercircuitrytokeepnoiseofftheADC122S051supplypin.
BecauseoftheADC122S051'slowpowerrequirements,itisalsopossibletouseaprecisionreferenceasapowersupplytomaximizeperformance.
Thefour-wireinterfaceisshownconnectedtoamicroprocessororDSP.
Figure50.
TypicalApplicationCircuitANALOGINPUTSAnequivalentcircuitforoneoftheADC122S051'sinputchannelsisshowninFigure51.
DiodesD1andD2provideESDprotectionfortheanaloginputs.
Atnotimeshouldanyinputgobeyond(VA+300mV)or(GND300mV),astheseESDdiodeswillbeginconducting,whichcouldresultinerraticoperation.
Forthisreason,theseESDdiodesshouldNOTbeusedtoclamptheinputsignal.
ThecapacitorC1inFigure51hasatypicalvalueof3pF,andismainlythepackagepincapacitance.
ResistorR1istheonresistanceofthemultiplexerandtrack/holdswitch,andistypically500ohms.
CapacitorC2istheADC122S051samplingcapacitorandistypically30pF.
TheADC122S051willdeliverbestperformancewhendrivenbyalow-impedancesourcetoeliminatedistortioncausedbythechargingofthesamplingcapacitance.
ThisisespeciallyimportantwhenusingtheADC122S051tosampleACsignals.
Alsoimportantwhensamplingdynamicsignalsisaband-passorlow-passfiltertoreduceharmonicsandnoise,improvingdynamicperformance.
Copyright2004–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:ADC122S051ADC122S051SNAS257E–NOVEMBER2004–REVISEDMARCH2013www.
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comFigure51.
EquivalentInputCircuitDIGITALINPUTSANDOUTPUTSTheADC122S051'sdigitaloutputDOUTislimitedby,andcannotexceed,thesupplyvoltage,VA.
Thedigitalinputpinsarenotpronetolatch-upand,andalthoughnotrecommended,SCLK,CSandDINmaybeassertedbeforeVAwithoutanylatch-uprisk.
POWERSUPPLYCONSIDERATIONSTheADC122S051isfullypowered-upwheneverCSislow,andfullypowered-downwheneverCSishigh,withoneexception:theADC122S051automaticallyenterspower-downmodebetweenthe16thfallingedgeofaconversionandthe1stfallingedgeofthesubsequentconversion(seeTimingDiagrams).
TheADC122S051canperformmultipleconversionsbacktoback;eachconversionrequires16SCLKcycles.
TheADC122S051willperformconversionscontinuouslyaslongasCSisheldlow.
Theusermaytradeoffthroughputforpowerconsumptionbysimplyperformingfewerconversionsperunittime.
ThePowerConsumptionvs.
SampleRatecurveintheTypicalPerformanceCharacteristicssectionshowsthetypicalpowerconsumptionoftheADC122S051versusthroughput.
Tocalculatethepowerconsumption,simplymultiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumption,andaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerdissipation.
PowerManagementWhentheADC122S051isoperatedcontinuouslyinnormalmode,themaximumthroughputisfSCLK/16.
ThroughputmaybetradedforpowerconsumptionbyrunningfSCLKatitsmaximum8MHzandperformingfewerconversionsperunittime,puttingtheADC122S051intoshutdownmodebetweenconversions.
AplotoftypicalpowerconsumptionversusthroughputisshownintheTypicalPerformanceCharacteristicssection.
Tocalculatethepowerconsumptionforagiventhroughput,multiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumptionandaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerconsumption.
Generally,theuserwillputthepartintonormalmodeandthenputthepartbackintoshutdownmode.
Notethatthecurveofpowerconsumptionvs.
throughputisnearlylinear.
Thisisbecausethepowerconsumptionintheshutdownmodeissosmallthatitcanbeignoredforallpracticalpurposes.
PowerSupplyNoiseConsiderationsThechargingofanyoutputloadcapacitancerequirescurrentfromthepowersupply,VA.
Thecurrentpulsesrequiredfromthesupplytochargetheoutputcapacitancewillcausevoltagevariationsonthesupply.
Ifthesevariationsarelargeenough,theycoulddegradeSNRandSINADperformanceoftheADC.
Furthermore,dischargingtheoutputcapacitancewhenthedigitaloutputgoesfromalogichightoalogiclowwilldumpcurrentintothediesubstrate,whichisresistive.
Loaddischargecurrentswillcause"groundbounce"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.
Thelargeristheoutputcapacitance,themorecurrentflowsthroughthediesubstrateandthegreateristhenoisecoupledintotheanalogchannel,degradingnoiseperformance.
Tokeepnoiseoutofthepowersupply,keeptheoutputloadcapacitanceassmallaspractical.
Iftheloadcapacitanceisgreaterthan35pF,usea100seriesresistorattheADCoutput,locatedasclosetotheADCoutputpinaspractical.
Thiswilllimitthechargeanddischargecurrentoftheoutputcapacitanceandimprovenoiseperformance.
20SubmitDocumentationFeedbackCopyright2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC122S051ADC122S051www.
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com13-Sep-2014Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesADC122S051CIMM/NOPBACTIVEVSSOPDGK81000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to85X06CADC122S051CIMMX/NOPBACTIVEVSSOPDGK83500Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to85X06CADC122S051QIMM/NOPBACTIVEVSSOPDGK81000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to85X06QADC122S051QIMMX/NOPBACTIVEVSSOPDGK83500Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to85X06Q(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
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TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
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Finishoptionsareseparatedbyaverticalruledline.
Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantADC122S051CIMM/NOPBVSSOPDGK81000178.
012.
45.
33.
41.
48.
012.
0Q1ADC122S051CIMMX/NOPBVSSOPDGK83500330.
012.
45.
33.
41.
48.
012.
0Q1ADC122S051QIMM/NOPBVSSOPDGK81000178.
012.
45.
33.
41.
48.
012.
0Q1ADC122S051QIMMX/NOPBVSSOPDGK83500330.
012.
45.
33.
41.
48.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
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com6-Sep-2014PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)ADC122S051CIMM/NOPBVSSOPDGK81000210.
0185.
035.
0ADC122S051CIMMX/NOPBVSSOPDGK83500367.
0367.
035.
0ADC122S051QIMM/NOPBVSSOPDGK81000210.
0185.
035.
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0367.
035.
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