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GC5316SLWS154AJANUARY2004REVISEDMARCH2004HIGHDENSITYDIGITALDOWNCONVERTERANDUPCONVERTERFEATURESDOptimizedforCDMA20001XandUMTSDUpto12UMTSor24CDMA2000DownconverterandUpconverterChannelsDMixedCDMA20001XandUMTSOperationDDDCInputandDUCOutputRatesto125MSPSDAnyDDCCanConnecttoAnyofFourInputPortsDAnyDUCCanSumintoAnyofFourOutputPortsDReal/ComplexDDCInputsandDUCOutputsDProgrammableAGConDDCOutputsDRxFiltering:6StageCIC,48TapCFIR,64TapPFIRDTxFiltering:6StageCIC,47TapCFIR,63TapPFIRD115-dBSFDRD16-BitDDCInputs,18-BitDUCOutputsD1.
5-VCore,3.
3-VI/O1DescriptionTheGC5316isahigh-densitymulti-channelcommunicationssignalprocessorintegratedcircuitthatprovidesbothdigitaldownconversionanddigitalupconversionoptimizedforcellularbasetransceiversystems.
ThedevicesupportsbothUMTSandCDMA2000(CDMA)airinterfacecellularstandards.
Thechipprovidesupto24CDMAdigitaldownconverter(DDC)anddigitalupconverter(DUC)channelsor12UMTSDDCandDUCchannels.
TheGC5316canalsosupportacombinationofCDMAandUMTSchannels.
TheDDCandDUCchannelsareindependentandoperatesimultaneously.
Thechipisidealforcellularbasetransceiversystemswherealargenumberofdigitalradiochannelsarerequired.
Eachofthe24CDMA(or12UMTS)channelscanoperateindependently.
OntheDDCsidetherearefour16bitinputportsthatcanacceptrealorcomplexinputdata.
Theinputportsaredrivenwithparalleldata,typicallyfromananalog-to-digitalconverter.
Eachdownconverterchannelcanbeprogrammedtoacceptdatafromanyoneofthefourinputports.
OntheDUCside,therearefour18-bitoutputports.
EachoutputportcansumanyoftheDUCchannelsinadaisy-chainfashion.
ThispermitscreatingastackofCDMAorUMTSsignals.
Theseportscanoutputeitherrealorcomplexdata.
RealoutputdatawouldgenerallydriveoneormoreD/Aconvertersandoutputthestackofsignalsatanintermediatefrequency(IF).
Complexdata(atbasebandoranIF)isusedwhenaquadraturemodulatorupconversionschemeisemployed.
Complexoutputdatacanalsobeusedwhentheoutputstackisfurtherprocessedusingcrestfactorreductionorpoweramplifierpredistortiontechniques.
TableofContents1Description12GC5316Receive33GC5316Transmit254GC5316GeneralControl455GC5316Programming486GC5316PinDescription627Specification70PRODUCTIONDATAinformationiscurrentasofpublicationdate.
ProductsconformtospecificationsperthetermsofTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
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1FunctionalBlockDiagram21166Control&Sync44JTAG1616161621SerialBasebandReceiveChannelOutputsSerialBasebandTransmitChannelInputsReceiveInputDataInterfaceReceiveInputData(fromA/Ds)tx_Iflagtx_clk_outtxout_atxout_btxout_ctxout_drxin_arxin_brxin_crxin_dadcclkd0d15a0a5rd_nwr_nce_nrxclktxclkrx_syncadtx_syncadreset_nsynccontrolsynccontrolrx_sync_outtx_sync_outinterruptsyncsyncDDCs29DUCs29syncsyncI&QI&QTransmitOutputInterfaceDDC02CDMA20001Xor1UMTSDDC12CDMA20001Xor1UMTSDDC102CDMA20001Xor1UMTSDDC112CDMA20001Xor1UMTSDUC112CDMA20001Xor1UMTSDUC102CDMA20001Xor1UMTSDUC12CDMA20001Xor1UMTSDUC02CDMA20001Xor1UMTStdotcktrst_ntditmsTransmitOutputData(toD/As)1.
2Package/OrderingInformationPRODUCTPACKAGELEADPACKAGEDESIGNATORSPECIFIEDTEMPERATURERANGEPACKAGEMARKINGORDERINGNUMBERTRANSPORTMEDIA,QUANTITYGC5316ThermallyEnhancedPlasticBGAw/HeatSlug388ZED40°Cto85°CGC5316IZEDGC5316IZEDTray,40GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com32GC5316Receive16161616ReceiveInputData(toA/Ds)ReceiveInputInterfaceGeneralpurposeoutputsyncFrameSyncDDC10&11SerialOutputsReceiveSyncsrx_distributionFrameSyncDDC0&1DDC02CDMA20001Xor1UMTSDDC12CDMA20001Xor1UMTSDDC102CDMA20001Xor1UMTSDDC112CDMA20001Xor1UMTSrx_syncarx_syncbrx_synccrx_syncdReceiveinputsyncrxin_arxin_brxin_crxin_daddcclkrxout_0_arxout_0_brxout_0_crxout_0_drxout_1_arxout_1_brxout_1_crxout_1_drx_sync_out_0rxout_10_arxout_10_brxout_10_crxout_10_drxout_11_arxout_11_brxout_11_crxout_11_drx_sync_out_5rx_sync_outICDMAChAICDMAChBQCDMAChAQCDMAChBForCDMAForUMTSImsbUMTSImsb1UMTSQmsbUMTSQmsb1UMTSrxclk(receivechipclock)DDCs2through9Figure1.
ReceiveSectionThereceivesectionoftheGC5316consistsofthereceiveinputinterface,therx_distributionbus,and12digitaldownconverterblocks.
Thepurposeofthereceiveinputinterfaceistoacceptsignaldatafromfourinputports(generallyfromanalog-to-digitalconverters)andtodistributethedatatotheDDCblocks.
Theinputinterfacealsohasauser-controlledtestgeneratorandnoisesource,aswellasaresamplingblock.
Theresampleracceptsrealinputsat3/4rxclkorrxclkrate,mixesdownbyFs/4,low-passfilters,anddecimatestorxclk/2.
Thisisusefulforhandlingdataat3/4rxclkrate(forexample,a92.
16-MSPSadcclkratewitha122.
88-MHzrxclk).
Itisalsousefultoprocessmorethan12CDMAsignalswhensamplingatrxclkrate.
Therx_distributionbusdistributesthefourchannelsofsignaldatatoeachofthe12DDCblocks.
EachDDCblockselectsoneofthefourchannelsfromtherx_distributionbusandthenperformsdownconversiontuning,programmabledelay,channelfilteringwithdecimation,powermeasurement,fixedgainadjust,andautomaticgaincontrol.
EachDDCblockcansupportoneUMTSchannelortwoCDMAchannels.
AnoptionalmodepermitsstackingtwoDDCblockstoprovidedouble-lengthchannelfiltering.
Tuned,filtered,anddecimatedsignaldataisoutputinbitserialformat.
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1ReceiveInputInterfaceFIFOResamplerBlockSelectSelectFIFOBypassBypass18181818Upper16of18Upper16of1816Test&NoiseGeneratorTest&NoiseGenerator1616ResamplerBlockSelectSelectFIFOFIFOBypassBypass18181818Upper16of18Upper16of18161616Test&NoiseGeneratorTest&NoiseGenerator16IQIQbus0bus1bus2bus3rxin_arxin_brxin_crxin_dSelectresampler_enaSpecial92.
16MSPSinputratemoderx_distributionFigure2.
ReceiveInputInterfaceThefourportssupportfourindependentrealinputsignalsortwocomplex.
ComplexsignaldataisinputwithIdatadrivingoneinputportandQdatadrivinganother.
Thismeansthatthereareonlytwosignaldataportsavailablewhenincomplexinputmode.
ThemappingofIandQdataontothefourinputportsisprogrammable.
2.
1.
1TestandNoiseGeneratorandFIFOIncomingdatafirstentersthetestandnoisegeneratorblock.
Thisblockcaneitherpassthedatathrough,replacetheinputdatawithapatterngeneratedinternally(usefulintest),orcanaddnoisetotheinputatauserprogrammablelevel.
Mostapplicationspassdatathroughthisblockunchangedbyclearingslf_tst_ena,rduz_sens_ena,andtst_on.
Testsequencesareusefulforboardbring-uporforpower-onself-test.
Boardbring-upandself-testproceduresandconfigurationfilesareavailableontheweb.
Self-testwillbedescribedingreaterdetailinalatersection.
Sufficetosayherethatthereceivedatainputisreplacedbypseudo-randompatternsatthispointintheprocessingchain.
Afewapplicationsthatrequirereceiverdesensitizationwhichisdonebyaddingdigitalnoisetotheinput.
Thesamepseudo-randomsequencegeneratorisusedasanoisesource.
Nz_pwr_maskisusedtoselectwhichinputdatabitsgetnoiseaddedtothem.
Inthiswaytheuserhascontroloverthenoisepowerintroducedinreceiverdesensitization.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com5Nextthesignalissenttoan8-stageFIFO.
Thisallowsanarbitraryphaserelationshipbetweenadcclkandrxclk.
Thefrequencyrelationshipisfixedbytheconfiguration.
TheFIFOcanbebypassed,clockingtheinputdatadirectlyonrxclk.
NotethatiftheFIFOisbypassed,theholdtimesarelongerthanusual.
Iftheinputrateisafraction(1/2,1/4,or1/8)ofrxclkthenssel_rxindetermineswhichofthemultiplerisingclockedgesareusedtosamplethedata.
Table1.
ProgrammingVARIABLEDESCRIPTIONrduz_sens_enaWhenenabledaddsnoisetotheADCinputusingnz_pwr_mask.
nz_pwr_maskSelectsthenoisebitstobeaddedtotheADCinputsamplewhenrduz_sens_enaisone.
adc_fifo_bypassWhenassertedbypassestheinputFIFO.
DataislatcheddirectlyusingtherxclkinputwhenFIFOisbypassed.
Shouldsetthisto0wheninputdataistobelatchedusingtheadcclkinput.
Mostapplicationsshouldnotbypassthefifo.
2.
1.
2ResamplerBlockTwoofthefour16-bitdatainputports,rxin_a,andrxin_chaveresamplerblocks.
Thedataisclockedfromanexternalclocksignaladcclk.
Therealinputsignalisdownconvertedbyadcclk/4andisthenlow-passfilteredanddecimated.
Decimationcanbeeitherby1.
5orby2.
Boththesedecimationmodessupportupto24CDMADDCchannels,or12UMTSDDCchannels.
2ResamplerDecimateby1.
53LPF24tapadcclk4adcclkrxclk34=1818busb(ord)busa(orc)IQatrxclk/2IQ16rxin_a(orc)atadcclkrx_distributionFigure3.
ResamplerDecimateby1.
5ModeThedecimateby1.
5moderequirestheinputdataratetobe3/4ofthereceiveclockrate(adcclkfrequencyis3/4rxclkfrequency).
A24-taplow-passdecimationfilterwithprogrammable18-bitcoefficientsremovesaliasimagesthatwouldfoldintothepassbandpriortodecimation.
Thefollowingtableshowstheperformanceoffiltersdesignedforvariousbandwidthswhentheresamplerisdecimatingby1.
5.
Thetablealsoshowstheresultingpassbandfrequenciesassumingtheinputdatarateis92.
16MSPS.
Eachhorizontalrowisaunique24-tapfilterwhichisavailableontheweb.
Table2.
ResamplerFilterPerformanceintheDecimateby1.
5ModeGENERALAPPLICATIONEXAMPLEAPPLICATIONadclk:92.
16MHzPASSBANDRIPPLESTOPBANDBANDWIDTHFLOWERFCENTERFUPPERofclkdBdBMHzMHzMHzMHz0.
050101.
518.
413.
82332.
30.
0609822.
1122334.
10.
07091.
725.
810.
12335.
90.
080.
0184.
129.
58.
32337.
80.
090.
0375.
633.
26.
52339.
60.
10.
0767.
136.
94.
62341.
50.
110.
1859.
540.
62.
82343.
30.
050101.
518.
413.
82332.
30.
0609822.
1122334.
1GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com6ResamplerDecimateby22LPF12tapadcclk4adcclkrxclk1=1818busb(ord)busa(orc)IQ@rxclk/2IQ16rxin_a(orc)@adcclkrx_distributionFigure4.
ResamplerDecimateby2ModeThedecimateby2modepermitsinputdataratesuptotherxclkrate(adcclkfrequencyequalsrxclkfrequency).
Thisisusefulforprocessinguptotworealinputsattherxclkrateandextractingmorethan12CDMAsignals.
A12-taplow-passdecimationfilterwithprogrammable18-bitcoefficientsremovesaliasimagesthatwouldfoldintothepassbandpriortodecimation.
Table3showstheperformanceoffiltersdesignedforvariousbandwidthswhentheresamplerisdecimatingby2.
Table3alsoshowstheresultingpassbandfrequenciesassumingtheinputdatarateis122.
88MHz.
Eachhorizontalrowisaunique12-tapfilterwhichisavailableontheweb.
Table3.
ResamplerFilterPerformanceintheDecimateby2ModeGENERALAPPLICATIONEXAMPLEAPPLICATIONadclk:122.
88MHzPASSBANDRIPPLESTOPBANDBANDWIDTHFLOWERFCENTERFUPPERofclkdBdBMHzMHzMHzMHz0.
060109.
814.
723.
330.
7238.
10.
07098.
817.
222.
130.
7239.
30.
08093.
419.
720.
930.
7240.
60.
090.
0189.
222.
119.
730.
7241.
80.
10.
0281.
524.
618.
430.
72430.
110.
0576.
82717.
230.
7244.
20.
120.
0971.
429.
51630.
7245.
50.
130.
1666.
531.
914.
730.
7246.
70.
140.
2861.
834.
413.
530.
7247.
9Theoutputofthisprocessingblockiscomplexatrxclk/2andgoesthroughtheselectortodrivetherx_distributionbus.
Idataforchannelrxin_aisroutedtoaselectordrivingDDCbus1,theQdataisinputtoaselectordrivingDDCbus0.
Idataforchannelrxin_cisroutedtoaselectordrivingDDCbus3,theQdataisinputtoaselectordrivingDDCbus2.
Table4.
ProgrammingVARIABLEDESCRIPTIONresampler_enaWhenasserted,turnsontheresamplersoninputportsrxin_aandrxin_c.
resampler_decim1=decimateby1.
5x,0=decimateby2xrate_selThisselectstheFIFOoutputratewhenadc_fifo_bypass=0.
Whenusingtheresampler,thisvalueshouldbeprogrammedtoa0.
Whensetto0,theFIFOoutputisclockedbyrxclk(gatedifresamplerisonanddecimatingby1.
5).
Whensetto1,theFIFOoutputrateis1/2ofrxclkrate.
Whensetto2,theFIFOoutputrateis1/4ofrxclkrate,andwhensetto3,theFIFOoutputisat1/8ofrxclkrate.
e.
g.
:Withrxclk122.
88MHz,setrate_selto0,1,2,or3respectivelyforadcclk122.
88,61.
44,30.
72,or15.
36MHz.
ssel_rxin(2:0)Synchronizestherx_distributionbussourceanddestinationandclockgenerationineachoftheDDCblocks.
ssel_resamp(2:0)SynchronizestheresamplerFs/4mixeranddecimation.
ssel_adc_fifo(2:0)SynchronizestheFIFOreadandwritepointers(fifodepth).
remix_onlySetto0forcomplexinputdata,orto1forrealdata.
Setthisvalueto0whenusingtheresampler.
Notethatmixedralandcomplexinputisnotallowed.
resamplercoefficientsTheresample's18-bitcoefficientsareloadedbythesoftwarecmd5316.
Theusermustprovideacoefficientfilewithoneintegercoefficientperline.
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2DDCOrganizationCDMADDCADDC0CDMADDCB181818184to1Switch4to1SwitchFromInputInterfaceDDC1DDC2DDC3DDC4DDC5DDC6DDC7DDC8DDC9DDC10DDC11Figure5.
ReceiveDDCBlocksTheGC5316providesdownconversionforupto24CDMA2000receivechannelsor12UMTSreceivechannels.
Downconversionchannelsareorganizedinto12DDCblocks.
EachDDCblockprovidestwoCDMA2000DDCchannels,AandB,oroneUMTSchannel.
EachDDCblockhasitsownregistersetandmaybeprogrammedindependently(exceptforparametersspecifyingtheconfigurationoftherx_distributionbus).
TwoDDCblocks(forexample,DDC0andDDC1)canbestrappedtogethertoformasingleUMTSDDCchannelwithdouble-lengthfiltering.
TheGC5316canthereforeprovidesixUMTSDDCchannelswithdouble-lengthFIRfiltering.
Configurationparametersendingin_aapplytotheACDMAchannelortotheUMTSchannel.
Parametersendingin_bapplytheBCDMAchannelandareunusedinUMTSmode.
ManyparametersaresharedbetweentheAandBchannelsinCDMAmode(suchasfiltercoefficients),whilekeyparametersareindependentforthetwochannels(suchasfrequency,phase,andgain).
BothCDMADDCchannelsinablockcanbeindependentlytuned,thoughtheywouldlikelybeusedasdiversitypairsandtunedtothesamefrequency.
FiltercoefficientsaresharedbetweenthetwoCDMADDCchannelswithinablock.
Table5.
ProgrammingVARIABLEDESCRIPTIONddc_duc_enaWhensetturnsontheDDC.
WhenclearedtheclocktotheDDCisstoppedreducingitspowerconsumptiontoessentiallyzero.
cdma_modeWhenset,putstheDDCblockindualCDMA2000mode.
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3ReceiveDownconverterFunctionBlocksAGCCFIRFilterDecby218FrequencyPhase3216NCODelayAdjustI,QSerialInterfaceupto18bits(25bitswithAGCdisabled)PFIRFilterDecby1SixStageCICFilterDec4324to2Select181818ZeroPadserialRMSPowerMeasureFigure6.
ReceiveDownconverterFunctionBlocksTheGC5316downconversionchannelcanprocesstwoCDMAcarriersorasingleUMTScarrier.
Signaldataisselectedfromoneoffourportsandcanbeeitherrealorcomplex.
Datafromtheselectedportismultipliedwithacomplex,programmablenumericallycontrolledoscillator(NCO)whichtunesthesignalofinteresttobaseband.
Thedelayadjustandzeropadblockspermitsadjustmentofthedelayintheend-to-endchannel.
Zeropaddinginterpolatesthesignaltotherxclkrate.
FilteringconsistsofasixstageCICfilterwhichdecimatesthetuneddatabyafactorfrom4to32,acompensatingFIRfilter(CFIR)whichdecimatesbyafactoroftwo,followedbyaprogrammableFIRfilter(PFIR)whichdoesnotdecimate.
TheRMSpowermetermeasuresthepowerwithinthechannel'sbandwidth.
TheAGCautomaticallydrivesthegainandkeepsthemagnitudeofthesignalatauser-specifiedlevel.
Thisallowsfewerbitstorepresentthesignal.
Theserialoutputinterfaceformatsandroundstheoutputdata.
Eachoftheaboveblocksisdescribedingreaterdetailinthefollowingsections.
2.
3.
1ReceiveMixer20SinCos1818FromInputDataInterfaceToChannelDelayFromNCO18181818DeMux&RoundIAQAIBQBInputSelect18181818Figure7.
ReceiverMixerTheinputselectroutesoneofthefourbusesinrx_distributiontotheIportandasecondbustotheQportofthemixer.
InCDMAmode,busselectionistimemultiplexedsothetwochannelsmayselectdifferentdatasourcesifdesired.
Table6showsthebusselection.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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BusSelectionSELECTVALUEDATATAKENFROMRX_DISTRIBUTIONBUSIDataQData0BusaBusa1BusbBusb2BuscBusc3BusdBusd4BusaBusb5BusaBusc6BusaBusd7BusbBusa8BusbBusc9BusbBusd10BuscBusa11BuscBusb12BuscBusd13BusdBusa14BusdBusb15BusdBuscThereceivemixertranslatestheinputfromselectortobasebandwheresubsequentfilteringisperformedtoisolatethesignalofinterest.
Themixerisacomplexmultiplierthataccepts18-bitIand18-bitQsignaldatafromthereceiveinputinterfaceand20-bitsineandcosinesequencesfromtheNCO.
TheNCOgeneratesamixingfrequency(sometimesreferredtoasalocaloscillator,orLO)specifiedbytheusersothatthedesiredsignalofinterestistunedto0Hz.
TheNCOisdiscussedindetailinthenextsection.
ADDCchannelcansupportoneUMTSsignaldirectly,ortwoCDMAchannelsathalftheinputrate.
WheninCDMAmodeeachchannelmaysetthepathselection,themixertuningandphaseindependently.
Themixeroutputproducestwocomplexstreams;onerepresentingthesignalpathfortheA-sideDDC,theothertheB-side.
Eachofthesestreamsdrivesachanneldelayandzeropadblock.
ThemaximuminputrateforUMTSisrxclkforeitherrealorcomplexinputdata.
Themaximumrx_distributionrateinCDMAmode(realorcomplexinputs)isrxclk/2.
Whenadcclk/rxclk>1/2,thisisnormallyaccomplishedusingtheresampler.
Forunusualcaseswhereadcclk/rxclk=1andtheresamplerisnotused,cdma_modemustbezerosoonlyonesignalcanbeprocessedinaDDCblock,evenifitisaCDMAsignal.
Themixergainis:Gain+2mixer_gain*2Table7.
ProgrammingVARIABLEDESCRIPTIONddcmux_sel_a(3:0)ProgramstheIandQcomplexinputdataroutingontotwoofthefourinputportsforstreamAofCDMADDCddcmux_sel_b(3:0)ProgramstheIandQcomplexinputdataroutingontotwoofthefourinputportsforstreamBofCDMADDCremix_onlySetto0forcomplexinputdata,orto1forrealdatach_rate_sel(1:0)InformstheDDCoftherx_distributionbusrate(1,1/2,1/4,or1/8rxclkforsettings0,1,2,or3respectively.
NotethisparametermustbethesameinallenabledDDCblocks.
mixer_gainWhenassertedadds6dBofgaininthemixer.
Thisgainishighlyrecommended.
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3.
2ReceiveNumberControlledOscillator(NCO)FrequencyWord3232PhaseOffsetDitherGenDitherSync32FrequencySync5ZeroPhaseSync16PhaseOffsetSync2318RegRegSin/CosTable20CosSinClrReg20Figure8.
ReceiveNumberControlledOscillatorTheNCOisadigitalcomplexoscillatorthatisusedtotranslate(ordownconvert)aninputsignalofinteresttobaseband.
Theblockproducesprogrammablecomplexdigitalsinusoidsbyaccumulatingafrequencywordwhichisprogrammedbytheuser.
TheoutputoftheaccumulatorisaphaseargumentthatindexesintoaSin/CosROMtablewhichproducesthecomplexsinusoid.
Aphaseoffsetcanbeaddedpriortoindexingifdesiredforchannelcalibrationpurposes.
ThischangestheSin/Cosphasewithrespecttootherchannels'NCOs.
A5-bitdithergeneratorisprovidedandgeneratesasmalllevelofdigitalpseudo-noisethatisaddedtothephaseargumentbelowthebottombitandisusefulforreducingNCOspuriousoutputs.
Table8.
ProgrammingVARIABLEDESCRIPTIONdither_ena(2)Whensetturnsditheron.
Clearingturnsditheroff.
test_bits_1(1:0)Testbits.
MUSTbeclearedfornormaloperation.
TheNCOspuriouslevelsarebetterthan–115dBC.
Addedphaseditherrandomizestheperiodicnatureofthephaseaccumulationprocessandreduceslow-levelspuriousenergy.
Forsomefrequencies(K*Fs/24),ditherisineffective–inthesecasesaninitialphaseoffourreducesNCOspurs.
Figure9andFigure10showthespurlevelperformanceoftheNCOwithoutdither,withdither,andwithaphaseoffsetvalue.
a)WorstCaseSpectrumWithoutDitherb)SpectrumWithDither(TunedtoSameFrequency)Figure9.
ExampleNCOSpursWithandWithoutDitherGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com11a)PlotWithoutDitherorPhaseInitializationb)PlotWithDitherandPhaseInitializationFigure10.
NCOPeakSpurPlotThetuningfrequencyisspecifiedasa32-bitfrequencywordandisprogrammedastwosequential16-bitwordsoverthecontrolport.
TheNCOoperatesatthesamespeedastherx_distributionorrxclk/(tadj_interp_decim+1).
TheNCOfrequencyresolutionissimplytheFclk/232.
Asanexample,ataninputclockrateof61.
44MHz,thefrequencystepsizewouldbeapproximately14milli-Hertz(mHz).
Thefrequencywordisdeterminedbythefollowingformula:FrequencyWord(indecimal)+232TuningFrequencyFclkNotethatfrequencytuningwordscanbepositiveornegativevalued.
Specifyingapositivefrequencyvaluetranslatesnegativefrequenciesupwardstowards0Hz.
Specifyinganegativetuningfrequencytranslatespositivefrequenciesdownwardstowards0Hz.
Table9.
ProgrammingVARIABLEDESCRIPTIONphase_add_a(31:0)32-bittuningfrequencywordfortheA-sideDDCwheninCDMAmode.
AlsoforUMTSmode.
phase_add_b(31:0)32-bittuningfrequencywordfortheB-sideDDCwheninCDMAmode.
NotusedinUMTSmode.
Eachofthe24CDMADDCchannelscanbeloadedwithuniquefrequencywords.
ThephaseoftheNCO'sSin/CosoutputcanbeadjustedrelativetothephaseofotherchannelNCOsbyspecifyingaphaseoffset.
Thephaseoffsetisprogrammedasa16-bitword,yieldingastepsizeofabout5.
5milliDegrees.
Thephaseoffsetwordisdeterminebytheformula:PhaseOffsetWord+216OffsetinDegrees360orPhaseOffsetWord+216OffsetinRadians2pTable10.
ProgrammingVARIABLEDESCRIPTIONphase_offset_a(15:0)16-bitphaseoffsetwordfortheA-sideDDCwheninCDMAmode.
AlsoforUMTSmode.
phase_offset_b(15:016-bitphaseoffsetwordfortheB-sideDDCwheninCDMAmode.
NotusedinUMTSmode.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com12Eachofthe24CDMADDCblockscanbeloadedwithuniquephaseoffsetwords.
VarioussynchronizationsignalsareavailablewhichareusedtosynchronizetheNCOsofallchannelswithrespecttoeachother.
Frequencysync(ssel_freq)andphaseoffsetsync(ssel_phase)determinewhenfrequencyandphaseoffsetchangesoccur.
Forexample,generatingafrequencysyncafterprogrammingthetwofrequencywordscausestheNCO(ormultipleNCOs)tochangefrequencyatthattime,ratherthanaftereachofthetwofrequencywordsareprogrammedoverthecontrolbus.
Notethatthefrequencyandphasewordsarenotloadedintotheworkingregisteruntiltheirrespectivesync'sarereceived.
Thezerophasesyncsignal(ssel_nco)isusedtoforcethesineandcosineoscillatorstotheirzerophasestate.
Notethatthisisaninstantaneousphasejump,sothessel_ncoshouldonlybeissuedwhenresettingachannel.
Dithersync(ssel_dither)canbeusedtosynchronizethedithergeneratorsofmultipleNCOs.
Thisisnormallyonlyrequiredforapplicationsthatareperformingbitmatchtesting.
TheNCOsusedinthetransmitsectionareidenticaltowhatisdescribedforthereceivesection.
Notethatthereisonesetofsync'sprovidedforeachDDC.
WhenoneDDCisusedtoprocesstwoCDMAsignalthesync'saresharedbetweenthem.
Table11.
ProgrammingVARIABLEDESCRIPTIONssel_nco(2:0)SyncsourceforNCOaccumulatorresetssel_dither(2:0)SyncsourceforNCOditherresetssel_freq(2:0)SyncsourceforNCOfrequencyregisterloadingssel_phase(2:0)SyncsourceforNCOphaseregisterloading2.
3.
3ReceiveFilteringandDecimationThepurposeofthereceivefilterchainistoisolatethesignalofinterest(andrejectallotherothers)thathasbeenpreviouslytranslatedtobasebandviathemixerandNCO.
Theoveralldecimationthroughthechainalsoneedstobeconsidered.
Thegoal,generally,istooutputtheisolatedsignalataratethatistwice(2X)thesignal'schiprate.
ForUMTS,thiswouldbe7.
68MSPS.
ForCDMAtheoutputrateshouldbe2.
4576MSPS.
Receivefilteringanddecimationisperformedinseveralstages:DZeropaddingtointerpolatetheinputsamplerateifneededuptotherxclkrateDHighratedecimation(4to32)usingasixstagecascade-integratecombfilter(CIC)DDecimatebytwocompensationfilteringusingtheprogrammablecompensatingFIRfilter(CFIR)DDecimatebyonepulse-shapefilteringviatheprogrammableFIRfilter(PFIR)CFIRFilterDecby2DelayAdjustPFIRFilterDecby1SixStageCICFilterDec432ZeroPadFromMixerFigure11.
DDCFilterChainThefollowingtablecontainssomeexampleslistingthedecimationandsampleratesattheoutputofeachblockforUMTSandCDMAstandardsatinputsampleratesof61.
44MSPSand15.
36MSPS,assumingtheGC5316isclockedat122.
88MHz.
Table12.
ExampleUMTSandCDMA2000DDCReceiveModesINPUTSAMPLERATE(MSPS)ZEROSADDEDZEROPADOUTPUTRATE(MSPS)CICDECIMATIONCICOUTPUTRATE(MSPS)CFIRDECIMATIONCFIROUTPUTRATE(MSPS)PFIRDECIMATIONPFIROUTPUTRATE(MSPS)UMTS61.
441122.
88815.
3627.
6817.
68UMTS15.
367122.
88815.
3627.
6817.
68CDMA61.
441122.
88254.
915222.
457612.
4576CDMA15.
367122.
88254.
915222.
457612.
4576GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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3.
4ReceiveChannelDelayAdjustandZeroInsertionFigure12.
DelayAdjustandZeroInsertionThereceivechanneldelayadjustfunctionisusedtoaddprogrammabledelaysinthechanneldownconvertpath.
AdjustingchanneldelaycanbeusedtocompensateforanalogelementsexternaltotheGC5316digitaldownconversionsuchascables,splitters,analogdownconverters,filters,etc.
Therearetwofunctionsthatneedtobeconsideredwithrespecttoprogrammingthechanneldelay;thedelaymemoryandthezeropadblocks.
Theparametertadj_interp_deciminformstheDDCblocktherateatwhichdataisarrivingontherx_distributionbus.
Thezeropadblockinterpolates(insertzeros)tobringthesignalsamplerateuptorxclkrate.
Thedelaymemoryprovidesupto64sampledelayattherx_distributionrate.
Readoffset(tadj_offset_coarse)isaprogrammabledifferencebetweenthereadandwritepointerstothedelaymemory.
Thisprovidesamaximumdifferentialdelaybetweenchannelsof64/rx_distribution_rate.
Atanrx_distributionrateof61.
44MSPSthe64memoryslotsinthedelaymemoryprovideanoveralldelaywindowofabout1s.
Thessel_taj_coarsesynccontrolsthetimingforupdatingthecoarseoffset.
Thezeropadblockinserts0,1,3,or7zerosbetweeneachsamplecomingfromthemixerbringingthesamplerateuptorxclk.
Thetadj_offset_fineparameterspecifieswhenthezerosareinsertedrelativetothessel_tadj_finesyncsignal.
Thispermitsafineadjustmentattherxclkrate.
The3-bitinsertoffsetparameterallowsthezerostobeinserteduptotadj_interp_decim(max8)high-speedclocksafterssel_tadj_finesyncisasserted.
Thisprovidesatimeadjustresolutionof1/rxclk.
ForUMTSandassumingaGC5316clockfrequencyof122.
88MHz,thetimeresolutionis3.
84MCPS/122.
88MSPS=1/32ofachip.
ForCDMA,theresolutionis1.
2288/122.
88=1/100ofachip.
Table13.
ProgrammingVARIABLEDESCRIPTIONtadj_offseta_coarse_a5:0)Readoffsetintothe64elementmemoryfortheAchannelDDC.
Note:Whentadj_offset_coarse_a=62,thenthedelayis–2.
Whentadj_offset_coarse_a=63,thenthedelayis–1.
Forallothervalues,theresultingdelayisequaltothevalue.
tadj_offset_coarse_b(5:0)Readoffsetintothe64elementmemoryfortheBchannelDDCwheninCDMAmode.
Note:Whentadj_offset_coarse_b=62,thenthedelayis–2.
Whentadj_offset_coarse_b=63,thenthedelayis–1.
Forallothervalues,theresultingdelayisequaltothevalue.
tadj_offset_fine_a(2:0)Controlsthezerooffset(fineadjust)fortheAsideoftheDDC.
tadj_offset_fine_b(2:0)Controlsthezerooffset(fineadjust)fortheBsideoftheDDCwheninCDMAmode.
tadj_interp_decim(2:0)Theinterpolationvalueminusone.
Validinterpolationsare(1,2,4,or8).
Validprogramvaluesforthisparameterare(0,1,3,or7).
SameforAandBchannelswheninCDMAmode.
ssel_tadj_fine(2:0)Selectsthesyncsourceforthefinetimeadjustssel_tadj_coarse(2:0)SelectsthesyncsourceforthecoarsetimedelayadjustGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com142.
3.
5ReceiveCICFilterZ1Z1Z1Z1Z1Zm1Z1Zm2Zm3Zm4Zm5Zm6Shiftm1,m2,m3,m4,m5,m6=1or2Decimateby432NRound&Limit2418185424Downshift536Figure13.
SixStageCICFilterTheCICfilterprovidesthefirststageoffilteringandlarge-valuedecimation.
Thefilterconsistsofsixstagesanddecimatesoverarangefrom4to32.
IdataandQdataarehandledseparatelywithtwoCICfilters.
Inaddition,wheninCDMAmode(twoCDMAchannelsprocessedwithinasingleDDC),anotherpairofCICfiltershandlestheB-sidechannel.
Thefilterresponseis(Sin(x)/x)6incharacterwherethekeyattributeisthattheresultingresponsenullsaliasbacktodcwhenthesignalisdecimated.
ThealiasingrejectionachieveddependsonthebandwidthofthesignalofinterestrelativetotheCICoutputsamplerate.
Agoodruleofthumbisthesignalofinterestshouldbelessthan25%oftheCICoutputrate.
ThismeansthattheCICdecimationvalueshouldbechosensothatthesignalexitingtheCICfilterisoversampledbyatleastafactoroffour.
(Generally,itiscloseenoughfordigitalsignalsthattheCICoutputratebeatleastfourtimesthesymbolrate).
ThefilterisequivalenttosixstagesofaFIRfilterwithuniformcoefficients(sixcombinedboxcarfilterstages).
EachfilterwouldbeoflengthNcicifm=1,or2*Ncicifm=2.
Thefilterismadeupofsixbanksof54-bitaccumulatorsectionsfollowedbysixbanksof24-bitsubtractorsections.
Eachofthesubtractorsectionscanbeindependentlyprogrammedwithadifferentialdelayofeitheroneortwo.
Ashiftblockfollowsthelastintegrationstageandcanshiftthe54bitaccumulateddatadownby36cic_scale(aprogrammablefactorfrom0to31bits).
TheCICfilterexhibitsadroopacrossitsfrequencyresponse.
ThisshouldbecompensatedineithertheCFIRorPFIRfiltersthatfollow.
Typically,droopcompensationisdoneintheCFIRbutitisalsopossibletocompensateforCICdroopinthePFIRfilter.
ThegainofthereceiveCICfilteris:Ncic6*2(numberofstageswhereM=2)*2(36+CIC_SCALE)whereCIC_SCALEis0to31.
ThereisnorolloverprotectioninternaltotheCICoratthefinalroundsotheusermustguaranteenosampleexceedsfullscalepriortorounding.
Forpracticalpurposes,thismeanstheCICgainmustbelessthanorequaltoone.
Afixedgainof12dBattheoutputoftheCICcanalsobeprogrammed.
ThepostCICgainisrolloverprotected.
PostCICgain=2(cic_gain_ddcx2).
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com15Table14.
ProgrammingVARIABLEDESCRIPTIONcic_interp_decim(4:0)TheCICdecimationratio(4to32)Ncic=cic_interp_decim+1.
ThisratioappliestobothAandBchannelsoftheDDCblock.
cic_scale_a(4:0)TheshiftvaluefortheAchannel.
cic_scale_b(4:0)TheshiftvaluefortheBchannel.
cic_gain_ddcWhenasserted,addsagainof12dBattheCICoutput.
cic_m2_ena_a(5:0)SetsthedifferentialdelayvalueMforeachoftheCICsubtractorstagesfortheAchannel.
Cic_m2_ena_a(0)controlsm1inthefigureabove.
cic_m2_ena_b(5:0)SetsthedifferentialdelayvalueMforeachoftheCICsubtractorstagesfortheBchannel.
cic_bypassTestfeature.
Clearfornormaloperations.
ssel_cic(2:0)Setssyncing(1of8sources)fortheCICdecimationmoment.
2.
3.
6ReceiveCompensationFIRFilterThereceiveCFIRfilterdecimatestheoutputoftheCICfilterbyafixedfactoroftwo.
Filtercoefficientsize,inputdatasize,andoutputdatasizeare18bits.
TheCFIRlengthcanbeprogrammed.
Thispermitsturningofftapsandsavingpowerifshorterfiltersareappropriate.
TheCFIRpowerdissipationisproportionaltoitslength.
Exploitingsymmetryofthecoefficientsbysettingsymmetric_cfirsavesasmallamountofpower(butprovidesnoadditionalavailabletaps).
ThemaximumCFIRfilterlengthisafunctionofGC5316clockrateandoutputsamplerateandislimitedbythenumberofcoefficientmemoryregisters.
Themaximumnumberoftapsis64andtheminimumnumberis14.
Lengthsbetweentheselimitscanbespecifiedinincrementsof2.
Subjecttotheaboveminimumandmaximumvalues,inthegeneralcase,thenumberoftapsavailableis:UMTMode:2rxclkoutputsamplerateCDMAModeifcic_iterp_decimiseven(decimatingbyanoddnumber):2(cic_intrp_decim)CDMAModeifcic_iterp_decimisodd(decimatingbyanevennumber):2(cic_intrp_decim)1)ForCDMA,assumingtheGC5316isclockedat122.
8MHzandwith2xoversampledoutputdata(2.
4576MSPS),theCFIRfilterlengthcanrangefrom14to48(not50)inincrementsof2.
ForUMTS,ataGC5316clockrateof122.
8MHzwith2xoversampledoutputdata(7.
68MSPS),theCFIRfilterlengthcanrangefrom14to32,inincrementsof2.
AsinglesetofprogrammedtapvaluesareusedforboththeA-sideandB-sideDDCchannels(twoCDMAchannels)withinasingleDDCblockwheninCDMAmode.
TheCFIRfilterperformstheconvolution,gainisappliedatfullprecision,thesignalisrounded,andthenhardlimited.
Thereisashifterattheoutputofthefilterthescalesthedatabyeither2e19or2e18.
Thegainthroughthefilteristherefore:Gain+Sum(CFIRcoefficients)2*19)cfir_gainwherecfir_gainis0or1GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONcrastsrttap_cfir(4:0)NumberofDDCCFIRfiltertapsis2(crastarttap+1)cfir_gainOnlyls-bitisused.
CFIRgain.
0=2e19,1=2e18TheCFIRfilter's18-bitcoefficientsareloadedintwo64wordmemories.
Zone2CFIRRAMholdsthelower2bitsofthe18bitcoefficients,.
ThisaddressisspecifiedbysettingupthepageregistertowritetoZone2andupperspacebitZp.
TheremainingbitsarespecifiedbyZZZZZwhichareGC5316addresspins.
ThetotaladdressisthusZpZZZZZwhichwritesto64locations.
TheCFIRfilter's18bitcoefficientsareloadedbythesoftwarecmd5316.
Theusermustprovideacoefficientfilewithoneintegercoefficientperline.
NotethattheCFIRfiltercoefficientsaresharedbytheAandBchannelsinCDMAmode.
2.
3.
7ReceiveProgrammableFIRFilterThereceiveprogrammableFIRfilter(PFIR)pulseshapesthebasebandsignaldata.
Itdoesnotperformanydecimation.
Filtercoefficientsize,input,andoutputdatasizeis18bits.
AspecialstrappedmodecanbeemployedforUMTSwheretwoadjacentDDCs(2kand2k+1,k=0to5)canbecombinedtoyieldafilterwithtwicethenumberofcoefficients.
ThePFIRlengthisprogrammable.
Thispermitsturningofftapsandsavingpowerifshortfiltersareappropriate.
Thefilter'soutputdatacanbeshiftedoverarangeof0to7bitswhereitisthenroundedandhardlimitedto18bits.
Theshiftrangeresultsinagainthatrangesfrom2e19to2e12.
ThegainofthePFIRblockis:Gain+Sum(CFIRcoefficients)2*19)pfir_gainwherepfir_gainranges07ThemaximumPFIRfilterlengthisafunctionofGC5316clockrateandoutputsamplerateandislimitedbythenumberofcoefficientmemoryregisters.
Themaximumnumberoftapsis64andtheminimumnumberis28(UMTS)or32(CDMA).
Lengthsbetweentheselimitscanbespecifiedinincrementsof4.
Subjecttotheaboveminimumandmaximumvalues,thenumberofmaximumtapsavailableis:UMTSMode:4rxclkoutputsamplerateStrappedMode:8rxclkoutputsamplerateCDMAMode:2rxclkoutputsamplerateThestrappedmodecanbeemployedforUMTSwheretwoadjacentDDCs(2kand2k+1,k=0to5)canbecombinedtoyieldafilterwithtwicethenumberofcoefficients.
ThismeanstheGC5316cansupportsixUMTSDDCchannelswithdouble-lengthfiltercoefficients.
Figure14showstheinterconnectbetweenthetwoDDCswhenthePFIRfiltersarestrapped.
Instrappedmode,dataoutofthelastPFIRdatadelayraminthemainDDC(DDC2k)issenttotheadjacentsecondaryDDC(DDC2k+1)PFIRasinputthusforminga128-tapdelayline.
Also,datareceivedfromtheadjacentPFIRsummersisaddedintothemainDDC'sPFIRsumtoformtheoutput.
Whenusingstrappedmode,setdouble_tapto2forthemain(even)DDCandto1forthesecondary(odd)DDC.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com17C0CN/21CN1CN/2PFIRPFIRFromCFIRFirstHalfCoefficientsSecondHalfCoefficientsTapDelayTapDelayDDC2KDDC2K+1Figure14.
DoubleTapModeInterconnectWhenindouble-tapmode,thefirsthalfofthecoefficientsshouldbeloadedintotheevenDDC,theremainingcoefficientsgointotheoddDDC.
TheevenDDCmustbeturnedon(ddc_duc_ena1),andtheoddDDCmustbeturnedoff(ddc_duc_ena0).
ForstrappedUMTSwithdoublelengthfilters,therangeoftapsavailableis56to128inincrementsofeight.
PFIRcoefficientsandgainshiftvaluesaresharedbetweenbothAandBCDMAchannelsinaDDCblock.
ThenumberofmaximumtapsavailablefordoublelengthUMTSmodeis:DoubleLengthUMTSMode:8x(rxclk÷outputsamplerate)Table16.
ProgrammingVARIABLEDESCRIPTIONcrastsrttap_pfir(3:0)NumberofDDCPFIRfiltertapsis4(crastartap+1)Fordouble-lengthPFIRthenumberoftapsis8(crastartap+1)pfir_gain(2:0)SetsthegainofthePFIRfilter.
double_tapWhenset,putstwoadjacentDDC(2kand2k+1,k=0to5)in127tapUMTSmode.
Setto0fornormalmode.
Setto2forthemain(even)DDCSetto1forthesecondary(odd)DDC.
Whenindoubletapmode,thefirsthalfofthecoefficientsshouldbeloadedintotheevenDDC,theremainingcoefficientsgointotheoddDDC.
ALSO:Indoubletapmode,theevenDDCmustbeturnedon(ddc_duc_ena1),andtheoddDDCmustbeturnedoff(ddc_duc_ena0).
ThePFIRfilter's18-oneintegercoefficientperline.
NotethatthePFIRfiltercoefficientsaresharedbytheAandBchannelsinCDMAmode.
Note:thattheabovePFIRfiltercoefficientsaresharedbetweenbothAandBsidesofaDDCblock.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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4ReceiveRMSPowerMeterIntegrate55bitsClearRegisterTransfer32IQ181818Bits(inincrementsof4samples)SyncRMSPowerInterrupt37SyncDelayCounter7Bits(insamples)Counter8Bits(inincrementsof1024samples)pmeter_sync_delay_ddcpmeter_integration_ddcTop3216PowerMeasurementTimeLineTime88SyncEventSyncDelayIntegrationStartIntegrationTimeIntegrationStartIntegrationTimeIntegrationTimeIntervalIntegrationStartIntervalIntegrationTimeCounterpmeter_interval_ddcIntervalInterruptInterruptInterruptFigure15.
ReceivePowerMeterandTimingEachDDCchannelincludesanRMSpowermeterwhichisusedtomeasurethetotalpowerwithinthechannelpassband.
ThepowermetersamplestheIandQdatastreamafterthePFIRfilter.
Both18-bitIandQdataaresquared,summed,andthenintegratedoveratimedeterminedbyaprogrammablecounter:pmeter_integration_ddc(16bits).
Theintegrationtimeisa16-bitwordwhichisprogrammedintothe18-bitcounter.
Integrationtime=4xpmeter_integration_ddc+1(inunitsofasampleperiodorgenerallychipperiod/2).
Thereisaprogrammable8-bitintervalcounterwhichsetstheintervaloverwhichpowermeasurementsarerepeated.
Thetimercountsinincrementsof1024samples.
Thisallowstheusertoselectintervalsfrom1x1024samplesupto256x1024samples.
Theintervaltime=1024xpmeter_interval_ddc.
Theintervaltimemustbegreaterthan(notequalto)theintegrationtime.
Thepowermeasurementprocessstartswithasyncevent(ssel_pmeter).
Theintegrationstartsatsyncevent+3chips+sync_delay.
The7-bitdelayregisterpermitsdelaysfrom3to130samplesaftersync.
Theintegrationcontinuesuntiltheintegrationcountismet.
Atthatpointthetop32bitsofthe55-bitaccumulatoristransferredtothereadregisterandaninterruptisgeneratedindicatingthepowervalueisreadytoread.
Theintervalcountercontinuesuntiltheprogrammedintervalcountisreached.
Whenreached,theintegrationcounterandtheintervalcounterstartoveragain.
Eachtimetheintegrationcountisreachedtheupper32bitsareagaintransferredtothereadregisteroverwritingthepreviousvalueandsendinganinterruptsignifyingthedataisreadytoberead.
Failuretoreadthedatatimelyresultsinoverwritingthepreviousintervalmeasurement.
Syncssel_pmeterstartstheprocess.
Wheneverasyncisreceived,allthecountersareresettozeronomatterwhatthestatus.
ForUMTS,IandQarecalculatedandtheintegratedpowerisread.
WheninCDMAmodethepoweriscalculatedforboththeAandBsignals,producingtwo32-bitresults.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com19ForCDMAmode,theintegrationtimeisslightlylonger.
ThepowerreadinCDMAmodewithadcinputis:Apower:[I2(Xx4+1)+Q2(Xx4+0)]223NotethatoneQsampleismissingfromtheintegration.
Bpower:[I2(Xx4+1)+Q2(Xx4+1)]223WhereXistheintegrationcount.
Table17.
ProgrammingFIELDDESCRIPTIONpmeter_result_a_lsb(15:0)Lower16bitsoftheADDCchannelpowermeasurementresult.
pmeter_result_a_msb(31:16)Upper16bitsoftheADDCchannelpowermeasurementresult.
pmeter_result_b_lsb(15:0)Lower16bitsoftheBDDCchannelpowermeasurementresult.
OnlyavailableforCDMA.
pmeter_result_b_msb(31:16)Upper16bitsoftheBDDCchannelpowermeasurementresult.
OnlyavailableforCDMA.
pmeter_integration_ddc(15:0)Integrationtime=4(1+pmeter_count_ddc).
pmeter_sync_delay_ddc(7:0)Startdelayfromsync=3+pmeter_sync_delay_ddc.
pmeter_interval_ddc(7:0)Intervaltime=1024(pmeter_interval_ddc+1).
Intervaltimemustbegreaterthan(notequal)integrationtime.
ssel_pmeter(2:0)Syncsourceoptionspmeter_sync_disableTurnsoffthesynctothechannelpowermeter.
Thiscanbeusedtoindividuallyturnoffsyncstoachannelspowermeter,whilestillhavingsyncstootherpowermetersonthechip.
2.
5ReceiveGainandAGCThereceiveAGCcanbeusedasasimplegainorasaflexibleAGC.
2.
5.
1ReceiveSimpleGainThereceiveAGCcanbeusedassimplegainbyfreezingtheAGCaccumulatoratitscurrentlevel,thenclearingthecurrentvalue.
Thisisdonebysettingtheagc_clearandagc_freezebits.
Theoutputcanberoundedfrom3to18bitsusingagc_rndorthefull25bitscanbeoutputbysettingagc_rnd_disable.
2.
5.
2ReceiveAGC82ShiftSelect225191819192424DelayDelayFreezeValidUnderLimitOverLimitAccumulateLimitUnder/OverDetectMagnitudeCompare18ValidClearShiftThreshold8Ucnt8Ocnt8Dblw4Dabv4Dzro4Dsat4Ucnt16Ocnt167integer&12Fractional7integer&12FractionalValidGain7integer&12Fractional18data+7overflow4RoundRoundA(t)=gainadjust4ZeroMaskInputOutput5S=+1,D=4bitshift(upto25bitsinAGCbypassmode)Figure16.
AGCBlockDiagramGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com20TheGC5316automaticgaincontrolcircuitisshownabove.
Thebasicoperationofthecircuitistomultiplythe18-bitinputdatafromthePFIRbya19-bitgainwordthatrepresentsagainorattenuationintherangeof0to128.
Thegainformatismixedintegerandfraction.
The7-bitintegerallowsthegaintobeboostedbyuptofactorof128(42dB).
The12-bitfractionalpartallowsthegaintobeadjustedupordowninstepsofonepartin4096,orapproximately0.
002dB.
Iftheintegerportioniszero,thenthecircuitattenuatesthesignal.
Thegainadjustedoutputdataissaturatedtofullscaleandthenroundedtobetween3and18bitsinstepsofonebitorthefull25bitsmaybeoutputbysettingagc_rnd_disable.
TheAGCportionofthecircuitisusedtoautomaticallyadjustthegainsothatthemedianmagnitudeoftheoutputdatamatchesatargetvalue,whichisperformedbycomparingthemagnitudeoftheoutputdatawithatargetthreshold.
Ifthemagnitudeisgreaterthanthethreshold,thenthegainisdecreased,otherwiseitisincreased.
Thegainisadjustedas:G(t)=G+A(t),whereGisthedefault,usersuppliedgainvalue,andA(t)isthetimevaryingadjustment.
A(t)isupdatedasA(t)=A(t)+G(t)*S*2D,whereS=1ifthemagnitudeislessthanthethresholdandis1ifthemagnitudeexceedsthethreshold,andwhereDsetstheadjustmentstepsize.
Notethattheadjustmentisafractionofthecurrentgain.
ThisisdesignedtosettheAGCnoiseleveltoaknownandacceptablelevelwhilekeepingtheAGCconvergenceandtrackingrateconstant,independentofthegainlevel.
ThesignaltoAGCnoiseratiowillbeequalto6*DdB,sofornoisepurposes,Dshouldbesetto5ormoretopreserveanSNR>30dB,whiletypicalCDMAorUMTSapplicationssetDconsiderablyhigher(longerAGCtimeconstant).
ThetimeconstantishowlongittakestheAGCtoconvergetowithin63%ofarequiredgainchange.
(Ittakesfourtimeconstantstoconvergetowithin98%ofthechange.
)IfoneassumesthedataisrandomwithaGaussiandistribution,whichisvalidforUMTSifmorethan12userswithdifferentcodeshavebeenoverlaid,thentherelationshipbetweentheRMSlevelandthemedianisMEDIAN=0.
6745*RMS,hencethethresholdshouldbesetto0.
6745timesthedesiredRMSlevel.
ThegainstepsizecanbesetusingfourdifferentvaluesofD,eachofwhichisa4-bitinteger.
Dcanrangefrom3to18.
TheusercanspecifyvaluesofDfordifferentsituations,i.
e.
,whenthesignalmagnitudeisbelowtheuser-specifiedthreshold(Dblw),isabovethethreshold(Dabv),isconsistentlyequaltozero(Dzro)orisconsistentlyequaltomaximum(Dsat).
ItisimportanttonotethatDrepresentsagainstepsize.
SmallervaluesofDrepresentlargergainsteps.
Thedefinitionofequaltozeroisanynumberwhenmaskedbyzero_maskisconsideredtobezero.
Thispermitsconsistentlyverysmallamplitudesignalstohavetheregainbeincreasedrapidly.
ThedifferentDvaluesallowstheusertosetdifferentattackanddecaytimeconstantswhenthesignalisinausefulworkingrange.
Whentheoutputsignalsoweakorsostrongthatnousefulinformationremainsthereisnoconcernaboutpreservingsignalqualityandthedesireistomovethesignalrapidlyintoausefulworkingrange.
Themagnitudeisconsideredtobeuselesslyweakbyusinga4-bitcounterthatcountsupeverytimethemasked8-bitmagnitudevalueiszero,andcountsdownotherwise.
Ifthecounter'svalueexceedsauserspecifiedthreshold,thenDzroisused.
Similarlythemagnitudeisconsidereduselesslystrongbyusingacounterthatcountsupwhenthemagnitudeismaximum,andcountsdownotherwise.
Ifthiscounterexceedsanotheruserspecifiedthreshold,thenDsatisused.
Asanexampleusingadc-signalinput,iftheAGC'scurrentgainataparticularmomentintimeis5.
123,andthemagnitudeoftheoutputsignalisgreaterthanzero,butlessthantheuser-programmedthreshold.
StepsizeDblwwillbeusedtoincreasethegainforthenextsample.
ThisrepresentstheAGCattackprofile.
IfDblwissettoavalueof5,thenthegainforthenextsamplewillbe5.
123+5.
123x25=5.
283.
Iftheoutputsignal'smagnitudeisstilllessthantheuser-programmedthreshold,thenthegainforthenextsamplewillbe5.
283+5.
283x25=5.
448.
Thiscontinuesuntiltheoutputsignal'smagnitudeexceedstheuser-programmedthreshold.
Whenthemagnitudeexceedsthreshold(butisnotsaturated),thenstepsizeDabvisautomaticallyemployedasasizeratherthanDblw.
TheAGCconvergeslinearlyindBwithastepsizeof40log(1+2D)whentheerrorisgreaterthan12dB(i.
e.
,thegainisoffby12dBormore).
Within6dB,thebehaviorisapproximatelyanexponentialdecaywithatimeconstantof2(D+0.
5)samples.
ThesuggestedvalueofDis5or6,whentheerrorisgreaterthan12dB(i.
e.
,inthefastrangedetectedbyconsistentlyzeroorsaturateddata).
Thisgivesastepsizeof0.
5dBor0.
25dBpersample.
Thesuggestedvaluewhenthegainisoffbylessthan12dBisD=10,givingaexponentialtimeconstantfordelayofaround1722samples(63%decayevery1722samples).
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com21012345671101001000100001000001000000SAMPLESD=3D=4D=5D=6D=7D=8D=9D=10D=11D=12D=13D=14D=15D=16D=17D=18D=18D=3Figure17.
AGCGainErrorvsSamplesTheAGCnoiseoncetheAGChasconvergedisarandomerrorofamplitude±2DrelativetotheRMSsignallevel.
Thismeansthattheerrorlevelis6*DdBbelowthesignalRMSlevel.
AtD=10(60dB)theerrorisnegligible.
TheplotbelowshowstheAGCresponseforvalesofDrangingfrom3to18.
ErrordBrepresentsthedistancethesignallevelisfromthedesiredtargetthreshold.
TheAGCisalsosubjecttouserspecifiedupperandloweradjustmentlimits.
TheAGCstopsincrementingthegainiftheadjustmentexceedsAmax.
ItstopsdecrementingthegainiftheadjustmentislessthanAmin.
Theinputdataisreceivedwithavalidflagthatishighwhenavalidsampleisreceived.
Forcomplexdata,theIandQsamplesareonthesamedatainputlineandarenottreatedindependently.
AnadjustmentismadeforthemagnitudeoftheIsample,andthenanotheradjustmentismadefortheQsample.
TheAGCoperatesonUMTSandCDMAdata.
WheninUMTSmodetheIandQdataareeachusedtoproducetheAGClevel.
ThereisnoseparateIpathgainandQpathgain.
WheninCDMAmodethereareseparategainlevelsforthesignalanddiversityIandQdata.
TheIandQforA(ortheSignal)pairiscalculatedandthentheIandQfortheB(ordiversity)pairiscalculated.
Thereisafreezemodeforholdingtheaccumulatoratitscurrentlevel.
ThisputstheAGCinaholdmodeusingtheuser-programmedgainalongwiththecurrentgain_adjustvalue.
Toonlyusetheuserprogrammedgainvalueasthegain,setthefreezebitandthencleartheaccumulator.
Whenusingthefreezebit,thefull25-bitoutputissentoutoftheAGCblocktosupporttransferringupto25bitswhentheAGCisdisabled.
ThecurrentAGCgainandstatecanalsobeoptionallyoutputwiththeDDCsIandQoutputdatabysettingthegain_monvariable.
Wheninthismode,thetop14bitsofthecurrentAGCgainwordareintegratedinwiththeAGC-modifiedIandQoutputdata.
Table18.
OutputDataFormatWithEmbeddedAGCGainDataOutputBits(17:10)Bits(9:4)Bits(3:2)Bits(1:0)IIoutputdataGain(18:11)00QQoutputdataGain(10:5)AGCState(1:0)00GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com22Table19.
ProgrammingVARIABLEDESCRIPTIONagc_dbelow(3:0)SetsthevalueofgainstepsizeDblw(data*currentgainbelowthreshold).
Dblw=3+agc_dbelow.
agc_dbelowrangesfrom0to15.
agc_dabove(3:0)SetsthevalueofgainstepsizeDabv(data*currentgainabovethreshold).
Dabv=3+agc_dabove.
agc_daboverangesfrom0to15.
agc_dzero(3:0)SetsthevalueofgainstepsizeDzro(data*currentgainconsistentlyzero).
Dzro=3+agc_dzero.
agc_dzerorangesfrom0to15.
agc_dsat(3:0)SetsthevalueofgainstepsizeDsat(data*currentgainconsistentlysaturated).
Dsat=3+agc_dsat.
agc_dsatrangesfrom0to15.
agc_zero_msk(3:0)Masksthelower4bitsofsignaldatasoastobeconsideredzeros.
agc_thres(7:0)AGCthreshold.
Comparedwithmagnitudeof8bitsofinput*gain.
agc_gaina_lsb(15:0)Lower16bitsof19-bitgainwordforDDCA.
Requiresasync(ssel_gain)toload.
agc_gaina_msb(18:16)Upper3bitsof19-bitgainwordforDDCA.
Requiresasync(ssel_gain)toload.
agc_gainb_lsb(15:0)Lower16bitsof19-bitgainwordforDDCB(inCDMAmode).
Requiresasync(ssel_gain)toload.
agc_gainb_msb(18:16)Upper3bitsof19-bitgainwordforDDCB(inCDMAmode).
Requiresasync(ssel_gain)toload.
ssel_gain(2:0)Synctoupdateagc_gainsettings.
NotethatbothAandBareupdated.
agc_zero_cntWhentheAGCoutput(input*gain)maskedmagnitudeiszerovaluethisnumberoftimes,theshiftvalueischangedtoagc_dzero.
agc_max_cntWhentheAGCoutput(input*gain)iszerovaluethisnumberoftimes,theshiftvalueischangedtoagc_dsat.
agc_md(3:0)AGCrounding.
Numberofoutputbits=18–agc_rnd.
agc_rnd_disableAGCroundingisdisabledwhenthisbitisset.
agc_freezeFreezestheadaptiveportionofthegaintocurrentvalue.
agc_clearClearstheadaptiveportionofthegain.
agc_amax(15:0)Themaximumvaluethatgaincanbeadjustedupto.
Top7bitsareinteger,bottom9bitsarefractional.
agc_amin(15:0)Theminimumvaluethatgaincanbeadjusteddownto.
Top7bitsareinteger,bottom9bitsarefractional.
gain_monWhenset,combinescurrentAGCgainwithIandQdata.
The18-bitoutputformatthusbecomes:IPortion:8bitsofAGC'dIdataGain(18:11)00QPortion:8bitsofAGC'dQdataGain(10:5)Status(1:0)00.
Note:Bit0ofstatus,whenset,indicatesthedataissaturated.
Bit1ofstatus,whenset,indicatesthedataiszero.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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6ReceiveOutputInterfaceClkdivSync4FrameDelay2IdataCDMAASerial2CDMAImsbImsb1QmsbQmsb11UMTSSharedbetweentwoDDCblocks,ImsbImsb1Imsb2Imsb3QmsbQmsb1Qmsb2Qmsb3FromadjacentDDCblockUMTSrxout_X_arxout_X_brxout_X_crxout_X_dwhereX=0to11QdataCDMAAIdataCDMABQdataCDMABDDCBlock2CDMA2000or1UMTSChannel8-PinModei.
e.
,2kand2k+1,k=0to5FrameStrobeFigure18.
ReceiveOutputInterfaceEachDDCblockhasfourserialoutputdatapins.
ThesepinsareusedtotransferdownconvertedI/QbasebanddataoutoftheGC5316forsubsequentprocessing.
TheusageofthesepinschangesdependingonhowtheDDCblockisconfigured.
WhentheblockisconfiguredfortwoCDMAchannels,apairofserialdatapinsprovidesseparateIandQdataoutputforthetwoDDCchannels.
Wordsizeisselectablefrom4to25bitswiththemostsignificantbitfirst.
Note,carefullythesignaltopinassignment,forexamplethatIaisassignedtorxout_X_aandQaisassignedtorxout_X_c.
WhentheDDCblockisconfiguredforasingleUMTSchannel,evenandoddIandQdatadrivethefourserialpinsseparately,mostsignificantbitfirst.
FourserialpinseachforIandQdatacanbeoptionallyemployed(insteadoftwoforIandtwoforQ)athalftheoutputrate.
ThiswouldmostlikelybeusedwhentwoDDCchannels(2kand2k+1,k=0to5)arecombinedtosupportdoublelengthPFIRfiltering(achannelissacrificed).
FormattingforIdataisthen:Imsb,Imsb1,Imsb2,Imsb3.
Qdataformattingis:Qmsb,Qmsb1,Qmsb2,Qmsb3.
TwoDDCblocksshareaframestrobeoutputpin.
Theframestrobeisdrivenhighwhenthechanneloutputsanotherframeofdata.
Theframestrobecanbeprogrammedtoarrivefrom0to3bitclocksearlyviaa2-bitcontrolparameter.
Frameintervalcanbeprogrammedfrom1to63bits.
Aprogrammable4-bitclockdividercircuitiscanbeusedtospecifytheserialbitrate.
Theclockdividercircuitissynchronizedusingasyncblockdiscussedlaterinthisdocument.
Programmingtheserialportclockdividerrequiressomethoughtanddependsuponthechannel'soveralldecimationratio,framesyncinterval,numberofoutputbits,andCDMAUMTSmode.
Ingeneral:Theserialclockdivideratio*theframesyncinterval=thetotalreceivedecimationTherelationshipbetweenthenumberofserialbitsoutput,clockdivideratio,andoveralldecimationratiois:CDMA:[overalldecimation(pser_rec_8pin)1)](pser_recv_clkdiv)1)upser_recv_bits)1UMTS:2[overalldecimation(pser_rec_8pin)1)](pser_recv_clkdiv)1)upser_recv_bits)1GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com24Figure19showstheDDCserialoutputtiming.
tsuthtpdrx_synccanbeapulseorlevelinterfacewillgeneratperiodicframestrobesusingprogrammedsyncinterval1rxclk+programmablebittimerxclkrx_syncrx_sync_outrxout(serialoutputdata)2txclk(programmable)Note:Withhalf-rateserialoutput,theMSBcomesout5rxclksafterrx_sync.
Withfull-rateserialoutput,theMSBcomesout4rxclksafterrx_sync.
MSB(pser_recv_fsdel=0pser_recv__clkdiv=1)Figure19.
DDCSerialOutputTimingTable20.
ProgrammingVARIABLEDESCRIPTIONpser_recv_fsinvl(6:0)Framesyncintervalinbitspser_recv_bits(4:0)Numberofdataoutputbits1.
i.
e.
:10001=18bitspser_recv_clkdiv(3:0)Receiveserialinterfaceclockdividerrate1.
0=rxclk,15=rxclk/16pser_recv_8pinWhenset,configurestheserialoutpinsfor4Iand4QinUMTSmode.
Whenclear,themodeis2Iand2Q.
Usedinconjunctionwithpser_recv_alt.
pser_recv_altWhenset,outputsQdatafromadjacentDDCchannel.
pser_recv_fsdel(1:0)Numberofbitclockstheframesyncisoutputearlywithrespecttoserialdata.
ssel_serial(2:0)Syncsource(1of8).
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com253GC5316TransmitTransmitOutputData(toD/As)DUCs29txin_0_atxin_0_btxin_1_atxin_1_atxin_10_atxin_10_btxin_11_atxin_11_btx_sync_out_0tx_sync_out_5DUC112CDMA2000or1UMTSDUC102CDMA2000or1UMTSDUC12CDMA2000or1UMTSDUC02CDMA2000or1UMTSTransmitOutputInterfaceI/QCDMAChAI/QCDMAChBIUMTSQUMTSFramesyncforDUC10&11FramesyncforDUC0&1DUC11Inputs:(basebanddata)I/QCDMAChAI/QCDMAChBIUMTSQUMTSDUC10Inputs:I/QCDMAChAI/QCDMAChBIUMTSQUMTSDUC1Inputs:I/QCDMAChAI/QCDMAChBIUMTSQUMTSDUC0Inputs:txclkTransmitSyncstx_syncatx_syncbtx_syncctx_syncdTransmitInputSyncstx_sync_outSumChainOutSumChainSumChainSumChainForUMTSForCDMAFigure20.
TransmitSectionTheGC5316transmitsectionprovidesupto24CDMA2000or12UMTSdigitalupconversion(DUC)channels.
Thereare12DUCblocks,DUC0throughDUC11.
EachblockcanbeconfiguredasasingleUMTSchannelortwoCDMAchannels.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com26TheoutputsofallDUCsdrivefourindependentcomplexsumchains.
AnyDUCcancontribute(ornot)toanyorallofthefoursumchains.
TheoutputofaDUCblock'ssumchaindrivesthesumchaininputofthenextblock.
ThefirstDUCtooutputdataisDUC0,whilethelastisDUC11.
ThefouroutputsofaDUCarethesumofallthecontributingchannelsofallthehighernumberedDUCblocksanditself.
ThesumchaininputsofDUC11aregrounded.
Withinthechain,allDUCblocksfrom0uptothehighestnumberedDUCinusemustbeturnedonotherwisethesumchainisbroken.
ThetransmitoutputinterfacetakesthefoursummedchainsofDUCoutputdatafromtheoutputofDUC0andthenscalesandroundstoauser-programmednumberofbits.
Compositepowermeterswithprogrammableintegrationperiodsandintervalscomputethepowerineachofthefouroutputstreams.
Thedataisthenformattedforoutputoverthefourtx_data_outoutputs.
3.
1DigitalUpconvertBlock(DUC)SixStageCICFilterInterp432SerialInterfaceI,QProgrammableFIRFilterInterpby2CompensatingFIRFilterInterpby2SerialGainFrequencyPhase3216DelayAdjustSum1InputNCOSum1OutputSum2InputSum2OutputSum3InputSum3OutputSum4InputSum4OutputToNextTransmitChannelFromPreviousTransmitChannel34RMSPowerMeter18181818161636Round4signontop16data15zerosonbottom185guardontop18data13onbottomPilotInsertion(UMTSonly)CDMAA&Bchannels,or1UMTSchannelFigure21.
DigitalUpconvertBlockThissectiondescribesthefunctionsavailableineachofthe12DUCblocks.
EachDUCblockhasitsownregistersetandmaybeprogrammedindividually.
Thefinaloutputratesmustmatchsincetheyareaddedtogether.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com27Thediagramaboveshowsthedifferentsignalprocessingblocksandgeneralsignalprocessingflowofanindividualtransmitchannel.
WithinaDUCblockasinglesetofhardwareperformsthesefunctionsforoneUMTSsignalortwoCDMAsignals.
WhenprocessingtwoCDMAsignalsthegain,round,powermeter,PFIRandCFIRblocksaretimesharedtoprocessbothsignalswithonesetofhardware.
EachDUCcansupportoneUMTSchannelortwoCDMAchannels.
EachDUCblockacceptsbasebandserialdata.
Atthispointthegaincanbeadjustedandapilotsequencecanbesummedwiththedata.
Powercanbemeasured,andthenthedataispulse-shapefilteredandinterpolatedtoahigherrate.
TheprogrammableFIRfilter(PFIR)isusedtopulseshapethedataandinterpolatesbyafactoroftwo.
ThecompensatingCICfilter(CFIR)compensatesfortheroll-offofthefollowingCICfilterandalsointerpolatesbyafactoroftwo.
TheCICfilterperformsadditionalinterpolationwhichisprogrammable.
Thedelayadjustblockpermitsthechannel'sdelaytobeadjustedrelativetoallotherDUCchannels.
Theinterpolated,filtered,anddelayeddataisthentunedtoauser-programmedfrequencywithadigitalmixerandoscillator.
TheDUC'soutputdatathendrivesfourindependentsumchainpaths,whereoutputdatafromeachDUCcanbesummedintofourcompositestreams.
Eachfunctionblockisdescribedingreaterdetailinsubsequentsections.
Table1.
ProgrammingVARIABLEDESCRIPTIONddc_duc_enaWhensetthisturnsontheDUC.
Whenunset,theblockisturnedoff.
cdma_modeWhenset,theDUCblockisinCDMA2000mode.
3.
1.
1TransmitSerialInputInterfaceFrameStrobeClkdivSync4FrameDelay2InterleavedI,Q2CDMACDMADUCChannelADUCBlockCDMADUCChannelBInterleavedI,Q1UMTSIQCHACHBSharedbetweentwoDUCblocks;ie2k&2k+1,k=0to51UMTSImsbImsb1QmsbQmsb1PinsfromadjacentDUCtxin_X_atxin_X_bFigure22.
TransmitSerialInputInterfaceEachDUCblockhastwoserialinputdatapins.
ThesepinsareusedtotransferI/QbasebanddataintotheDUCchannelforinterpolation,filtering,andtuningtoacarrierfrequency.
HowthesepinsareuseddependsonthechannelconfigurationoftheDUCblock.
WhentheblockisconfiguredfortwoCDMAchannels,onepin(txin_X_a)acceptsserialdataforsignalA,theotherpin(txin_X_b)forsignalB.
InputIandQdata,programmableupto18bits,ismultiplexedovertheserialinputpinstartingwiththemostsignificantIbit.
Themaximuminputbitrateistxclk.
Theinterfacecanbeprogrammedtoacceptupto32bits,butonlytheupper18bitswillbeusedasinputsignaldata.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com28WhentheblockisconfiguredforasingleUMTSchannel,thetxin_aisforIdata,andtxin_bcarriestheQdata.
Themostsignificantbitissentfirst.
Thefourpinmodeisalesscommonmode.
Itemploysanothertwopinsfromtheadjacent(2k+1)DUC,sacrificingtheuseofthatDUCinordertoallowreduceddatarateontheserialpins.
TheIdata(Imsb,Imsb1)arecarriedontxin_(2k)_aandtxin_(2k)_b,whiletheQdata(QmsbQmsb1)iscarriedontxin_(2k+1)_aandtxin_(2k+1)_b.
EachpairofDUCblocks2kand2k+1sharetheclockdivision,framedelay,syncgeneration,andaframestrobeoutputpin.
Aprogrammableclockdividercircuitcanbeusedtospecifytheserialbitratewithrespecttotxclk.
Thedividerisprogrammedastxclk/(1+serp_trans_clkdiv).
Theclockdividercircuitissynchronizedusingageneralsyncblockdiscussedinanothersectionofthisdocument.
Theframesyncintervalcanbeprogrammedfrom1to127bits(whicharedividedclocks).
Thenumberofbitsinawordissetas(serp_tran_bits+1).
Theframestrobeisanoutputfromthegc5316thatindicateswhenthemsbisexpected.
Theframestrobecanbeprogrammedtoarrivefrom0to3-bitclocksaheadofwhenthemsbisexpectedviatheserp_tran_fsdelparameter.
Thesourcemusttransmitallofitsdatabeforethenextframestrobeisgenerated.
Useoftheframestrobeisoptionalinthatwhenthemsbisexpectedisdeterminedbythesync(ssel_serial).
Theparameterchosenmustsatisfythefollowingconstraints:Dserp_tran_fsinvx(serp_tran_clkdiv+1)=4x(cic_interp_decim+1)Dserp_tran_fsinv>=(serp_tran_bits+1)2forCDMAmodeDserp_tran_fsinv>=(serp_tran_bits+1)forUMTSmodeDserp_tran_fsinv>=(serp_tran_bits+1)0.
5forfourpinmodeNOTE:Forhalf-ratedata(whenserp_tran_clkdiv=1),theMSBoftheinputdatastreamiscapturedonthe4thrisingedgeoftxclk,aftertxsyncoccurs.
Forfull-ratedata(whenserp_tran_clkdiv=0),theMSBoftheinputdatastreamiscapturedonthe3rdrisingedgeoftxclk,aftertxsyncoccurs.
Figure23showsthetransmitserialinputtiming.
txclktxsync2txclktx_sync_outMSBMSB12txclk(programmable)(serp_tran_fsdel=0serp_tran_clkdiv=1)txin(serialinputdata)tsuthtsuthtpdFigure23.
TransmitSerialInputTimingGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONserp_tran_bits(4:0)Numberofserialinputbitsinaword–1.
i.
e.
,10001=18bitsserp_tran_fsinvl(6:0)Framesyncintervalinbitsserp_tran_fsdel(1:0)ThenumberofserialbitsafterframestrobethatthedataMSBisexpected.
serp_tran_4pin0=2pininputmode.
AppliestoUMTSmodeforseparateIandqdatabits,aswellasCDMAmodewhereonepinisforinterleavedI/QdatafortheCDMAAchannelandanotherpinforinterleavedI/QdatafortheCDMABchannel.
1=4pinmode.
AppliestoUMTSmodewherethechannelhastwobitsforIdata(ImsbandImsb1)andtwobitsforQdata(QmsbandQmsb1)serp_tran_clkdiv(3:0)Serialinputdatabitclockdividerfactor1ssel_serial(2:0)SyncsourceTheparametersaresetforapairofDUCblocks;i.
e.
,for2kand2k+1DUCs,wherek=0to5.
3.
1.
2TransmitGainFigure24.
TransmitGainBlockThetransmitgainblockisamultiplierthatincreasesordecreasestheleveloftheinputdata.
Theunsigned16-bitgainwordisinterpretedwiththebinarypointthreebitsdownfromtheMSB.
Itmultipliestheinputdataby(gainword/8192).
Themaximumgainistherefore65535/8192.
TherearedifferentgainregistersfortheAandBsignalsinCDMAmode.
Atransferregisterincombinationwithasync(ssel_gain)isusedtosynchronizegainchangesacrossmultiplechannels.
Table3.
ProgrammingVARIABLEDESCRIPTIONgainfora(15:0)GainfortheA-sideDUC.
Interpretedasgainfora/8192andisunsigned.
gainforb(15:0)GainfortheB-sideDUC.
Interpretedasgainforb/8192andisunsigned.
ssel_gain(2:0)SyncsourceGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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1.
3TransmitUMTSPilotCodeInsertion171615141312111098765432LowerRegisterLoad(alwaysloadedwithall1s)1017161514131211109876543218UpperRegisterLoad10OutputLogicIQIStateIQIQQI00011011GGGGGGGGG(Gain)AReg16Negate1616SyncSyncDelayCounter16Bits(insamples)Delay16Synchronization16-BitCounterforGainNegationFigure25.
PilotCodeInsertionLogicThepilotcodeinsertionblockisusedtogenerateUMTSpilotscramblingsequencesanddoesnotapplywhentransmittingCDMA.
ThepilotsequenceissummedwiththeUMTSinputbasebanddatapriortoPFIRfiltering.
Thesequenceiscomplexandgeneratedfromtwo18-bitshiftregisters,eachwithauniquesetoffeedbacktaps.
Specifictapsareexclusive/orcombinedtoformtheIandQstreams.
Thestreamsarethenmodifiedbyauser-programmedcomplexgainvalue.
ThegainwordGisasigned16-bitvalue.
Theoutputsequenceis+G.
Settinggaintozeroturnsoffpilotinsertion.
Note:GainMUSTbesettozeroforCDMAoperation.
Theupper18-bitshiftregisterisprogrammedwithastartingsequencebasedonthedesiredprimaryscramblingcode(PSC).
Thereare512startsequencesforalloftheBTScodes.
Thelowerregisterisalwaysstartedwithastringofall1s.
Whendiversitychannelsareemployed,acounterinthesynchronizationblocktogglesthesignofthegainvalueinaprescribedfashion.
TheUMTSframestartswithpositivegainfor256chips,thentogglestonegativegainfor512chips,thentogglesagaintopositivegainfor512chips,etc.
untiltheendoftheframe.
Thelast256chipsoftheframewillbenegativegain.
Thissequencerepeatsforsubsequentframes.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONpilot_psc(15:0)Lower16bitsofthe18-bitpilotLFSRinitialsequence.
pilot_psc(17:16)Upper2bitsofthe18-bitpilotLFSRinitialsequence.
pilot_diversitySetsmainordiversitypilotgeneration.
0=main,1=diversitypilot_delay(15:0)Unsigneddelayvalue(inchips)fromsyncevent.
0to38399chips.
pilot_gain_0(15:0)Gainvalue.
pilot_gain_0andpilot_gain_1mustbesettothesamevalueforproperoperation.
Mustbesetto0forCDMAoperation.
pilot_gain_1(15:0)Gainvalue.
pilot_gain_0andpilot_gain_1mustbesettothesamevalueforproperoperation.
Mustbesetto0forCDMAoperation.
ssel_pilot(2:0)Syncsource3.
1.
4TransmitChannelRMSPowerMeterSyncEventSyncDelayIntegrationStartIntegrationTimeIntegrationStartIntegrationTimeIntegrationTimeIntervalTimeIntegrationStartIntervalTimeInterruptInterruptInterruptTimeIntegrate50bitsClearRegisterTransfer32IQ181813Bits(inincrementsof4samples)SyncRMSPowerInterrupt37SyncDelayCounter7Bits(insamples)IntervalCounter9Bits(inincrementsof64samples)pmeter_sync_delay_ducTop321397pmeter_integration_ducIntegrationPeriodCounterpmeter_interval_ducPowerMeasurementTimeLineFigure26.
TransmitChannelRMSPowerMeterEachtransmitchannelincludesanRMSpowermeterusedtomeasuretheRMSpowerwithinthechannel.
Functionally,thepowermeterblockisidenticaltotheRMSpowermeterblocksusedinthereceivechain.
ThepowermetersamplestheIandQdatastreambeforethePFIRfilter.
Both18-bitIandQdataaresquared,summed,andthenintegratedoveratimedeterminedbypmeter_integration_duc(13bits).
Integrationtime=4xpmeter_integration_duc+1(inunitsofasampleperiodorgenerallyachipperiod).
Thereisaprogrammable9-bitintervalcounterwhichsetstheintervaloverwhichpowermeasurementsarerepeated.
Thetimercountsinincrementsof64samples.
Theintervaltime=64(pmeter_interval_duc+1)Theintervaltimemustbegreaterthan(notequalto)theintegrationtime.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com32Thepowermeasurementprocessstartswithasyncevent(ssel_pmeter).
Theintegrationstartsatsyncevent+3chips+sync_delay.
The7-bitdelayregisterpermitsdelaysfrom3to130samplesaftersync.
Theintegrationcontinuesuntiltheintegrationcountismet.
Atthatpointthetop32bitsofthe50-bitaccumulatoristransferredtothereadregisterandaninterruptisgeneratedindicatingthepowervalueisreadytoread.
Theintervalcountercontinuesuntiltheprogrammedintervalcountisreached.
Whenreached,theintegrationcounterandtheintervalcounterstartoveragain.
Eachtimetheintegrationcountisreachedtheupper32bitsareagaintransferredtothereadregisteroverwritingthepreviousvaluesendinganinterruptsignifyingthedataisreadytoberead.
Failuretoreadthedatatimelyresultsinoverwritingthepreviousintervalmeasurement.
Syncssel_pmeterstartstheprocess.
Wheneverasyncisreceived,allthecountersareresettozeronomatterwhatthestatus.
ForUMTS,IandQarecalculatedandtheintegratedpowerisread.
WheninCDMAmodethepoweriscalculatedforboththeAandBsignals,producingtwo32-bitresults.
ForCDMAmode,theintegrationtimeisslightlylonger.
ThepowerreadinCDMAmodewithadcinputis:DApower:[I2x(Xx4+1)+Q2x(Xx4+0)]x218.
Note,oneQsampleismissingfromtheintegration.
DBpower:[I2x(Xx4+1)+Q2x(Xx4+1)]x218WhereXistheintegrationcount.
Table5.
ProgrammingVARIABLEDESCRIPTIONpmeter_result_a_lsb(15:0)Lower16bitsoftheAchannelpowermeasurement.
pmeter_result_a_msb(31:16)Upper16bitsoftheAchannelpowermeasurement.
pmeter_result_b_lsb(15:0)Lower16bitsoftheBchannelpowermeasurementresult.
OnlyavailableinCDMAmode.
pmeter_integration_duc(12:0)Integrationtime=4xpmeter_integration_duc+1.
pmeter_sync_delay_duc(6:0)Syncdelaycountinsamples.
pmeter_interval_duc(9:0)Intervaltime=64(pmeter_interval_duc+1).
Intervaltimemustbegreaterthan(notequal)integrationtime.
ssel_pmeter(2:0)Syncsourceoptions.
pmeter_sync_disableTurnsoffsynctothechannel'spowermeter3.
1.
5TransmitFilterChainGC5316transmitfilteringisperformedinthreestages:DInterpolatebytwopulse-shapefilteringusingtheprogrammableFIRfilter(PFIR)DInterpolatebytwocompensationfilteringusingtheprogrammablecompensatingFIRfilter(CFIR)DHigh-rateinterpolation(4to32)usingthesixstagecascade-integratecombfilter(CIC)Figure27.
DUCFilterChainThepurposeofthetransmitfilterchainistointerpolatetheinputsignaldatauptothemixerclockrate,nominally122.
88MHz.
ThefollowingtableprovidestwoexamplesofhowtheinterpolationcanbeallocatedamongthethreedifferentfiltersforbothCDMAandUMTS.
Table6.
ExampleUMTSandCDMA2000DUCTransmitModesINPUTRATERATEPFIRINTERPOLATIONCFIRINTERPOLATIONCICINTERPOLATIONOVERALLINTERPOLATIONCDMA1.
2288MSPS2225100UMTS3.
84MSPS22832GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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1.
5.
1TransmitProgrammableFIRFilterThetransmitprogrammableFIRfilter(PFIR)pulseshapesthebasebandsignaldataandinterpolatesbyafixedfactoroftwo.
ThePFIRlengthisprogrammable.
Thispermitsturningofftapsandsavingpowerifshortfiltersareappropriate.
ThemaximumPFIRfilterlengthisafunctionofGC5316clockrateandinputsamplerateandislimitedbythenumberofcoefficientmemoryregisters.
ThenumberoftapsavailablerangesinCDMAmoderangesfrom31to63,inUMTSmodeitrangesfrom15to63.
Bothinincrementsoffourtaps.
Subjecttotheaboverange,themaximumnumberoftapsavailableis:DUMTSMode:2x(txclk÷inputsamplerate)DCDMAMode:txclk÷inputsamplerateAssumingatxclkof122.
88MHz,bothUMTS(3.
84MSPS)andCDMA(1.
2288MSPS)modesprovide63taps.
ThesamePFIRcoefficientsareusedforboththeAandBsignalsinCDMAmode.
ThePFIRfilterconsistsof32forwardandreversedataRAMcellseach36bitsinwidth.
Thecoefficientmemoryprovidesstorageforupto63unique18-bittaps.
A19x18multiplierandfull-precisionaccumulatorformthefilterconvolution.
Anoptional(pfir_gain)up-shiftofonefollows.
Finally,theoutputishard-limited.
ThePFIRgainis:Gain=sum(coefficients)x2pfir_gain18Table7.
ProgrammingVARIABLEDESCRIPTIONcrastsrttap_pfir(4:0)NumberofDUCPFIRfiltertapsis(2xcrastarttap)+1cdma_modeWhenset,putstheCFIRandPFIRblocksinCDMA2000mode.
symmetric_pfirSetto1iffilterissymmetric.
Thissavesamodestamountofpower.
ThePFIRfilter's18-bitcoefficientsareloadedbythesoftwarecmd5316.
Theusermustprovideacoefficientfilewithoneintegercoefficientperline.
NotethatthePFIRfiltercoefficientsaresharedbytheAandBsignalsinCDMAmode.
3.
1.
5.
2TransmitCompensatingFIRfilterThetransmitCFIRfilterinterpolatesbyafixedfactoroftwoandisusuallyprogrammedtocompensatefortheCICfilter'sroll-off.
TheCFIRfilterlengthisprogrammable.
Thispermitsturningofftapsandsavingpowerifshortfiltersareappropriate.
ThemaximumCFIRfilterlengthisafunctionofGC5316clockrateandinputsamplerateandislimitedbythenumberofcoefficientmemoryregisters.
ThenumberofCFIRtapsinCDMAmodeis31to47,whileinUMTSmodeitis15to31.
Thenumberoftapsmaybeincreasedinincrementsoffourtaps.
Subjecttotheaboveminimum,maximum,andincrementvalues,themaximumnumberoftapsavailableis:DUMTSMode:txclk÷inputsamplerateDCDMAMode:0.
5x(txclk÷inputsamplerate)Assumingatxclkof122.
88MHz,UMTS(at3.
84MSPS)modewouldprovide31tapsandCDMA(1.
2288MSPS)modeprovides47taps.
TheCFIRcoefficientsaresharedbytheAandBsignalsinCDMAmode.
CFIRgainis:Gain=sum(coefficients)x2cfir_gain19GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONcrastsrttap_cfir(4:0)ThesebitsdefinethenumberoftapsthatCFIRusesforthefiltering.
DUCCFIR:(2xcrastarttap_cfir)+1,Note:crastarttap_cfirmustbeodd.
symmetric_cfirSetto1iffilterissymmetric.
Savesabitofpower.
cfir_gainCFIRgainadjustment.
ThePFIRfilter's18-bitcoefficientsareloadedbythesoftwarecmd5316.
Theusermustprovideacoefficientfilewithoneintegercoefficientperline.
NotethatthePFIRfiltercoefficientsaresharedbytheAandBsignalsinCDMAmode.
3.
1.
5.
3TransmitCICFilter18OutZm1Z1ZeroPadby331Z1Z1Z1Z1Shift031&Round50ShiftN18Zm2Zm3Zm4Zm5Z1m1,m2,m3,m4,m5,m6=1or2Zm6In2419202122232429343944Force0Figure28.
TransmitCICFilterThetransmitsixstageCICfilterinterpolatesoveraprogrammablerangefrom4to32.
Thefilterismadeupofsixbanksof24-bitsubtractorsectionsfollowedbysixbanksofintegratorsections.
Eachofthesixsubtractorsectionscanbeindependentlyprogrammedwithadifferentialdelayofoneortwo.
Ashiftblockfollowsthelastintegrationstageandcanshiftthe50-bitaccumulateddatadownby31TCIC_SHIFTbitsyielding18-bitoutputdata.
TheCICfilterexhibitsadroopacrossitsfrequencyresponse.
UsuallytheprecedingCFIRfilterprecompensatesfortheCICdroopwithagraduallyrisingfrequencyresponse.
However,itisalsopossibletoprovidetheprecompensationinthePFIRfilter.
CICinterpolationfilterscanbecomeunstableifanexternalevent(suchasacosmicparticle)disturbsastoragenodeintheCICintegratorsection.
Thiscanaddabiaswhichsubsequentlyintegratesoutofcontrol.
TheGC5316transmitCICemploysapatentedmethodtodetectandthenautomaticallyflushandresetthefilter.
Registerbitsareavailabletodisableandtotestthisauto-flushfeature.
AmaskableinterruptbecomesactiveifaCICerroroccurred.
ThegainoftheCICfilteris:Ncic5x2(numberofstageswhereM=2)x2(CIC_SCALE31)whereCIC_SCALEis0to31.
Ncicistheinterpolationratioandisprogrammedascic_interp_decim+1.
SincetheCICoutputisfullrateforbothUMTSandCDMA,acompletehardwarepathisrequiredforeachofthesignalsAandBfromthispointoninthetransmitsignalpath.
ForCDMA,therearefourindependentCICfilters(I/QforsignalAandI/QforsignalB).
ForUMTS,thetwosignalBCICfiltersaredisabled.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONcic_interp_decim(4:0)TheCICinterpolationisNcic=cic_interp_decim+1.
ThisratioappliestobothAandBchannelsoftheDUCblockinCDMAmode.
Legalvaluesforcic_interp_decimare3to31.
cic_scale_a(4:0)TheshiftvaluefortheAchannel.
Avalueof0isnoshift,eachincrementinvalueincreasestheamplitudeoftheshifteroutputbyafactorof2.
cic_scale_b(4:0)TheshiftvaluefortheBchannel.
Avalueof0isnoshift,eachincrementinvalueincreasestheamplitudeoftheshifteroutputbyafactorof2.
cic_m2_ena_a(5:0)SetsthedifferentialdelayvalueMforeachoftheCICsubtractorstagesfortheAchannel.
Cic_m2_en_a(0)controlsm1,cic_m2_en_a(5)controlsthem5.
AsetbitprogramsthedifferentialdelayMto2,ifclearedMisprogrammedto1.
cic_m2_ena_b(5:0)SetsthedifferentialdelayvalueMforeachoftheCICsubtractorstagesfortheBchannel.
ssel_cic(2:0)Syncsourcecic_auto_flush_dis(3:0)WhensetdisablestheCICautoflush.
Bits{0,1,2,3}correspondtoCICsfor{CDMAAIdata,CDMAAQdata,CDMABIdata,CDMABQdata}sections.
cic_auto_flush_test(3:0)OnrisingforcesaCICoverflowerror.
Programto0thento1foredgetooccur.
Bits{0,1,2,3}correspondtoCICsfor{CDMAAIdata,CDMAAQdata,CDMABIdata,CDMABQdata}sections.
cic_auto_flush_clear(3:0)OnrisingclearsaCICoverflowcondition.
Programto0thento1foredgetooccur.
Bits{0,1,2,3}correspondtoCICsfor{CDMAAIdata,CDMAAQdata,CDMABIdata,CDMABQdata}sections.
3.
1.
6TransmitAdjustableChannelDelayFigure29.
TransmitDelayAdjustmentThetransmitchanneldelayadjustfunctionpermitstheusertoaddaprogrammabletimedelayineachoftheupconverterpaths.
Thisisusedtocalibratemultipletransmitchannelsintheoverallbasetransceiversystem.
Theadjustabledelaycompensatesforanalogelementsexternaltothedigitalupconversionsuchascables,splitters,analogupconverters,filters,etc.
,andtocompensatefordifferentialdelaybetweenchannelswithintheGC5316.
ThereisanadditionaldelayoftwooutputsampletimesforeachpairofDUCblockstoallowforpipeliningofthesumchain(specifically,DUC0and1havethesamedelay,DUCs2and3arethesamebutaretwooutputsampletimeslargerthanDUC0and1,etc.
).
Therearetwoelementsthatneedtobeconsideredwithrespecttoprogrammingthedelay:thedecimationanddelaymemoryblocks.
Thedecimationfunctionreducesthesampleratefromtxclktothedesiredoutputrate.
Thedecimationamountissetbyparameter(tadj_interp_decim+1).
Phasingofthedecimationoperationpermitsfinerdelayresolution.
The3-bitdelayoffsetparameterpermitsfinerdelayresolutioninstepsofthereciprocaloftheGC5316'stxclockrate.
At122.
88MHz,thiswouldequatetoatimedelayresolutionof8.
1ns(1/32chipforUMTS,1/100ofachipforCDMA).
Theoffsetmaybesetfrom0totadj_interp_decim.
Thecoarsedelayadjustmentisdoneusingadelaymemoryof64memorylocationsby36bits(18forIand18forQ).
Readandwritepointersinthememoryareseparatedbytadj_offset_coarse.
Datawrittenintoalocationisreadouttadj_offset_coarseoutputsampletimeslater.
24locationsareneededtoequalizethetimedelaywithintheGC5316forvariouschannels.
Theremaining40locationsprovideatotaldelayofuptoabout1.
3swhentheDUCoutputdatarateis30.
72MSPS.
Asyncsignalpermitsthedecimationoperationtobesynchronizedovermultiplechannels.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONtadj_offset_coarse_a(5:0)Readoffsetintothe64elementmemoryfortheAchannelDUC.
Whentadj_offset_coarse_a=62,thenthedelayis–2.
Whentadj_offset_coarse_a=63,thenthedelayis–1.
Forallothervalues,theresultingdelayisequaltothevalue.
tadj_offset_coarse_b(5:0)Readoffsetintothe64elementmemoryfortheBchannelDUCwheninCDMAmode.
Note:Whentadj_offset_coarse_b=62,thenthedelayis–2.
Whentadj_offset_coarse_b=63,thenthedelayis–1.
Forallothervalues,theresultingdelayisequaltothevalue.
tadj_offset_fine_a(2:0)Controlsthezerooffset(fineadjust)fortheAsideoftheDUC.
Seenotebelowformapping.
tadj_offset_fine_b(2:0)Controlsthezerooffset(fineadjust)fortheBsideoftheDUCwheninCDMAmode.
Seethenotebelowformapping.
tadj_interp_decim(2:0)Thedecimationvalue(1,2,4,or8)fortheDUC.
SameforAandBchannelswheninCDMAmode.
ssel_tadj_fine(2:0)Selectsthesyncsourceforthefinetimeadjustssel_tadj_coarse(2:0)SelectsthesyncsourceforthecoarsetimedelayadjustNOTE:Thefineadjustismappeddifferently.
Foradecimationvalueof1theonlylegalsettingis0andthereisnofineadjustmentsincethereisnodecimationmoment.
tadj_offset_fine=0finedelayby0Foradecimationvalueof2:tadj_offset_fine=0finedelayby0tadj_offset_fine=1finedelayby1Foradecimationvalueof4:tadj_offset_fine=0finedelayby0tadj_offset_fine=1finedelayby1tadj_offset_fine=2finedelayby2tadj_offset_fine=3finedelayby1Foradecimationvalueof8:tadj_offset_fine=0finedelayby0tadj_offset_fine=1finedelayby1tadj_offset_fine=2finedelayby2tadj_offset_fine=3finedelayby3tadj_offset_fine=4finedelayby4tadj_offset_fine=5finedelayby5tadj_offset_fine=6finedelayby6tadj_offset_fine=7finedelayby1GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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1.
7TransmitMixerQI20SinCos18182121RoundFromChannelDelayToSumChainFromNCOFigure30.
TransmitMixerThetransmitmixer,likethereceivemixer,isacomplexmultiplierwhichtakesthebasebandIandQdatathathasbeenpreviouslypulse-shapedandinterpolatedandtranslatestoacarrierfrequencyprogrammedintotheNCO.
Themixerdatasizeis18bitsforthesignalpathand20bitsfortheNCOpath.
Thegainthroughthemixeris–12dB.
Itcanbeincreasedby6dBthroughacontrolbit.
Itisrecommendedthatthisextragainalwaysbeused.
Theoutputisthenroundedto21bits.
Mixergain=2mixer_gain2Themixeroutputofeachchanneliscombineddaisy-chainfashioninfoursumchainadderblocksthataredescribedinasubsequentsection.
ForCDMA,themaximumoutputrateistxclk/2.
ThemaximumoutputrateforUMTSistxclk.
Table11.
ProgrammingVARIABLEDESCRIPTIONmixer_gainWhenassertedadds6dBofgaininthemixer.
Shouldalwaysbeset.
3.
1.
8TransmitNCOFrequencyWord3232PhaseOffsetDitherGenDitherSync32FrequencySync5ZeroPhaseSync16PhaseOffsetSync2318RegRegSin/CosTable20CosSinClrReg20Figure31.
TransmitNCOTheNCOisadigitalcomplexoscillatorthatisusedtotranslate(orupconvert)interpolatedandfilteredbasebandsignalstoaprogrammablecarrierfrequency.
Theblockproducesprogrammablecomplexdigitalsinusoidsbyaccumulatingafrequencywordwhichisprogrammedbytheuser.
TheoutputoftheaccumulatorisaphaseargumentthatindexesintoaSin/CosROMtablewhichproducesthecomplexsinusoid.
Aphaseoffsetcanbeaddedpriortoindexingifdesiredforchannelcalibrationpurposes.
ThischangestheSin/Cosphasewithrespecttootherchannels'NCOs.
A5-bitdithergeneratorisprovidedandgeneratesasmalllevelofdigitalpseudo-noisethatisaddedtothephaseargumentbelowthebottombitandisusefulforreducingNCOspuriousoutputs.
Table12.
ProgrammingVARIABLEDESCRIPTIONdither_enaWhensetturnsditheron.
Clearingturnsditheroff.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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AddedphaseditherrandomizestheROMlookupslightly,hencetheROMlookuperror–spreadingthespuriousenergyaroundratherthanconcentratingitinafewfrequencies.
ThephaseditherisaddedbelowthelsboftheROMlookup.
Ifthetuningfrequencyhasnohighbitsmorethan17bitsbelowthemsb,thephaseditherhasnoeffect.
IfthetuningfrequencyisamultipleofFs/96thenaninitialphaseoffsetoffouroftenreducesNCOspurs.
Figure32andFigure33showthespurlevelperformanceoftheNCOwithoutdither,withdither,andwithaphaseoffsetvalue.
a)WorstCaseSpectrumWithoutDitherb)SpectrumWithDither(TunedtoSameFrequency)Figure32.
ExampleNCOSpursWithandWithoutDitheringa)PlotWithoutDitherorPhaseInitializationb)PlotWithDitherandPhaseInitializationFigure33.
NCOPeakSpurPlotThetuningfrequencyisspecifiedasa32-bitfrequencywordandisprogrammedasthreesequential16-bitwordsoverthecontrolport.
TheNCOoperatesatthesamespeedasthetxclk/(tadj_interp_decim+1).
ThefrequencyresolutionissimplytheFclk/232.
TheNCOfrequencyresolutionissimplytheFclk/232.
Asanexample,ataninputclockrateof61.
44MHz,thefrequencystepsizewouldbeapproximately14MHz.
Thefrequencywordisdeterminedbytheformula:Frequencyword(indecimal)=232xTuningFrequency/FclkNOTE:Frequencytuningwordscanbepositiveornegativevalued.
Specifyingapositivefrequencyvaluetranslatesbasebandfrequenciesupward.
Specifyinganegativetuningfrequencytranslatesbasebandfrequenciesdownwards.
Table13.
ProgrammingVARIABLEDESCRIPTIONphase_add_a(31:0)32-bittuningfrequencywordfortheAsignalwheninCDMAmode.
AlsoforUMTSmode.
phase_add_b(31:0)32-bittuningfrequencywordfortheBsignalwheninCDMAmode.
NotusedinUMTSmode.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com39ThephaseoftheNCO'sSin/CosoutputcanbeadjustedrelativetothephaseofotherchannelNCOsbyspecifyingaphaseoffset.
Thephaseoffsetisprogrammedasa16-bitword,yieldingastepsizeofabout5.
5milliDegrees.
Thephaseoffsetwordisdeterminebythefollowingformula:PhaseOffsetWord=216xOffset_in_Degrees/360or,PhaseOffsetWord=216xOffset_in_Radians/2πTable14.
ProgrammingVARIABLEDESCRIPTIONphase_offset_a(15:0)16-bitphaseoffsetwordfortheAsignalwheninCDMAmode.
AlsoforUMTSmode.
phase_offset_b(15:0)16-bitphaseoffsetwordfortheBsignalwheninCDMAmode.
NotusedinUMTSmode.
Varioussynchronizationsignalsareavailable,whichareusedtosynchronizetheNCOsofallchannelswithrespecttoeachother.
Frequencysyncandphaseoffsetsyncdeterminewhenfrequencyandphaseoffsetchangesoccur.
Forexample,generatingafrequencysyncafterprogrammingthetwofrequencywordscausestheNCO(ormultipleNCOs)tochangefrequencyatthattime,ratherthanaftereachofthethreefrequencywordsisprogrammedoverthecontrolbus.
Thezerophasesyncsignalisusedtoforcethesineandcosineoscillatorstotheirzerophasestate.
DithersynccanbeusedtosynchronizethedithergeneratorsofmultipleNCOs.
TheNCOsusedinthetransmitsectionareidenticaltowhatisdescribedforthereceivesection.
Table15.
ProgrammingVARIABLEDESCRIPTIONssel_nco(2:0)SyncsourceforNCOaccumulatorresetssel_dither(2:0)SyncsourceforNCOditherresetssel_freq(2:0)SyncsourceforNCOfrequencyregisterloadingssel_phase(2:0)SyncsourceforNCOphaseregisterloadingGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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1.
9TransmitSumChainOr1UMTSChannelCDMADUCBCDMADUCA26DUC0Or1UMTSChannelCDMADUCBCDMADUCAOr1UMTSChannelCDMADUCBCDMADUCADUC11DUC1DUCs210ToScaleandRoundblockSUM0SUM1SUM2SUM3262626Figure34.
TransmitSumChainThetransmitsumchainisadaisy-chainofallDUCoutputsintofourindependentcompositeoutputstreams.
EachDUCoutputdrivesfourcomplexadders,eachsummingtheDUC'scontributionintothesumchain.
TheDUCoutputdatadrivingtheaddersis21bits.
Thesumchainpartialsumoutputsare26bitstoallowforwordgrowth.
EachDUCoutputcancontributetoanyofthefoursumchains,ornot,viaprogrammableenablelines.
Theoutputofthelastdaisy-chainedsumisthenthecompositeofallofthe24CDMAor12UMTSchannels.
Oneshouldalwaysensurethatwithinasumchain,therearenoDUCspowereddownwithlowernumbersthanthosethatareactivewithhighernumbers,thusbreakingthechain.
Inotherwords,ifDUCs35areusedandactive,DUCs02mustnotbepowereddown.
Asshowninthediagramabove,eachDUCcontainsaportionofthesumchain.
WithintheprogrammingforeachDUConecanenableaddingresultsfromthatDUCsignalpath(s)toeachofthefoursum-chainsusingtheparametersbelow.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONsumchn_sel_a(3:0)EnablebitssignalAcontributiontothefoursumchainoutputs.
SignalAOut0000SignalAaddedtonobusses0001SignalAI/Qtobus00010SignalAI/Qtobus10010SignalAI/Qtobus10100SignalAI/Qtobus21000SignalAI/Qtobus3Note:SignalAoutputcancontributetoanycombinationofthefoursumchainoutputs.
Theabove4-bitcodecanrangefrom0to15.
sumchn_sel_b(3:0)EnablebitsforsignalBcontributiontothefoursumchains(onlywheninCDMAmode).
SignalBOut0000SignalBaddedtonobusses0001SignalBI/Qtobus00010SignalBI/Qtobus10100SignalBI/Qtobus21000SignalBI/Qtobus3Note:SignalBoutputcancontributetoanycombinationofthefoursumchainoutputs.
Theabove4-bitcodecanrangefrom0to15.
3.
2TransmitSumChainShiftingandRoundingFigure35.
FinalSumChainScaleandRoundBlockSummeddataisscaledfrom26bitsdownto18bits.
Thedesired18bitscanbetakenanywhereoverthe26bitsumchainoutputwindowviaaprogrammableregister.
These18bitscanrangefromsumchain(25:8)onthetopend,tosumchain(17:0)onthebottomendofthe26bitoutput.
Thescaleddataisthenhard-limitedandroundedto18,16,14,or12bits.
RoundeddataisMSBjustifiedwiththebottombitszeroed.
Forexample,12-bitroundingwouldforcetheoutputdatatothetop12bitsofthe18-bitwordandthebottom6bitswouldbezeroed.
Gain=2interf_scale5GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONinterf_scale_0(3:0)interf_scale_1(3:0)interf_scale_2(3:0)interf_scale_3(3:0)Selectsthesumchainscalevalueforeachofthefoursumchains.
The18-bitoutputcanbeslideanywhereacrossthe26-bitwindow.
0000=sumchain(25:8)0001=sumchain(24:7)…0111=sumchain(18:1)1000=sumchain(17:0)interf_round(1:0)Specifiestheroundingofallfoursumchains.
00=18bits01=16bits10=14bits11=12bits3.
2.
1TransmitPowerMetersFigure36.
TransmitPowerMeterBlockThecompositepowerineachofthefourtransmitsumchainscanbemeasuredusingpowermeterssimilartothoseusedintheindividualDDCandDUCblocks.
TherearefourcompositeRMSpowermeters,oneforeachofthefoursumchains.
Eachoftheabovepowermetersareindependentlyprogrammablewithrespecttothemeasurementperiod,interval,anddelayfromsync.
Thefollowingtwosectionsdescribethesumchainpowermetersinmoredetail.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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2.
1.
1TransmitCompositeRMSPowerMeterIntegrate58bitsClearRegisterTransfer32IQ1818SyncRMSPowerInterruptFromSumchain373636IntegrationPeriodCounter21BitsSyncDelayCounter9Bits(in8sampleincrements)IntervalCounter21Bits(insamples)pmeterX_sync_delaypmeerX_intervalpmeterX_integration21219SyncEventSyncDelayIntegrationStartIntegrationTimeIntegrationStartIntegrationTimeIntegrationTimeIntervalTimeIntegrationStartIntervalTimeInterruptInterruptInterruptTimePowerMeasurementTimeLineFigure37.
TransmitRMSPowerMeterTheGC5316providesfourindependenttransmitoutputports,eachofwhichisthesumofanumberofindividualtransmitcarriers(asumchain).
FourcompositeRMSpowermetersmeasurestheRMSpowerofthecombinedcarriersineachofthefoursumchains.
ThesepowermetersaresimilartothoseusedtomeasuretheRMSpowerofeachindividualchannel,buthavedifferentcounterlengths.
Theinputtothepowermeteristhescaledandroundedoutputofasumchain.
Poweriscalculatedbysquaringeach18-bitIandQsample,summing,andthenintegratingthesummed-squaredresultsintoa58-bitaccumulator.
Theintegrationtimeispmeter_integration(21bits)outputsampleperiods.
Thereisaprogrammable21-bitintervalcounterwhichsetstheintervaloverwhichpowermeasurementsarerepeated.
Theintervaltime=pmeter_interval+1.
Theintervaltimemustbegreaterthan(notequalto)theintegrationtime.
Ameasurementintegrationperiodisstartedatthebeginningofeachintervaltime.
Theprocessbeginswithasynceventstartingthe9-bitdelaycounter.
Afterthedelaycount+2samples,theintegrationintervalisstarted.
ThepoweriscalculatedforeachIandQsampleandaddedtothe58-bitaccumulator.
Theintegrationcontinuesuntiltheintegrationcountismetatwhichpointtheupper32bitsofthe58-bitintegratoraretransferredtothereadregisterandaninterruptisgenerated.
Anewmeasurementperiodstartsattheendoftheintervalperiod.
NOTE:EachofthefourcompositeRMSpowermeterblockshasitsowndelaysync,interval,andintegrationperiodcounters,aswellasseparatesyncsourceregisters.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ProgrammingVARIABLEDESCRIPTIONcomp_pmeterX_result_lsb(15:0)Lower16bitsofthecompositepowermeasurementforsumchainX.
X=0,1,2,or3comp_pmeterX_result_msb(31:16)Upper16bitsofthecompositepowermeasurementforsumchainX.
X=0,1,2,or3comp_pmeterX_integration_lsb(15:0)Lower16bitsofthe21-bitintegrationperiod.
X=0,1,2,or3comp_pmeterX_integration_msb(20:16)Upper5bitsofthe21-bitintegrationperiod.
X=0,1,2,or3comp_pmeterX_sync_delay(8:0)Powermeterdelaysyncperiod.
X=0,1,2,or3comp_pmeterX_interval_lsb(15:0)Lower16bitsofthe21-bitmeasurementinterval.
X=0,1,2,or3comp_pmeterX_interval_msb(20:16)Upper5bitsofthe21-bitmeasurementinterval.
TheIntervaltimemustbegreaterthantheintegrationtimeforeachofthefourcompositepowermeters.
X=0,1,2,or3ssel_comp_pmeter_X(2:0)Syncsource.
X=0,1,2,or33.
3GC5316TransmitOutputInterfacetxclk_outFormat2181818txout_atxout_btxout_ctxout_dIQSumChain0IQSumChain1IQSumChain2IQSumChain3tx_i_flagFigure38.
TransmitOutputInterfaceTheGC5316providesfourtransmitoutputsignaldataports.
Eachportcanbeenabledordisabled.
Disabledportsareheldlowandcanalsobetri-stated.
Each18-bitportoutputsthesumofthecarrierscontributingtothecompositesignalstack.
Outputdatacanberealorcomplexvalued.
ComplexI/Qdatacanbeoutputeitherinterleavedoverasingleoutputport,or,overtwoportsseparately.
RealoutputdatawouldgenerallybeselecteddrivingasingleD/AconvertertoanIFfrequency.
Complexoutputdatawouldbeselectedwhensubsequentpost-processingsuchaspoweramplifierpredistortionisemployed.
ComplexoutputscanalsobeusedtodriveapairofD/Aconverters(oneforI,theotherforQ)fordirectI/Qupconversionusingaquadraturemodulatordevice.
IandQcomplexoutputdatacanbeinterleavedoverasingle18-bitport,or,simultaneouslyovertwoseparateoutputportsathalftherate.
Signaltx_I_flagisactivewhenIdataisbeingoutputwhenincomplexoutputinterleavedmode.
Whencomplexoutputdataisnoninterleaved,Idataisoutputonport0andQdataisoutputonport1forsumchain0.
Forsumchain1,Idataisoutputonport2andQdataisoutputonport3.
Realoutputdataisoutputoverasingle18-bitport.
ForCDMAmode,themaximumrealoutputrateistxclk/2.
ThemaximumrealoutputrateforUMTSmodeistxclk.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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Ifthecomplexoutputdataisinterleavedonasinglebus,themaximumrateistxclk/2forbothUMTSandCDMAandthetoggleratebetweenIandQsamplesistxclk.
NOTE:Thetx_clk_outsignalcannotbeatfullrate(txclkrate)ifthemixerisnotatfullrate(forCDMAmode,themixercannotbeatfullrate).
Ifafull-rateclockoutputsignalisdesired,thetst_clksignalcanbeused,withthetst_rateparameterprogrammedto0.
Table19.
ProgrammingVARIABLEDESCRIPTIONinterf_ena(3:0)Whenbitsareset,enablesthecorrespondingoutputs.
Whencleared,outputsaredisabledandheldlow.
interf_realWhenset,outputsarereal.
Whencleared,outputsarecomplex.
interf_interlWhenset,complexdataisoutputinterleaved.
tristate(3)Whenset,turnsontx_data_out3outputs.
tristate(2)Whenset,turnsontx_data_out2outputsaswellassync_tst,aflag_tst,andclk_tst.
tristate(1)Whenset,turnsontx_data_out1outputs.
tristate(0)Whenset,turnsontx_data_out0outputsaswellastx_iflagandtx_clk_out.
trt_rateThevalueherecontrolstheoutputclockrateontheclk_tstpin.
Avalueof0givesafullrateoutputclock(txclkrate),a1giveshalfrateoutputclock,a3gives1/4thrateoutputclock,andsoon.
Thenumberoftxclkcyclesforwhichtheclk_tstsignalishigh+low=1+tst_rate.
4GC5316GeneralControlTheGC5316isconfiguredoverabidirectional16-bitparalleldatamicroprocessorcontrolport.
Thecontrolportpermitsaccesstothecontrolregisterswhichconfigurethechip.
Thecontrolregistersareorganizedusingapaged-accessschemeusingsixaddresslines.
Halfofthe64addresses(address32throughaddress63)representglobalregisters.
Theother32(address0throughaddress31)arepagedresisters.
Thisarrangementpermitsaccessingalargenumberofcontrolregistersusingrelativelyfewaddresslines.
Globaladdress33isthepageregister.
Writinga16-bitvaluetothisregistersetsthepagetowhichfuturewriteorreadoperationsperformed.
Thesepaged-registerscontaintheactualparametersthatconfigurethechipandareaccessedbywriting/readingaddress0throughaddress31.
Globalregisters(address32throughaddress63)areusedtoread/writeGC5316parametersthatareglobalinnatureandcanbenefitfromsingleread/writeoperations.
Examplesincludechipstatus,reset,syncoptions,checksumrampparameters,andthepageregister.
4.
1ControlData,Address,andStrobesThecontrolbusconsistsof16bidirectionalcontroldatalinesC[0:15],6addresslinesA[0:5],areadenablelineRD,awriteenablelineWR,andachipenablelineCE.
TheselinesusuallyinterfacetoamicroprocessororDSPchipandisintendedtolooklikeablockofmemory.
Dataiswrittenby:1)SettingupthedesiredaddressA[0:5],2)SettingCElow,3)SettingthedesireddataonC[0:15],andthen4)PulsingWRlow.
DataiswrittenwhenWRreturnshigh.
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2MPUTimingDiagramsCE_NRD_NWR_ND(15:0)A(5:0)RD_NistiedtoGNDWR_NCE_ND(15:0)A(5:0)XXXXVALIDXXXXVALIDtUPCKLtUPCKHtd(UP)thtsu(UPA)th2-PinMode(CE_Nisthestrobe,WR_Nselectdirection)tUPCKLtUPCKHtd(UP)3-PinMode(RD_Nisthestrobe)Figure39.
ReadDiagramsCE_NWR_NRD_ND(15:0)A(5:0)CE_NRD_NistiedtoGNDD(15:0)A(5:0)WR_Ntsu(UPD)tsu(UPD)t3tUPCKLtUPCKHth(UPD)tUPCKLtUPCKHth(UPD)3-PinMode(WR_Nisthestrobe)2-PinMode(CE_Nisthestrobe,WR_Nselectdirection)Figure40.
WriteDiagramsGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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3InterruptHandlingWhenaGC5316blocksetsaninterrupt,theinterruptpingoesactiveiftheinterruptsourceisnotmasked.
Themicroprocessorshouldthenreadthethreeinterruptflagregisterstodeterminethesourceoftheinterrupt.
Themicroprocessorthenhastoreadtheinterruptsourcecircuitsregister(s)tocleartheinterruptpinandinterruptflagregisterbit.
Thethreeinterruptregistersarelistedintheglobalregisterspartofthecontrolregisterssection.
4.
4SyncSignalsVariousfunctionblockswithintheGC5316needtobesynchronizedinordertorealizepredictableresults.
TheGC5316providesaflexiblesystemwhereeachfunctionblockthatrequiressynchronizationcanbeindependentlysynchronizedfromeitherdevicepinsorfromasoftwareone-shot.
Theone-shotoptionissetupandtriggeredthroughcontrolregisters.
Thereceiveandtransmitsectionsofthechipeachhavefourhardwaresyncinputpinsavailable.
Thesesyncpinsarequalifiedonthechip'srisingclockedge.
Table1showsthedifferentsyncmodesavailableforbothreceiveandtransmitsections.
Table1.
DifferentSyncModesAvailableforBothReceiveandTransmitSectionsMODERECEIVESYNCSOURCETRANSMITSYNCSOURCE0RxSyncATxSyncA1RxSyncBTxSyncB2RxSyncCTxSyncC3RxSyncDTxSyncD4DDCsynccounterTCDUCsynccounterTC5DDCsynctriggeredbyone-shotDUCsynctriggeredbyone-shot60(alwaysoff)0(alwaysoff)71(alwayson)1(alwayson)Table2throughTable5summarizetheblockswhichhavefunctionsthatcanbesynchronizedusingtheaboveeightsyncoptions:Table2.
TransmitCommonSyncsSYNCNAMEPURPOSEssel_comp_pmeterInitializesthexmitcompositepowermeterssel_duc_counterInitializesthexmitcommonsynccounterssel_duc_serpInitializesthexmitserialinterfacessel_duc_gainUpdatesthegainregisterssel_duc_pilotInitializesthexmitpilotgeneratorandupdatesthepilotgainssel_duc_tadjUpdatesthedelayadjustregisterssel_duc_pmeterInitializesthexmitchannelpowermeterTable3.
TransmitChannelSyncsSYNCNAMEPURPOSEssel_duc_ncoResetstheNCOaccumulatorssel_duc_freqUpdatestheNCOfreqregistersssel_duc_phaseUpdatestheNCOphaseregisterssel_duc_ditherResetstheNCOditherGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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ReceiveCommonSyncsSYNCNAMEPURPOSEssel_ddc_counterInitializesthereceivesynccounterssel_ddcInitializesthereceiveADCsamplesinterfaceandclockgencircuits(includingCICdecimation)ssel_ddc_tadjUpdatesthedelayadjustregisterssel_ddc_pmeterInitializesthereceivepowermeterssel_ddc_agcUpdatestheAGCregistersssel_ddc_pserInitializesthereceiveserialinterfaceTable5.
ReceiveChannelSyncsSYNCNAMEPURPOSEssel_ddc_ncoResetstheNCOaccumulatorssel_ddc_freqUpdatestheNCOfreqregistersssel_ddc_phaseUpdatestheNCOphaseregister4.
5InitializationChipinitializationproceduresareavailablefromTexasInstruments.
4.
6GC5316BoardDiagnosticsTheGC5316containsbuilt-intestfeaturesthatcanbeusedtoconfirmthatthechipisoperatingcorrectlyandtohelpusersdebugtheirboardsandsystemsthatconatintheGC5316.
Thediagnositcandboardtestprocedurescanbedownloadfromthewebatwww.
ti.
comastheGC5316DiagnosticsDesigner'sKit.
5GC5316ProgrammingThecmd5016program,itsuser'sguide,andexampleconfigurationfilescanbedownloadedfromthewebatwww.
ti.
comastheGC5316ConfigurationDesigner'sKit.
TheGC5316containsover7,000controlandcoefficientregistersthatmustbewrittentoinordertofullyconfigurethechip.
Ratherthanprogrameachoftheseregistersindividually,TexasInstrumentssuppliesaconfigurationprogramcalledcmd5316whichacceptstop-levelconfigurationinformationforthechipandthengeneratesthefullregistermapandcontrolwritesrequiredtoprogramthechip.
Theconfigurationcontrolshavebeendefinedinthefunctionaldescriptionofeachsectionofthechip.
Thefollowingtablessummarizethesecontrolsandidentifywhichregisterandwhichbitswithintheregisterstheyoccupy.
Eachcontrolregistertablehasacolumnidentifyingwhetherthevariablemustbespecifiedbytheuserincmd5316(U),istypicallyleftatthedefaultvalueanddoesnotneedtobespecified(D),iscomputedbycmd5316andshouldnotbeset(C),orisforexpertuseonly(E).
Tablesarealsoincludedthatshowthetoplevelpagemappingforthechipcontrols,thestatusandmeasurementresultregisters,andadditionalcontrolsthatareusedwiththeGC101/GC5316DIMMevaluationplatform.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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1cmd5316KeywordsThesekeywordsareusedbythecmd5316programtosetgeneralconfigurationparameters.
NAMEARGUMENTUSEDESCRIPTIONprintconfigGlobalTellscmd5316togenerateaconfigurationoutputfileforgeneraluse.
printgc101GlobalTellscmd5316togenerateaconfigurationoutputfileforGC101use.
printanalysisGlobalTellscmd5316togenerateaanalysisoutputfileprinttableGlobalTellscmd5316togenerateatableoutputfileprintpowerGlobalTellscmd5316togenerateanapproximatepowerconsumptionoutputfile.
rxclkclockfrequencyinMHzGlobalUsedtocalculatereceivetuningfrequenciestxclkclockfrequencyinMHzGlobalUsedtocalculatetransmittuningfrequenciesadc_resamplerfilenameforresamplertapsGeneralReceiveSpecifiesthefilenamecontainingtheresamplertapsddcchannelnumberDDCChannelsAllcontrolsafterthiskeywordapplytothisDDCchannelcopy_ddcchanchannelnumberDDCChannelsCopytheDDCchannelcommandsfromthespecifiedchanneltothecurrentchannelducchannel_numberDUCChannelsAllcontrolsafterthiskeywordapplytothisDUCchannelcopy_ducchanchannel_numberDUCChannelsCopytheDUCchannelcommandsfromthespecifiedchanneltothecurrentchannelfreqatuningfrequencyinMHzDDCsandDUCsSetstheNCOtuningfrequencyfortheUMTSchannelorforthea-pathinthecurrentchannelifinCDMAmode.
freqbtuningfrequencyinMHzDDCsandDUCsSetstheNCOtuningfrequencyfortheb-pathinthecurrentchannelifinCDMAmode.
pfir_coefffilenameforpfirtapsDDCsandDUCsSpecifiesthefilenamecontainingthepfirtapscfir_coefffilenameforcfirtapsDDCsandDUCsSpecifiesthefilenamecontainingthecfirtapsoverall_gainaoverallchannelgainDDCsandDUCsOptionalSpecifiestheoverallgainfortheUMTSchannelorthea-pathinthecurrentchannelifinCDMAmode.
overall_gainboverallchannelgainDDCsandDUCsOptionalSpecifiestheoverallgainfortheb-pathinthecurrentchannelifinCDMAmode.
5.
1.
1GC5316DIMMKeywordsThesekeywordsareusedtocontrolhowtheGC5316DIMMoperatesintheGC101evaluationboard.
NAMEARGUMENTTYPEDEFAULTUSEDESCRIPTIONloopback0or1G0GC5316DIMMWhenasserted,txout_aoutputconnectedtorxin_ainput,elserxin_ainputfromGC101.
spin00or1G0GC5316DIMMWhenasserted,txin_[0:5]_[a:b]portsareactive,elsedatafromGC101assumedtogotorxin_a.
spin10or1G0GC5316DIMMWhenasserted,txin_[6:11]_[a:b]portsareactive,elsedatafromGC101assumedtogotorxin_b.
sigout003G3GC5316DIMM00–txout_aenabled,01–txout_cenabled,10–rxout_[0:3]_[a:d]enabled,11noneenabled.
sigout103G3GC5316DIMM00–txout_benabled,01–txout_denabled,10–rxout_[4:7]_[a:d]enabled,11noneenabled.
txout_lsb0or1G0GC5316DIMMWhenasserted,the2lsb'seachofactivetxoutareoutputtoGC101,elsethevariousstrobes/syncoutsareoutput.
sel_syncout03G3GC5316DIMM(iftxout_lsb=0)selectswhichsignalsareoutput.
00tx_sync_out+tx_i_flag,01sync_tst+aflag_tst,10tx_sync_out0+interrupt,11rx_sync_out+test6.
res_op_en03G3GC5316DIMM(iftxout_lsb=0)when00,test9+test11isoutput,test7+test8dataisoutputif01,andrx_sync_out0when10.
sel_clkout03G0GC5316DIMMSelectstheoutputclocksource.
00txclk_out,01clk_tst,10clkout+.
adcclk_set0or1G0GC5316DIMMWhenasserted,gatedadcclk.
When0,NORgatebypassed(i.
e.
adcclkwillbethesameasrxclk).
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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1.
2PageMapThispagemapdescribeswhichpagesandwhatregisterswithinthepagesareused.
Allotherpagesareunused.
Thistableisprovidedforreferenceonly,theregistersandthebitswithintheregistersaredescribedinthefollowingcontrolregistertables.
PAGESADDRESSDESCRIPTIONBASE+000andBASE+020001FPFIRCoefficients,2LSBsBASE+040andBASE+060001FPFIRCoefficients,16MSBsBASE+080andBASE+0A0001FCFIRCoefficients,2LSBsBASE+040andBASE+0E0001FCFIRCoefficients,16MSBsBASE+100001FChannelControlRegistersBASE+120001DChannelControlRegistersWhereBASEis(DUCnx0200)forDUCnfrom0to11,andis(DDCnx0200+2000)forDDCnfrom0to1118000009GeneralReceiveControlRegisters18000A1Fadc_resamplercoefficients18200004adc_resamplercoefficients182006GeneralReceiveControlRegisters1C000011and1A1EGeneralTransmitControlRegisters1C200007and0CGeneralTransmitControlRegisters5.
1.
3StatusandRead-OnlyRegistersTheseregisterscanbeaccessedbytheusertoreadstatusorreadmeasurementresultsfromthechip.
Theseregisternamesarenotusedincmd5316.
NAMEPAGEADDRESSLSBPOSITIONBITWIDTHDESCRIPTIONVersionGlobal2005A5-bitreadonlyregisterindicatingthecurrentGC5316revisionstatusinter_pmeterGlobal25124Indicateswhichtransmitcompositepowermetergeneratedtheinterruptinter_tx_pmeterGlobal26412Indicateswhichtransmitpowermetergeneratedtheinterruptinter_rx_pmeter_msbGlobal2604Indicateswhichreceivepowermetergeneratedtheinterrupt4MSBsinter_rx_pmeter_lsbGlobal2788Indicateswhichreceivepowermetergeneratedtheinterrupt8LSBsinter_tx_cicGlobal28012Indicateswhichtransmitcicoverflowdetectgeneratedtheinterruptcomp_pmeter0_lsb1C200001616LSBsofcompositpowermeter0comp_pmeter0_msb1C200101616MSBsofcompositpowermeter0comp_pmeter1_lsb1C200201616LSBsofcompositpowermeter1comp_pmeter1_msb1C200301616MSBsofcompositpowermeter1comp_pmeter2_lsb1C200401616LSBsofcompositpowermeter2comp_pmeter2_msb1C200501616MSBsofcompositpowermeter2comp_pmeter3_lsb1C200601616LSBsofcompositpowermeter3comp_pmeter3_msb1C200701616MSBsofcompositpowermeter3tx_chk_sum1C200C016Transmitchecksumresultpmeter_a_lsbBASE+012007016DDCapowermeter16LSBspmeter_a_msbBASE+012008016DDCapowermeter16MSBspmeter_b_lsbBASE+012009016DDCbpowermeter16LSBspmeter_b_msbBASE+01200A016DDCbpowermeter16MSBsddc_chk_sumBASE+012013016DDCchecksumBASE=(DDCnx0200+2000)forDDCchannels,whereDDCnequals0to11GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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4GlobalControlVariablesTheseregisterscontainglobalcontrolsfortheGC5316.
Theseregistersarenotpagedandareaccesseddirectlyusingaddresses3263(203fhex)VARIABLENAMETYPEADDRESSLSBPOSITIONBITWIDTHDEFAULTDESCRIPTIONpageE210160ThePageregisterselectswhichpageaddresses001F(031)willaccess.
slf_tst_enaD221510(TESTINGPURPOSES)TurnsonthechecksumLFSRforreceiveandtransmit.
rduz_sens_enaD221410Whenenabled,addsnoisetotheLSB'stotheADCinputs.
tst_sel_chanE22120(TESTINGPURPOSES)Ineachslice,thesebitscontrolwhichtst_outissenttothetransmitblock.
(whichduc/ddcintheslice)tst_onE22010(TESTINGPURPOSES)Whenassertedthetestbusisactive,txout_c(17:0),andtxout_d(17:0)formthe36-bittestwordoutput.
Thefollowingtristatesareactivelow,0turnstheoutputon,1tristatesit.
tristate_10E231011Reservedoutputsfortest,mustbesetto1(tristate)tristate_9C23911Thisbitturnsontheslice5tx_sync,rx_sync,andrxserialdataoutputs.
tristate_8C23811Thisbitturnsontheslice4tx_sync,rx_sync,andrxserialdataoutputs.
tristate_7C23711Thisbitturnsontheslice3tx_sync,rx_sync,andrxserialdataoutputs.
tristate_6C23611Thisbitturnsontheslice2tx_sync,rx_sync,andrxserialdataoutputs.
tristate_5C23511Thisbitturnsontheslice1tx_sync,rx_sync,andrxserialdataoutputs.
tristate_4C23411Thisbitturnsontheslice0tx_sync,rx_sync,rxserialdata,tx_sync_out,andrx_sync_outoutputs.
tristate_3C23311Thisturnsonthetxout_doutputs.
tristate_2C23211Thisturnsonthetxout_cCLK_TST,IFLAG_TST,andSYNC_TSToutputs.
tristate_1C23111Thisturnsonthetxout_boutputs.
tristate_0C23011Thisturnsonthetxout_a,TX_IFLAG,andTXCLK_OUToutputs.
tx_oneshotD241510Whensetaoneshotpulseissenttothetransmitblocksforsyncing.
Thisonlyworksiftheblocksareprogrammedtoseetheoneshot.
Tousetheoneshotagain,itmustbeprogrammedbacktoa'0'andthenbacktoa'1'.
rx_oneshotD24710Whensetaoneshotpulseissenttothereceiveblocksforsyncing.
Thisonlyworksiftheblocksareprogrammedtoseetheoneshot.
Tousetheoneshotagain,itmustbeprogrammedbacktoa'0'andthenbacktoa'1'.
imask_comp_pmeterD291240Interruptmaskbitsforthetransmitcompositepowermeterimask_tx_pmeterD2A4120Interruptmaskbitsforthecompositepowermeterimask_rx_pmeter_msbD2A040Interruptmaskbitsforthereceivecompositepowermeter4MSBsGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com52imask_rx_pmeter_lsbD2B880Interruptmaskbitsforthereceivecompositepowermeter8LSBsimask_tx_cicD2C0120Interruptmaskbitsforoverflowdetectioninthetransmitcics5.
1.
5GeneralReceiveControlsTheseregisterscontrolthereceiveinterfacetotheDDCchannelsVARIABLENAMETYPEPAGEADDRESSLSBPOSITIONBITWIDTHDEFAULTDESCRIPTIONddc_counter_lsbD180050166553532-bitintervaltimercommontoallDDCsyncinputs.
Thistimermaybeprogrammedtoanyintervalcount,andeachDDCsynchronizationinputcanselectthiscounterasasource.
ThiscounterincrementsoneachRXclockrisingedge.
16LSBsddc_counter_msbD180060166553532-bitintervaltimercommontoallDDCsyncinputs.
16MSBsssel_ddc_counterU18007830SelectsthesyncsourcefortheDDCsynccounter.
ddc_counter_widthD18007080SetsthewidthofthecountergeneratedsyncpulseinRXclockcycles,from1to256.
Thewidthofthetheddc_counterpulseshouldbesetwideenoughtobeassertedforanentireclockperiodoftheslowestblocktousethissyncssel_adc_fifoU180081236SelectsthesyncsourcefortheadcFIFOblock.
SyncreinitializesthereadandwritepointersoftheFIFO.
ssel_resampU18008830SelectsthesyncsourcefortheADC_RESAMPLERblock.
ssel_rxsync_outU18008430SelectsthesyncsourcefortheRXSYNC_OUTpin.
ssel_rxinU18008030Synchronizestherx_distributionbussourceanddestinationandclockgenerationineachoftheDDCblocks.
rate_selU180091420ThisselectstheFIFOoutputratewhenadc_fifo_bypass=0.
Whenusingtheresampler,thisvalueshouldbeprogrammedtoa0.
Whensetto0,theFIFOoutputisclockedbyrxclk(gatedifresamplerisonanddecimatingby1.
5).
Whensetto1,theFIFOoutputrateis1/2ofrxclkrate.
Whensetto2,theFIFOoutputrateis1/4ofrxclkrate,andwhensetto3,theFIFOoutputisat1/8ofrxclkrate.
E.
g.
:Withrxclk122.
88MHz,setrate_selto0,1,2or3respectivelyforadcclk122.
88,61.
44,30.
72or15.
36MHz.
resampler_enaU180091310WhenassertedturnsontheADC_RESAMPLERblock.
adc_fifo_bypassD180091010Whenasserted,theadc_fifoisbypassed.
InputdataisthenclockedindirectlyusingtheRXCLKinput.
Thessel_rxinselectionvaluewillcontrolthelocationoftheinternallygeneratedsampleclockwhenthisbitisasserted.
resampler_decimD18009911ThistellstheADC_RESAMPLERblockthedecimationfactor(1=1.
5X,0=2X)nz_pwr_maskD182060160Usedalongwithrduz_sens_ena,itselectsthenoisebitstobeaddedtotheADCinputsamplewhenasserted.
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6GeneralTransmitControlsTheseregisterscontrolthetransmitoutputinterfacefromtheDUCchannels.
VARIABLENAMETYPEPAGEADDRESSLSBPOSITIONBITWIDTHDEFAULTDESCRIPTIONtst_sel_sliceE1C00001330(TESTINGPURPOSES)Thisselectsthesliceblockthatisgeneratingthetst_outdata.
(whichDUC/DDC)tst_rateE1C00051150Thevalueherecontrolstheoutputclockrateontheclk_tstpin.
Avalueof0givesafull-rateoutputclock(txclkrate),a1giveshalf-rateoutputclock,a3gives1/4thrateoutputclock,andsoon.
Thenumberoftxclkcyclesforwhichtheclk_tstsignalishigh+low=1+tst_rate.
interf_roundD1C0000820Controlsroundpointonthetransmitoutputdata;{00=18b,01=16b,10=14b,11=12b}.
RoundedoutputdataisMSBjustified.
Forexample,a12broundpointcausestheoutputdatatobepresentedontheoutputpins(17:6),andtheoutputpins(5:0)tobeheldlow.
interf_enaD1C00004415Enablestheindividualtransmitoutputbusses3through0.
Disabledbussesarealwaysheldlow.
interf_interlU1C0000110EnablesinterleavedI/Qdatawhenasserted.
interf_realU1C0000011Enablesrealonlyoutputswhenasserted.
Complexdataisoutputwhencleared.
interf_scale_3U1C00011240Selectsthescalingbetweenthesumchainoutputsignalsandthetransmitoutputpinsandtransmitcompositepowermeters.
Appropriatelimitingandroundingisperformedasrequiredbytheprogrammedroundpoint.
Gain=2(interf_scale).
Forsumchain3.
interf_scale_2U1C0001840Selectsthescalingbetweenthesumchainoutputsignalsandthetransmitoutputpinsandtransmitcompositepowermeters.
Appropriatelimitingandroundingisperformedasrequiredbytheprogrammedroundpoint.
Gain=2(interf_scale).
Forsumchain2interf_scale_1U1C0001440Selectsthescalingbetweenthesumchainoutputsignalsandthetransmitoutputpinsandtransmitcompositepowermeters.
Appropriatelimitingandroundingisperformedasrequiredbytheprogrammedroundpoint.
Gain=2(interf_scale).
Forsumchain1interf_scale_0U1C0001040Selectsthescalingbetweenthesumchainoutputsignalsandthetransmitoutputpinsandtransmitcompositepowermeters.
Appropriatelimitingandroundingisperformedasrequiredbytheprogrammedroundpoint.
Gain=2(interf_scale).
Forsumchain0GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com54comp_pmeter0_count_lsbD1C00020160Thisisthenumberofsamplesetstoaccumulateforapowermeasurement.
IaandQa(signal)areeachsquaredandaccumulated.
EachpairofIandQareequaltooneintegrationcount.
Theaccumulationintervalisinitiatedwhenthesyncisassertedandtheprogrammedsync_delayhasexpiredorwhentheintervalstarttimeisreached.
Whentheintegrationcountisreached,theaccumulatedpowersaremadeavailableforMPUaccessandaninterruptisgenerated.
Bits015comp_pmeter0_count_msbD1C0003050Bits1620ofthenumberofsamplesetstoaccumulateforapowermeasurement.
(Usedinconjunctionwiththepreviousvariable.
)comp_pmeter0_sync_delayD1C0003790Programmablestartdelayfromsync,ineightoutputsampleunits.
comp_pmeter0_interval_lsbD1C00040160Thisistheintervaloverwhichtheintegrationisrestartedandmustbegreaterthantheintegrationcount.
TheintervalstartcounterandRMSpoweraccumulationisstartedatthesyncpulseaftertheprogrammeddelayandeverytimetheintervalcounterreachesitslimit.
Bits015comp_pmeter0_interval_msbD1C0005050Bits1620oftheintervaloverwhichtheintegrationisrestarted.
(Usedinconjunctionwiththepreviousvariable.
)comp_pmeter1_count_lsbD1C00060160Seedescriptionforpmeter0comp_pmeter1_count_msbD1C0007050Seedescriptionforpmeter0comp_pmeter1_sync_delayD1C0007790Seedescriptionforpmeter0comp_pmeter1_interval_lsbD1C00080160Seedescriptionforpmeter0comp_pmeter1_interval_msbD1C0009050Seedescriptionforpmeter0comp_pmeter2_count_lsbD1C000A0160Seedescriptionforpmeter0comp_pmeter2_count_msbD1C000B050Seedescriptionforpmeter0comp_pmeter2_sync_delayD1C000B790Seedescriptionforpmeter0comp_pmeter2_interval_lsbD1C000C0160Seedescriptionforpmeter0comp_pmeter2_interval_msbD1C000D050Seedescriptionforpmeter0comp_pmeter3_count_lsbD1C000E0160Seedescriptionforpmeter0comp_pmeter3_count_msbD1C000F050Seedescriptionforpmeter0comp_pmeter3_sync_delayD1C000F790Seedescriptionforpmeter0comp_pmeter3_interval_lsbD1C00100160Seedescriptionforpmeter0comp_pmeter3_interval_msbD1C0011050Seedescriptionforpmeter0duc_counter_lsbD1C001A0166553532-bitintervaltimercommontoallDUCsyncinputs.
Thistimermaybeprogrammedtoanyintervalcount,andeachDUCsynchronizationinputcanselectthiscounterasasource.
ThiscounterincrementsoneveryTXCLKrisingedge.
Bits015duc_counter_msbD1C001B01665535Bits1631oftheabovementioned32-bitintervaltimer.
ssel_duc_counterU1C001C830SelectsthesyncsourcefortheDUCsynccounter.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com55duc_counter_widthD1C001C080SetsthewidthofthecountergeneratedsyncpulseinTXclockcycles,from1to256.
ThewidthofthispulsemustbelongenoughtobecapturedbytheslowestblocktousetheDUCcountersync.
ssel_comp_pmeter_0U1C001D1230Selectsthesyncsourceforcompositepowermeter0.
ssel_comp_pmeter_1U1C001D830Selectsthesyncsourceforcompositepowermeter1.
ssel_comp_pmeter_2U1C001D430Selectsthesyncsourceforcompositepowermeter2.
ssel_comp_pmeter_3U1C001D030Selectsthesyncsourceforcompositepowermeter3.
ssel_txsync_outU1C001E030SelectsthesyncsourcefortheTXSYNC_OUTpin.
5.
1.
7DDCorDUCChannelControlsThesecontrolsareusedbyboththeDDCorDUCchannels.
Thesefolloweithertheddcortheduckeywordsinthecmd5316configurationfile.
VARIABLENAMETYPEPAGEADDRESSLSBPOSITIONBITWIDTHDEFAULTDESCRIPTIONcdma_modeU010001511WhenassertedtheblockisinthedualchannelCDMA2000mode.
crastarttap_pfirC01000850ThesebitsdefinethenumberoftapsthatPFIRusesforthefiltering.
AnotherwayoflookingatthesebitsisthatthisvalueisthelocationintheRAMofthecentertap.
DUCPFIR:(2xcrastarttap_pfir)+1,DDCPFIR:4(crastarttap_pfir+1),DDCPFIRlongmode:8(crastarttap_pfir+1).
Note:crastarttap_pfirmustbeoddforaDUCcrastarttap_cfirC01000350ThesebitsdefinethenumberoftapsthatCFIRusesforthefiltering.
DUCCFIR:(2xcrastarttap_cfir)+1,DDCCFIR:2(crastarttap_cfir+1).
Note:crastarttap_cfirmustbeoddforaDUCpfir_gainU010011330ThisisthegainforthePFIR.
Therangeisfrom2e19to2e12forthereceivePFIR.
("000"=2e19and"111"=2e12)ForthetransmitPFIRhowever,onlytheLSBofthewordisusedanditselectseither2e18when'0'or2e17when'1'.
cfir_gainU01001510ThisisthegainfortheCFIR.
0=2e19,1=2e18.
cic_scale_aU01000E1150ThissetsthegainshiftattheoutputoftheCDMAAchannel(orUMTSchannel)CIC.
0x00isnoshift,eachincrementby1increasesthesignalamplitudeby2X.
cic_scale_bU01000E650ThissetsthegainshiftattheoutputoftheCDMABchannelCIC.
0x00isnoshift,eachincrementby1increasesthesignalamplitudeby2X.
cic_interp_decimU01000E0524SetstheCICinterpolation,whereinterpolationiscic_interp_decim+1inthedigitalupconverters.
SetstheCICdecimation,wheredecimationiscic_interp_decim+1inthedigitaldownconverters.
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com56cic_m2_ena_aD01000F1060ProgramstheCDMAAchannel(orUMTSchannel)CICfirsectionsMvalueto2whenset,1whencleared.
cic_m2_ena_a(0)controlstheMvalueforthefirstcombsectionandcic_m2_ena_a(5)controlstheMvalueforthelastcombsection.
cic_m2_ena_bD01000F460ProgramstheCDMABchannelCICfirsectionsMvalueto2whenset,1whencleared.
cic_m2_ena_b(0)controlstheMvalueforthefirstcombsectionandcic_m2_ena_b(5)controlstheMvalueforthelastcombsection.
tadj_offset_coarse_aD0100111060Thisispartofthetimedelayadjust.
Thisisthecoarseoffsetandisreallyanoffsetfromthewriteaddressinthedelayram.
ThisvalueaffectstheAchannelifCDMAmodeisbeingused,ortheUMTSchannel.
EachLSBisonemoreoffsetbetweeninputtothecoursedelayblockandtheoutputofthecourseblock.
tadj_offset_coarse_bD010011460Thisispartofthetimedelayadjust.
Thisisthecoarseoffsetandisreallyanoffsetfromthewriteaddressinthedelayram.
ThisvalueaffectstheBchannelifCDMAmodeisbeingused.
EachLSBisonemoreoffsetbetweeninputtothecoursedelayblockandtheoutputofthecourseblock.
tadj_offset_fine_aD0100121330Thisispartofthetimedelayadjust.
Thisisthefineadjustvalue.
Itadjuststhetimedelayattheclockrate.
ThisvalueaffectstheAchannelifCDMAmodeisbeingused,ortheUMTSchannel.
tadj_offset_fine_bD0100121030Thisispartofthetimedelayadjust.
Thisisthefineadjustvalue.
Itadjuststhetimedelayattheclockrate.
ThisvalueaffectstheBchannelifCDMAmodeisbeingused.
tadj_interp_decimU010012731Thisisthedecimationorinterpolationvalueforthefinetimeadjustblock.
Decimationorinterpolationcanbefrom1to8.
ThisvalueaffectsboththeAandBchannelsifCDMAmodeisbeingused,ortheUMTSchannel.
phase_add_a_lsbC0100130160This32bitwordisusedtocontrolthefrequencyoftheNCO.
Derivedfromthekeywordfreqabycmd5316.
(forCDMAchannelAorUMTSchannel).
Lower16bits.
phase_add_a_msbC0100140160Upper16bitsoftheabove32-bitword.
phase_add_b_lsbC0100150160This32-bitwordisusedtocontrolthefrequencyoftheNCO.
Derivedfromthekeywordfreqbbycmd5316.
(forCDMAchannelB).
Lower16bits.
phase_add_b_msbC0100160160Upper16bitsoftheabove32-bitword.
phase_offset_aD0100170160ThisisthefixedphaseoffsetaddedtotheoutputofthefrequencyaccumulatorforsinusoidgenerationintheNCO.
(UMTSmodeandAchannelinCDMAmode)phase_offset_bD0100180160ThisisthefixedphaseoffsetaddedtotheoutputofthefrequencyaccumulatorforsinusoidgenerationintheNCOforCDMABchannel.
dither_enaD0100191510Thisbitcontrolswhetherornotditheristurnedon(1)oroff(0).
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com57test_bits_1E0100191320TESTBITS.
Setto'0'fornormaloperation.
pmeter_sync_disableD0100191210Turnsoffthesynctothechannelpowermeter.
Thiscanbeusedtoindividuallyturnoffsyncstoachannelspowermeter,whilestillhavingsyncstootherpowermetersonthechip.
ddc_duc_enaU0100191110WhensetthisturnsontheDUCorDDC.
Whenunset,theclockstothisblockareturnedoff.
mixer_gainU010019910Addsafixed6dBofgaintothemixeroutput(beforeroundandlimiting)whenasserted.
Elseadds12-dBgainwhendeasserted.
mpu_ram_readE010019810(TESTINGPURPOSES)AllowsthecoefficientRAMsinthePFIR/CFIRtobereadoutthempudatabus.
Thiscannotbedoneduringnormaloperationandmustbedonewhenthestateoftheoutputdataisnotimportant.
THISBITMUSTBESETONLYDURINGTHEREADOPERATION.
sumchn_sel_bU010019442ThiswordcontrolsthesecondsetofadditionsfortheCDMABsignalinthesumchnoutput.
Theselectionbitsarenotmutuallyexclusive.
sumchn_sel_aU010019041ThiswordcontrolsthefirstsetofadditionsfortheCDMAAsignal(orUMTSsignal)inthesumchnoutput.
Theselectionbitsarenotmutuallyexclusive.
tst_sel_blockE01001A060(TESTINGPURPOSES)Thisistheselectionofwhichsignalcomesoutthetestbus.
Whenaconstant'0'isselectedthisalsoreducespowerbypreventingthedataattheinputofthetestblockfromchanging.
Itdoesnotstoptheclockhowever.
ssel_pmeterU01200B830Selectsthesyncsourceforthechannelpowermeter.
ssel_serialU01200B030SelectsthesyncsourcefortheDUCandDDCserialinterfacestatemachines.
ssel_tadj_fineU01200C1230Selectsthesyncsourceforthefinetimeadjustdecimation(DUC)orzerostuff(DDC)moment.
ssel_tadj_coarseU01200C830Selectsthesyncsourceforthecoursetimeadjustdelayselection.
ssel_gainU01200C430SelectsthesyncsourcefortheDUCgainregisterorDDCAGCgainregister.
ssel_ncoU01200D1230SelectsthesyncsourcefortheNCOaccumulatorreset.
ssel_ditherU01200D830SelectsthesyncsourcefortheNCOphasedithergeneratorreset.
ssel_freqU01200D430SelectsthesyncsourcefortheNCOfrequencyregister.
ssel_phaseU01200D030SelectsthesyncsourcefortheNCOphaseoffsetregister.
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8DDCChannelControlsThesecontrolsareusedbytheDDCchannels.
Thesefollowtheddckeywordinthecmd5316configurationfile.
VARIABLENAMETYPEPAGEADDRESSLSBPOSITIONBITWIDTHDEFAULTDESCRIPTIONpmeter_integration_ddcD010020160Thisisthenumberoffoursamplesetstoaccumulateforapowermeasurement.
InCDMAmode,onesamplesetistheIandQofthesignalanddiversity.
IaandQa(signal)areeachsquaredandaccumulatedandIbandQb(diversity)aresquaredandaccumulated.
InUMTSmode,eachIandQpairaresquaredandaccumulated.
Foursamplesareequaltooneintegrationcount.
Thecountisinitiatedwhenthesyncisassertedorwhentheintervalstarttimeisreached.
Whentheintegrationcountisreached,theaccumulatedpowersaremadeavailableforMPUaccessandaninterruptisgenerated.
pmeter_sync_delay_ddcD01003880Thedelayfromselectedsyncsourcetowhenthepowercalculationstarts.
pmeter_interval_ddcD01003080Thestartintervaltimeristheintervaloverwhichtheintegrationisrestartedandmustbegreaterthantheintegrationcount.
TheintervalstartcounterandRMSpoweraccumulationisstartedatthesyncpulseaftertheprogrammeddelayandeverytimetheintervalcounterreachesitslimit.
Thisvalueisin1024sampleunits.
cic_gain_ddcU01000E510Addsafixedgainof12dBattheCICoutputwhenasserted.
test_enaE0100191010TESTBIT.
Setto'0'fornormaloperation.
agc_dbelowD01001D1240ThevaluetoshiftthegainthatisthenaddedtotheaccumulatorwhenthevalueoftheincomingdataxcurrentgainvalueisbelowtheThreshold.
agc_daboveD01001D840ThevaluetoshiftthegainthatisthensubtractedfromtheaccumulatorwhenthevalueoftheincomingdataxthecurrentgainvalueisabovetheThreshold.
agc_dzeroD01001D440Thevaluetoshiftthegainthatisthenaddedtotheaccumulatorwhenthevalueoftheincomingdataxcurrentgainvaluesconsistentlyequaltozero.
agc_dsatD01001D040Thevaluetoshiftthegainthatisthensubtractedformtheaccumulatorwhenthevalueoftheincomingdataxthecurrentgainvalueisconsistentlyequaltomaximum.
agc_zero_mskD01001E1240Masksthelower4bitsofthemagnitudeoftheinputsignalsothattheyarecountedaszeros.
agc_rndD01001E840DetermineswheretoroundtheoutputoftheAGC.
0000is18bitsareout.
Thenumberofbitsoutoftheagcis18agc_rnd.
agc_thresD01001E080Thisisthethresholdthatthedataxgainiscomparedto.
Thisvalueiscomparedtothemagnitudeoftheuppereightbitsoftheagcoutput.
(Inputxgain).
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com59agc_gaina_msbU01001F1330Upper3bitsoftheCDMAchannelA(orUMTS)gainvalue.
agc_freezeU01001F1211Keepstheagcfromadaptingandonlymultipliestheinputdatabytheprogrammedgain.
ShouldbeassertedwhentheAGCalgorithmistobebypassed.
agc_max_cntD01001F840whentheagc_output(inputxgain)isatfullscaleforthisnumberoftimesthenthegainshiftvalueischangedtoD3.
agc_gainb_msbU01001F530Upper3bitsoftheCDMAchannelBgainvalue.
agc_clearU01001F410ClearstheAGCaccumulator.
ShouldassertthiswhentheAGCisinbypassmode.
agc_zero_cntD01001F040Whentheagc_output(inputxgain)iszerovalueforthisnumberoftimesthenthegainshiftvalueischangedtoagc_dzero.
agc_gaina_lsbU012000164096Thisisthelower16bitsofthetotal19bitsofprogrammablegain.
Thegainavalueisalwayspositivewiththeupper7bitsbeingtheintegervalueandthelower12bitsbeingthefractional.
ThisgainvalueisusedforallUMTSoperationsandforchannelAdatawheninCDMAmode.
Thisholdsthelowerfourintegerbitsandthe12fractionalbits.
Theupper3integerbitsarestoredintheagc_gaina_msbvariable.
Avalueof0001000000000000isunitygain.
agc_gainb_lsbU012010164096Thisisthelower16bitsofthetotal19bitsofprogrammablegain.
Thegainbvalueisalwayspositivewiththeupper7bitsbeingtheintegervalueandthelower12bitsbeingthefractional.
ThisgainvalueisusedforchannelBdatawheninCDMAmode.
Thisholdsthelowerfourintegerbitsandthe12fractionalbits.
Theupper3integerbitsarestoredintheagc_gainb_msbvariable.
Avalueof0001000000000000isunitygain.
agc_amaxD01202016512Themaximumvaluethatgaincanbeadjustedupto.
Thetop7bitsareintegerandbottomthe9bitsarefractional.
agc_aminD01203016512Theminimumvaluethatgaincanbeadjusteddownto.
Thetop7bitsareintegerandthebottom9bitsarefractional.
pser_recv_fsinvlU012048725Receiveserialinterfaceframesyncintervalinbitclocks.
pser_recv_bitsU012040517Numberofoutputbitspersample1;for18bits,thisissetto{10001}.
pser_recv_clkdivU012051241Receiveserialinterfaceclockdividerrate1;0isfullrateand15dividestheclockby16.
Forexample,torunthereceiveserialinterfaceat1/4thereceiveclock,setpser_recv_clkdiv(3:0)=0011.
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com60pser_recv_8pinD01205710Whenset,fourpinsareusedforIandfourpinsforQinUMTSmode.
Whencleared,twopinsareusedforIandtwopinsforQ.
Thisisusedincombinationwiththepser_recv_altbit.
Whenthisbitisset,itwouldbesetintwoadjacentDDCchannels;onewouldalsosetthepser_recv_altbit.
ThiscausestheIchanneltobeserializedonfourpinsandtheQchanneltobeserializedontheadjacentchannelsfourpins.
pser_recv_altD01205610Whenset,thischannel'sreceiveserialinterfaceoutputstheQdatafromtheadjacentDDCchannel.
(setto0forevenDDCandto1forODDDDC)pser_recv_fsdelD01205021DelaybetweenthereceiveframesyncoutputandtheMSBofserialdata{3,2,1,0}.
ddcmux_sel_aU012061240ControlswhichsamplesgotothemixerforI/Q.
(forCDMAchannelAorUMTSchannel).
ddcmux_sel_bU01206440ControlswhichsamplesgotothemixerforI/Q.
(forCDMAchannelB).
gain_monD012061010CombinesthegainwiththeI/Qoutputsignalswhenasserted.
LookattheAGCdescriptionformoreinfoaboutthestatusbits.
rnd_disableD012061111TurnsoffroundingattheAGCoutputifset.
NormalAGCoutputotherwise.
ch_rate_selU01206820TellstheDDCwhattheinputclockrateforthechannelis.
0rxclk,1–rxclk/2,2–rxclk/4,3–rxclk/8.
Forexample,iftheresampler_ena=1,theoutputoftheresamplerblockisatrxclk/2rate.
Soch_rate_selshouldbesetto1.
remix_onlyU01206310AssertthiswhenonlyrealinputisavailableattheDDC'smixerinputs.
ThisbitholdstheQportionofthesignalto0.
cic_bypassD01206210(TESTINGPURPOSES)Ifassertedthenthedatafromtherxin_aandrxin_barefeddirectlyintothecfirinputasIandQrespectively.
rxin_a(0)alsofunctionsasthesync_cfirsignalandshouldriseatthebeginningofinputdata.
double_tapD01206020Setto0fornormalmode.
Indoubletapmode,dataoutofthelastPFIRraminthemainDDC(evennumberedDDC)issenttotheadjacentsecondaryDDC(oddnumberedDDC)PFIRasinputthusforminga128-tapdelayline.
AlsodatareceivedfromthesecondaryPFIRsummersisaddedintotheMainDDC'sPFIRsumtoformtheoutput.
ThisenablesusingaPFIRoflengthupto128insteadof64asinthenormalmode.
Whenusingdoubletapmode,setdouble_tapto2forthemain(even)DDCandto1forthesecondary(odd)DDC.
ssel_cicU01200B1230SelectsthesyncsourcefortheDDCCICfilterdecimationmoment.
NoeffectforDUC.
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9DUCChannelControlsThesecontrolsareusedbytheDUCchannels.
Thesefollowtheduckeywordinthecmd5316configurationfile.
VARIABLENAMETYPEPAGEADDRESSLSBPOSITIONBITWIDTHDEFAULTDESCRIPTIONsymmetric_pfirC0100001410Whenassertedtheblock'sPFIRissymmetric.
DUConlysymmetric_cfirC0100001310Whenassertedtheblock'sCFIRissymmetric.
DUConlypmeter_integration_ducD0100020130Thisisthenumberoffoursamplesetstoaccumulateforapowermeasurement.
InCDMAmode,onesamplesetistheIandQofthesignalanddiversity.
IaandQa(signal)areeachsquaredandaccumulatedandIbandQb(diversity)aresquaredandaccumulated.
InUMTSmode,eachIandQpairaresquaredandaccumulated.
Foursamplesareequaltooneintegrationcount.
Thecountisinitiatedwhenthesyncisassertedorwhentheintervalstarttimeisreached.
Whentheintegrationcountisreached,theaccumulatedpowersaremadeavailableforMPUaccessandaninterruptisgenerated.
pmeter_sync_delay_ducD010003970Thedelayfromselectedsyncsourcetowhenthepowercalculationstarts.
pmeter_interval_ducD010003090Thestartintervaltimeristheintervaloverwhichtheintegrationisrestartedandmustbegreaterthantheintegrationcount.
TheintervalstartcounterandRMSpoweraccumulationisstartedatthesyncpulseaftertheprogrammeddelayandeverytimetheintervalcounterreachesitslimit.
Thisvalueisin64sampleunits.
pilot_gain_0D0100040160Pilotchannelgainword,alignedwithMSBoftheinputdata.
0xFFFFgeneratesafullscalecomplexpilotsignaladdedtotheusersignal.
Settingthegainto0x0000causesnopilotsignaltobeadded.
OnlyvalidforUMTS,shouldbesetto0x0000forCDMA.
pilot_gain_1D0100050160ThisvalueMUSTbesettothesamevalueaspilot_gain_0.
pilot_psc_lsbD0100060161Thelower16bitsofthe18-bitpilotXLFSRinitialvalue.
This18bwordisloadedonpilotsyncevent.
Thevalueloadedherethatcorrespondsto3gppprimaryscramblingcode(PSC)0is0x00001.
Usersmustcalculatethecorrectinitialvaluetoimplementtheother511PSCs.
pilot_psc_msbD0100071420Theupper2bitsofthe18-bitpilotXLFSRinitialvalue.
This18bwordisloadedonpilotsyncevents.
Thevalueloadedherethatcorrespondsto3gppprimaryscramblingcode(PSC)0is0x00001.
Usersmustcalculatethecorrectinitialvaluetoimplementtheother511PSCs.
pilot_diversityD0100071310Selectbetweenmainanddiversitypilotsymbolgeneration.
(0=main,1=diversity)pilot_delayD0100080160Unsigneddelayvalueinchipsfromthepilotsyncevent,from0to38399chips.
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com62gainforaU01000C0168192ThisistheunsignedgainthatismultipliedwiththeCDMAchannelAorUMTSchannelinputsignal.
Thegainmultiplyiscalculatedasgainfora/8192.
gainforbU01000D0168192ThisistheunsignedgainthatismultipliedwiththeCDMAchannelBinputsignal.
cic_auto_flush_disE0100101240DisablestheautomaticflushfeatureintheCICaccumulators.
cic_flush_testE010010840ForcesanoverflowdetectionintheCIConlyonarisingedgeofthisbit,thereforeitmustbeprogrammedto'0'andthenbackto'1'fortheedgetooccur.
cic_flush_clearE010010440Clearsanoverflowerrormanuallywhenset,againonlyonarisingedgedoesthisoccur.
serp_tran_bitsU01001B11517Numberofinputbitspersample1;for18bits,thisissetto{10001}.
serp_tran_fsdelD01001B821DelaybetweenframesyncoutputandMSBofserialdata{3,2,1,0}.
serp_tran_4pinD01001B710Selects2-pinmodewhenclearedand4-pinmodewhenset.
serp_tran_fsinvlU01001B0750Transmitserialinterfaceframesyncintervalinbitclocks.
serp_tran_clkdivU01001C041Transmitserialinterfaceclockdividerrate1;0isfullrate,and15dividestheclockby16.
Forexample,toruntheserialinterfaceat1/4thetransmitclock,setserp_tran_clkdiv(3:0)=0011.
ssel_pilotU01200B430SelectsthesyncsourcefortheDUCpilotcodegenerator.
6GC5316PinDescription6.
1TransmitSectionSignalsSIGNALNAMEBALLDESIGTYPEDESCRIPTIONtxclkK26inputTransmitclockinputtxin_0_aT23inputDUC0serialindata.
CDMAA:I/QUMTS:Itxin_1_aU25inputDUC1serialindata.
CDMAA:I/QUMTS:Itxin_0_bT24inputDUC0serialindata.
CDMAB:I/QUMTS:Qtxin_1_bU26inputDUC1serialindata.
CDMAB:I/QUMTS:Qtxin_2_aW26inputDUC2serialindata.
CDMAA:I/QUMTS:Itxin_3_aV25inputDUC3serialindata.
CDMAA:I/QUMTS:Itxin_2_bU24inputDUC2serialindata.
CDMAB:I/QUMTS:Qtxin_3_bV26inputDUC3serialindata.
CDMAB:I/QUMTS:Qtxin_4_aY26inputDUC4serialindata.
CDMAA:I/QUMTS:Itxin_5_aW25inputDUC5serialindata.
CDMAA:I/QUMTS:Itxin_4_bV24inputDUC4serialindata.
CDMAB:I/QUMTS:Qtxin_5_bU23inputDUC5serialindata.
CDMAB:I/QUMTS:Qtxin_6_aW23inputDUC6serialindata.
CDMAA:I/QUMTS:Itxin_7_aAA26inputDUC7serialindata.
CDMAA:I/QUMTS:Itxin_6_bY25inputDUC6serialindata.
CDMAB:I/QUMTS:Qtxin_7_bW24inputDUC7serialindata.
CDMAB:I/QUMTS:Qtxin_8_aY23inputDUC8serialindata.
CDMAA:I/QUMTS:IGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com63txin_9_aAB26inputDUC9serialindata.
CDMAA:I/QUMTS:Itxin_8_bAA25inputDUC8serialindata.
CDMAB:I/QUMTS:Qtxin_9_bY24inputDUC9serialindata.
CDMAB:I/QUMTS:Qtxin_10_aAA23inputDUC10serialindata.
CDMAA:I/QUMTS:Itxin_11_aAC26inputDUC11serialindata.
CDMAA:I/QUMTS:Itxin_10_bAB25inputDUC10serialindata.
CDMAB:I/QUMTS:Qtxin_11_bAA24inputDUC11serialindata.
CDMAB:I/QUMTS:Qtx_sync_out_0AB24outputTransmitserialinterfacestrobeforDUC0,1(txin_[0,1]_[a,b])tx_sync_out_1AC25outputTransmitserialinterfacestrobeforDUC2,3(txin_[2,3]_[a,b])tx_sync_out_2AD26outputTransmitserialinterfacestrobeforDUC4,5(txin_[4,5]_[a,b])tx_sync_out_3AB23outputTransmitserialinterfacestrobeforDUC6,7(txin_[6,7]_[a,b])tx_sync_out_4AC24outputTransmitserialinterfacestrobeforDUC8,9(txin_[8,9]_[a,b])tx_sync_out_5AD23outputTransmitserialinterfacestrobeforDUC10,11(txin_[10,11]_[a,b])tx_syncaK24inputTransmitsyncinputtx_syncbJ25inputTransmitsyncinputtx_synccH26inputTransmitsyncinputtx_syncdK23inputTransmitsyncinputtx_sync_outF23outputTransmitgeneralpurposeoutputsynctxclk_outE23outputTransmitoutputclocktx_i_flagD24outputTransmitoutputiflagtxout_a_17B19outputTransmitoutputbusaMSBtxout_a_16A20outputTransmitoutputbusatxout_a_15C19outputTransmitoutputbusatxout_a_14B20outputTransmitoutputbusatxout_a_13A21outputTransmitoutputbusatxout_a_12D19outputTransmitoutputbusatxout_a_11C20outputTransmitoutputbusatxout_a_10B21outputTransmitoutputbusatxout_a_9A22outputTransmitoutputbusatxout_a_8D20outputTransmitoutputbusatxout_a_7C21outputTransmitoutputbusatxout_a_6B22outputTransmitoutputbusatxout_a_5A23outputTransmitoutputbusatxout_a_4C22outputTransmitoutputbusatxout_a_3B23outputTransmitoutputbusatxout_a_2A24outputTransmitoutputbusatxout_a_1D22outputTransmitoutputbusatxout_a_0C23outputTransmitoutputbusaLSBtxout_b_17B14outputTransmitoutputbusbMSBtxout_b_16C14outputTransmitoutputbusbtxout_b_15D14outputTransmitoutputbusbtxout_b_14A15outputTransmitoutputbusbtxout_b_13B15outputTransmitoutputbusbtxout_b_12C15outputTransmitoutputbusbtxout_b_11A16outputTransmitoutputbusbtxout_b_10B16outputTransmitoutputbusbtxout_b_9A17outputTransmitoutputbusbtxout_b_8C16outputTransmitoutputbusbGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com64txout_b_7B17outputTransmitoutputbusbtxout_b_6D16outputTransmitoutputbusbtxout_b_5A18outputTransmitoutputbusbtxout_b_4C17outputTransmitoutputbusbtxout_b_3B18outputTransmitoutputbusbtxout_b_2A19outputTransmitoutputbusbtxout_b_1D17outputTransmitoutputbusbtxout_b_0C18outputTransmitoutputbusbLSBtxout_c_17C9outputTransmitoutputbuscMSBtxout_c_16D10outputTransmitoutputbusctxout_c_15A8outputTransmitoutputbusctxout_c_14B9outputTransmitoutputbusctxout_c_13C10outputTransmitoutputbusctxout_c_12A9outputTransmitoutputbusctxout_c_11D11outputTransmitoutputbusctxout_c_10B10outputTransmitoutputbusctxout_c_9C11outputTransmitoutputbusctxout_c_8A10outputTransmitoutputbusctxout_c_7B11outputTransmitoutputbusctxout_c_6A11outputTransmitoutputbusctxout_c_5C12outputTransmitoutputbusctxout_c_4B12outputTransmitoutputbusctxout_c_3A12outputTransmitoutputbusctxout_c_2D13outputTransmitoutputbusctxout_c_1C13outputTransmitoutputbusctxout_c_0B13outputTransmitoutputbuscLSBtxout_d_17C4outputTransmitoutputbusdMSBtxout_d_16D5outputTransmitoutputbusdtxout_d_15A3outputTransmitoutputbusdtxout_d_14B4outputTransmitoutputbusdtxout_d_13C5outputTransmitoutputbusdtxout_d_12A4outputTransmitoutputbusdtxout_d_11B5outputTransmitoutputbusdtxout_d_10C6outputTransmitoutputbusdtxout_d_9D7outputTransmitoutputbusdtxout_d_8A5outputTransmitoutputbusdtxout_d_7B6outputTransmitoutputbusdtxout_d_6C7outputTransmitoutputbusdtxout_d_5D8outputTransmitoutputbusdtxout_d_4A6outputTransmitoutputbusdtxout_d_3B7outputTransmitoutputbusdtxout_d_2C8outputTransmitoutputbusdtxout_d_1A7outputTransmitoutputbusdtxout_d_0B8outputTransmitoutputbusdLSBGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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2ReceiveSectionSignalsSIGNALNAMEBALLDESIGTYPEDESCRIPTIONrxclkL24inputReceiveclockinputadcclkD3inputadcinputclockrxin_a_15E4inputReceiveinputdatabusaMSBrxin_a_14C1inputReceiveinputdatabusarxin_a_13D2inputReceiveinputdatabusarxin_a_12E3inputReceiveinputdatabusarxin_a_11F4inputReceiveinputdatabusarxin_a_10D1inputReceiveinputdatabusarxin_a_9E2inputReceiveinputdatabusarxin_a_8F3inputReceiveinputdatabusarxin_a_7G4inputReceiveinputdatabusarxin_a_6E1inputReceiveinputdatabusarxin_a_5F2inputReceiveinputdatabusarxin_a_4G3inputReceiveinputdatabusarxin_a_3H4inputReceiveinputdatabusarxin_a_2F1inputReceiveinputdatabusarxin_a_1G2inputReceiveinputdatabusarxin_a_0H3inputReceiveinputdatabusaLSBrxin_b_15G1inputReceiveinputdatabusbMSBrxin_b_14H2inputReceiveinputdatabusbrxin_b_13J3inputReceiveinputdatabusbrxin_b_12K4inputReceiveinputdatabusbrxin_b_11H1inputReceiveinputdatabusbrxin_b_10J2inputReceiveinputdatabusbrxin_b_9K3inputReceiveinputdatabusbrxin_b_8J1inputReceiveinputdatabusbrxin_b_7L4inputReceiveinputdatabusbrxin_b_6K2inputReceiveinputdatabusbrxin_b_5L3inputReceiveinputdatabusbrxin_b_4K1inputReceiveinputdatabusbrxin_b_3L2inputReceiveinputdatabusbrxin_b_2M4inputReceiveinputdatabusbrxin_b_1L1inputReceiveinputdatabusbrxin_b_0M3inputReceiveinputdatabusbLSBrxin_c_15M2inputReceiveinputdatabuscMSBrxin_c_14M1inputReceiveinputdatabuscrxin_c_13N3inputReceiveinputdatabuscrxin_c_12N2inputReceiveinputdatabuscrxin_c_11P2inputReceiveinputdatabuscrxin_c_10P3inputReceiveinputdatabuscrxin_c_9P4inputReceiveinputdatabuscrxin_c_8R1inputReceiveinputdatabuscrxin_c_7R2inputReceiveinputdatabuscrxin_c_6R3inputReceiveinputdatabuscrxin_c_5T1inputReceiveinputdatabuscrxin_c_4R4inputReceiveinputdatabuscGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com66rxin_c_3T2inputReceiveinputdatabuscrxin_c_2U1inputReceiveinputdatabuscrxin_c_1T3inputReceiveinputdatabuscrxin_c_0U2inputReceiveinputdatabuscLSBrxin_d_15T4inputreceiveinputdatabusMSBrxin_d_14V1inputReceiveinputdatabusdrxin_d_13U3inputReceiveinputdatabusdrxin_d_12V2inputReceiveinputdatabusdrxin_d_11W1inputReceiveinputdatabusdrxin_d_10U4inputReceiveinputdatabusdrxin_d_9V3inputReceiveinputdatabusdrxin_d_8W2inputReceiveinputdatabusdrxin_d_7Y1inputReceiveinputdatabusdrxin_d_6W3inputReceiveinputdatabusdrxin_d_5Y2inputReceiveinputdatabusdrxin_d_4AA1inputReceiveinputdatabusdrxin_d_3W4inputReceiveinputdatabusdrxin_d_2Y3inputReceiveinputdatabusdrxin_d_1AA2inputReceiveinputdatabusdrxin_d_0AB1inputReceiveinputdatabusdLSBrx_syncaJ24inputReceivesyncinputrx_syncbH25inputReceivesyncinputrx_synccG26inputReceivesyncinputrx_syncdH24inputReceivesyncinputrx_sync_outAF7outputReceivegeneralpurposeoutputsyncrx_sync_out_0AF23outputReceiveserialinterfacestrobeforDDC0,1(rxout_[0,1]_[ad])rx_sync_out_1AE20outputReceiveserialinterfacestrobeforDDC2,3(rxout_[2,3]_[ad])rx_sync_out_2AF18outputReceiveserialinterfacestrobeforDDC4,5(rxout_[4,5]_[ad])rx_sync_out_3AF15outputReceiveserialinterfacestrobeforDDC6,7(rxout_[6,7]_[ad])rx_sync_out_4AD12outputReceiveserialinterfacestrobeforDDC8,9(rxout_[8,9]_[ad])rx_sync_out_5AE9outputReceiveserialinterfacestrobeforDDC10,11(rxout_[10,11]_[ad])rxout_0_aAF22outputDDC0serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_0_bAC20outputDDC0serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_0_cAD21outputDDC0serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_0_dAE22outputDDC0serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_1_aAD22outputDDC1serialoutdata.
CDMAA:Idata.
UMTS:Imsbrxout_1_bAE23outputDDC1serialoutdata.
CDMAB:Idata.
UMTS:Imsb1rxout_1_cAF24outputDDC1serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_1_dAC22outputDDC1serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_2_aAD18outputDDC2serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_2_bAE19outputDDC2serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_2_cAF20outputDDC2serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_2_dAD19outputDDC2serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_3_aAF21outputDDC3serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_3_bAC19outputDDC3serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_3_cAD20outputDDC3serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_3_dAE21outputDDC3serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_4_aAF17outputDDC4serialoutdata.
CDMAA:IdataUMTS:ImsbGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
ti.
com67rxout_4_bAD16outputDDC4serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_4_cAE17outputDDC4serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_4_dAC16outputDDC4serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_5_aAD17outputDDC5serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_5_bAE18outputDDC5serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_5_cAF19outputDDC5serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_5_dAC17outputDDC5serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_6_aAE13outputDDC6serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_6_bAE14outputDDC6serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_6_cAD14outputDDC6serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_6_dAC14outputDDC6serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_7_aAE15outputDDC7serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_7_bAD15outputDDC7serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_7_cAF16outputDDC7serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_7_dAE16outputDDC7serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_8_aAD11outputDDC8serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_8_bAF10outputDDC8serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_8_cAE11outputDDC8serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_8_dAF11outputDDC8serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_9_aAE12outputDDC9serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_9_bAF12outputDDC9serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_9_cAC13outputDDC9serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_9_dAD13outputDDC9serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_10_aAE8outputDDC10serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_10_bAD9outputDDC10serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_10_cAC10outputDDC10serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_10_dAF8outputDDC10serialoutdata.
CDMAB:QdataUMTS:Qmsb1rxout_11_aAD10outputDDC11serialoutdata.
CDMAA:IdataUMTS:Imsbrxout_11_bAF9outputDDC11serialoutdata.
CDMAB:IdataUMTS:Imsb1rxout_11_cAC11outputDDC11serialoutdata.
CDMAA:QdataUMTS:Qmsbrxout_11_dAE10outputDDC11serialoutdata.
CDMAB:QdataUMTS:Qmsb1GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com686.
3MicroprocessorSignalsSIGNALNAMEBALLDESIGTYPEDESCRIPTIONd0AD8input/outputMPUregisterinterfacedatabusLSBd1AE7input/outputMPUregisterinterfacedatabusd2AF6input/outputMPUregisterinterfacedatabusd3AC8input/outputMPUregisterinterfacedatabusd4AD7input/outputMPUregisterinterfacedatabusd5AE6input/outputMPUregisterinterfacedatabusd6AF5input/outputMPUregisterinterfacedatabusd7AC7input/outputMPUregisterinterfacedatabusd8AD6input/outputMPUregisterinterfacedatabusd9AE5input/outputMPUregisterinterfacedatabusd10AF4input/outputMPUregisterinterfacedatabusd11AD5input/outputMPUregisterinterfacedatabusd12AE4input/outputMPUregisterinterfacedatabusd13AF3input/outputMPUregisterinterfacedatabusd14AC5input/outputMPUregisterinterfacedatabusd15AD4input/outputMPUregisterinterfacedatabusMSBa0AB4inputMPUregisterinterfaceaddressbusLSBa1AD1inputMPUregisterinterfaceaddressbusa2AC2inputMPUregisterinterfaceaddressbusa3AB3inputMPUregisterinterfaceaddressbusa4AA4inputMPUregisterinterfaceaddressbusa5AC1inputMPUregisterinterfaceaddressbusMSBrd_nY4inputMPUregisterinterfaceread–activelowwr_nAA3inputMPUregisterinterfacewrite–activelowce_nAB2inputMPUregisterinterfacechipenable–activelowreset_nR24inputChipreset–activelowinterruptAC3outputChipinterrupt6.
4JTAGSignalsSIGNALNAMEBALLDESIGTYPEDESCRIPTIONtdiN23inputJTAGtestdataintmsM26inputJTAGtestmodeselecttrst_nM25inputJTAGtestreset(sameastrst–the"_n"isforconsistencybeingactivelow)tckM24inputJTAGtestclocktdoL26outputJTAGtestdataoutGC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com696.
5FactoryTestandNoConnectSignalsSIGNALNAMEBALLDESIGTYPENOTEtestmode0R26inputDonotconnecttestmode1P24inputDonotconnectscanenP25inputDonotconnectaflag_tstE24outputDonotconnectsync_tstD25outputDonotconnectclk_tstC26outputDonotconnectfa002_scanT26inputDonotconnectfa002_clkR23inputDonotconnectfa002_outT25outputDonotconnectzeroN25inputDonotconnectF26,G24,G25,H23,L23inputTieeachpinhighthrough100-resistorstoVPADK25,M23,L25,N24,R25,D26,E25,E26,F24,F25,G23,J26noconnectDonotconnect6.
6PowerandGroundSignalsSIGNALNAMEBALLDESIGDESCRIPTIONGNDA1,A2,A13,A14,A25,A26,B1,B3,B24,B26,C2,C25,N1,N26,P1,P26,AD2,AD25,AE1,AE24,AE3,AE26,AF1,AF2,AF13,AF14,AF25,AF26,L11,L12,L13,L14,L15,L16,M11M16,N11N16,P11P16,R11R16,T11T16GroundVCOREB2,D4,N4,AC4,AE2,B25,D23,P23,AC23,AE25,C3,J4,V4,AD3,C24,J23,V23,AD24CorepowerVPADD6,D12,D18,AC6,AC12,AC18,D9,D15,D21,AC9,AC15,AC21I/Opower6.
7PowerMonitoringSIGNALNAMEBALLDESIGDESCRIPTIONvcoremonN24Thesepinsmonitortheinternalpowerdistribution.
Theycannotcarrysignificantcurrentandshouldnotbeconnectedtonormalpowerandground.
Itisrecommendedthatthispinbebroughttoasmallprobepointforfuturemonitoring/debuggingpurposes.
gndmonR25Itisrecommendedthatthispinbebroughttoaprobepointforfuturemonitoring/debuggingpurposes.
6.
8JTAGTheJTAGstandardforboundaryscantestingisimplementedforboardtestingpurposes.
Internalscantestisnotbesupported.
FivedevicepinsarededicatedforJTAGsupport:tdi,tdo,tms,tck,andtrst_n.
TheBSDLfileisavailableontheweb.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com707Specifications7.
1AbsoluteMaximumRatingsPARAMETERSYMBOLMINMAXUNITSPadringsupplyvoltageVPAD0.
34VCoresupplyvoltageVCORE0.
31.
8VInputvoltage(undershootandovershoot)VIN0.
5VPAD+0.
5VClampcurrentforaninputoroutput2020mAStoragetemperatureTstg65140_CJunctiontemperatureTJ105_CLeadsolderingtemperature(10seconds)300_CESDclassificationClass2(Passed2.
5-kVHBM,500-VCDM,150-VMM)MoisturesensitivityClass4(4daysfloorlifeat30°C/60%H)ReflowconditionsJEDECstandard,240°CmaxCAUTION:Exceedingtheabsolutemaximumratings(minormax)maycausepermanentdamagetothepart.
Thesearestressonlyratingsandarenotintendedforoperation.
7.
2RecommendedOperatingConditionsPARAMETERMINMAXUNITSPadringsupplyvoltage,VPAD33.
6VCoresupplyvoltage,VCORE1.
51.
65VSupplyvoltagedifferenceVPAD–VCORE2VTemperatureambient,noairflow(1),TA4085°CJunctiontemperature(2),TJ105°C(1)ChipsspecificationsinTables6.
4and6.
5areproductiontestedto100°Ccasetemperature.
QAtestsareperformedat85°C.
(2)Thermalmanagementwillberequiredforfullrateoperation,seethefollowingtableandSection7.
4.
Thecircuitisdesignedforjunctiontemperaturesupto125°C.
Sustainedoperationatelevatedtemperaturesreduceslong-termreliability.
Lifetimecalculationsbasedonmaximumjunctiontemperatureof105°C.
7.
3ThermalCharacteristicsTHERMALCONDUCTIVITY388BGAUNITS3WThetajunction-to-ambient(stillair),θJA13.
5°C/WThetajunction-to-ambient(2m/sestimated),θJA2m9.
3°C/WThetajunction-to-case,θJC2.
4°C/W(3)AirflowreducesθJAandishighlyrecommended.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com717.
4PowerConsumptionThemaximumpowerconsumptionisafunctionoftheoperatingmodeofthechip.
Thecmd5316estimatesthetypicalpowersupplycurrentforthechipinaspecificconfiguration.
TheACCharacteristicstableprovidesmaximumcurrentinamaximumconfigurationusedinproductiontest.
CurrentconsumptiononthepadsupplyisprimarilyduetotheexternalloadsandfollowsCxVxF.
Internalloadsareestimatedat2pFperpin.
Dataoutputshaveatransitiondensityofgoingfromazerotoaone,onceperfourclocks,whileclockoutputstransitioneverycycle.
Theframestrobesconsumenegligiblepowerduetothelowtransitionfrequency.
Ingeneral:Ipad=ΣDataPad/4xCxFxV+ΣClockPadxCxFxVAworstcasecurrentwouldbealltransmitandreceiveportsoperatingat125MHz.
Ipad=(1+(4x18+4x2x6)/4)x(C+2pF)xFoutxVpad=31x22pFx125MHzx3.
3V=280mA.
Amoretypicalapplicationwithtwoportsactivewoulduseroughly150mA.
7.
5DCOperatingConditions(40°Cto85°Ccaseunlessotherwisenoted)PARAMETERVPAD=3Vto3.
6VUNITSPARAMETERMINTYPMAXUNITSVILVoltageinputlow(4)0.
8VVIHVoltageinputhigh(4)2VVOLVoltageoutputlow(4)(IOL=2mA)0.
5VVOHVoltageoutputhigh(4)(IOH=2mA)2.
4VPADV|IPU|Pullupcurrent(VIN=0V)(tdi,tms,trst_n,reset_n)(nominal20A)(4)535A|IPD|Pulldowncurrent(VIN=VPAD)(allotherinputsandbidirs)(nominal20A)(4)535ALeakage(VIN=VPAD)(tdi,tms,trst_n,reset_n)(4)2|IIN|Leakage(VIN=0)(allotherinputsandbidirs)(4)2A|IIN|Leakage(VIN=0orVPAD)(alloutputs)(4)2AICCQQuiescentsupplycurrent,ICORE(4)8mACINCapacitanceforinputs(5)5pFCBICapacitanceforbidirectionals(5)5pFNOTE:Voltagesaremeasuredatlowspeed.
Outputvoltagesaremeasuredwiththeindicatedcurrentload.
NOTE:Currentsaremeasuredatnominalvoltages,hightemperature(100°Cforproductiontest,85°CforQA).
(4)Eachpartistestedat100°Ccasetemperatureforthegivenspecification.
Lotsaresampletestedat40°C.
(5)Controlledbydesignandprocessandnotdirectlytested.
GC5316SLWS154AJANUARY2004REVISEDMARCH2004www.
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com727.
6ACCharacteristicsPARAMETERMINMAXUNITFCKClockfrequency(adcclk,rxclk,txclk)inselectedmodes(6)(9)125MHzFCKClockfrequency(adcclk,rxclk,txclk)unrestricted(6)80MHztADCKLtRXCKLtTXCKLClocklowperiod(belowVIL)(adcclk,rxclk,txclk)(6)3nstADCKHtRXCKHtTXCKHClockhighperiod(aboveVIH)(adcclk,rxclk,txclk)(6)3nstr,tfClockriseandfalltimes(VILtoVIH)(adcclk,rxclk,txclk)(8)2nstsu(TX)Inputsetup(txin_[011]_[ab],tx_sync[ad])beforetxclkrises(6)2.
2nstsu(RX)Inputsetup(rx_sync[ad])beforerxclkrises(6)2.
5nstsu(RXB)Inputsetup(rxin_[ad]_[015])beforerxclkrisesadc_fifobypassed(6)0.
4nstsu(AD)Inputsetup(rxin[ad]_[015])beforeadcclkrisesadc_fifoactive(6)2.
2nsth(TX)Inputhold(txin_[011]_[ab],tx_sync[ad])aftertxclkrises(6)1.
1nsth(RX)Inputhold(rx_sync[ad])afterrxclkrises(6)0.
5nsth(RXB)Inputhold(rxin[ad]_[015])afterrxclkrisesadc_fifobypassed(6)3.
5nsth(AD)Inputhold(rxin[ad]_[015])afteradcclkrisesadc_fifoactive(6)1nstd(TX)Dataoutputdelay(tx_sync_out_[05],tx_iflag,txout_[ad]_[017])aftertxclkrises(6)6.
5nstd(RX)Dataoutputdelay(rx_sync_out_[05],rxout_[011]_[ad])afterrxclkrises(6)6.
5nstOH(TX)Dataoutputhold(tx_sync_out_[05],tx_iflag,txout_[ad]_[017])aftertxclkrises(6)1.
5nstOH(RX)Dataoutputhold(rx_sync_out_[05],rxout_[011]_[ad])afterrxclkrises(6)1.
5nsFJCKJTAGclockfrequency(tck)(6)40MHztJCKLJTAGclocklowperiod(belowVIL)(tck)(6)8nstJCKHJTAGclockhighperiod(aboveVIH)(tck)(6)8nstsu(J)JTAGinput(tdiortms)setupbeforetckgoeshigh(6)2nsth(J)JTAGinput(tdiortms)holdtimeaftertckgoeshigh(6)9nstd(J)JTAGoutput(tdo)delayfromfallingedgeoftck(6)6nstsu(UPA)Microprocessoraddresssetuptofallingedgeofcontrols(6)2.
5nsth(UPA)Microprocessoraddressholdfromrisingedgeofcontrols(6)2nstsu(UPD)Microprocessordatasetuptorisingedgeofcontrolsduringwrites(6)12nsth(UPD)Microprocessordataholdfromrisingedgeofcontrolsduringwrites(6)2.
6nsthMicroprocessordataoutputholdfromrisingedgeofcontrols(read)(7)0nstd(UP)Microprocessordataoutputdelayfromfallingedgeofcontrols(read)(6)36nstUPCKLMicroprocessorcontrollowtime(6)30nstUPCKHMicroprocessorcontrolhightime(6)8.
4nsNOTE:TimingismeasuredfromtherespectiveclockatVPAD/2toinputoroutputatVPAD/2.
Outputloadingisa50-transmissionlinewhosedelayiscalibratedout.
(6)Eachpartistestedat90°Ccasetemperatureforthegivenspecification.
Lotsaresampletestedat40°C.
(7)Controlledbydesignandprocessandnotdirectlytested.
Verifiedoninitialpartevaluation.
(8)Recommendedpractice.
(9)Excludingrx_sync_out,rx_sync_out_[15],tx_sync_out,tx_sync_out_[15].
Resampleractiveoradcclk<80MHz.
PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinishMSLPeakTemp(3)GC5316IZEDACTIVEBGAZED38840Green(RoHS&noSb/Br)SNAGCULevel-3-260C-168HR(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
ti.
com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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