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CY91F467BA/466BACY91F465BB/464BBFR60CY91460BSeries,32-bitMicrocontrollerDatasheetCypressSemiconductorCorporation198ChampionCourtSanJose,CA95134-1709408-943-2600DocumentNumber:002-04608Rev.
*CRevisedJanuary24,2019CY91460Bseriesisalineofgeneral-purpose32-bitRISCmicrocontrollersdesignedforembeddedcontrolapplicationswhichrequirehigh-speedreal-timeprocessing,suchasconsumerdevicesandon-boardvehiclesystems.
ThisseriesusestheFR60CPU,whichiscompatiblewiththeFRfamilyofCPUs.
ThisseriescontainstheLIN-USARTandCANcontrollers.
FeaturesFR60CPUCore32-bitRISC,load/storearchitecture,five-stagepipeline16-bitfixed-lengthinstructions(basicinstructions)Instructionexecutionspeed:1instructionpercycleInstructionsincludingmemory-to-memorytransfer,bitmanip-ulation,andbarrelshiftinstructions:InstructionssuitableforembeddedapplicationsFunctionentry/exitinstructionsandregisterdatamulti-loadstoreinstructions:InstructionssupportingClanguageRegisterinterlockfunction:Facilitatingassembly-languagecodingBuilt-inmultiplierwithinstruction-levelsupportSigned32-bitmultiplication:5cyclesSigned16-bitmultiplication:3cyclesInterrupts(savePC/PS):6cycles(16prioritylevels)HarvardarchitectureenablingprogramaccessanddataaccesstobeperformedsimultaneouslyInstructionscompatiblewiththeFRfamilyInternalPeripheralResourcesGeneral-purposeports:Maximum108portsDMAC(DMAController)Maximumof5channelsabletooperatesimultaneously2transfersources(internalperipheral/software)ActivationsourcecanbeselectedusingsoftwareAddressingmodespecifiesfull32-bitaddresses(increment/decrement/fixed)Transfermode(demandtransfer/bursttransfer/steptransfer/blocktransfer)Transferdatasizeselectablefrom8/16/32-bitMulti-bytetransferenabled(bysoftware)DMACdescriptorinI/Oareas(200Hto240H,1000Hto1024H)A/Dconverter(successiveapproximationtype)10-bitresolution:maximum32channelsConversiontime:minimum1μsExternalinterruptinputs:maximum16channels6channelssharedwithCANRXorI2CpinsBitsearchmodule(forREALOS)Functiontosearchthefirstbitpositionof''1'',''0'',''changed''fromtheMSB(mostsignificantbit)withinonewordLIN-USART(fullduplexdoublebuffer):4or7channels,dependingonpinmultiplexingClocksynchronous/asynchronousselectableSync-breakdetectionInternaldedicatedbaudrategeneratorI2Cbusinterface(supports400kbps):2channelsMaster/slavetransmissionandreceptionArbitrationfunction,clocksynchronizationfunctionCANcontroller(C-CAN):3or6channels(dependingonthedevice)Maximumtransferspeed:1Mbps32transmission/receptionmessagebuffersSoundgenerator:1channelTonefrequency:PWMfrequencydivide-by-two(reloadvalue+1)Alarmcomparator:1channelMonitorexternalvoltageGenerateaninterruptincaseofvoltagelower/higherthanthedefinedthresholds(referencevoltage)16-bitPPGtimer:maximum16channels16-bitreloadtimer:8channels16-bitfree-runtimer:8channels(1channeleachforICUandOCU)Inputcapture:maximum8channels(operatesinconjunctionwiththefree-runtimer)Outputcompare:maximum8channels(operatesinconjunctionwiththefree-runtimer)Up/Downcounter:2channels(2*8-bitor1*16-bit)WatchdogtimerReal-timeclockLow-powerconsumptionmodes:Sleep/stopmodefunctionLowvoltagedetectioncircuitClocksupervisorMonitorsthesub-clock(32kHz)andthemainclock(4MHz),CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage2of127andswitchestoarecoveryclock(CRoscillator,etc.
)whentheoscillationsstop.
ClockmodulatorClockmonitorSub-clockcalibrationCorrectsthereal-timeclocktimerwhenoperatingwiththe32kHzorCRoscillatorMainoscillatorstabilizationtimerGeneratesaninterruptinsub-clockmodeafterthestabilizationwaittimehaselapsedonthe23-bitstabilizationwaittimecounterSub-oscillatorstabilizationtimerGeneratesaninterruptinmainclockmodeafterthestabili-zationwaittimehaselapsedonthe15-bitstabilizationwaittimecounterPackageandTechnologyPackage:QFP-144CMOS180nmtechnologyPowersupplyrange3Vto5V(1.
8Vinternallogicprovidedbyastep-downvoltageconverter)Operatingtemperaturerange:between40°Cand+125°CCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage3of127Contents1.
ProductLineup.
42.
PinAssignment.
72.
1CY91F467BA/466BAwithMD_3=172.
2CY91F467BA/466BAwithMD_3=082.
3CY91F465BB/464BBwithMD_3=192.
4CY91F465BB/464BBwithMD_3=0103.
PinDescription.
113.
1CY91F467BA/466BAANDCY91F465BB/464BBwithMD_3=1113.
2CY91F467BA/466BAANDCY91F465BB/464BBwithMD_3=0164.
I/OCircuitTypes.
215.
HandlingDevices.
275.
1PreventingLatch-up.
275.
2HandlingofunusedInputPins.
275.
3PowerSupplyPins.
275.
4CrystalOscillatorCircuit.
275.
5NotesonUsingExternalClock275.
6ModePins(MD_x)285.
7NotesonOperatinginPLLClockMode.
285.
8Pull-upControl286.
NotesonDebugger.
296.
1ExecutionoftheRETICommand296.
2BreakFunction.
296.
3OperandBreak.
296.
4NotesonPSRegister297.
BlockDiagram.
307.
1CY91F467BA/466BAwithMD_3=1307.
2CY91F467BA/466BAwithMD_3=0317.
3CY91F465BB/464BBwithMD_3=1327.
4CY91F465BB/464BBwithMD_3=0338.
CPUandControlUnit348.
1Features.
348.
2InternalArchitecture.
348.
3ProgrammingModel.
358.
4Registers.
369.
EmbeddedProgram/DataMemory(Flash)399.
1FlashFeatures.
399.
2OperationModes399.
3FlashAccessinCPUMode409.
4ParallelFlashProgrammingMode.
479.
5PoweronSequenceinParallelProgrammingMode.
.
.
.
.
509.
6FlashSecurity5010.
MemorySpace5311.
MemoryMaps.
5411.
1CY91F467BA,CY91F466BA.
5411.
2CY91F465BB,CY91F464BB.
5512.
I/OMap.
5612.
1CY91F467BA/466BA,CY91F465BB/464BB5612.
2FlashMemoryandExternalBusArea8313.
InterruptVectorTable.
8714.
RecommendedSettings.
9114.
1PLLandClockGearSettings.
9114.
2ClockModulatorSettings.
9215.
ElectricalCharacteristics.
9715.
1AbsoluteMaximumRatings9715.
2RecommendedOperatingConditions.
10015.
3DCCharacteristics.
10115.
4A/DConverterCharacteristics10415.
5AlarmComparatorCharacteristics.
10815.
6FlashMemoryProgram/EraseCharacteristics10915.
7ACCharacteristics11016.
OrderingInformation.
12217.
PackageDimension.
12318.
RevisionHistory.
12419.
MainChangesinThisEdition.
125DocumentHistory126CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage4of1271.
ProductLineupFeatureCY91V460CY91F465BB/464BBCY91F467BA/466BAMax.
corefrequency(CLKB)80MHz100MHz96MHzMax.
resourcefrequency(CLKP)40MHz50MHz48MHzMax.
externalbusfrequency(CLKT)40MHz50MHz48MHzMax.
CANfrequency(CLKCAN)20MHz50MHz48MHzTechnology0.
35μm0.
18μm0.
18μmWatchdogyesyesyesWatchdog(RCosc.
based)yes(disengageable)yesyesBitSearchyesyesyesResetinput(INITX)yesyesyesHardwarestandbyinput(HSTX)yesnonoClockModulatoryesyesyesClockMonitoryesyesyesLowPowerModeyesyesyesDMA5ch5ch5chMMU/MPUMPU(16ch)[1]MPU(8ch)[1]MPU(8ch)[1]FlashmemoryEmulationSRAM32bitreaddataCY91F465BB:544KByteCY91F464BB:416KByteCY91F467BA:1088KByteCY91F466BA:832KByteSatelliteFlashmemory---FlashProtection-yesyesD-RAM64KByte24KByte24KByteID-RAM64KByte16KByte16KByteFlash-Cache(Instructioncache)16KByte8KByte8KByteBoot-ROM/BI-ROM4KBytefixed4KByte4KByteRTC1ch1ch1chFreeRunningTimer8ch8ch[2]8ch[2]ICU8chMD_3=0:8chMD_3=1:4ch[3]MD_3=0:8chMD_3=1:4ch[3]OCU8chMD_3=0:8chMD_3=1:4ch[4]MD_3=0:8chMD_3=1:4ch[4]ReloadTimer8ch8ch[5]8ch[5]PPG16-bit16chMD_3=0:16chMD_3=1:8ch[6]MD_3=0:16chMD_3=1:8ch[6]PFM16-bit1ch--SoundGenerator1ch1ch1chUp/DownCounter(8/16bit)4ch(8-bit)/2ch(16-bit)MD_3=0:2ch(8-bit)/1ch(16bit)MD_3=1:NA[7]MD_3=0:2ch(8-bit)/1ch(16bit)MD_3=1:NA[7]C_CAN6ch(128msg)3ch(32msg)6ch(32msg)CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage5of1271.
MPUchannelsuseEDSUbreakpointregisters(sharedoperationbetweenMPUandEDSU).
2.
FreeRunningTimer:MD3=0:CH1and0cannotselectexternalclock(bit7ofTCCS1,0)MD3=1:CH3,2,1,and0cannotselectexternalclock(bit7ofTCCS3,2,1,0)FeatureCY91V460CY91F465BB/464BBCY91F467BA/466BALIN-USART4ch+4chFIFO+8chMD_3=0:3ch+4chFIFO[8]MD_3=1:4chFIFOMD_3=0:3ch+4chFIFO[8]MD_3=1:4chFIFOI2C(400K)4ch2ch2chFRexternalbusyes(32bitaddr,32bitdata)MD_3=0:noMD_3=1:yes(22bitaddr,16bitdata)MD_3=0:noMD_3=1:yes(22bitaddr,16bitdata)ExternalInterrupts16chMD_3=0:16chMD_3=1:12ch[9]MD_3=0:16chMD_3=1:12ch[9]NMIInterrupts1ch1ch1chSMC6ch--LCDcontroller(40x4)1ch--ADC(10-bit)32chMD_3=0:32chMD_3=1:16chMD_3=0:32chMD_3=1:16chAlarmComparator2ch1ch1chSupplySupervisor(lowvoltagedetection)yesyesyesClockSupervisoryesyesyesMainclockoscillator4MHz4MHz4MHzSubclockoscillator32kHz32kHz32kHzRCoscillator100kHz100kHz/2MHz100kHz/2MHzPLLx20x25x25DSU4yesnonoEDSUyes(32BP)[1]yes(16BP)[1]yes(16BP)[1]Supplyvoltage3V/5V3V/5V3V/5VRegulatoryesyesyesPowerconsumptionn.
a.
16busadapterDMAC5channelsClockmodulatorClockmonitorMONCLKInterruptcontrollerINT0toINT3,INT8totoINT15Externalinterrupt12channelsClocksupervisorClockcontrolPPGtimer8channelsReloadtimer8channelsFree-runtimer8channelsInputcapture4channelsOutputcompare4channelsAlarmcomparator1channelLIN-USART4channels2channelsIC2RealtimeclockA/Dconverter16channelsSoundgenerator1channelRDXWRX0toWRX1CSX0toCSX1A0toA21D16toD31ExternalbusinterfaceSYSCLKRDYCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage31of1277.
2CY91F467BA/466BAwithMD_3=0AIN0toAIN1BIN0toBIN1ZIN0toZIN1TTG0/8toTTG7/15PPG0toPPG15TIN0toTIN7TOT0toTOT7CK2toCK7ICU0toICU7OCU0toOCU7ALARM_0SDA0toSDA1SCL0toSCL1AN0toAN31ATGXSGASG0SIN2toSIN7,SIN0SOT2toSOT7,SOT0SCK2toSCK7RX0toRX5TX0toTX5R-bus16I-bus32D-bus32FR60CPUcoreFlash-Cache8KbytesFlashmemory1088Kbytes(CY91F467BA)832Kbytes(CY91F466BA)ID-RAM16KbytesBusconverterD-RAM24KbytesBitsearchCAN6channels3216busadapterDMAC5channelsClockmodulatorClockmonitorMONCLKInterruptcontrollerINT0toINT15Externalinterrupt16channelsClocksupervisorClockcontrolPPGtimer16channelsReloadtimer8channelsFree-runtimer8channelsInputcapture8channelsOutputcompare8channelsUp/downcounter2channelsAlarmcomparator1channelLIN-USART7channels2channelsIC2RealtimeclockA/Dconverter32channelsSoundgenerator1channelCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage32of1277.
3CY91F465BB/464BBwithMD_3=1TTG0/8toTTG3/11PPG8toPPG15TIN0toTIN3TOT0toTOT3CK4toCK7ICU0toICU3OCU0toOCU3ALARM_0SDA0toSDA1SCL0toSCL1AN0toAN15ATGXSGASG0SIN4toSIN7SOT4toSOT7SCK4toSCK7RX0toRX2TX0toTX2R-bus16I-bus32D-bus32FR60CPUcoreFlash-Cache8KbytesFlashmemory544Kbytes(CY91F465BB)416Kbytes(CY91F464BB)ID-RAM16KbytesBusconverterD-RAM24KbytesBitsearchCAN3channels3216busadapterDMAC5channelsClockmodulatorClockmonitorMONCLKInterruptcontrollerINT0toINT3,INT8totoINT15Externalinterrupt12channelsClocksupervisorClockcontrolPPGtimer8channelsReloadtimer8channelsFree-runtimer8channelsInputcapture4channelsOutputcompare4channelsAlarmcomparator1channelLIN-USART4channels2channelsIC2RealtimeclockA/Dconverter16channelsSoundgenerator1channelRDXWRX0toWRX1CSX0toCSX1A0toA21D16toD31ExternalbusinterfaceSYSCLKRDYCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage33of1277.
4CY91F465BB/464BBwithMD_3=0AIN0toAIN1BIN0toBIN1ZIN0toZIN1TTG0/8toTTG7/15PPG0toPPG15TIN0toTIN7TOT0toTOT7CK2toCK7ICU0toICU7OCU0toOCU7ALARM_0SDA0toSDA1SCL0toSCL1AN0toAN31ATGXSGASG0SIN2toSIN7,SIN0SOT2toSOT7,SOT0SCK2toSCK7RX0TX0R-bus16I-bus32D-bus32FR60CPUcoreFlash-Cache8KbytesFlashmemory416Kbytes(CY91F464HB)ID-RAM16KbytesBusconverterD-RAM16KbytesBitsearchCAN1channel3216busadapterDMAC5channelsClockmodulatorClockmonitorMONCLKInterruptcontrollerINT0toINT15Externalinterrupt16channelsClocksupervisorClockcontrolPPGtimer16channelsReloadtimer8channelsFree-runtimer8channelsInputcapture8channelsOutputcompare8channelsUp/downcounter2channelsAlarmcomparator1channelLIN-USART7channels2channelsIC2RealtimeclockA/Dconverter32channelsSoundgenerator1channelCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage34of1278.
CPUandControlUnitTheFRfamilyCPUisahighperformancecorethatisdesignedbasedontheRISCarchitecturewithadvancedinstructionsforembeddedapplications.
8.
1FeaturesAdoptionofRISCarchitectureBasicinstruction:1instructionpercycleGeneral-purposeregisters:32-bit*16registers4GbyteslinearmemoryspaceMultiplierinstalled32-bit*32-bitmultiplication:5cycles16-bit*16-bitmultiplication:3cyclesEnhancedinterruptprocessingfunctionQuickresponsespeed(6cycles)Multiple-interruptsupportLevelmaskfunction(16levels)EnhancedinstructionsforI/OoperationMemory-to-memorytransferinstructionBitprocessinginstructionBasicinstructionwordlength:16bitsLow-powerconsumptionSleepmode/stopmode8.
2InternalArchitectureTheFRfamilyCPUusestheHarvardarchitectureinwhichtheinstructionbusanddatabusareindependentofeachother.
A32-bit16-bitbufferisconnectedtothe32-bitbus(D-bus)toprovideaninterfacebetweentheCPUandperipheralresources.
AHarvardPrincetonbusconverterisconnectedtoboththeI-busandD-bustoprovideaninterfacebetweentheCPUandthebuscontroller.
CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage35of1278.
3ProgrammingModel8.
3.
1BasicProgrammingModelILMSCRCCRFPSPAC.
.
.
.
.
.
.
.
.
.
.
.
XXXXXXXXH00000000HXXXXXXXXH.
.
.
.
.
.
.
.
.
R0R1R12R13R14R15PCRSRPTBRSSPUSPMDLMDH.
.
.
.
.
.
32bitsInitialvalueGeneral-purposeregistersProgramcounterProgramstatusTablebaseregisterReturnpointerSystemstackpointerUserstackpointerMultiply÷registersCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage36of1278.
4Registers8.
4.
1General-PurposeRegisterRegistersR0toR15aregeneral-purposeregisters.
Theseregisterscanbeusedasaccumulatorsforcomputationoperationsandaspointersformemoryaccess.
Ofthe16registers,enhancedcommandsareprovidedforthefollowingregisterstoenabletheiruseforparticularapplications.
R13:VirtualaccumulatorR14:FramepointerR15:StackpointerInitialvaluesatresetareundefinedforR0toR14.
ThevalueforR15is00000000H(SSPvalue).
8.
4.
2PS(ProgramStatus)Thisregisterholdstheprogramstatus,andisdividedintothreeparts,ILM,SCR,andCCR.
Allundefinedbits(-)inthediagramarereservedbits.
Thereadvaluesarealways"0".
Writeaccesstothesebitsisinvalid.
FPSPAC.
.
.
.
.
.
.
.
.
.
.
.
XXXXXXXXH00000000HXXXXXXXXH.
.
.
.
.
.
.
.
.
R0R1R12R13R14R15.
.
.
.
.
.
32bitsInitialvalueBitposition→bit20bit0bit7bit8bit10bit16ILMSCRCCRbit31CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage37of1278.
4.
3CCR(ConditionCodeRegister)SV:SupervisorflagS:StackflagI:InterruptenableflagN:NegativeenableflagZ:ZeroflagV:OverflowflagC:Carryflag8.
4.
4SCR(SystemConditionRegister)Flagforstepdivision(D1,D0)Thisflagstoresinterimdataduringexecutionofstepdivision.
Steptracetrapflag(T)Thisflagindicateswhetherthesteptracetrapisenabledordisabled.
Thesteptracetrapfunctionisusedbyemulators.
Whenanemulatorisinuse,itcannotbeusedinexecutionofuserprograms.
8.
4.
5ILM(InterruptLevelMaskRegister)Thisregisterstoresinterruptlevelmaskvalues,andthevaluesstoredinILM4toILM0areusedforlevelmasking.
Theregisterisinitializedtovalue"01111B"atreset.
8.
4.
6PC(ProgramCounter)Theprogramcounterindicatestheaddressoftheinstructionthatisbeingexecuted.
Theinitialvalueatresetisundefined.
-000XXXXBbit0bit1bit2bit3bit4bit5bit6bit7CVZNISSVInitialvaluebit10bit8bit9D1D0TXX0BInitialvaluebit18bit16bit17ILM2ILM1ILM001111BILM3ILM4bit20bit19Initialvaluebit0bit31XXXXXXXXHInitialvalueCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage38of1278.
4.
7TBR(TableBaseRegister)ThetablebaseregisterstoresthestartingaddressofthevectortableusedinEITprocessing.
Theinitialvalueatresetis000FFC00H.
8.
4.
8RP(ReturnPointer)Thereturnpointerstorestheaddressforreturnfromsubroutines.
DuringexecutionofaCALLinstruction,thePCvalueistransferredtothisRPregister.
DuringexecutionofaRETinstruction,thecontentsoftheRPregisteraretransferredtoPC.
Theinitialvalueatresetisundefined.
8.
4.
9USP(UserStackPointer)Theuserstackpointer,whentheSflagis"1",thisregisterfunctionsastheR15register.
TheUSPregistercanalsobeexplicitlyspecified.
Theinitialvalueatresetisundefined.
ThisregistercannotbeusedwithRETIinstructions.
8.
4.
10Multiply&DivideRegistersTheseregistersareformultiplicationanddivision,andareeach32bitsinlength.
Theinitialvalueatresetisundefined.
bit0bit31000FFC00HInitialvaluebit0bit31XXXXXXXXHInitialvaluebit0bit31XXXXXXXXHInitialvaluebit0MDLbit31MDHCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage39of1279.
EmbeddedProgram/DataMemory(Flash)9.
1FlashFeaturesCY91F467BA:1088Kbytes(16*64Kbytes+8*8Kbytes=8.
5Mbits)CY91F466BA:832Kbytes(12*64Kbytes+8*8Kbytes=6.
5Mbits)CY91F465BB:544Kbytes(8*64Kbytes+4*8Kbytes=4.
25Mbits)CY91F464BB:416Kbytes(6*64Kbytes+4*8Kbytes=3.
25Mbits)Programmablewaitstatesforread/writeaccessFlashandBootsecuritywithsecurityvectorat0x0014:8000-0x0014:800FBootsecurityBasicspecification:SameasMBM29LV400TC(exceptsizeandpartofsectorconfiguration)9.
2OperationModes9.
2.
164-bitCPUMode(AvailableonCY91F467BA/466BAOnly):CPUreadsandexecutesprogramsinword(32-bit)lengthunits.
Flashwritingisnotpossible.
ActualFlashMemoryaccessisperformedind-word(64-bit)lengthunits.
9.
2.
232-bitCPUMode:CPUreadsandexecutesprogramsinword(32-bit)lengthunits.
ActualFlashMemoryaccessisperformedinword(32-bit)lengthunits.
9.
2.
316-bitCPUMode:CPUreadsandwritesinhalf-word(16-bit)lengthunits.
ProgramexecutionfromtheFlashisnotpossible.
ActualFlashMemoryaccessisperformedinword(16-bit)lengthunits.
9.
2.
4FlashMemoryMode(ExternalAccesstoFlashMemoryEnabled)Note:TheoperationmodeoftheflashmemorycanbeselectedusingaBoot-ROMfunction.
Thefunctionstartaddressis0xBF60.
TheparameterdescriptionisgivenintheHardwareManualinchapter54.
6"FlashAccessModeSwitching".
CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage40of1279.
3FlashAccessinCPUMode9.
3.
1FlashConfiguration9.
3.
1.
1FlashMemoryMapCY91F467BAROMS1ROMS0addr+6ROMS5ROMS4ROMS6ROMS7ROMS3ROMS2dat[31:16]dat[15:0]dat[31:0]dat[31:0]dat[31:16]dat[15:0]16bitread/write32bitread/writedat[63:0]64bitreadaddr+7addr+2SA0(8KB)SA16(64KB)SA10(64KB)SA21(64KB)SA19(64KB)Address0014:FFFFh0014:C000h0014:BFFFh0014:8000hSA7(8KB)SA5(8KB)SA3(8KB)SA1(8KB)SA23(64KB)SA6(8KB)SA4(8KB)SA2(8KB)SA22(64KB)SA20(64KB)0013:FFFFh0012:0000h0011:FFFFh0010:0000hSA18(64KB)0014:7FFFh0014:4000h0014:3FFFh0014:0000h000F:FFFFh000E:0000hSA15(64KB)000D:FFFFh000C:0000h000B:FFFFh000A:0000haddr+5SA11(64KB)SA8(64KB)SA9(64KB)addr+0addr+1addr+3addr+40009:FFFFh0008:0000h0007:FFFFh0006:0000h0005:FFFFh0004:0000hSA17(64KB)SA14(64KB)SA12(64KB)SA13(64KB)CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage41of1279.
3.
1.
2FlashMemoryMapCY91F466BAROMS7addr+3addr+40009:FFFFh0008:0000h0007:FFFFh0006:0000h0005:FFFFh0004:0000hSA12(64KB)SA13(64KB)0014:7FFFh0014:4000h0014:3FFFh0014:0000h000F:FFFFh000E:0000hSA15(64KB)000D:FFFFh000C:0000h000B:FFFFh000A:0000hSA17(64KB)SA14(64KB)SA22(64KB)SA20(64KB)0013:FFFFh0012:0000h0011:FFFFh0010:0000hSA18(64KB)SA7(8KB)SA5(8KB)SA3(8KB)SA1(8KB)SA23(64KB)SA6(8KB)SA4(8KB)SA2(8KB)Addr0014:FFFFh0014:C000h0014:BFFFh0014:8000haddr+7addr+2SA0(8KB)SA16(64KB)SA10(64KB)SA21(64KB)SA19(64KB)dat[15:0]16bitread/write32bitread64bitreadROMS2dat[31:16]dat[15:0]dat[31:0]dat[31:0]dat[31:16]ROMS1ROMS0addr+6ROMS5ROMS4ROMS6ROMS3addr+5SA11(64KB)SA8(64KB)SA9(64KB)addr+0addr+1LegendMemorynotavailableinthisareaMemoryavailableinthisareadat[63:0]CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage42of1279.
3.
1.
3FlashMemoryMapCY91F465BBROMS7LegendMemorynotavailableinthisareaaddr+3addr+40009:FFFFh0008:0000h0007:FFFFh0006:0000h0005:FFFFh0004:0000hSA12(64KB)SA13(64KB)0014:7FFFh0014:4000h0014:3FFFh0014:0000h000F:FFFFh000E:0000hSA15(64KB)000D:FFFFh000C:0000h000B:FFFFh000A:0000hSA17(64KB)SA14(64KB)SA22(64KB)SA20(64KB)0013:FFFFh0012:0000h0011:FFFFh0010:0000hSA18(64KB)SA7(8KB)SA5(8KB)SA3(8KB)SA1(8KB)SA23(64KB)SA6(8KB)SA4(8KB)SA2(8KB)Addr0014:FFFFh0014:C000h0014:BFFFh0014:8000haddr+7addr+2SA0(8KB)SA16(64KB)SA10(64KB)SA21(64KB)SA19(64KB)dat[15:0]16bitread/write32bitreadROMS2dat[31:16]dat[15:0]dat[31:0]dat[31:0]dat[31:16]ROMS1ROMS0addr+6ROMS5ROMS4ROMS6ROMS3Memoryavailableinthisareaaddr+5SA11(64KB)SA8(64KB)SA9(64KB)addr+0addr+1CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage43of1279.
3.
1.
4FlashMemoryMapCY91F464BBROMS7addr+3addr+40009:FFFFh0008:0000h0007:FFFFh0006:0000h0005:FFFFh0004:0000hSA12(64KB)SA13(64KB)0014:7FFFh0014:4000h0014:3FFFh0014:0000hSA15(64KB)000D:FFFFh000C:0000h000B:FFFFh000A:0000hSA17(64KB)SA14(64KB)SA22(64KB)SA20(64KB)0013:FFFFh0012:0000h0011:FFFFh0010:0000hSA18(64KB)000F:FFFFh000E:0000hSA7(8KB)SA5(8KB)SA3(8KB)SA1(8KB)SA23(64KB)SA6(8KB)SA4(8KB)SA2(8KB)Address0014:FFFFh0014:C000h0014:BFFFh0014:8000haddr+7addr+2SA0(8KB)SA16(64KB)SA10(64KB)SA21(64KB)SA19(64KB)dat[15:0]16bitread/write32bitreadLegendMemorynotavailableinthisareaROMS2dat[31:16]dat[15:0]dat[31:0]dat[31:0]dat[31:16]ROMS1ROMS0addr+6ROMS5ROMS4ROMS6ROMS3Memoryavailableinthisareaaddr+5SA11(64KB)SA8(64KB)SA9(64KB)addr+0addr+1CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage44of1279.
3.
2FlashAccessTimingSettingsinCPUModeThefollowingtableslistallsettingsforagivenmaximumCoreFrequency(throughthesettingofCLKBormaximumclockmodulation)forFlashreadandwriteaccess.
9.
3.
2.
1FlashReadTimingSettings(SynchronousRead)9.
3.
2.
2FlashWriteTimingSettings(SynchronousWrite)CoreClock(CLKB)ATDALEHEQWEXHWTCRemarkto24MHz000-1to48MHz001-2to96MHz113-4to100MHz113-4notavailableonCY91F467-BA/CY91F466BACoreClock(CLKB)ATDALEHEQWEXHWTCRemarkto16MHz0--03to32MHz0--04to48MHz0--05to64MHz1--06to96MHz1--07to100MHz1--07notavailableonCY91F467-BA/CY91F466BACY91460BSeriesDocumentNumber:002-04608Rev.
*CPage45of1279.
3.
3AddressMappingfromCPUtoParallelProgrammingModeThefollowingtablesshowthecalculationfromCPUaddressestoflashmacroaddresseswhichareusedinparallelprogramming.
9.
3.
3.
1AddressMappingCY91F467BANote:FAresultiswithout20:0000hoffsetforparallelFlashprogramming.
SetoffsetbykeepingFA[21]=1asdescribedinsection"ParallelFlashprogrammingmode".
9.
3.
3.
2AddressMappingCY91F466BANote:FAresultiswithout20:0000hoffsetforparallelFlashprogramming.
SetoffsetbykeepingFA[21]=1asdescribedinsection"ParallelFlashprogrammingmode".
CPUAddress(addr)ConditionFlashSectorsFA(FlashAddress)Calculation14:0000hto14:FFFFhaddr[2]==0SA0,SA2,SA4,SA6(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2-(addr/2)%4+addr%4-05:0000h14:0000hto14:FFFFhaddr[2]==1SA1,SA3,SA5,SA7(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2+00:2000h-(addr/2)%4+addr%4-05:0000h04:0000hto13:FFFFhaddr[2]==0SA8,SA10,SA12,SA14,SA16,SA18,SA20,SA22(64Kbyte)FA:=addr-addr%02:0000+(addr%02:0000h)/2-(addr/2)%4+addr%4+0C:0000h04:0000hto13:FFFFhaddr[2]==1SA9,SA11,SA13,SA15,SA17,SA19,SA21,SA23(64Kbyte)FA:=addr-addr%02:0000h+(addr%02:0000h)/2+01:0000h-(addr/2)%4+addr%4+0C:0000hCPUAddress(addr)ConditionFlashSectorsFA(FlashAddress)Calculation14:0000hto14:FFFFhaddr[2]==0SA0,SA2,SA4,SA6(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2-(addr/2)%4+addr%4-05:0000h14:0000hto14:FFFFhaddr[2]==1SA1,SA3,SA5,SA7(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2+00:2000h-(ad-dr/2)%4+addr%4-05:0000h04:0000hto0F:FFFFhaddr[2]==0SA8,SA10,SA12,SA14,SA16,SA18(64Kbyte)FA:=addr-addr%02:0000+(addr%02:0000h)/2-(addr/2)%4+ad-dr%4+0C:0000h04:0000hto0F:FFFFhaddr[2]==1SA9,SA11,SA13,SA15,SA17,SA19(64Kbyte)FA:=addr-addr%02:0000h+(addr%02:0000h)/2+01:0000h-(ad-dr/2)%4+addr%4+0C:0000hCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage46of1279.
3.
3.
3AddressMappingCY91F465BBNote:FAresultiswithout20:0000hoffsetforparallelFlashprogramming.
SetoffsetbykeepingFA[21]=1asdescribedinsection"ParallelFlashprogrammingmode".
9.
3.
3.
4AddressMappingCY91F464BBNote:FAresultiswithout20:0000hoffsetforparallelFlashprogramming.
SetoffsetbykeepingFA[21]=1asdescribedinsection"ParallelFlashprogrammingmode".
CPUAddress(addr)ConditionFlashSectorsFA(FlashAddress)Calculation14:8000hto14:FFFFhaddr[2]==0SA4,SA6(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2-(addr/2)%4+addr%4-0D:0000h14:8000hto14:FFFFhaddr[2]==1SA5,SA7(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2+00:2000h-(addr/2)%4+addr%4-0D:0000h08:0000hto0F:FFFFhaddr[2]==0SA12,SA14,SA16,SA18(64Kbyte)FA:=addr-addr%02:0000+(addr%02:0000h)/2-(addr/2)%4+addr%408:0000hto0F:FFFFhaddr[2]==1SA13,SA15,SA17,SA19(64Kbyte)FA:=addr-addr%02:0000h+(addr%02:0000h)/2+01:0000h-(addr/2)%4+addr%4CPUAddress(addr)ConditionFlashSectorsFA(FlashAddress)Calculation14:8000hto14:FFFFhaddr[2]==0SA4,SA6(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2-(addr/2)%4+addr%4-0D:0000h14:8000hto14:FFFFhaddr[2]==1SA5,SA7(8Kbyte)FA:=addr-addr%00:4000h+(addr%00:4000h)/2+00:2000h-(addr/2)%4+addr%4-0D:0000h0A:0000hto0F:FFFFhaddr[2]==0SA14,SA16,SA18(64Kbyte)FA:=addr-addr%02:0000+(addr%02:0000h)/2-(addr/2)%4+addr%40A:0000hto0F:FFFFhaddr[2]==1SA15,SA17,SA19(64Kbyte)FA:=addr-addr%02:0000h+(addr%02:0000h)/2+01:0000h-(addr/2)%4+addr%4CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage47of1279.
4ParallelFlashProgrammingMode9.
4.
1FlashConfigurationinParallelFlashProgrammingMode9.
4.
1.
1ParallelFlashProgrammingMode(MD[2:0]=111):CY91F467BACY91F466BARemark:AlwayskeepFA[0]=0andFA[21]=116bitwritemodeDQ[15:0]DQ[15:0]SA20(64KB)SA19(64KB)SA18(64KB)FA[21:0]003E:FFFFh003E:0000h003D:FFFFh003D:0000h003F:FFFFh003F:0000hSA23(64KB)SA22(64KB)SA21(64KB)003C:FFFFh003C:0000h003B:FFFFh003B:0000h003A:FFFFh003A:0000h0039:FFFFh0039:0000hSA17(64KB)0038:FFFFh0038:0000h0037:FFFFh0037:0000hSA16(64KB)SA15(64KB)0036:FFFFh0036:0000h0035:FFFFh0035:0000hSA14(64KB)SA13(64KB)0034:FFFFh0034:0000h0033:FFFFh0033:0000hSA12(64KB)SA11(64KB)0032:FFFFh0032:0000h0031:FFFFh0031:0000hSA10(64KB)SA9(64KB)0030:FFFFh0030:0000h002F:FFFFh002F:E000hSA8(64KB)SA7(8KB)002F:7FFFh002F:6000hSA4(8KB)SA3(8KB)002F:DFFFh002F:C000h002F:BFFFh002F:A000hSA6(8KB)SA5(8KB)002F:1FFFh002F:0000hSA0(8KB)FA[1:0]=00FA[1:0]=10002F:5FFFh002F:4000h002F:3FFFh002F:2000hSA2(8KB)SA1(8KB)002F:9FFFh002F:8000h16bitwritemodeDQ[15:0]DQ[15:0]SA20(64KB)SA19(64KB)SA18(64KB)FA[21:0]SA23(64KB)SA22(64KB)SA21(64KB)003B:FFFFh003B:0000h003A:FFFFh003A:0000h0039:FFFFh0039:0000hSA17(64KB)0038:FFFFh0038:0000h0037:FFFFh0037:0000hSA16(64KB)SA15(64KB)0036:FFFFh0036:0000h0035:FFFFh0035:0000hSA14(64KB)SA13(64KB)0034:FFFFh0034:0000h0033:FFFFh0033:0000hSA12(64KB)SA11(64KB)0032:FFFFh0032:0000h0031:FFFFh0031:0000hSA10(64KB)SA9(64KB)0030:FFFFh0030:0000h002F:FFFFh002F:E000hSA8(64KB)SA7(8KB)002F:7FFFh002F:6000hSA4(8KB)SA3(8KB)002F:DFFFh002F:C000h002F:BFFFh002F:A000hSA6(8KB)SA5(8KB)002F:1FFFh002F:0000hSA0(8KB)FA[1:0]=00FA[1:0]=10002F:5FFFh002F:4000h002F:3FFFh002F:2000hSA2(8KB)SA1(8KB)002F:9FFFh002F:8000hCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage48of127CY91F465BBCY91F464BBRemark:AlwayskeepFA[0]=0andFA[21]=1SA0(8KB)FA[1:0]=00FA[1:0]=10SA2(8KB)SA1(8KB)0017:9FFFh0017:8000hSA4(8KB)SA3(8KB)0017:DFFFh0017:C000h0017:BFFFh0017:A000hSA6(8KB)SA5(8KB)0017:FFFFh0017:E000hSA8(64KB)SA7(8KB)SA10(64KB)SA9(64KB)0018:FFFFh0018:0000hSA12(64KB)SA11(64KB)001A:FFFFh001A:0000h0019:FFFFh0019:0000hSA14(64KB)SA13(64KB)001C:FFFFh001C:0000h001B:FFFFh001B:0000hSA16(64KB)SA15(64KB)001E:FFFFh001E:0000h001D:FFFFh001D:0000hSA17(64KB)001F:FFFFh001F:0000hSA19(64KB)SA18(64KB)DQ[15:0]DQ[15:0]Remark:AlwayskeepFA[0]=0andFA[20]=116bitwritemodeLegendMemoryavailableinthisareaMemorynotavailableinthisareaFA[20:0]FA[20:0]SA0(8KB)FA[1:0]=00FA[1:0]=10SA2(8KB)SA1(8KB)0017:9FFFh0017:8000hSA4(8KB)SA3(8KB)0017:DFFFh0017:C000h0017:BFFFh0017:A000hSA6(8KB)SA5(8KB)0017:FFFFh0017:E000hSA8(64KB)SA7(8KB)SA10(64KB)SA9(64KB)SA12(64KB)SA11(64KB)001A:FFFFh001A:0000hSA14(64KB)SA13(64KB)001C:FFFFh001C:0000h001B:FFFFh001B:0000hSA16(64KB)SA15(64KB)001E:FFFFh001E:0000h001D:FFFFh001D:0000hSA17(64KB)001F:FFFFh001F:0000hSA19(64KB)SA18(64KB)DQ[15:0]DQ[15:0]Remark:AlwayskeepFA[0]=0andFA[20]=116bitwritemodeLegendMemoryavailableinthisareaMemorynotavailableinthisareaCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage49of1279.
4.
2PinConnectionsinParallelProgrammingModeResettingaftersettingtheMD[2:0]pinsto[111]willhaltCPUfunctioning.
Atthistime,theFlashmemory'sinterfacecircuitenablesdirectcontroloftheFlashmemoryunitfromexternalpinsbydirectlylinkingsomeofthesignalstoGP-Ports.
Pleaseseetablebelowforsignalmapping.
Inthismode,theFlashmemoryappearstotheexternalpinsasastand-aloneunit.
Thismodeisgenerallysetwhenwriting/erasingusingtheparallelFlashprogrammer.
Inthismode,alloperationsofthe8.
5MbitsFlashmemory'sAutoAlgorithmsareavailable.
Table1.
CorrespondencebetweenMBM29LV400TCandFlashMemoryControlSignalsMBM29LV400TCExternalpinsFR-CPUModeCY91F467BA/466BA/F465BB/F464BBExternalPinsCommentFlashMemoryModeNormalFunctionPinNumber-INITX-INITX84RESET-FRSTXGP16_670--MD2MD276Setto'1'--MD1MD175Setto'1'--MD0MD074Setto'1'RY/BYFMCS:RDYbitRY/BYXGP18_2100BYTEInternallyfixedto'H'BYTEXGP16_468WEInternalcontrolsignal+controlviainterfacecircuitWEXGP16_771OEOEXGP07_73CECEXGP07_62-ATDINGP18_6103Setto'0'-EQINGP18_5102Setto'0'-TESTXGP16_569Setto'1'-RDYIGP18_4101Setto'0'A-1InternaladdressbusFA0GP05_517Setto'0'A0toA3FA1toFA4GP19_0toGP19_2,GP19_492to95A4toA7FA5toFA8GP19_5toGP19_6,GP18_0toGP18_196to99A8toA11FA9toFA12GP06_0toGP06_34to7A12toA15FA13toFA16GP06_4toGP06_78to11A16toA18FA17toFA19GP05_0toGP05_212to14A19FA20GP05_315Seenote[1]1.
A19isusedasaddressbitonCY91F467BA/F466BA.
ForCY91F465BB/F464BB,setthispinto'1'.
-FA21GP05_416Seenote[2]2.
ForCY91F467BA/F466BA,setthispinto'1'.
ForCY91F465BB/F464BB,thispincanbeleftopen.
DQ0toDQ7InternaldatabusDQ0toDQ7GP00_0toGP00_728to35DQ8toDQ15DQ8toDQ15GP01_0toGP01_720to27CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage50of1279.
5PoweronSequenceinParallelProgrammingModeTheflashmemorycanbeaccessedinprogrammingmodeafteracertainwaittime,whichisneededforSecurityVectorfetch:MinimumwaittimeafterVDD5/VDD5Rpoweron:2.
76msMinimumwaittimeafterINITXrising:1.
0ms9.
6FlashSecurity9.
6.
1VectorAddressesTwoFlashSecurityVectors(FSV1,FSV2)arelocatedparalleltotheBootSecurityVectors(BSV1,BSV2)controllingtheprotectionfunctionsoftheFlashSecurityModule:FSV1:0x14:8000BSV1:0x14:8004FSV2:0x14:8008BSV2:0x14:800C9.
6.
2SecurityVectorFSV1ThesettingoftheFlashSecurityVectorFSV1isresponsibleforthereadandwriteprotectionmodesandtheindividualwriteprotectionofthe8KBytessectors.
9.
6.
2.
1FSV1(bit31tobit16)ThesettingoftheFlashSecurityVectorFSV1bits[31:16]isresponsibleforthereadandwriteprotectionmodes.
Table2.
ExplanationofthebitsintheFlashSecurityVectorFSV1[31:16]FSV1[31:19]FSV1[18]WriteProtectionLevelFSV1[17]WriteProtectionFSV1[16]ReadProtectionFlashSecurityModesetallto'0'setto'0'setto'0'setto'1'ReadProtection(alldevicemodes,exceptINTVECmodeMD[2:0]="000")setallto'0'setto'0'setto'1'setto'0'WriteProtection(alldevicemodes,withoutexception)setallto'0'setto'0'setto'1'setto'1'ReadProtection(alldevicemodes,exceptINTVECmodeMD[2:0]="000")andWriteProtection(alldevicemodes)setallto'0'setto'1'setto'0'setto'1'ReadProtection(alldevicemodes,exceptINTVECmodeMD[2:0]="000")setallto'0'setto'1'setto'1'setto'0'WriteProtection(alldevicemodes,exceptINTVECmodeMD[2:0]="000")setallto'0'setto'1'setto'1'setto'1'ReadProtection(alldevicemodes,exceptINTVECmodeMD[2:0]="000")andWriteProtection(alldevicemodesexceptINTVECmodeMD[2:0]="000")CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage51of1279.
6.
2.
2FSV1(bit15tobit0)CY91F467BA/466BAThesettingoftheFlashSecurityVectorFSV1bits[15:0]isresponsiblefortheindividualwriteprotectionofthe8KBytessectors.
ItisonlyevaluatedifwriteprotectionbitFSV1[17]isset.
Table3.
ExplanationoftheBitsintheFlashSecurityVectorFSV1[15:0]Note:ItismandatorytoalwayssetthesectorwheretheFlashSecurityVectorsFSV1andFSV2arelocatedtowriteprotected(heresectorSA4).
OtherwiseitispossibletooverwritetheSecurityVectortoasettingwhereitispossibletoeitherreadouttheFlashcontentormanipulatedatabywriting.
Seesection"FlashaccessinCPUmode"foranoverviewaboutthesectororganisationoftheFlashMemory.
9.
6.
2.
3FSV1(bit15tobit0)CY91F465BB/464BBThesettingoftheFlashSecurityVectorFSV1bits[15:0]isresponsiblefortheindividualwriteprotectionofthe8KBytessectors.
ItisonlyevaluatedifwriteprotectionbitFSV1[17]isset.
Table4.
ExplanationofthebitsintheFlashSecurityVectorFSV1[15:0]Note:ItismandatorytoalwayssetthesectorwheretheFlashSecurityVectorsFSV1andFSV2arelocatedtowriteprotected(heresectorSA4).
OtherwiseitispossibletooverwritetheSecurityVectortoasettingwhereitispossibletoeitherreadouttheFlashcontentormanipulatedatabywriting.
Seesection"FlashaccessinCPUmode"foranoverviewaboutthesectororganisationoftheFlashMemory.
FSV1bitSectorEnableWriteProtectionDisableWriteProtectionCommentFSV1[0]SA0setto"0"setto"1"FSV1[1]SA1setto"0"setto"1"FSV1[2]SA2setto"0"setto"1"FSV1[3]SA3setto"0"setto"1"FSV1[4]SA4setto"0"Writeprotectionismanda-tory!
FSV1[5]SA5setto"0"setto"1"FSV1[6]SA6setto"0"setto"1"FSV1[7]SA7setto"0"setto"1"FSV1[15:8]notavailableFSV1bitSectorEnableWriteProtectionDisableWriteProtectionCommentFSV1[3:0]notavailableFSV1[4]SA4setto"0"—Writeprotectionismanda-tory!
FSV1[5]SA5setto"0"setto"1"FSV1[6]SA6setto"0"setto"1"FSV1[7]SA7setto"0"setto"1"FSV1[15:8]notavailableCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage52of1279.
6.
3SecurityVectorFSV2CY91F467BA/466BAThesettingoftheFlashSecurityVectorFSV2bits[31:0]isresponsiblefortheindividualwriteprotectionofthe64KBytesectors.
ItisonlyevaluatedifwriteprotectionbitFSV1[17]isset.
Table5.
ExplanationoftheBitsintheFlashSecurityVectorFSV2[31:0]Note:Seesection"FlashaccessinCPUmode"foranoverviewaboutthesectororganisationoftheFlashMemory.
9.
6.
4SecurityVectorFSV2CY91F465BB/464BBThesettingoftheFlashSecurityVectorFSV2bits[31:0]isresponsiblefortheindividualwriteprotectionofthe64KBytesectors.
ItisonlyevaluatedifwriteprotectionbitFSV1[17]isset.
Table6.
ExplanationoftheBitsintheFlashSecurityVectorFSV2[31:0]Note:Seesection"FlashaccessinCPUmode"foranoverviewaboutthesectororganisationoftheFlashMemory.
FSV2bitSectorEnableWriteProtectionDisableWriteProtectionCommentFSV2[0]SA8setto"0"setto"1"FSV2[1]SA9setto"0"setto"1"FSV2[2]SA10setto"0"setto"1"FSV2[3]SA11setto"0"setto"1"FSV2[4]SA12setto"0"setto"1"FSV2[5]SA13setto"0"setto"1"FSV2[6]SA14setto"0"setto"1"FSV2[7]SA15setto"0"setto"1"FSV2[8]SA16setto"0"setto"1"FSV2[9]SA17setto"0"setto"1"FSV2[10]SA18setto"0"setto"1"FSV2[11]SA19setto"0"setto"1"FSV2[12]SA20(CY91F467BA)setto"0"setto"1"FSV2[13]SA21(CY91F467BA)setto"0"setto"1"FSV2[14]SA22(CY91F467BA)setto"0"setto"1"FSV2[15]SA23(CY91F467BA)setto"0"setto"1"FSV2[31:16]setto"0"setto"1"notavailableFSV2bitSectorEnableWriteProtectionDisableWriteProtectionCommentFSV2[3:0]notavailableFSV2[4]SA12(CY91F465BB)setto"0"setto"1"FSV2[5]SA13(CY91F465BB)setto"0"setto"1"FSV2[6]SA14setto"0"setto"1"FSV2[7]SA15setto"0"setto"1"FSV2[8]SA16setto"0"setto"1"FSV2[9]SA17setto"0"setto"1"FSV2[10]SA18setto"0"setto"1"FSV2[11]SA19setto"0"setto"1"FSV2[31:12]notavailableCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage53of12710.
MemorySpaceTheFRfamilyhas4Gbytesoflogicaladdressspace(232addresses)availabletotheCPUbylinearaccess.
DirectaddressingareaThefollowingaddressspaceareaisusedforI/O.
Thisareaiscalleddirectaddressingarea,andtheaddressofanoperandcanbespecifieddirectlyinaninstruction.
Thesizeofdirectlyaddressableareadependsonthelengthofthedatabeingaccessedasshownbelow.
Bytedataaccess:000Hto0FFHHalfwordaccess:000Hto1FFHWorddataaccess:000Hto3FFHCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage54of12711.
MemoryMaps11.
1CY91F467BA,CY91F466BACY91F467BACY91F466BA00000000H00000400HI/O(directaddressingarea)I/O00002000H00004000HFlash-Cache(8KBytes)00001000HDMA00006000H00007000HFlashmemorycontrol00008000H0000B000HBootROM(4Kbytes)0000C000HCAN0000D000H0002A000HD-RAM(0wait,24Kbytes)00030000HID-RAM(16Kbytes)00034000H00040000HFlashmemory(1088Kbytes)00150000H00180000HExternalbusarea00500000HExternaldatabusFFFFFFFFHNote:Accessprohibitedareas00000000H00000400HI/O(directaddressingarea)I/O00002000H00004000HFlash-Cache(8KBytes)00001000HDMA00006000H00007000HFlashmemorycontrol00008000H0000B000HBootROM(4Kbytes)0000C000HCAN0000D000H0002A000HD-RAM(0wait,24Kbytes)00030000HID-RAM(16Kbytes)00034000H00040000HFlashmemory(768Kbytes)00150000H00180000HExternalbusarea00500000HExternaldatabusFFFFFFFFHNote:Accessprohibitedareas00140000HFlashmemory(64Kbytes)00100000HExternalbusarea00080000HCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage55of12711.
2CY91F465BB,CY91F464BBCY91F465BBCY91F464BB00000000H00000400HI/O(directaddressingarea)I/O00002000H00004000HFlash-Cache(8KBytes)00001000HDMA00006000H00007000HFlashmemorycontrol00008000H0000B000HBootROM(4Kbytes)0000C000HCAN0000D000H0002A000HD-RAM(0wait,24Kbytes)00030000HID-RAM(16Kbytes)00034000H00040000HFlashmemory(512Kbytes)00150000H00180000HExternalbusarea00500000HExternaldatabusFFFFFFFFHNote:Accessprohibitedareas00148000HFlashmemory(32Kbytes)00100000HExternalbusarea00080000HExternalbusarea00000000H00000400HI/O(directaddressingarea)I/O00002000H00004000HFlash-Cache(8KBytes)00001000HDMA00006000H00007000HFlashmemorycontrol00008000H0000B000HBootROM(4Kbytes)0000C000HCAN0000D000H0002A000HD-RAM(0wait,24Kbytes)00030000HID-RAM(16Kbytes)00034000H00040000HFlashmemory(384Kbytes)00150000H00180000HExternalbusarea00500000HExternaldatabusFFFFFFFFHNote:Accessprohibitedareas00148000HFlashmemory(32Kbytes)00100000HExternalbusarea00080000HExternalbusarea000A0000HCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage56of12712.
I/OMap12.
1CY91F467BA/466BA,CY91F465BB/464BBNote:Initialvaluesofregisterbitsarerepresentedasfollows:"1":Initialvalue"1""0":Initialvalue"0""X":Initialvalue"undefined""-":NophysicalregisteratthislocationAccessisbarredwithanundefineddataaccessattribute.
AddressRegisterBlock+0+1+2+3000000HPDR0[R/W]XXXXXXXXPDR1[R/W]XXXXXXXXPDR2[R/W]XXXXXXXXPDR3[R/W]XXXXXXXXT-unitportdataregisterRead/writeattributeRegisterinitialvalueafterresetRegistername(column1registerataddress4n,column2registerataddress4n+1.
.
.
)Leftmostregisteraddress(forwordaccess,theregisterincolumn1becomestheMSBsideofthedata.
)CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage57of127AddressRegisterBlock+0+1+2+3000000HPDR00[R/W]XXXXXXXXPDR01[R/W]XXXXXXXXReservedReservedR-busPortDataRegister000004HReservedPDR05[R/W]--XXXXXXPDR06[R/W]XXXXXXXXPDR07[R/W]XXXXXXXX000008HPDR08[R/W]X--X---XPDR09[R/W]XXPDR10[R/W]XReserved00000CHReservedReservedPDR14[R/W]XXXXXXXXPDR15[R/W]XXXXXXXX000010HPDR16[R/W]XXXXXXXXPDR17[R/W]XXXXXXXXPDR18[R/W]-XXX-XXXPDR19[R/W]-XXX-XXX000014HPDR20[R/W]-XXX-XXXPDR21[R/W]XXPDR22[R/W]XXXXXXXXPDR23[R/W]XXXXXXXX000018HPDR24[R/W]XXXXXXXXReservedPDR26[R/W]XXXXXXXXPDR27[R/W]XXXXXXXX00001CHPDR28[R/W]XXXXXXXXPDR29[R/W]XXXXXXXXReservedReserved000020Hto00002CHReserved000030HEIRR0[R/W]CY91F467BA:00000000:MD3=011110000:MD3=1CY91F465BB:XXXXXXXXENIR0[R/W]00000000ELVR0[R/W]0000000000000000Externalinterrupt(INT0toINT7)000034HEIRR1[R/W]CY91F467BA:00000000CY91F465BB:XXXXXXXXENIR1[R/W]00000000ELVR1[R/W]0000000000000000Externalinterrupt(INT8toINT15)000038HDICR[R/W]0HRCL[R/W]0--11111RBSYNCDelayinterrupt00003CHReservedReserved000040HSCR00[R/W,W]00000000SMR00[R/W,W]00000000SSR00[R/W,R]00001000RDR00/TDR00[R/W]00000000LIN-USART0000044HESCR00[R/W]00000X00ECCR00[R/W,R,W]-00000XXReserved000048H00004CHReservedReserved000050HSCR02[R/W,W]00000000SMR02[R/W,W]00000000SSR02[R/W,R]00001000RDR02/TDR02[R/W]00000000LIN-USART2000054HESCR02[R/W]00000X00ECCR02[R/W,R,W]-00000XXReservedCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage58of127000058HSCR03[R/W,W]00000000SMR03[R/W,W]00000000SSR03[R/W,R]00001000RDR03/TDR03[R/W]00000000LIN-USART300005CHESCR03[R/W]00000X00ECCR03[R/W,R,W]-00000XXReserved000060HSCR04[R/W,W]00000000SMR04[R/W,W]00000000SSR04[R/W,R]00001000RDR04/TDR04[R/W]00000000LIN-USART4withFIFO000064HESCR04[R/W]00000X00ECCR04[R/W,R,W]-00000XXFSR04[R]---00000FCR04[R/W]0001-000000068HSCR05[R/W,W]00000000SMR05[R/W,W]00000000SSR05[R/W,R]00001000RDR05/TDR05[R/W]00000000LIN-USART5withFIFO00006CHESCR05[R/W]00000X00ECCR05[R/W,R,W]-00000XXFSR05[R]---00000FCR05[R/W]0001-000000070HSCR06[R/W,W]00000000SMR06[R/W,W]00000000SSR06[R/W,R]00001000RDR06/TDR06[R/W]00000000LIN-USART6withFIFO000074HESCR06[R/W]00000X00ECCR06[R/W,R,W]-00000XXFSR06[R]---00000FCR06[R/W]0001-000000078HSCR07[R/W,W]00000000SMR07[R/W,W]00000000SSR07[R/W,R]00001000RDR07/TDR07[R/W]00000000LIN-USART7withFIFO00007CHESCR07[R/W]00000X00ECCR07[R/W,R,W]-00000XXFSR07[R]---00000FCR07[R/W]0001-000000080HBGR100[R/W]00000000BGR000[R/W]00000000ReservedReservedBaudrateGeneratorLIN-USART0to7000084HBGR102[R/W]00000000BGR002[R/W]00000000BGR103[R/W]00000000BGR003[R/W]00000000000088HBGR104[R/W]00000000BGR004[R/W]00000000BGR105[R/W]00000000BGR005[R/W]0000000000008CHBGR106[R/W]00000000BGR006[R/W]00000000BGR107[R/W]00000000BGR007[R/W]00000000000090Hto0000CCHReservedReserved0000D0HIBCR0[R/W]00000000IBSR0[R]00000000ITBAH0[R/W]00ITBAL0[R/W]00000000I2C00000D4HITMKH0[R/W]00----11ITMKL0[R/W]11111111ISMK0[R/W]01111111ISBA0[R/W]-00000000000D8HReservedIDAR0[R/W]00000000ICCR0[R/W]-0011111Reserved0000DCHIBCR1[R/W]00000000IBSR1[R]00000000ITBAH1[R/W]00ITBAL1[R/W]00000000I2C10000E0HITMKH1[R/W]00----11ITMKL1[R/W]11111111ISMK1[R/W]01111111ISBA1[R/W]-00000000000E4HReservedIDAR1[R/W]00000000ICCR1[R/W]-0011111ReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage59of1270000E8Hto0000FCHReservedReserved000100HGCN10[R/W]0011001000010000ReservedGCN20[R/W]----0000PPGControl0to3000104HGCN11[R/W]0011001000010000ReservedGCN21[R/W]----0000PPGControl4to7000108HGCN12[R/W]0011001000010000ReservedGCN22[R/W]----0000PPGControl8to11000110HPTMR00[R]1111111111111111PCSR00[W]XXXXXXXXXXXXXXXXPPG0000114HPDUT00[W]XXXXXXXXXXXXXXXXPCNH00[R/W]0000000-PCNL00[R/W]000000-0000118HPTMR01[R]1111111111111111PCSR01[W]XXXXXXXXXXXXXXXXPPG100011CHPDUT01[W]XXXXXXXXXXXXXXXXPCNH01[R/W]0000000-PCNL01[R/W]000000-0000120HPTMR02[R]1111111111111111PCSR02[W]XXXXXXXXXXXXXXXXPPG2000124HPDUT02[W]XXXXXXXXXXXXXXXXPCNH02[R/W]0000000-PCNL02[R/W]000000-0000128HPTMR03[R]1111111111111111PCSR03[W]XXXXXXXXXXXXXXXXPPG300012CHPDUT03[W]XXXXXXXXXXXXXXXXPCNH03[R/W]0000000-PCNL03[R/W]000000-0000130HPTMR04[R]1111111111111111PCSR04[W]XXXXXXXXXXXXXXXXPPG4000134HPDUT04[W]XXXXXXXXXXXXXXXXPCNH04[R/W]0000000-PCNL04[R/W]000000-0000138HPTMR05[R]1111111111111111PCSR05[W]XXXXXXXXXXXXXXXXPPG500013CHPDUT05[W]XXXXXXXXXXXXXXXXPCNH05[R/W]0000000-PCNL05[R/W]000000-0000140HPTMR06[R]1111111111111111PCSR06[W]XXXXXXXXXXXXXXXXPPG6000144HPDUT06[W]XXXXXXXXXXXXXXXXPCNH06[R/W]0000000-PCNL06[R/W]000000-0000148HPTMR07[R]1111111111111111PCSR07[W]XXXXXXXXXXXXXXXXPPG700014CHPDUT07[W]XXXXXXXXXXXXXXXXPCNH07[R/W]0000000-PCNL07[R/W]000000-0000150HPTMR08[R]1111111111111111PCSR08[W]XXXXXXXXXXXXXXXXPPG8000154HPDUT08[W]XXXXXXXXXXXXXXXXPCNH08[R/W]0000000-PCNL08[R/W]000000-0AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage60of127000158HPTMR09[R]1111111111111111PCSR09[W]XXXXXXXXXXXXXXXXPPG900015CHPDUT09[W]XXXXXXXXXXXXXXXXPCNH09[R/W]0000000-PCNL09[R/W]000000-0000160HPTMR10[R]1111111111111111PCSR10[W]XXXXXXXXXXXXXXXXPPG10000164HPDUT10[W]XXXXXXXXXXXXXXXXPCNH10[R/W]0000000-PCNL10[R/W]000000-0000168HPTMR11[R]1111111111111111PCSR11[W]XXXXXXXXXXXXXXXXPPG1100016CHPDUT11[W]XXXXXXXXXXXXXXXXPCNH11[R/W]0000000-PCNL11[R/W]000000-0000170Hto00017CHReservedReserved000180HReservedICS01[R/W]00000000ReservedICS23[R/W]00000000InputCapture0to3000184HIPCP0[R]XXXXXXXXXXXXXXXXIPCP1[R]XXXXXXXXXXXXXXXX000188HIPCP2[R]XXXXXXXXXXXXXXXXIPCP3[R]XXXXXXXXXXXXXXXX00018CHOCS01[R/W]---0--000000--00OCS23[R/W]---0--000000--00OutputCompare0to3000190HOCCP0[R/W]XXXXXXXXXXXXXXXXOCCP1[R/W]XXXXXXXXXXXXXXXX000194HOCCP2[R/W]XXXXXXXXXXXXXXXXOCCP3[R/W]XXXXXXXXXXXXXXXX000198HSGCRH[R/W]0000--00SGCRL[R/W]--0--000SGFR[R/W,R]XXXXXXXXXXXXXXXXSoundGenerator00019CHSGAR[R/W]00000000ReservedSGTR[R/W]XXXXXXXXSGDR[R/W]XXXXXXXX0001A0HADERH[R/W]0000000000000000ADERL[R/W]0000000000000000A/DConverter0001A4ADCS1[R/W]00000000ADCS0[R/W]00000000ADCR1[R]000000XXADCR0[R]XXXXXXXX0001A8HADCT1[R/W]00010000ADCT0[R/W]00101100ADSCH[R/W]---00000ADECH[R/W]---000000001ACHReservedACSR0[R/W]-11XXX00ReservedReservedAlarmComparator0to10001B0HTMRLR0[W]XXXXXXXXXXXXXXXXTMR0[R]XXXXXXXXXXXXXXXXReloadTimer0(PPG0,PPG1)0001B4HReservedTMCSRH0[R/W]---00000TMCSRL0[R/W]0-0000000001B8HTMRLR1[W]XXXXXXXXXXXXXXXXTMR1[R]XXXXXXXXXXXXXXXXReloadTimer1(PPG2,PPG3)0001BCHReservedTMCSRH1[R/W]---00000TMCSRL1[R/W]0-000000AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage61of1270001C0HTMRLR2[W]XXXXXXXXXXXXXXXXTMR2[R]XXXXXXXXXXXXXXXXReloadTimer2(PPG4,PPG5)0001C4HReservedTMCSRH2[R/W]---00000TMCSRL2[R/W]0-0000000001C8HTMRLR3[W]XXXXXXXXXXXXXXXXTMR3[R]XXXXXXXXXXXXXXXXReloadTimer3(PPG6,PPG7)0001CCHReservedTMCSRH3[R/W]---00000TMCSRL3[R/W]0-0000000001D0HTMRLR4[W]XXXXXXXXXXXXXXXXTMR4[R]XXXXXXXXXXXXXXXXReloadTimer4(PPG8,PPG9)0001D4HReservedTMCSRH4[R/W]---00000TMCSRL4[R/W]0-0000000001D8HTMRLR5[W]XXXXXXXXXXXXXXXXTMR5[R]XXXXXXXXXXXXXXXXReloadTimer5(PPG10,PPG11)0001DCHReservedTMCSRH5[R/W]---00000TMCSRL5[R/W]0-0000000001E0HTMRLR6[W]XXXXXXXXXXXXXXXXTMR6[R]XXXXXXXXXXXXXXXXReloadTimer6(PPG12,PPG13)0001E4HReservedTMCSRH6[R/W]---00000TMCSRL6[R/W]0-0000000001E8HTMRLR7[W]XXXXXXXXXXXXXXXXTMR7[R]XXXXXXXXXXXXXXXXReloadTimer7(PPG14,PPG15)(A/DConverter)0001ECHReservedTMCSRH7[R/W]---00000TMCSRL7[R/W]0-0000000001F0HTCDT0[R/W]XXXXXXXXXXXXXXXXReservedTCCS0[R/W]00000000FreeRunningTimer0(ICU0,ICU1)0001F4HTCDT1[R/W]XXXXXXXXXXXXXXXXReservedTCCS1[R/W]00000000FreeRunningTimer1(ICU2,ICU3)0001F8HTCDT2[R/W]XXXXXXXXXXXXXXXXReservedTCCS2[R/W]00000000FreeRunningTimer2(OCU0,OCU1)0001FCHTCDT3[R/W]XXXXXXXXXXXXXXXXReservedTCCS3[R/W]00000000FreeRunningTimer3(OCU2,OCU3)AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage62of127000200HDMACA0[R/W]000000000000XXXXXXXXXXXXXXXXXXXXDMAC000204HDMACB0[R/W]0000000000000000XXXXXXXXXXXXXXXX000208HDMACA1[R/W]000000000000XXXXXXXXXXXXXXXXXXXX00020CHDMACB1[R/W]0000000000000000XXXXXXXXXXXXXXXX000210HDMACA2[R/W]000000000000XXXXXXXXXXXXXXXXXXXX000214HDMACB2[R/W]0000000000000000XXXXXXXXXXXXXXXX000218HDMACA3[R/W]000000000000XXXXXXXXXXXXXXXXXXXX00021CHDMACB3[R/W]0000000000000000XXXXXXXXXXXXXXXX000220HDMACA4[R/W]000000000000XXXXXXXXXXXXXXXXXXXXDMAC000224HDMACB4[R/W]0000000000000000XXXXXXXXXXXXXXXX000228Hto00023CHReserved000240HDMACR[R/W]00--0000Reserved000244Hto0002CCHReservedReserved0002D0HReservedICS045[R/W]00000000ReservedICS67[R/W]00000000InputCapture4to70002D4HIPCP4[R]XXXXXXXXXXXXXXXXIPCP5[R]XXXXXXXXXXXXXXXX0002D8HIPCP6[R]XXXXXXXXXXXXXXXXIPCP7[R]XXXXXXXXXXXXXXXX0002DCHOCS45[R/W]---0--000000--00OCS67[R/W]---0--000000--00OutputCompare4to70002E0HOCCP4[R/W]XXXXXXXXXXXXXXXXOCCP5[R/W]XXXXXXXXXXXXXXXX0002E4HOCCP6[R/W]XXXXXXXXXXXXXXXXOCCP7[R/W]XXXXXXXXXXXXXXXX0002E8Hto0002ECHReservedReserved0002F0HTCDT4[R/W]XXXXXXXXXXXXXXXXReservedTCCS4[R/W]00000000FreeRunningTimer4(ICU4,ICU5)0002F4HTCDT5[R/W]XXXXXXXXXXXXXXXXReservedTCCS5[R/W]00000000FreeRunningTimer5(ICU6,ICU7)0002F8HTCDT6[R/W]XXXXXXXXXXXXXXXXReservedTCCS6[R/W]00000000FreeRunningTimer6(OCU4,OCU5)0002FCHTCDT7[R/W]XXXXXXXXXXXXXXXXReservedTCCS7[R/W]00000000FreeRunningTimer7(OCU6,OCU7)AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage63of127000300HUDRC1[W]00000000UDRC0[W]00000000UDCR1[R]00000000UDCR0[R]00000000Up/DownCounter0to1000304HUDCCH0[R/W]00000000UDCCL0[R/W]00001000ReservedUDCS0[R/W]00000000000308HUDCCH1[R/W]00000000UDCCL1[R/W]00001000ReservedUDCS1[R/W]0000000000030CHto00031CHReservedReserved000320HGCN13[R/W]0011001000010000ReservedGCN23[R/W]----0000PPGControl12to15000324Hto00032CHReservedReserved000330HPTMR12[R]1111111111111111PCSR12[W]XXXXXXXXXXXXXXXXPPG12000334HPDUT12[W]XXXXXXXXXXXXXXXXPCNH12[R/W]0000000-PCNL12[R/W]000000-0000338HPTMR13[R]1111111111111111PCSR13[W]XXXXXXXXXXXXXXXXPPG1300033CHPDUT13[W]XXXXXXXXXXXXXXXXPCNH13[R/W]0000000-PCNL13[R/W]000000-0000340HPTMR14[R]1111111111111111PCSR14[W]XXXXXXXXXXXXXXXXPPG14000344HPDUT14[W]XXXXXXXXXXXXXXXXPCNH14[R/W]0000000-PCNL14[R/W]000000-0000348HPTMR15[R]1111111111111111PCSR15[W]XXXXXXXXXXXXXXXXPPG1500034CHPDUT15[W]XXXXXXXXXXXXXXXXPCNH15[R/W]0000000-PCNL15[R/W]000000-0000350Hto00038CHReservedReserved000390HROMS[R]1111111100000000(CY91F467BA/466BA)1111111101000011(CY91F465BB/464BB)ReservedROMSelectRegister000394Hto0003ECHReservedReserved0003F0HBSD0[W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXBitSearchModule0003F4HBSD1[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0003F8HBSDC[W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0003FCHBSRR[R]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000400Hto00043CHReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage64of127000440HICR00[R/W]---11111ICR01[R/W]---11111ICR02[R/W]---11111ICR03[R/W]---11111InterruptController000444HICR04[R/W]---11111ICR05[R/W]---11111ICR06[R/W]---11111ICR07[R/W]---11111000448HICR08[R/W]---11111ICR09[R/W]---11111ICR10[R/W]---11111ICR11[R/W]---1111100044CHICR12[R/W]---11111ICR13[R/W]---11111ICR14[R/W]---11111ICR15[R/W]---11111000450HICR16[R/W]---11111ICR17[R/W]---11111ICR18[R/W]---11111ICR19[R/W]---11111000454HICR20[R/W]---11111ICR21[R/W]---11111ICR22[R/W]---11111ICR23[R/W]---11111000458HICR24[R/W]---11111ICR25[R/W]---11111ICR26[R/W]---11111ICR27[R/W]---1111100045CHICR28[R/W]---11111ICR29[R/W]---11111ICR30[R/W]---11111ICR31[R/W]---11111000460HICR32[R/W]---11111ICR33[R/W]---11111ICR34[R/W]---11111ICR35[R/W]---11111000464HICR36[R/W]---11111ICR37[R/W]---11111ICR38[R/W]---11111ICR39[R/W]---11111000468HICR40[R/W]---11111ICR41[R/W]---11111ICR42[R/W]---11111ICR43[R/W]---1111100046CHICR44[R/W]---11111ICR45[R/W]---11111ICR46[R/W]---11111ICR47[R/W]---11111000470HICR48[R/W]---11111ICR49[R/W]---11111ICR50[R/W]---11111ICR51[R/W]---11111000474HICR52[R/W]---11111ICR53[R/W]---11111ICR54[R/W]---11111ICR55[R/W]---11111000478HICR56[R/W]---11111ICR57[R/W]---11111ICR58[R/W]---11111ICR59[R/W]---1111100047CHICR60[R/W]---11111ICR61[R/W]---11111ICR62[R/W]---11111ICR63[R/W]---11111InterruptController000480HRSRR[R/W]10000000STCR[R/W]00110011TBCR[R/W]00XXXX00CTBR[W]XXXXXXXXClockControl000484HCLKR[R/W]----0000WPR[W]XXXXXXXXDIVR0[R/W]00000011DIVR1[R/W]00000000000488HReservedReserved00048CHPLLDIVM[R/W]----0000PLLDIVN[R/W]--000000PLLDIVG[R/W]----0000PLLMULG[R/W]00000000PLLInterface000490HPLLCTRL[R/W]----0000Reserved000494HOSCC1[R/W]010OSCS1[R/W]00001111OSCC2[R/W]010OSCS2[R/W]00001111Main/SubOscillatorControl(Reserved)000498HPORTEN[R/W]00ReservedPortInputEnableControlAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage65of1270004A0HReservedWTCER[R/W]00WTCR[R/W]00000000000-00-0RealTimeClock(WatchTimer)0004A4HReservedWTBR[R/W]---XXXXXXXXXXXXXXXXXXXXX0004A8HWTHR[R/W]---00000WTMR[R/W]--000000WTSR[R/W]--000000Reserved0004ACHCSVTR[R/W]---00010CSVCR[R/W]-011100CSCFG[R/W]0X000000CMCFG[R/W]00000000Clock-Supervisor/Selector/Monitor0004B0HCUCR[R/W]0--00CUTD[R/W]1000000000000000CalibrationofSubClock0004B4HCUTR1[R]00000000CUTR2[R]00000000000000000004B8HCMPR[R/W]--00001011111101ReservedCMCR[R/W]-001--00ClockModulator0004BCHCMT1[R/W]000000001---0000CMT2[R/W]--000000--0000000004C0HCANPRE[R/W]0---0000CANCKD[R/W]--000000ReservedCANClockControl0004C4HLVSEL[R/W]00000111LVDET[R/W]00000-00HWWDE[R/W]00HWWD[R/W,W]00011000LowVoltageDetection/HardwareWatchdog0004C8HOSCRH[R/W]000--001OSCRL[R/W]000WPCRH[R/W]000--001WPCRL[R/W]00Main-/Sub-OscillationSta-bilisationTimer0004CCHOSCCR[R/W]00ReservedREGSEL[R/W]--000110REGCTR[R/W]---0--00Main-OscillationStandbyControl/Main/SubRegulatorControl0004D0Hto00063CHReservedReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage66of127000640HASR0[R/W]0000000000000000ACR0[R/W]1111**0000000000[2]ExternalBusUnit000644HASR1[R/W]XXXXXXXXXXXXXXXXACR1[R/W]XXXXXXXXXXXXXXXX000648HASR2[R/W]XXXXXXXXXXXXXXXXACR2[R/W]XXXXXXXXXXXXXXXX00064CHASR3[R/W]XXXXXXXXXXXXXXXXACR3[R/W]XXXXXXXXXXXXXXXX000650HASR4[R/W]XXXXXXXXXXXXXXXXACR4[R/W]XXXXXXXXXXXXXXXX000654HASR5[R/W]XXXXXXXXXXXXXXXXACR5[R/W]XXXXXXXXXXXXXXXX000658HASR6[R/W]XXXXXXXXXXXXXXXXACR6[R/W]XXXXXXXXXXXXXXXX00065CHASR7[R/W]XXXXXXXXXXXXXXXXACR7[R/W]XXXXXXXXXXXXXXXX000660HAWR0[R/W]0111111111111*11AWR1[R/W]XXXXXXXXXXXXXXXX000664HAWR2[R/W]XXXXXXXXXXXXXXXXAWR3[R/W]XXXXXXXXXXXXXXXX000668HAWR4[R/W]XXXXXXXXXXXXXXXXAWR5[R/W]XXXXXXXXXXXXXXXX00066CHAWR6[R/W]XXXXXXXXXXXXXXXXAWR7[R/W]XXXXXXXXXXXXXXXX000670HMCRA[R/W]XXXXXXXXMCRB[R/W]XXXXXXXXReserved000674HReserved000678HIOWR0[R/W]XXXXXXXXIOWR1[R/W]XXXXXXXXIOWR2[R/W]XXXXXXXXIOWR3[R/W]XXXXXXXX00067CHReserved000680HCSER[R/W]00000001CHER[R/W]11111111ReservedTCR[R/W]0000****[3]000684HRCRH[R/W]00XXXXXXRCRL[R/W]XXXX0XXXReserved000688Hto0007F8HReservedExternalBusUnit0007FCHReservedMODR[W]XXXXXXXXReservedModeRegister000800Hto000CFCHReservedReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage67of127000D00HPDRD00[R]XXXXXXXXPDRD01[R]XXXXXXXXReservedR-busPortDataDirectReadRegister000D04HReservedPDRD05[R]--XXXXXXPDRD06[R]XXXXXXXXPDRD07[R]XXXXXXXX000D08HPDRD08[R]X--X---XPDRD09[R]XXPDRD10[R]XReserved000D0CHReservedPDRD14[R]XXXXXXXXPDRD15[R]XXXXXXXX000D10HPDRD16[R]XXXXXXXXPDRD17[R]XXXXXXXXPDRD18[R]-XXX-XXXPDRD19[R]-XXX-XXX000D14HPDRD20[R]-XXX-XXXPDRD21[R]XPDRD22[R]XXXXXXXXPDRD23[R]XXXXXXXX000D18HPDRD24[R]XXXXXXXXReservedPDRD26[R]XXXXXXXXPDRD27[R]XXXXXXXX000D1CHPDRD28[R]XXXXXXXXPDRD29[R]XXXXXXXXReserved000D20Hto000D3CHReserved000D40HDDR00[R/W]00000000DDR01[R/W]00000000ReservedR-busPortDirectionRegister000D44HReservedDDR05[R/W]--000000DDR06[R/W]00000000DDR07[R/W]00000000000D48HDDR08[R/W]0--0---0DDR09[R/W]00DDR10[R/W]0Reserved000D4CHReservedDDR14[R/W]00000000DDR15[R/W]00000000000D50HDDR16[R/W]00000000DDR17[R/W]00000000DDR18[R/W]-000-000DDR19[R/W]-000-000000D54HDDR20[R/W]-000-000DDR21[R/W]00DDR22[R/W]00000000DDR23[R/W]00000000000D58HDDR24[R/W]00000000ReservedDDR26[R/W]00000000DDR27[R/W]00000000000D5CHDDR28[R/W]00000000DDR29[R/W]00000000Reserved000D60Hto000D7CHReservedReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage68of127000D80HPFR00[R/W]11111111PFR01[R/W]11111111ReservedR-busPortFunctionRegister000D84HReservedPFR05[R/W]--111111PFR06[R/W]11111111PFR07[R/W]11111111000D88HPFR08[R/W]1--1--11PFR09[R/W]11PFR10[R/W]1Reserved000D8CHReservedPFR14[R/W]00000000PFR15[R/W]00000000000D90HPFR16[R/W]00000000PFR17[R/W]00000000PFR18[R/W]-000-000PFR19[R/W]-000-000000D94HPFR20[R/W]-000-000PFR21[R/W]00PFR22[R/W]0000-0-0PFR23[R/W]-0000000000D98HPFR24[R/W]00000000ReservedPFR26[R/W]00000000PFR27[R/W]00000000000D9CHPFR28[R/W]00000000PFR29[R/W]00000000Reserved000DA0Hto000DC4HReserved000DC8HReservedEPFR10[R/W]0ReservedR-busPortExtraFunctionRegister000DCCHReservedEPFR14[R/W]00000000EPFR15[R/W]00000000000DD0HEPFR16[R/W]0-00----ReservedEPFR18[R/W]-000-000EPFR19[R/W]-0---0--000DD4HEPFR20[R/W]-000-000EPFR21[R/W]Reserved000DD8HReservedEPFR26[R/W]00000000EPFR27[R/W]00000000000DDCHto000DFCHReservedReserved000E00HPODR00[R/W]00000000PODR01[R/W]00000000ReservedR-busPortOutputDriveSelectRegister000E04HReservedPODR05[R/W]--000000PODR06[R/W]00000000PODR07[R/W]00000000000E08HPODR08[R/W]0--0---0PODR09[R/W]00PODR10[R/W]0Reserved000E0CHReservedPODR14[R/W]00000000PODR15[R/W]00000000000E10HPODR16[R/W]00000000PODR17[R/W]00000000PODR18[R/W]-000-000PODR19[R/W]-000-000000E14HPODR20[R/W]-000-000PODR21[R/W]00PODR22[R/W]00000000PODR23[R/W]00000000000E18HPODR24[R/W]00000000ReservedPODR26[R/W]00000000PODR27[R/W]00000000000E1CHPODR28[R/W]00000000PODR29[R/W]00000000Reserved000E20Hto000E3CHReservedReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
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*CPage70of127000EC0HPPER00[R/W]00000000PPER01[R/W]00000000ReservedR-busPortPull-Up/DownEnableRegister000EC4HReservedPPER05[R/W]--000000PPER06[R/W]00000000PPER07[R/W]00000000000EC8HPPER08[R/W]0--0---0PPER09[R/W]00PPER10[R/W]0Reserved000ECCHReservedPPER14[R/W]00000000PPER15[R/W]00000000000ED0HPPER16[R/W]00000000PPER17[R/W]00000000PPER18[R/W]-000-000PPER19[R/W]-000-000000ED4HPPER20[R/W]-000-000PPER21[R/W]00PPER22[R/W]00000000PPER23[R/W]00000000000ED8HPPER24[R/W]00000000ReservedPPER26[R/W]00000000PPER27[R/W]00000000000EDCHPPER28[R/W]00000000PPER29[R/W]00000000Reserved000EE0Hto000EFCHReservedReserved000F00HPPCR00[R/W]11111111PPCR01[R/W]11111111ReservedR-busPortPull-Up/DownControlRegister000F04HReservedPPCR05[R/W]--111111PPCR06[R/W]11111111PPCR07[R/W]11111111000F08HPPCR08[R/W]1--1---1PPCR09[R/W]11PPCR10[R/W]1Reserved000F0CHReservedPPCR14[R/W]00000000PPCR15[R/W]11111111000F10HPPCR16[R/W]00000000PPCR17[R/W]00000000PPCR18[R/W]-111-111PPCR19[R/W]-111-111000F14HPPCR20[R/W]-111-111PPCR21[R/W]11PPCR22[R/W]11111111PPCR23[R/W]11111111000F18HPPCR24[R/W]11111111ReservedPPCR26[R/W]11111111PPCR27[R/W]11111111000F1CHPPCR28[R/W]11111111PPCR29[R/W]11111111Reserved000F20Hto000F3CHReservedReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage71of127001000HDMASA0[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXDMAC001004HDMADA0[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001008HDMASA1[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00100CHDMADA1[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001010HDMASA2[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001014HDMADA2[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001018HDMASA3[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00101CHDMADA3[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001020HDMASA4[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001024HDMADA4[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX001028Hto003FFCHReservedReserved002000Hto006FFCHFlash-cachesizeis8Kbytes:004000Hto005FFCHFlash-cache/I-RAMarea007000HFMCS[R/W]01101000FMCR[R/W]----0000FCHCR[R/W]0010000011FlashMemory/I-CacheControlRegister007004HFMWT[R/W]1111111111111111ReservedFMPS[R/W]000007008HFMAC[R]0000000000000000000000000000000000700CHFCHA0[R/W]0000000000000000000000I-CacheNon-cacheableareasettingRegister007010HFCHA1[R/W]0000000000000000000000007014Hto007FFCHReservedReserved008000Hto00BFFCHBoot-ROMsizeis4Kbytes:00B000Hto00BFFCH(instructionaccessis1waitcycle,dataaccessis1waitcycle)BootROMarea00C000HCTRLR0[R/W]0000000000000001STATR0[R/W]0000000000000000CAN0ControlRegister00C004HERRCNT0[R]0000000000000000BTR0[R/W]001000110000000100C008HINTR0[R]0000000000000000TESTR0[R/W]00000000X000000000C00CHBRPE0[R/W]0000000000000000CBSYNC0AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage72of12700C010HIF1CREQ0[R/W]0000000000000001IF1CMSK0[R/W]0000000000000000CAN0IF1Register00C014HIF1MSK20[R/W]1111111111111111IF1MSK10[R/W]111111111111111100C018HIF1ARB20[R/W]0000000000000000IF1ARB10[R/W]000000000000000000C01CHIF1MCTR0[R/W]0000000000000000Reserved00C020HIF1DTA10[R/W]0000000000000000IF1DTA20[R/W]000000000000000000C024HIF1DTB10[R/W]0000000000000000IF1DTB20[R/W]000000000000000000C028Hto00C02CHReserved00C030HIF1DTA20[R/W]0000000000000000IF1DTA10[R/W]000000000000000000C034HIF1DTB20[R/W]0000000000000000IF1DTB10[R/W]000000000000000000C038Hto00C03CHReserved00C040HIF2CREQ0[R/W]0000000000000001IF2CMSK0[R/W]0000000000000000CAN0IF2Register00C044HIF2MSK20[R/W]1111111111111111IF2MSK10[R/W]111111111111111100C048HIF2ARB20[R/W]0000000000000000IF2ARB10[R/W]000000000000000000C04CHIF2MCTR0[R/W]0000000000000000Reserved00C050HIF2DTA10[R/W]0000000000000000IF2DTA20[R/W]000000000000000000C054HIF2DTB10[R/W]0000000000000000IF2DTB20[R/W]000000000000000000C058Hto00C05CHReserved00C060HIF2DTA20[R/W]0000000000000000IF2DTA10[R/W]000000000000000000C064HIF2DTB20[R/W]0000000000000000IF2DTB10[R/W]000000000000000000C068Hto00C07CHReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage73of12700C080HTREQR20[R]0000000000000000TREQR10[R]0000000000000000CAN0StatusFlags00C084Hto00C08CHReservedReserved00C090HNEWDT20[R]0000000000000000NEWDT10[R]000000000000000000C094Hto00C09CHReservedReserved00C0A0HINTPND20[R]0000000000000000INTPND10[R]000000000000000000C0A4Hto00C0ACHReservedReserved00C0B0HMSGVAL20[R]0000000000000000MSGVAL10[R]000000000000000000C0B4Hto00C0FCHReservedReserved00C100HCTRLR1[R/W]0000000000000001STATR1[R/W]0000000000000000CAN1ControlRegister00C104HERRCNT1[R]0000000000000000BTR1[R/W]001000110000000100C108HINTR1[R]0000000000000000TESTR1[R/W]00000000X000000000C10CHBRPE1[R/W]0000000000000000CBSYNC100C110HIF1CREQ1[R/W]0000000000000001IF1CMSK1[R/W]0000000000000000CAN1IF1Register00C114HIF1MSK21[R/W]1111111111111111IF1MSK11[R/W]111111111111111100C118HIF1ARB21[R/W]0000000000000000IF1ARB11[R/W]000000000000000000C11CHIF1MCTR1[R/W]0000000000000000Reserved00C120HIF1DTA11[R/W]0000000000000000IF1DTA21[R/W]000000000000000000C124HIF1DTB11[R/W]0000000000000000IF1DTB21[R/W]000000000000000000C128Hto00C12CHReserved00C130HIF1DTA21[R/W]0000000000000000IF1DTA11[R/W]000000000000000000C134HIF1DTB21[R/W]0000000000000000IF1DTB11[R/W]000000000000000000C138Hto00C13CHReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage74of12700C140HIF2CREQ1[R/W]0000000000000001IF2CMSK1[R/W]0000000000000000CAN1IF2Register00C144HIF2MSK21[R/W]1111111111111111IF2MSK11[R/W]111111111111111100C148HIF2ARB21[R/W]0000000000000000IF2ARB11[R/W]000000000000000000C14CHIF2MCTR1[R/W]0000000000000000Reserved00C150HIF2DTA11[R/W]0000000000000000IF2DTA21[R/W]000000000000000000C154HIF2DTB11[R/W]0000000000000000IF2DTB21[R/W]000000000000000000C158Hto00C15CHReserved00C160HIF2DTA21[R/W]0000000000000000IF2DTA11[R/W]000000000000000000C164HIF2DTB21[R/W]0000000000000000IF2DTB11[R/W]000000000000000000C168Hto00C17CHReserved00C180HTREQR21[R]0000000000000000TREQR11[R]0000000000000000CAN1StatusFlags00C184Hto00C18CHReservedReserved00C190HNEWDT21[R]0000000000000000NEWDT11[R]000000000000000000C194Hto00C19CHReservedReserved00C1A0HINTPND21[R]0000000000000000INTPND11[R]000000000000000000C1A4Hto00C1ACHReservedReserved00C1B0HMSGVAL21[R]0000000000000000MSGVAL11[R]000000000000000000C1B4Hto00C1FCHReservedReserved00C200HCTRLR2[R/W]0000000000000001STATR2[R/W]0000000000000000CAN2ControlRegister00C204HERRCNT2[R]0000000000000000BTR2[R/W]001000110000000100C208HINTR2[R]0000000000000000TESTR2[R/W]00000000X000000000C20CHBRPE2[R/W]0000000000000000CBSYNC2AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage75of12700C210HIF1CREQ2[R/W]0000000000000001IF1CMSK2[R/W]0000000000000000CAN2IF1Register00C214HIF1MSK22[R/W]1111111111111111IF1MSK12[R/W]111111111111111100C218HIF1ARB22[R/W]0000000000000000IF1ARB12[R/W]000000000000000000C21CHIF1MCTR2[R/W]0000000000000000Reserved00C220HIF1DTA12[R/W]0000000000000000IF1DTA22[R/W]000000000000000000C224HIF1DTB12[R/W]0000000000000000IF1DTB22[R/W]000000000000000000C228Hto00C22CHReserved00C230HIF1DTA22[R/W]0000000000000000IF1DTA12[R/W]000000000000000000C234HIF1DTB22[R/W]0000000000000000IF1DTB12[R/W]000000000000000000C238Hto00C23CHReserved00C240HIF2CREQ2[R/W]0000000000000001IF2CMSK2[R/W]0000000000000000CAN2IF2Register00C244HIF2MSK22[R/W]1111111111111111IF2MSK12[R/W]111111111111111100C248HIF2ARB22[R/W]0000000000000000IF2ARB12[R/W]000000000000000000C24CHIF2MCTR2[R/W]0000000000000000Reserved00C250HIF2DTA12[R/W]0000000000000000IF2DTA22[R/W]000000000000000000C254HIF2DTB12[R/W]0000000000000000IF2DTB22[R/W]000000000000000000C258Hto00C25CHReserved00C260HIF2DTA22[R/W]0000000000000000IF2DTA12[R/W]000000000000000000C264HIF2DTB22[R/W]0000000000000000IF2DTB12[R/W]000000000000000000C268Hto00C27CHReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage76of12700C280HTREQR22[R]0000000000000000TREQR12[R]0000000000000000CAN2StatusFlags00C284Hto00C28CHReservedReserved00C290HNEWDT22[R]0000000000000000NEWDT12[R]000000000000000000C294Hto00C29CHReservedReserved00C2A0HINTPND22[R]0000000000000000INTPND12[R]000000000000000000C2A4Hto00C2ACHReservedReserved00C2B0HMSGVAL22[R]0000000000000000MSGVAL12[R]000000000000000000C2B4Hto00C2FCHReservedReserved00C300HCTRLR3[R/W]0000000000000001STATR3[R/W]0000000000000000CAN3ControlRegisterNote:NotonCY91F465BB/CY91F464BB00C304HERRCNT3[R]0000000000000000BTR3[R/W]001000110000000100C308HINTR3[R]0000000000000000TESTR3[R/W]00000000X000000000C30CHBRPE3[R/W]0000000000000000CBSYNC3AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage77of127AddressRegisterBlock+0+1+2+300C310HIF1CREQ3[R/W]0000000000000001IF1CMSK3[R/W]0000000000000000CAN3IF1RegisterNote:NotonCY91F465BB/CY91F464BB00C314HIF1MSK23[R/W]1111111111111111IF1MSK13[R/W]111111111111111100C318HIF1ARB23[R/W]0000000000000000IF1ARB13[R/W]000000000000000000C31CHIF1MCTR3[R/W]0000000000000000Reserved00C320HIF1DTA13[R/W]0000000000000000IF1DTA23[R/W]000000000000000000C324HIF1DTB13[R/W]0000000000000000IF1DTB23[R/W]000000000000000000C328Hto00C32CHReserved00C330HIF1DTA23[R/W]0000000000000000IF1DTA13[R/W]000000000000000000C334HIF1DTB23[R/W]0000000000000000IF1DTB13[R/W]000000000000000000C338Hto00C33CHReserved00C340HIF2CREQ3[R/W]0000000000000001IF2CMSK3[R/W]0000000000000000CAN3IF2RegisterNote:NotonCY91F465BB/CY91F464BB00C344HIF2MSK23[R/W]1111111111111111IF2MSK13[R/W]111111111111111100C348HIF2ARB23[R/W]0000000000000000IF2ARB13[R/W]000000000000000000C34CHIF2MCTR3[R/W]0000000000000000Reserved00C350HIF2DTA13[R/W]0000000000000000IF2DTA23[R/W]000000000000000000C354HIF2DTB13[R/W]0000000000000000IF2DTB23[R/W]000000000000000000C358Hto00C35CHReserved00C360HIF2DTA23[R/W]0000000000000000IF2DTA13[R/W]000000000000000000C364HIF2DTB23[R/W]0000000000000000IF2DTB13[R/W]000000000000000000C368Hto00C37CHReservedCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage78of12700C380HTREQR23[R]0000000000000000TREQR13[R]0000000000000000CAN3StatusFlagsNote:NotonCY91F465BB/CY91F464BB00C384Hto00C38CHReserved00C390HNEWDT23[R]0000000000000000NEWDT13[R]000000000000000000C394Hto00C39CHReserved00C3A0HINTPND23[R]0000000000000000INTPND13[R]000000000000000000C3A4Hto00C3ACHReserved00C3B0HMSGVAL23[R]0000000000000000MSGVAL13[R]000000000000000000C3B4Hto00C3FCHReserved00C400HCTRLR4[R/W]0000000000000001STATR4[R/W]0000000000000000CAN4ControlRegisterNote:NotonCY91F465BB/CY91F464BB00C404HERRCNT4[R]0000000000000000BTR4[R/W]001000110000000100C408HINTR4[R]0000000000000000TESTR4[R/W]00000000X000000000C40CHBRPE4[R/W]0000000000000000CBSYNC400C410HIF1CREQ4[R/W]0000000000000001IF1CMSK4[R/W]0000000000000000CAN4IF1RegisterNote:NotonCY91F465BB/CY91F464BB00C414HIF1MSK24[R/W]1111111111111111IF1MSK14[R/W]111111111111111100C418HIF1ARB24[R/W]0000000000000000IF1ARB14[R/W]000000000000000000C41CHIF1MCTR4[R/W]0000000000000000Reserved00C420HIF1DTA14[R/W]0000000000000000IF1DTA24[R/W]000000000000000000C424HIF1DTB14[R/W]0000000000000000IF1DTB24[R/W]000000000000000000C428Hto00C42CHReserved00C430HIF1DTA24[R/W]0000000000000000IF1DTA14[R/W]000000000000000000C434HIF1DTB24[R/W]0000000000000000IF1DTB14[R/W]000000000000000000C438Hto00C43CHReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage79of12700C440HIF2CREQ4[R/W]0000000000000001IF2CMSK4[R/W]0000000000000000CAN4IF2RegisterNote:NotonCY91F465BB/CY91F464BB00C444HIF2MSK24[R/W]1111111111111111IF2MSK14[R/W]111111111111111100C448HIF2ARB24[R/W]0000000000000000IF2ARB14[R/W]000000000000000000C44CHIF2MCTR4[R/W]0000000000000000Reserved00C450HIF2DTA14[R/W]0000000000000000IF2DTA24[R/W]000000000000000000C454HIF2DTB14[R/W]0000000000000000IF2DTB24[R/W]000000000000000000C458Hto00C45CHReserved00C460HIF2DTA24[R/W]0000000000000000IF2DTA14[R/W]000000000000000000C464HIF2DTB24[R/W]0000000000000000IF2DTB14[R/W]000000000000000000C468Hto00C47CHReserved00C480HTREQR24[R]0000000000000000TREQR14[R]0000000000000000CAN4StatusFlagsNote:NotonCY91F465BB/CY91F464BB00C484Hto00C48CHReserved00C490HNEWDT24[R]0000000000000000NEWDT14[R]000000000000000000C494Hto00C49CHReserved00C4A0HINTPND24[R]0000000000000000INTPND14[R]000000000000000000C4A4Hto00C4ACHReserved00C4B0HMSGVAL24[R]0000000000000000MSGVAL14[R]000000000000000000C4B4Hto00C4FCHReserved00C500HCTRLR5[R/W]0000000000000001STATR5[R/W]0000000000000000CAN5ControlRegisterNote:NotonCY91F465BB/CY91F464BB00C504HERRCNT5[R]0000000000000000BTR5[R/W]001000110000000100C508HINTR5[R]0000000000000000TESTR5[R/W]00000000X000000000C50CHBRPE5[R/W]0000000000000000CBSYNC5AddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage80of12700C510HIF1CREQ5[R/W]0000000000000001IF1CMSK5[R/W]0000000000000000CAN5IF1RegisterNote:NotonCY91F465BB/CY91F464BB00C514HIF1MSK25[R/W]1111111111111111IF1MSK15[R/W]111111111111111100C518HIF1ARB25[R/W]0000000000000000IF1ARB15[R/W]000000000000000000C51CHIF1MCTR5[R/W]0000000000000000Reserved00C520HIF1DTA15[R/W]0000000000000000IF1DTA25[R/W]000000000000000000C524HIF1DTB15[R/W]0000000000000000IF1DTB25[R/W]000000000000000000C528Hto00C52CHReserved00C530HIF1DTA25[R/W]0000000000000000IF1DTA15[R/W]000000000000000000C534HIF1DTB25[R/W]0000000000000000IF1DTB15[R/W]000000000000000000C538Hto00C53CHReserved00C540HIF2CREQ5[R/W]0000000000000001IF2CMSK5[R/W]0000000000000000CAN5IF2RegisterNote:NotonCY91F465BB/CY91F464BB00C544HIF2MSK25[R/W]1111111111111111IF2MSK15[R/W]111111111111111100C548HIF2ARB25[R/W]0000000000000000IF2ARB15[R/W]000000000000000000C54CHIF2MCTR5[R/W]0000000000000000Reserved00C550HIF2DTA15[R/W]0000000000000000IF2DTA25[R/W]000000000000000000C554HIF2DTB15[R/W]0000000000000000IF2DTB25[R/W]000000000000000000C558Hto00C55CHReserved00C560HIF2DTA25[R/W]0000000000000000IF2DTA15[R/W]000000000000000000C564HIF2DTB25[R/W]0000000000000000IF2DTB15[R/W]000000000000000000C568Hto00C57CHReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage81of12700C580HTREQR25[R]0000000000000000TREQR15[R]0000000000000000CAN5StatusFlagsNote:NotonCY91F465BB/CY91F464BB00C584Hto00C58CHReserved00C590HNEWDT25[R]0000000000000000NEWDT15[R]000000000000000000C594Hto00C59CHReserved00C5A0HINTPND25[R]0000000000000000INTPND15[R]000000000000000000C5A4Hto00C5ACHReserved00C5B0HMSGVAL25[R]0000000000000000MSGVAL15[R]000000000000000000C5B4Hto00EFFCHReserved00F000HBCTRL[R/W]1111110000000000EDSU/MPU00F004HBSTAT[R/W]0000000000010--00000000F008HBIAC[R]000000000000000000F00CHBOAC[R]000000000000000000F010HBIRQ[R/W]000000000000000000F014Hto00F01CHReserved00F020HBCR0[R/W]00000000000000000000000000F024HBCR1[R/W]00000000000000000000000000F028HBCR2[R/W]00000000000000000000000000F02CHBCR3[R/W]00000000000000000000000000F030Hto00F07CHReservedReservedAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage82of1271.
dependsonthenumberofavailableCANchannels2.
ACR0[11:10]dependsonModevectorfetchinformationonbuswidth3.
TCR[3:0]INITvalue=0000,keepsvalueafterRST00F080HBAD0[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXEDSU/MPU00F084HBAD1[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F088HBAD2[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F08CHBAD3[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F090HBAD4[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F094HBAD5[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F098HBAD6[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F09CHBAD7[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0A0HBAD8[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0A4HBAD9[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0A8HBAD10[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0ACHBAD11[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0B0HBAD12[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0B4HBAD13[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0B8HBAD14[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0BCHBAD15[R/W]XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00F0C0Hto01FFFCHReservedEDSU/MPU020000Hto02FFFCHD-RAMsizeis24Kbytes:02A000H-02FFFCH(dataaccessis0waitcycles)D-RAMarea030000Hto03FFFCHID-RAMsizeis16Kbytes:030000H-033FFCH(instructionaccessis0waitcycles,dataaccessis1waitcycle)ID-RAMareaAddressRegisterBlock+0+1+2+3CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage83of12712.
2FlashMemoryandExternalBusArea12.
2.
1CY91F467BA/466BA64bitreaddat[63:0]32bitread/writedat[31:0]dat[31:0]16bitread/writedat[31:16]dat[15:0]dat[31:16]dat[15:0]AddressRegisterBlock+0+1+2+3+4+5+6+7040000Hto05FFF8HSA8(64KB)SA9(64KB)ROMS0060000Hto07FFF8HSA10(64KB)SA11(64KB)ROMS1080000Hto09FFF8HSA12(64KB)SA13(64KB)ROMS20A0000Hto0BFFF8HSA14(64KB)SA15(64KB)ROMS30C0000Hto0DFFF8HSA16(64KB)SA17(64KB)ROMS40E0000Hto0FFFF0HSA18(64KB)SA19(64KB)ROMS50FFFF8HFMV[R]06000000HFRV[R]0000BFF8H100000Hto11FFF8HSA20(64KB,CY91F467BA)Reserved(CY91F466BA)SA21(64KB,CY91F467BA)Reserved(CY91F466BA)ROMS6120000Hto13FFF8HSA22(64KB,CY91F467BA)Reserved(CY91F466BA)SA23(64KB,CY91F467B)Reserved(CY91F466BA)140000Hto143FF8HSA0(8KB)SA1(8KB)ROMS7144000Hto17FF8HSA2(8KB)SA3(8KB)148000Hto14BFF8HSA4(8KB)SA5(8KB)14C000Hto14FFF8HSA6(8KB)SA7(8KB)150000Hto17FFF8HReservedCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage84of127Notes:Writeoperationstoaddress0FFFF8Hand0FFFFCHarenotpossible.
Whenreadingtheseaddresses,thevaluesshownabovewillberead.
64bitreaddat[63:0]32bitread/writedat[31:0]dat[31:0]16bitread/writedat[31:16]dat[15:0]dat[31:16]dat[15:0]AddressRegisterBlock+0+1+2+3+4+5+6+7180000Hto1BFFF8HExternalBusAreaROMS81C0000Hto1FFFF8HROMS9200000Hto27FFF8HROMS10280000Hto2FFFF8HROMS11300000Hto37FFF8HROMS12380000Hto3FFFF8HROMS13400000Hto47FFF8HROMS14480000Hto4FFFF8HROMS15CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage85of12712.
2.
2CY91F465BB/464BB32bitreaddat[31:0]dat[31:0]16bitread/writedat[31:16]dat[15:0]dat[31:16]dat[15:0]AddressRegisterBlock+0+1+2+3+4+5+6+7040000Hto05FFF8HReservedReservedROMS0060000Hto07FFF8HReservedReservedROMS1080000Hto09FFF8HSA12(64KB)Reserved(CY91F464BB)SA13(64KB)Reserved(CY91F464BB)ROMS20A0000Hto0BFFF8HSA14(64KB)SA15(64KB)ROMS30C0000Hto0DFFF8HSA16(64KB)SA17(64KB)ROMS40E0000Hto0FFFF0HSA18(64KB)SA19(64KB)ROMS50FFFF8HFMV[R]06000000HFRV[R]0000BFF8H100000Hto11FFF8HExternalBusAreaROMS6120000Hto13FFF8H140000Hto143FF8HExternalBusAreaROMS7144000Hto17FF8H148000Hto14BFF8HSA4(8KB)SA5(8KB)14C000Hto14FFF8HSA6(8KB)SA7(8KB)150000Hto17FFF8HReservedCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage86of127Notes:Writeoperationstoaddress0FFFF8Hand0FFFFCHarenotpossible.
Whenreadingtheseaddresses,thevaluesshownabovewillberead.
OnCY91F465BB/F464BB,writeaccesstotheflashisonlypossiblein16-bitmode.
32bitread/writedat[31:0]dat[31:0]16bitread/writedat[31:16]dat[15:0]dat[31:16]dat[15:0]AddressRegisterBlock+0+1+2+3+4+5+6+7180000Hto1BFFF8HExternalBusAreaROMS81C0000Hto1FFFF8HROMS9200000Hto27FFF8HROMS10280000Hto2FFFF8HROMS11300000Hto37FFF8HROMS12380000Hto3FFFF8HROMS13400000Hto47FFF8HROMS14480000Hto4FFFF8HROMS15CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage87of12713.
InterruptVectorTableInterruptInterruptnumberInterruptLevel[1]InterruptVector[2]DMAResourceNumberDecimalHexa-DecimalSettingRegisterRegisterAddressOffsetDefaultVectorAddressReset000——3FCH000FFFFCH—Modevector101——3F8H000FFFF8H—Systemreserved202——3F4H000FFFF4H—Systemreserved303——3F0H000FFFF0H—Systemreserved404——3ECH000FFFECH—CPUsupervisormode(INT#5instruction)[5]505——3E8H000FFFE8H—MemoryProtectionexception[5]606——3E4H000FFFE4H—Systemreserved707——3E0H000FFFE0H—Systemreserved808——3DCH000FFFDCH—Systemreserved909——3D8H000FFFD8H—Systemreserved100A——3D4H000FFFD4H—Systemreserved110B——3D0H000FFFD0H—Systemreserved120C——3CCH000FFFCCH—Systemreserved130D——3C8H000FFFC8H—Undefinedinstructionexception140E——3C4H000FFFC4H—NMIrequest150FFHfixed3C0H000FFFC0H—ExternalInterrupt01610ICR00440H3BCH000FFFBCH0,16ExternalInterrupt117113B8H000FFFB8H1,17ExternalInterrupt21812ICR01441H3B4H000FFFB4H2,18ExternalInterrupt319133B0H000FFFB0H3,19ExternalInterrupt42014ICR02442H3ACH000FFFACH20ExternalInterrupt521153A8H000FFFA8H21ExternalInterrupt62216ICR03443H3A4H000FFFA4H22ExternalInterrupt723173A0H000FFFA0H23ExternalInterrupt82418ICR04444H39CH000FFF9CH—ExternalInterrupt92519398H000FFF98H—ExternalInterrupt10261AICR05445H394H000FFF94H—ExternalInterrupt11271B390H000FFF90H—ExternalInterrupt12281CICR06446H38CH000FFF8CH—ExternalInterrupt13291D388H000FFF88H—ExternalInterrupt14301EICR07447H384H000FFF84H—ExternalInterrupt15311F380H000FFF80H—ReloadTimer03220ICR08448H37CH000FFF7CH4,32ReloadTimer13321378H000FFF78H5,33ReloadTimer23422ICR09449H374H000FFF74H34ReloadTimer33523370H000FFF70H35CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage88of127ReloadTimer43624ICR1044AH36CH000FFF6CH36ReloadTimer53725368H000FFF68H37ReloadTimer63826ICR1144BH364H000FFF64H38ReloadTimer73927360H000FFF60H39FreeRunTimer04028ICR1244CH35CH000FFF5CH40FreeRunTimer14129358H000FFF58H41FreeRunTimer2422AICR1344DH354H000FFF54H42FreeRunTimer3432B350H000FFF50H43FreeRunTimer4442CICR1444EH34CH000FFF4CH44FreeRunTimer5452D348H000FFF48H45FreeRunTimer6462EICR1544FH344H000FFF44H46FreeRunTimer7472F340H000FFF40H47CAN04830ICR16450H33CH000FFF3CH—CAN14931338H000FFF38H—CAN25032ICR17451H334H000FFF34H—CAN3NotonCY91F465BB/464BB5133330H000FFF30H—CAN4NotonCY91F465BB/464BB5234ICR18452H32CH000FFF2CH—CAN5NotonCY91F465BB/464BB5335328H000FFF28H—LIN-USART0RX5436ICR19453H324H000FFF24H6,48LIN-USART0TX5537320H000FFF20H7,49Reserved5638ICR20454H31CH000FFF1CH8,50Reserved5739318H000FFF18H9,51LIN-USART2RX583AICR21455H314H000FFF14H52LIN-USART2TX593B310H000FFF10H53LIN-USART3RX603CICR22456H30CH000FFF0CH54LIN-USART3TX613D308H000FFF08H55SystemReserved623EICR23*3457H304H000FFF04H—DelayedInterrupt633F300H000FFF00H—SystemReserved[4]6440ICR24458H2FCH000FFEFCH—SystemReserved[4]65412F8H000FFEF8H—LIN-USART(FIFO)4RX6642ICR25459H2F4H000FFEF4H10,56LIN-USART(FIFO)4TX67432F0H000FFEF0H11,57LIN-USART(FIFO)5RX6844ICR2645AH2ECH000FFEECH12,58LIN-USART(FIFO)5TX69452E8H000FFEE8H13,59LIN-USART(FIFO)6RX7046ICR2745BH2E4H000FFEE4H60LIN-USART(FIFO)6TX71472E0H000FFEE0H61LIN-USART(FIFO)7RX7248ICR2845CH2DCH000FFEDCH62LIN-USART(FIFO)7TX73492D8H000FFED8H63InterruptInterruptnumberInterruptLevel[1]InterruptVector[2]DMAResourceNumberDecimalHexa-DecimalSettingRegisterRegisterAddressOffsetDefaultVectorAddressCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage89of127I2C0744AICR2945DH2D4H000FFED4H—I2C1754B2D0H000FFED0H—Reserved764CICR3045EH2CCH000FFECCH64Reserved774D2C8H000FFEC8H65Reserved784EICR3145FH2C4H000FFEC4H66Reserved794F2C0H000FFEC0H67Reserved8050ICR32460H2BCH000FFEBCH68Reserved81512B8H000FFEB8H69Reserved8252ICR33461H2B4H000FFEB4H70Reserved83532B0H000FFEB0H71Reserved8454ICR34462H2ACH000FFEACH72Reserved85552A8H000FFEA8H73Reserved8656ICR35463H2A4H000FFEA4H74Reserved87572A0H000FFEA0H75Reserved8858ICR36464H29CH000FFE9CH76Reserved8959298H000FFE98H77Reserved905AICR37465H294H000FFE94H78Reserved915B290H000FFE90H79InputCapture0925CICR38466H28CH000FFE8CH80InputCapture1935D288H000FFE88H81InputCapture2945EICR39467H284H000FFE84H82InputCapture3955F280H000FFE80H83InputCapture49660ICR40468H27CH000FFE7CH84InputCapture59761278H000FFE78H85InputCapture69862ICR41469H274H000FFE74H86InputCapture79963270H000FFE70H87OutputCompare010064ICR4246AH26CH000FFE6CH88OutputCompare110165268H000FFE68H89OutputCompare210266ICR4346BH264H000FFE64H90OutputCompare310367260H000FFE60H91OutputCompare410468ICR4446CH25CH000FFE5CH92OutputCompare510569258H000FFE58H93OutputCompare61066AICR4546DH254H000FFE54H94OutputCompare71076B250H000FFE50H95SoundGenerator1086CICR4646EH24CH000FFE4CH—Reserved1096D248H000FFE48H—SystemReserved1106EICR47[3]46FH244H000FFE44H—SystemReserved1116F240H000FFE40H—PPG011270ICR48470H23CH000FFE3CH15,96PPG111371238H000FFE38H97InterruptInterruptnumberInterruptLevel[1]InterruptVector[2]DMAResourceNumberDecimalHexa-DecimalSettingRegisterRegisterAddressOffsetDefaultVectorAddressCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage90of1271.
TheInterruptControlRegisters(ICRs)arelocatedintheinterruptcontrollerandsettheinterruptlevelforeachinterruptrequest.
AnICRisprovidedforeachinterruptrequest.
2.
ThevectoraddressforeachEIT(exception,interruptortrap)iscalculatedbyaddingthelistedoffsettothetablebaseregistervalue(TBR).
TheTBRspecifiesthetopoftheEITvectortable.
TheaddresseslistedinthetableareforthedefaultTBRvalue(000FFC00H).
TheTBRisinitializedtothisvaluebyareset.
TheTBRissetto000FFC00HaftertheinternalbootROMisexecuted.
3.
ICR23andICR47canbeexchangedbysettingtheREALOScompatibilitybit(addr0C03H:IOS[0])4.
UsedbyREALOS5.
MemoryProtectionUnit(MPU)supportPPG211472ICR49471H234H000FFE34H98PPG311573230H000FFE30H99PPG411674ICR50472H22CH000FFE2CH100PPG511775228H000FFE28H101PPG611876ICR51473H224H000FFE24H102PPG711977220H000FFE20H103PPG812078ICR52474H21CH000FFE1CH104PPG912179218H000FFE18H105PPG101227AICR53475H214H000FFE14H106PPG111237B210H000FFE10H107PPG121247CICR54476H20CH000FFE0CH108PPG131257D208H000FFE08H109PPG141267EICR55477H204H000FFE04H110PPG151277F200H000FFE00H111Up/DownCounter012880ICR56478H1FCH000FFDFCH—Up/DownCounter1129811F8H000FFDF8H—Reserved13082ICR57479H1F4H000FFDF4H—Reserved131831F0H000FFDF0H—RealTimeClock13284ICR5847AH1ECH000FFDECH—CalibrationUnit133851E8H000FFDE8H—A/DConverter013486ICR5947BH1E4H000FFDE4H14,112Systemreserved135871E0H000FFDE0H—AlarmComparator013688ICR6047CH1DCH000FFDDCH—Reserved137891D8H000FFDD8H—LowVoltageDetection1388AICR6147DH1D4H000FFDD4H—Reserved1398B1D0H000FFDD0H—TimebaseOverflow1408CICR6247EH1CCH000FFDCCH—PLLClockGear1418D1C8H000FFDC8H—DMAController1428EICR6347FH1C4H000FFDC4H—Main/SubOSCstabilitywait1438F1C0H000FFDC0H—Securityvector14490——1BCH000FFDBCH—UsedbytheINTinstruction.
145to25591toFF——1B8Hto000H000FFDB8Hto000FFC00H—InterruptInterruptnumberInterruptLevel[1]InterruptVector[2]DMAResourceNumberDecimalHexa-DecimalSettingRegisterRegisterAddressOffsetDefaultVectorAddressCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage91of12714.
RecommendedSettings14.
1PLLandClockGearSettingsPleasenotethatforCY91F467BA/466BAandCY91F465BB/464BBthecorebaseclockfrequenciesarevalidinthe1.
8VoperationmodeoftheMainregulatorandFlash.
Table7.
RecommendedPLLDividerandClockGearSettingsPLLInput(CLK)[MHz]FrequencyParameterClockGearParameterPLLOutput(X)[MHz]CoreBaseClock[MHz]RemarksDIVMDIVNDIVGMULGMULG42251624200100NotonCY91F467-BA/466BA422416241929642231624184924222162417688422116201688442201620160804219162015276421816201447242171616136684216161612864421516161206042141616112564213161210452421216129648421116128844441016241604044916241443644816241283244716241122846616241442448516281602041041632160164123163214412CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage92of12714.
2ClockModulatorsettingsThefollowingtableshowsallpossiblesettingsfortheClockModulatorinabaseclockfrequencyrangefrom32MHzupto88MHz.
TheFlashaccesstimesettingsneedtobeadjustedaccordingtoFmaxwhilethePLLandclockgearsettingsshouldbesetaccordingtobaseclockfrequency.
Table8.
ClockModulatorSettings,FrequencyRangeandSupportedSupplyVoltageModulationDegree(k)RandomNo(N)CMPR[hex]Baseclk[MHz]Fmin[MHz]Fmax[MHz]13026F8879.
598.
5NotonCY91F467BA/466BA13026F8476.
193.
813026F8072.
689.
11502AE8068.
795.
823046E8068.
795.
813026F7669.
184.
51502AE7665.
390.
81702ED766298.
1NotonCY91F467BA/466BA23046E7665.
390.
833066D766298.
1NotonCY91F467BA/466BA13026F7265.
579.
91502AE726285.
81702ED7258.
892.
723046E726285.
833066D7258.
892.
713026F686275.
31502AE6858.
780.
91702ED6855.
787.
319032C68539523046E6858.
780.
92504AC68539533066D6855.
787.
343086C68539513026F6458.
570.
71502AE6455.
375.
91702ED6452.
58219032C6449.
989.
1111036B6447.
697.
6NotonCY91F467BA/466BA23046E6455.
375.
92504AC6449.
989.
133066D6452.
58243086C6449.
989.
1CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage93of127530A6B6447.
697.
6NotonCY91F467BA/466BA13026F6054.
966.
11502AE6051.
9711702ED6049.
376.
719032C6046.
983.
3111036B6044.
791.
323046E6051.
9712504AC6046.
983.
333066D6049.
376.
743086C6046.
983.
3530A6B6044.
791.
313026F5651.
461.
61502AE5648.
666.
11702ED5646.
171.
419032C5643.
877.
6111036B5641.
884.
911303AA5639.
993.
823046E5648.
666.
12504AC5643.
877.
62704EA5639.
993.
833066D5646.
171.
43506AA5639.
993.
843086C5643.
877.
6530A6B5641.
884.
9630C6A5639.
993.
813026F5247.
8571502AE5245.
261.
21702ED5242.
966.
119032C5240.
871.
8111036B5238.
878.
611303AA5237.
186.
811503E95235.
596.
9NotonCY91F467BA/466BA23046E5245.
261.
22504AC5240.
871.
82704EA5237.
186.
833066D5242.
966.
13506AA5237.
186.
843086C5240.
871.
8ModulationDegree(k)RandomNo(N)CMPR[hex]Baseclk[MHz]Fmin[MHz]Fmax[MHz]CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage94of127530A6B5238.
878.
6630C6A5237.
186.
8730E695235.
596.
9NotonCY91F467BA/466BA13026F4844.
252.
51502AE4841.
856.
41702ED4839.
660.
919032C4837.
766.
1111036B4835.
972.
311303AA4834.
379.
911503E94832.
889.
123046E4841.
856.
42504AC4837.
766.
12704EA4834.
379.
933066D4839.
660.
93506AA4834.
379.
943086C4837.
766.
1530A6B4835.
972.
3630C6A4834.
379.
9730E694832.
889.
113026F4440.
648.
11502AE4438.
451.
61702ED4436.
455.
719032C4434.
660.
4111036B443366.
111303AA4431.
57311503E94430.
181.
423046E4438.
451.
62504AC4434.
660.
42704EA4431.
5732905284428.
992.
133066D4436.
455.
73506AA4431.
57343086C4434.
660.
44508A84428.
992.
1530A6B443366.
1630C6A4431.
573730E694430.
181.
48310684428.
992.
113026F403743.
6ModulationDegree(k)RandomNo(N)CMPR[hex]Baseclk[MHz]Fmin[MHz]Fmax[MHz]CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage95of1271502AE4034.
946.
81702ED4033.
150.
519032C4031.
554.
8111036B403059.
911303AA4028.
766.
111503E94027.
473.
723046E4034.
946.
82504AC4031.
554.
82704EA4028.
766.
12905284026.
383.
333066D4033.
150.
53506AA4028.
766.
13706E74025.
395.
843086C4031.
554.
84508A84026.
383.
3530A6B403059.
9630C6A4028.
766.
1730E694027.
473.
78310684026.
383.
39312674025.
395.
813026F3633.
339.
21502AE3631.
5421702ED3629.
945.
319032C3628.
449.
2111036B3627.
153.
811303AA3625.
859.
311503E93624.
766.
123046E3631.
5422504AC3628.
449.
22704EA3625.
859.
32905283623.
774.
733066D3629.
945.
33506AA3625.
859.
33706E73622.
885.
843086C3628.
449.
24508A83623.
774.
7530A6B3627.
153.
8630C6A3625.
859.
3730E693624.
766.
18310683623.
774.
7ModulationDegree(k)RandomNo(N)CMPR[hex]Baseclk[MHz]Fmin[MHz]Fmax[MHz]CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage96of1279312673622.
885.
813026F3229.
734.
71502AE322837.
31702ED3226.
640.
219032C3225.
343.
6111036B3224.
147.
711303AA322352.
511503E9322258.
623046E322837.
32504AC3225.
343.
62704EA322352.
52905283221.
166.
121105663219.
589.
133066D3226.
640.
23506AA322352.
53706E73220.
375.
943086C3225.
343.
64508A83221.
166.
1530A6B3224.
147.
7550AA63219.
589.
1630C6A322352.
5730E69322258.
68310683221.
166.
19312673220.
375.
910314663219.
589.
1ModulationDegree(k)RandomNo(N)CMPR[hex]Baseclk[MHz]Fmin[MHz]Fmax[MHz]CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage97of12715.
ElectricalCharacteristics15.
1AbsoluteMaximumRatingsParameterSymbolRatingUnitRemarksMinMaxPowersupplyslewrate50V/msPowersupplyvoltage1[1]VDD5R0.
3+6.
0VPowersupplyvoltage2[1]VDD50.
3+6.
0VRelationshipofthesupplyvoltagesAVCC5VDD5-0.
3VDD35-0.
3VDD5+0.
3VDD35+0.
3VAtleastonepinofthePorts26to29(ANn)isusedasdigitalinputoroutput.
VSS5-0.
3VDD35-0.
3VDD5+0.
3VDD35+0.
3VAllpinsofthePorts26to29(ANn)followtheconditionofVIAAnalogpowersupplyvoltage[1]AVCC50.
3+6.
0V[2]Analogreferencepowersupplyvoltage[1]AVRH0.
3+6.
0V[2]Inputvoltage1[1]VI1Vss50.
3VDD5+0.
3VAnalogpininputvoltage[1]VIAAVss50.
3AVcc5+0.
3VOutputvoltage1[1]VO1Vss50.
3VDD5+0.
3VMaximumclampcurrentICLAMP4.
0+4.
0mA[3]TotalmaximumclampcurrentΣ|ICLAMP|20mA[3]"L"levelmaximumoutputcurrent[4]IOL10mA"L"levelaverageoutputcurrent[5]IOLAV8mA"L"leveltotalmaximumoutputcurrentΣIOL100mA"L"leveltotalaverageoutputcurrent[6]ΣIOLAV50mA"H"levelmaximumoutputcurrent[4]IOH10mA"H"levelaverageoutputcurrent[5]IOHAV4mA"H"leveltotalmaximumoutputcurrentΣIOH100mA"H"leveltotalaverageoutputcurrent[6]ΣIOHAV25mAPermittedoperatingfrequencyCY91F465BB/F464BBfmax,CLKB100MHzTA≤105°Cfmax,CLKP50fmax,CLKT50fmax,CLKCAN50PermittedoperatingfrequencyCY91F465BB/F464BBfmax,CLKB96MHzTA≤125°Cfmax,CLKP48fmax,CLKT48fmax,CLKCAN48PermittedoperatingfrequencyCY91F467BA/F466BAfmax,CLKB96MHzTA≤105°Cfmax,CLKP48fmax,CLKT48fmax,CLKCAN48CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage98of1271.
TheparameterisbasedonVSS5=AVSS5=0.
0V.
2.
AVCC5andAVRH5mustnotexceedVDD5+0.
3V.
3.
Usewithinrecommendedoperatingconditions.
UsewithDCvoltage(current).
+BsignalsareinputsignalsthatexceedtheVDD5voltage.
+Bsignalsshouldalwaysbeappliedbyconnectingalimitingresistorbetweenthe+Bsignalandthemicrocontroller.
Thevalueofthelimitingresistorshouldbesetsothatthecurrentinputtothemicrocontrollerpindoesnotexceedtheratedvalueatanytime,eitherinstantaneouslyorforanextendedperiod,whenthe+Bsignalisinput.
Notethatwhenthemicrocontrollerdrivecurrentislow,suchasinthelowpowerconsumptionmodes,the+Binputpotentialcanincreasethepotentialatthepowersupplypinviaaprotectivediode,possiblyaffectingotherdevices.
Notethatifthe+Bsignalisinputwhenthemicrocontrollerisoff(notfixedat0V),powerissuppliedthroughthe+Binputpin;therefore,themicrocontrollermaypartiallyoperate.
Notethatifthe+Bsignalisinputatpower-on,sincethepowerissuppliedthroughthepin,thepower-onresetmaynotfunctioninthepowersupplyvoltage.
Donotleave+Binputpinsopen.
Figure2.
ExampleofRecommendedCircuit:PermittedoperatingfrequencyCY91F467BA/F466BAfmax,CLKB92MHzTA≤125°Cfmax,CLKP46fmax,CLKT46fmax,CLKCAN46Permittedpowerdissipation[7]PD1200*8mWTA≤85°C600*8mWTA≤105°C1300*8mWTA≤105°C,noFlashprogram/erase[9]1000*8mWTA≤115°C,noFlashprogram/erase[9]750*8mWTA≤125°C,noFlashprogram/erase[9]OperatingtemperatureTA40+125°CStoragetemperatureTstg55+150°CParameterSymbolRatingUnitRemarksMinMaxP-chN-chVCCRInput/outputequivalentcircuit+Binput(0Vto16V)LimitingresistorProtectivediodeCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage99of1274.
Maximumoutputcurrentisdefinedasthevalueofthepeakcurrentflowingthroughanyoneofthecorrespondingpins.
5.
Averageoutputcurrentisdefinedasthevalueoftheaveragecurrentflowingthroughanyoneofthecorrespondingpinsfora100msperiod.
6.
Totalaverageoutputcurrentisdefinedasthevalueoftheaveragecurrentflowingthroughallofthecorrespondingpinsfora100msperiod.
7.
Themaximumpermittedpowerdissipationdependsonmtheambienttemperature,theairflowvelocityandthethermalconductanceofthepackageonthePCB.
Theactualpowerdissipationdependsonthecustomerapplicationandcanbecalculatedasfollows:PD=PIO+PINTPIO=Σ(VOL*IOL+VOH+IOH)(IOloadpowerdissipation,sumisperformedonallIOports)PINT=VDD5R*ICC+AVCC5*IA+AVRH5*IR(internalpowerdissipation)8.
WorstcasevaluefortheQFPpackagemountedona4-layerPCBatspecifiedTAwithoutairflow.
9.
PleasecontactCypressforreliabilitylimitationswhenusingundertheseconditions.
WARNING:Semiconductordevicescanbepermanentlydamagedbyapplicationofstress(voltage,current,temperature,etc.
)inexcessofabsolutemaximumratings.
Donotexceedtheseratings.
CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage100of12715.
2RecommendedOperatingConditions(VSS5=AVSS5=0.
0V)WARNING:Therecommendedoperatingconditionsarerequiredinordertoensurethenormaloperationofthesemiconductordevice.
Allofthedevice'selectricalcharacteristicsarewarrantedwhenthedeviceisoperatedwithintheseranges.
Alwaysusesemiconductordeviceswithintheirrecommendedoperatingconditionranges.
Operationoutsidetheserangesmayadverselyaffectreliabilityandcouldresultindevicefailure.
Nowarrantyismadewithrespecttouses,operatingconditions,orcombinationsnotrepresentedonthedatasheet.
Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontacttheirrepresentativesbeforehand.
ParameterSymbolValueUnitRemarksMinTypMaxPowersupplyvoltageVDD53.
0-5.
5VVDD5R3.
0-5.
5VInternalregulatorAVCC53.
0-5.
5VA/DconverterSmoothingcapacitoratVCC18CpinCS-4.
7-mFUseaX7Rceramiccapacitororacapacitorthathassimilarfrequencycharacteristics.
Powersupplyslewrate--50V/msOperatingtemperatureTA-40-+125°CMainOscillationstabilisationtime10msLock-uptimePLL(4MHz->16.
.
.
100MHz)0.
6msESDProtection(Humanbodymodel)Vsurge2kVRdischarge=1.
5kWCdischarge=100pFRCOscillatorfRC100kHzfRC2MHz50110022004kHzMHzVDDCORE≥1.
65VCSAVSS5VSS5VCC18CCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage101of12715.
3DCCharacteristics(VDD5=AVCC5=3.
0Vto5.
5V,VSS5=AVSS5=0V,TA=40°Cto+125°C)ParameterSymbolPinNameConditionValueUnitRemarksMinTypMaxInput"H"voltageVIH-PortinputsifCMOSHysteresis0.
8/0.
2inputisselected0.
8*VDD-VDD+0.
3VCMOShysteresisinput-PortinputsifCMOSHysteresis0.
7/0.
3inputisselected0.
7*VDD-VDD+0.
3V4.
5VVDD5.
5V0.
74*VDD-VDD+0.
3V3VVDD2iftSCYCI=(2*k+1)*tCLKP,thenm=k+1,wherekisaninteger>1Notes:TheabovevaluesareACcharacteristicsforCLKsynchronousmode.
tCLKPisthecycletimeoftheperipheralclock.
ParameterSymbolPinNameConditionVDD5=3.
0Vto4.
5VVDD5=4.
5Vto5.
5VUnitMinMaxMinMaxSerialclockcycletimetSCYCISCKnInternalclockoperation(mastermode)4tCLKP-4tCLKP-nsSCK↓→SOTdelaytimetSLOVISCKnSOTn-3030-2020nsSOT→SCK↓delaytimetOVSHISCKnSOTnm*tCLKP-30[1]-m*tCLKP-20[1]-nsValidSIN→SCK↑setuptimetIVSHISCKnSINntCLKP+55-tCLKP+45-nsSCK↑→validSINholdtimetSHIXISCKnSINn0-0-nsSerialclock"H"pulsewidthtSHSLESCKnExternalclockoperation(slavemode)tCLKP+10-tCLKP+10-nsSerialclock"L"pulsewidthtSLSHESCKntCLKP+10-tCLKP+10-nsSCK↓→SOTdelaytimetSLOVESCKnSOTn-2tCLKP+55-2tCLKP+45nsValidSIN→SCK↑setuptimetIVSHESCKnSINn10-10-nsSCK↑→validSINholdtimetSHIXESCKnSINntCLKP+10-tCLKP+10-nsSCKrisingtimetFESCKn-20-20nsSCKfallingtimetRESCKn-20-20nsCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage112of127Figure4.
InternalClockMode(MasterMode)Figure5.
ExternalClockMode(SlaveMode)tIVSHIVOHtSHIXItSLOVItSCYCIVOLSOTnSCKnforESCR:SCES=0SCKnforESCR:SCES=1tOVSHIVOLVOLVOLVOLVOLVOHVOHVOHVOHVOHSINntIVSHEVOHtSHIXEtSLOVEtSLSHEVOLSOTnSCKnforESCR:SCES=0SCKnforESCR:SCES=1VOLVOLVOLVOLVOHVOHVOHVOLVOHVOHVOHSINntSHSLEVOLtREVOHtFEVOLCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage113of12715.
7.
4I2CACTimingsatVDD5=3.
0to5.
5VConditionsduringACmeasurementsAllACtestsweremeasuredunderthefollowingconditions:-IOdrive=3mA-VDD5=3.
0Vto5.
5V,Iload=3mA-VSS5=0V-Ta=-40°Cto+125°C-Cl=50pF-VOL=0.
3*VDD5-VOH=0.
7*VDD5-EPILR=0,PILR=0(CMOSHysteresis0.
3*VDD5/0.
7*VDD5)15.
7.
4.
1FastMode:(VDD5=3.
5Vto5.
5V,VSS5=AVSS5=0V,TA=40°Cto+125°C)1.
Thenoisefilterwillsuppresssinglespikeswithapulsewidthof0nsandbetween(1to1.
5)cyclesofperipheralclock,dependingonthephaserelationshipbetweenI2Csignals(SDA,SCL)andperipheralclock.
Note:tCLKPisthecycletimeoftheperipheralclock.
ParameterSymbolPinNameValueUnitRemarkMinMaxSCLclockfrequencyfSCLSCLn0400kHzHoldtime(repeated)STARTcondition.
Afterthisperiod,thefirstclockpulseisgen-eratedtHD;STASCLn,SDAn0.
6μsLOWperiodoftheSCLclocktLOWSCLn1.
3μsHIGHperiodoftheSCLclocktHIGHSCLn0.
6μsSetuptimeforarepeatedSTARTconditiontSU;STASCLn,SDAn0.
6μsDataholdtimeforI2C-busdevicestHD;DATSCLn,SDAn00.
9μsDatasetuptimetSU;DATSCLnSDAn100nsRisetimeofbothSDAandSCLsignalstrSCLn,SDAn20+0.
1Cb300nsFalltimeofbothSDAandSCLsignalstfSCLn,SDAn20+0.
1Cb300nsSetuptimeforSTOPconditiontSU;STOSCLn,SDAn0.
6μsBusfreetimebetweenaSTOPandSTARTconditiontBUFSCLn,SDAn1.
3μsCapacitiveloadforeachbuslineCbSCLn,SDAn400pFPulsewidthofspikesuppressedbyinputfiltertSPSCLn,SDAn0(1.
.
1.
5)*tCLKPns[1]CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage114of127SDASSrPSSCLtHD;STAtrtrtSPtSU;ST0tSU;STAtSU;DATtHD;DATtHD;STAtLOWtHIGHtBUFtftfCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage115of12715.
7.
5Free-RunTimerClock(VDD5=3.
0Vto5.
5V,VSS5=AVSS5=0V,TA=40°Cto+125°C)Note:tCLKPisthecycletimeoftheperipheralclock.
15.
7.
6TriggerInputTiming(VDD5=3.
0Vto5.
5V,VSS5=AVSS5=0V,TA=40°Cto+125°C)Note:tCLKPisthecycletimeoftheperipheralclock.
ParameterSymbolPinNameConditionValueUnitMinMaxInputpulsewidthtTIWHtTIWLCKn4tCLKPnsParameterSymbolPinNameConditionValueUnitMinMaxInputcaptureinputtriggertINPICUn5tCLKPnsA/DconvertertriggertATGXATGX5tCLKPnstTIWHtTIWLCKnVIHVIHVILVILICUn,ATGXtATGX,tINPCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage116of12715.
7.
7ExternalBusACTimingsatVDD35=3.
0to5.
5VNote:ThischapterisapplicabletoCY91F467BA/F466BAConditionsduringACmeasurementsAllACtestsweremeasuredunderthefollowingconditions:-IOdrive=5mA-VDD35=4.
5Vto5.
5V,Iload=3mA-VSS5=0V-Ta=40°Cto+125°C-Cl=50pF-VOL=0.
5*VDD35-VOH=0.
5*VDD35-EPILR=0,PILR=1(AutomotiveLevel=worstcase)15.
7.
7.
1BasicTiming(VDD35=3.
0Vto5.
5V,Vss5=AVss5=0V,TA=40°Cto+125°C)Note:tCLKTisthecycletimeoftheexternalbusclock.
ParameterSymbolPinNameValueUnitMinMaxSYSCLKtCLCHSYSCLK1/2xtCLKT-11/2*tCLKT+9nstCHCL1/2*tCLKT-91/2*tCLKT+1nsSYSCLK↓toCSXndelaytimetCLCSLSYSCLKCSXn-8nstCLCSH-12nsSYSCLK↑toCSXndelaytime(Addr→CSdelay)tCHCSL-6+1nsSYSCLK↓toAddressvaliddelaytimetCLAVSYSCLKA21toA0-13nsCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage117of127SYSCLKCSXndelayedCSXnASXADDRESSBAAXtCHCSLtCLASLtCLAVtCLBALtCLASHtCLCSLtCLCHtCHCLtCYCtCLCSHtCLBAHCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage118of12715.
7.
7.
2Synchronous/AsynchronousReadAccess(VDD35=3.
0Vto5.
5V,Vss5=AVss5=0V,TA=40°Cto+125°C)ParameterSymbolPinNameValueUnitMinMaxSYSCLK↑toRDXdelaytimeTCHRLSYSCLKRDX-71nsTCHRH-42nsDatavalidtoRDX↑setuptimeTDSRHRDXD31toD1633-nsRDX↑toDatavalidholdtimeTRHDXRDXD31toD160-nsSYSCLK↓toWRXn(asbyteenable)delaytimeTCLWRLSYSCLKWRXn-8nsTCLWRH0-nsSYSCLK↓toCSXndelaytimeTCLCSLSYSCLKCSXn-8nsTCLCSH-12nsSYSCLKCSXnWRXn(asbyteenable)RDXDATAINtDSRHtRHDXtCHRHtCHRLtCLWRLtCLWRHtCLCSHtCLCSLCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage119of12715.
7.
7.
3SynchronousWriteAccess(VDD35=3.
0Vto5.
5V,Vss5=AVss5=0V,TA=40°Cto+125°C)ParameterSymbolPinNameValueUnitMinMaxSYSCLK↓toWRXndelaytimeTCLWRLSYSCLKWRXn-8nsTCLWRH0-nsDatavalidtoWRXn↓setuptimeTDSWRLWRXnD31toD16-7-nsWRXn↑toDatavalidholdtimeTWRHDHWRXnD31toD16tCLKT-20-nsSYSCLK↓toCSXndelaytimeTCLCSLSYSCLKCSXn-8nsTCLCSH-12nsSYSCLKCSXnWRXnDATAOUTtCLWRHtCLWRLtDSWRLtWRHDHtCLCSHtCLCSLCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage120of12715.
7.
7.
4AsynchronousWriteAccess(VDD35=3.
0Vto5.
5V,Vss5=AVss5=0V,TA=40°Cto+125°C)ParameterSymbolPinNameValueUnitMinMaxWRXn↓toWRXn↑pulsewidthTWRLWRHWRXntCLKT-nsDatavalidtoWRXn↓setuptimeTDSWRLWRXnD31toD161/2*tCLKT-10-nsWRXn↑toDatavalidholdtimeTWRHDHWRXnD31toD161/2*tCLKT-19-nsWRXntoCSXndelaytimeTCLWRLWRXnCSXn-1/2*tCLKTnsTWRHCH1/2*tCLKT-nsCSXnWRXnDATAOUTTWRHDHTWRHCHTCLWRLTWRLWRHTDSWRLCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage121of12715.
7.
7.
5RDYWaitCycleInsertion(VDD35=3.
0Vto5.
5V,Vss5=AVss5=0V,TA=40°Cto+125°C)ParameterSymbolPinNameValueUnitMinMaxRDYsetuptimeTRDYSSYSCLKRDY34nsRDYholdtimeTRDYHSYSCLKRDY0nsSYSCLKRDYtRDYStRDYHCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage122of12716.
OrderingInformationPartnumberPackageRemarksCY91F467BAPMC-GS-UJE2144-pinplasticLQFP(LQS144)CY91460BSeriesDocumentNumber:002-04608Rev.
*CPage123of12717.
PackageDimension002-13015*ACY91460BSeriesDocumentNumber:002-04608Rev.
*CPage124of12718.
RevisionHistorySpansionPublicationNumber:DS07-16609-1EVersionDateRemark2.
02008-06-19Initialversion2.
12008-08-15ProofreadingresultsfromFJincorporated;Correctedpinoutdrawings;IOCIRCUITTYPES:correctedsometyposlikeontheotherdatasheets;HANDLINGDEVICES:updatedthesection"NotesonPSregister"forbetterunderstanding;InterruptVectorTable:correctedthefootnotesFLASH:addednoteabouttheoperationmodeswitchingcapabilityinBootROM;correctedflashsecurityvectorFSV2assignments,correctedsectionaboutparallelprogramming,correctedsectionpinconnectionsinparallelprogrammingmodesothatthereisonlyonepageaddedsection"PoweronSequenceinparallelprogrammingmode";ELECTRICALCHARACTERISTICS:removedthenotethatanaloginput/outputpinscannotac-cept+Bsignalinput;splittedILVintoexternalandinternalLVdetectioncurrentADCCharacteristics:Correctedtheitemsaboutnonlinearityerror;Correctedthecompanyname3.
02009-01-09Page1:CorrecteddocumentnamefieldintopheaderBlockDiagram:RemovedSCK0(LIN-USART0isasynchronousonly)AddedTa=125CcharacteristicsCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage125of12719.
MainChangesinThisEditionNOTE:Pleasesee"DocumentHistory"forlaterrevisedinformation.
PageSectionChangeResults10415.
ElectricalCharacteristics15.
4.
A/DconvertercharacteristicsCorrectedthecolumn"Value"and"Unit"oftheparameter"Zeroreadingvoltage"and"Fullscalereadingvoltage".
(Value:AVRL-1.
5→AVRL-1.
5LSBAVRL+0.
5→AVRL+0.
5LSBAVRL+2.
5→AVRL+2.
5LSBAVRH-3.
5→AVRH-3.
5LSBAVRH-1.
5→AVRH-1.
5LSBAVRH+0.
5→AVRH+0.
5LSBUnit:LSB→V)*B---MarketingPartNumberschangedfromanMBprefixtoaCYprefix.
71221232.
PinAssignment16.
OrderingInformation17.
PackageDimensionPackagedescriptionmodifiedtoJEDECdescription.
12216.
OrderingInformationDeletedthefollowingMarketingpartnumberasfollows:MB91F465BBPMC-GSE2RevisedMarketingPartNumbersasfollows:before)MB91F467BAPMC-GSE2after)CY91F467BAPMC-GS-UJE2*C--10215.
3DCCharacteristicsRevisedtheUnit.
before)Inputleakagecurrent:mAAnaloginputleakagecurrent:mAPull-upresistance:kWPull-downresistance:kWafter)Inputleakagecurrent:μAAnaloginputleakagecurrent:μAPull-upresistance:kΩPull-downresistance:kΩCY91460BSeriesDocumentNumber:002-04608Rev.
*CPage126of127DocumentHistoryDocumentTitle:CY91F467BA/466BA,CY91F465BB/464BB,FR60CY91460BSeries,32-bitMicrocontrollerDatasheetDocumentNumber:002-04608RevisionECNOrig.
ofChangeSubmissionDateDescriptionofChange**AKIH08/17/2009MigratedtoCypressandassigneddocumentnumber002-04608.
Nochangetodocumentcontentsorformat.
*A5221423AKIH04/25/2016UpdatedtoCypresstemplate*B6314451SHUS09/19/2018MarketingPartNumberschangedfromanMBprefixtoaCYprefix.
2.
PinAssignments16.
PackageDimension17.
OrderingInformationFordetails,pleasesee19.
MainChangesinthisEdition*C6456716SHUS01/24/2019RevisedtheUnit.
Fordetails,pleasesee19.
MainChangesinthisEditionDocumentNumber:002-04608Rev.
*CRevisedJanuary24,2019Page127of127CY91460BSeriesCypressSemiconductorCorporation2009-2019.
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