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ADC08500www.
ti.
comSNAS373E–MAY2007–REVISEDAPRIL2013ADC08500HighPerformance,LowPower8-Bit,500MSPSA/DConverterCheckforSamples:ADC085001FEATURESDESCRIPTIONTheADC08500isalowpower,highperformance2InternalSample-and-HoldCMOSanalog-to-digitalconverterthatdigitizesSingle+1.
9V±0.
1VOperationsignalsto8bitsresolutionatsamplingratesuptoChoiceofSDRorDDROutputClocking500MSPS.
Consumingatypical0.
8Wattsat500MSPSfromasingle1.
9Voltsupply,thisdeviceisMultipleADCSynchronizationCapabilityensuredtohavenomissingcodesoverthefullEnsuredNoMissingCodesoperatingtemperaturerange.
TheuniquefoldingandSerialInterfaceforExtendedControlinterpolatingarchitecture,thefullydifferentialcomparatordesign,theinnovativedesignoftheFineAdjustmentofInputFull-ScaleRangeandinternalsample-and-holdamplifierandtheself-OffsetcalibrationschemeenableaveryflatresponseofallDutyCycleCorrectedSampleClockdynamicparametersbeyondNyquist,producingahigh7.
5ENOBwitha250MHzinputsignalandaAPPLICATIONS500MHzsampleratewhileprovidinga10-18B.
E.
R.
OutputformattingisoffsetbinaryandtheLVDSDirectRFDownConversiondigitaloutputsarecompatiblewithIEEE1596.
3-1996,DigitalOscilloscopeswiththeexceptionofanadjustablecommonmodeSatelliteSet-topBoxesvoltagebetween0.
8Vand1.
2V.
CommunicationsSystemsTheconverterhasa1:2demultiplexerthatfeedstwoTestInstrumentationLVDSbusesandreducestheoutputdatarateoneachbustohalfthesamplingrate.
KEYSPECIFICATIONSTheconvertertypicallyconsumeslessthan3.
5mWResolution8BitsinthePowerDownModeandisavailableina128-lead,thermallyenhancedexposedpadHLQFPandMaxConversionRate500MSPS(min)operatesovertheIndustrial(-40°C≤TA≤+85°C)BitErrorRate10-18(typ)temperaturerange.
ENOB@250MHzInput7.
5Bits(typ)DNL±0.
15LSB(typ)PowerConsumption–Operating0.
8W(typ)–PowerDownMode3.
5mW(typ)1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2007–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
ti.
comBlockDiagramFigure1.
2SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013PinConfiguration*Exposedpadonbackofpackagemustbesolderedtogroundplanetoensureratedperformance.
Figure2.
128-LeadHLQFPSeeNNB0128APackageCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comPINDESCRIPTIONSANDEQUIVALENTCIRCUITSPinFunctionsPinNo.
SymbolEquivalentCircuitDescriptionOutputVoltageAmplitudeandSerialInterfaceClock.
TiethispinhighfornormaldifferentialDCLKanddataamplitude.
Groundthispinforareduceddifferentialoutputamplitudeandreducedpowerconsumption.
SeeTheLVDSOutputs.
When3OutV/SCLKtheextendedcontrolmodeisenabled,thispinfunctionsastheSCLKinputwhichclocksintheserialdata.
SeeNORMAL/EXTENDEDCONTROLfordetailsontheextendedcontrolmode.
SeeTHESERIALINTERFACEfordescriptionoftheserialinterface.
DCLKEdgeSelect,DoubleDataRateEnableandSerialDataInput.
ThisinputsetstheoutputedgeofDCLK+atwhichtheoutputdatatransitions.
WhenthispinisfloatingorconnectedtoOutEdge/DDR/1/2thesupplyvoltage,DDRclockingisenabled.
SeeDouble4SDATADataRate.
Whentheextendedcontrolmodeisenabled,thispinfunctionsastheSDATAinput.
SeeNORMAL/EXTENDEDCONTROLfordetailsontheextendedcontrolmode.
SeeTHESERIALINTERFACEfordescriptionoftheserialinterface.
DCLKReset.
Apositivepulseonthispinisusedtoresetand15DCLK_RSTsynchronizetheDCLKoutsofmultipleconverters.
SeeMULTIPLEADCSYNCHRONIZATIONfordetaileddescription.
PowerDownPin.
AlogichighonthePDpinputstheentire26PDdeviceintothePowerDownMode.
CalibrationCycleInitiate.
AminimumtCAL_LinputclockcycleslogiclowfollowedbyaminimumoftCAL_Hinputclockcycles30CALhighonthispininitiatestheselfcalibrationsequence.
SeeSelfCalibrationforanoverviewofself-calibrationandOn-CommandCalibrationforadescriptionofon-commandcalibration.
FullScaleRangeSelectandExtendedControlEnable.
Innon-extendedcontrolmode,alogiclowonthispinsetsthefull-scaledifferentialinputrangetoareducedVINinputlevel.
Alogichighonthispinsetsthefull-scaledifferentialinputrangetoahigherVINinputlevel.
SeeConverterElectricalCharacteristics.
To14FSR/ECEenabletheextendedcontrolmode,wherebytheserialinterfaceandcontrolregistersareemployed,allowthispintofloatorconnectittoavoltageequaltoVA/2.
SeeNORMAL/EXTENDEDCONTROLforinformationontheextendedcontrolmode.
CalibrationDelayandSerialInterfaceChipSelect.
Withalogichighorlowonpin14,thispinfunctionsasCalibrationDelayandsetsthenumberofclockcyclesafterpowerupbefore127CalDly/SCScalibrationbegins.
SeeSelf-Calibration.
Withpin14floating,thispinactsastheenablepinfortheserialinterfaceinputandtheCalDlyvaluebecomes"0"(shortdelaywithnoprovisionforalongpower-upcalibrationdelay).
4SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013PINDESCRIPTIONSANDEQUIVALENTCIRCUITS(continued)PinFunctionsPinNo.
SymbolEquivalentCircuitDescriptionLVDSClockinputpinsfortheADC.
Thedifferentialclocksignalmustbea.
c.
coupledtothesepins.
Theinputsignalissampled18CLK+onthefallingedgeofCLK+.
SeeAcquiringtheInputfora19CLK-descriptionofacquiringtheinputandTHECLOCKINPUTSforanoverviewoftheclockinputs.
AnalogsignalinputstotheADC.
Thedifferentialfull-scaleinputrangeofthisinputisprogrammableusingtheFSRpin14innormalmodeandtheInputFull-ScaleVoltageAdjustregisterin11VIN+theextendedcontrolmode.
RefertotheVINspecificationinthe10VINConverterElectricalCharacteristicsforthefull-scaleinputrangeinthenormalmode.
RefertoREGISTERDESCRIPTIONforthefull-scaleinputrangeintheextendedcontrolmode.
CommonModeVoltage.
Thispinisthecommonmodeoutputind.
c.
couplingmodeandalsoservesasthea.
c.
couplingmodeselectpin.
Whend.
c.
couplingisused,thevoltageoutputatthispinisrequiredtobethecommonmodeinputvoltageatVIN+7VCMOandVINwhend.
c.
couplingisused.
Thispinshouldbegroundedwhena.
c.
couplingisusedattheanaloginputs.
Thispiniscapableofsourcingorsinking100μA.
SeeTHEANALOGINPUT.
31VBGBandgapoutputvoltagecapableof100μAsource/sink.
CalibrationRunningindication.
Thispinisatalogichighwhen126CalRuncalibrationisrunning.
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comPINDESCRIPTIONSANDEQUIVALENTCIRCUITS(continued)PinFunctionsPinNo.
SymbolEquivalentCircuitDescriptionExternalbiasresistorconnection.
32REXTNominalvalueis3.
3kOhms(±0.
1%)toground.
SeeSelf-Calibration.
TemperatureDiodePositive(Anode)andNegative(Cathode).
34Tdiode_PThesepinsmaybeusedfordietemperaturemeasurements,35Tdiode_Nhowevernospecifiedaccuracyisimpliedorensured.
SeeThermalManagement.
83D7-84D7+85D6-86D6+89D5-90D5+91D4-InputchannelLVDSDataOutputsthatarenotdelayedinthe92D4+outputdemultiplexer.
ComparedwiththeDdoutputs,these93D3-outputsrepresentthelatertimesamples.
Theseoutputsshould94D3+alwaysbeterminatedwitha100differentialresistor.
95D2-96D2+100D1-101D1+102D0-103D0+104Dd7-105Dd7+106Dd6-107Dd6+111Dd5-112Dd5+113Dd4-InputchannelLVDSDataOutputsthataredelayedbyoneCLK114Dd4+cycleintheoutputdemultiplexer.
ComparedwiththeDoutputs,115Dd3-theseoutputsrepresenttheearliertimesample.
Theseoutputs116Dd3+shouldalwaysbeterminatedwitha100differentialresistor.
117Dd2-118Dd2+122Dd1-123Dd1+124Dd0-125Dd0+6SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013PINDESCRIPTIONSANDEQUIVALENTCIRCUITS(continued)PinFunctionsPinNo.
SymbolEquivalentCircuitDescriptionOutOfRangeoutput.
Adifferentialhighatthesepinsindicatesthatthedifferentialinputisoutofrange(outsidetherange79OR+±VIN/2asprogrammedbytheFSRpininnon-extendedcontrol80OR-modeortheInputFull-ScaleVoltageAdjustregistersettingintheextendedcontrolmode).
DifferentialClockoutputsusedtolatchtheoutputdata.
Delayedandnon-delayeddataoutputsaresuppliedsynchronoustothis82DCLK+signal.
Thissignalisat1/2theinputclockrateinSDRmode81DCLK-andat1/4theinputclockrateintheDDRmode.
TheDCLKoutputsarenotactiveduringacalibrationcycle,thereforethisisnotrecommendedasasystemclock.
2,5,8,13,16,17,20,VAAnalogpowersupplypins.
Bypassthesepinstoground.
25,28,33,12840,51,62,OutputDriverpowersupplypins.
BypassthesepinstoDR73,88,99,VDRGND.
110,1211,6,9,12,21,24,27,GNDGroundreturnforVA.
4142,53,64,74,87,97,DRGNDGroundreturnforVDR.
108,11922,23,29,36–39,43–50,52,54–61,63,NCNoConnection.
Makenoconnectiontothesepins.
65–72,75–78,98,109,120Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comAbsoluteMaximumRatings(1)(2)(3)SupplyVoltage(VA,VDR)2.
2VSupplyDifferenceVDR-VA0Vto100mVVoltageonAnyInputPin(ExceptVIN+,VIN-)0.
15Vto(VA+0.
15V)VoltageonVIN+,VIN-(MaintainingCommonMode)-0.
15Vto2.
5VGroundDifference|GND-DRGND|0Vto100mVInputCurrentatAnyPin(4)±25mAPackageInputCurrent(4)±50mAPowerDissipationatTA=85°C2.
0WESDSusceptibility(5)HumanBodyModel2500VMachineModel250VStorageTemperature65°Cto+150°C(1)AllvoltagesaremeasuredwithrespecttoGND=DRGND=0V,unlessotherwisespecified.
(2)Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposuretoabsolute–maximum–ratedconditionsforextendedperiodsmayaffectdevicereliability.
(3)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityandspecifications.
(4)Whentheinputvoltageatanypinexceedsthepowersupplylimits(thatis,lessthanGNDorgreaterthanVA),thecurrentatthatpinshouldbelimitedto25mA.
The50mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof25mAtotwo.
Thislimitisnotplaceduponthepower,groundanddigitaloutputpins.
(5)Humanbodymodelis100pFcapacitordischargedthrougha1.
5kresistor.
Machinemodelis220pFdischargedthroughZEROOhms.
OperatingRatings(1)(2)AmbientTemperatureRange40°C≤TA≤+85°CSupplyVoltage(VA)+1.
8Vto+2.
0VDriverSupplyVoltage(VDR)+1.
8VtoVAAnalogInputCommonModeVoltageVCMO±50mVVIN+,VIN-VoltageRange(MaintainingCommonMode)0Vto2.
15V(100%dutycycle)0Vto2.
5V(10%dutycycle)GroundDifference(|GND-DRGND|)0VCLKPinsVoltageRange0VtoVADifferentialCLKAmplitude0.
4VP-Pto2.
0VP-P(1)Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposuretoabsolute–maximum–ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)AllvoltagesaremeasuredwithrespecttoGND=DRGND=0V,unlessotherwisespecified.
PackageThermalResistance(1)PackageθJAθJC(TopofPackage)θJ-PAD(ThermalPad)128-LeadExposedPad25°C/W10°C/W2.
8°C/WHLQFP(1)SolderingprocessmustcomplywithTI'sReflowTemperatureProfilespecifications.
Refertowww.
TI.
com/packaging.
Reflowtemperatureprofilesaredifferentforlead-freeandnon-lead-freepackages.
8SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013ConverterElectricalCharacteristicsThefollowingspecificationsapplyaftercalibrationforVA=VDR=+1.
9VDC,OutV=1.
9V,VINFSR(a.
c.
coupled)=differential870mVP-P,CL=10pF,Differential,a.
c.
coupledSinewaveInputClock,fCLK=500MHzat0.
5VP-Pwith50%dutycycle,VBG=Floating,Non-ExtendedControlMode,SDRMode,REXT=3300±0.
1%,AnalogSignalSourceImpedance=100ΩDifferential.
BoldfacelimitsapplyforTA=TMINtoTMAX.
AllotherlimitsTA=25°C,unlessotherwisenoted.
See(1)(2)UnitsSymbolParameterConditionsTypical(3)Limits(3)(Limits)STATICCONVERTERCHARACTERISTICSDCCoupled,1MHzSineWaveINLIntegralNon-Linearity±0.
3±0.
9LSB(max)OverRangedDCCoupled,1MHzSineWaveOverDNLDifferentialNon-Linearity±0.
15±0.
6LSB(max)RangedResolutionwithNoMissingCodes8Bits1.
5LSB(min)VOFFOffsetError-0.
50.
5LSB(max)VOFF_ADJInputOffsetAdjustmentRangeExtendedControlMode±45mVPFSEPositiveFull-ScaleError(4)±25mV(max)NFSENegativeFull-ScaleError(4)±25mV(max)FS_ADJFull-ScaleAdjustmentRangeExtendedControlMode±20±15%FSDYNAMICCONVERTERCHARACTERISTICSFPBWFullPowerBandwidth1.
7GHzB.
E.
R.
BitErrorRate10-18Error/SampleGainFlatnessd.
c.
to500MHz±0.
5dBFSfIN=50MHz,VIN=FSR0.
5dB7.
5BitsENOBEffectiveNumberofBitsfIN=124MHz,VIN=FSR0.
5dB7.
57.
1Bits(min)fIN=248MHz,VIN=FSR0.
5dB7.
57.
1Bits(min)fIN=50MHz,VIN=FSR0.
5dB47dBSINADSignal-to-NoisePlusDistortionRatiofIN=124MHz,VIN=FSR0.
5dB4744.
5dB(min)fIN=248MHz,VIN=FSR0.
5dB4744.
5dB(min)fIN=50MHz,VIN=FSR0.
5dB48dBSNRSignal-to-NoiseRatiofIN=124MHz,VIN=FSR0.
5dB47.
545.
3dB(min)fIN=248MHz,VIN=FSR0.
5dB47.
545.
3dB(min)fIN=50MHz,VIN=FSR0.
5dB-55dBTHDTotalHarmonicDistortionfIN=124MHz,VIN=FSR0.
5dB-5647.
5dB(max)fIN=248MHz,VIN=FSR0.
5dB-5647.
5dB(max)(1)Theanaloginputsareprotectedasshownbelow.
InputvoltagemagnitudesbeyondtheAbsoluteMaximumRatingsmaydamagethisdevice.
(2)Toensureaccuracy,itisrequiredthatVAandVDRbewellbypassed.
Eachsupplypinmustbedecoupledwithseparatebypasscapacitors.
Additionally,achievingratedperformancerequiresthatthebacksideexposedpadbewellgrounded.
(3)TypicalfiguresareatTA=25°C,andrepresentmostlikelyparametricnorms.
TestlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
(4)CalculationofFull-ScaleErrorforthisdeviceassumesthattheactualreferencevoltageisexactlyitsnominalvalue.
Full-ScaleErrorforthisdevice,therefore,isacombinationofFull-ScaleErrorandReferenceVoltageError.
SeeTransferCharacteristicFigure4.
ForrelationshipbetweenGainErrorandFull-ScaleError,seeSpecificationDefinitionsforGainError.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comConverterElectricalCharacteristics(continued)ThefollowingspecificationsapplyaftercalibrationforVA=VDR=+1.
9VDC,OutV=1.
9V,VINFSR(a.
c.
coupled)=differential870mVP-P,CL=10pF,Differential,a.
c.
coupledSinewaveInputClock,fCLK=500MHzat0.
5VP-Pwith50%dutycycle,VBG=Floating,Non-ExtendedControlMode,SDRMode,REXT=3300±0.
1%,AnalogSignalSourceImpedance=100ΩDifferential.
BoldfacelimitsapplyforTA=TMINtoTMAX.
AllotherlimitsTA=25°C,unlessotherwisenoted.
See(1)(2)UnitsSymbolParameterConditionsTypical(3)Limits(3)(Limits)fIN=50MHz,VIN=FSR0.
5dB60dB2ndHarmSecondHarmonicDistortionfIN=124MHz,VIN=FSR0.
5dB60dBfIN=248MHz,VIN=FSR0.
5dB60dBfIN=50MHz,VIN=FSR0.
5dB65dB3rdHarmThirdHarmonicDistortionfIN=124MHz,VIN=FSR0.
5dB65dBfIN=248MHz,VIN=FSR0.
5dB65dBfIN=50MHz,VIN=FSR0.
5dB55dBSFDRSpurious-FreedynamicRangefIN=124MHz,VIN=FSR0.
5dB5647.
5dB(min)fIN=248MHz,VIN=FSR0.
5dB5647.
5dB(min)fIN1=121MHz,VIN=FSR7dBIMDIntermodulationDistortion-50dBfIN2=126MHz,VIN=FSR7dB(VIN+)(VIN)>+FullScale255OutofRangeOutputCode(InadditiontoOROutputhigh)(VIN+)(VIN)02pFAnalogInputCapacitance,NormalCINoperation(5)(6)Eachinputpintoground1.
6pF94(min)RINDifferentialInputResistance100106(max)ANALOGOUTPUTCHARACTERISTICS0.
95V(min)VCMOCommonModeOutputVoltageICMO=±100A1.
261.
45V(max)VA=1.
8V0.
60VVCMOinputthresholdtosetDCVCMO_LVLCouplingmodeVA=2.
0V0.
66VCommonModeOutputVoltageTCVCMOTA=40°Cto+85°C118ppm/°CTemperatureCoefficientCLOADMaximumVCMOloadCapacitance80pFVCMO1.
20V(min)VBGBandgapReferenceOutputVoltageIBG=±100A1.
261.
33V(max)BandgapReferenceVoltageTA=40°Cto+85°CTCVBG28ppm/°CTemperatureCoefficientIBG=±100AMaximumBandgapReferenceLoadCLOADVBG80pFCapacitanceTEMPERATUREDIODECHARACTERISTICS192Avs.
12A,71.
23mVTJ=25°CΔVBETemperatureDiodeVoltage192Avs.
12A,85.
54mVTJ=85°C(5)Theanalogandclockinputcapacitancesarediecapacitancesonly.
Additionalpackagecapacitancesof0.
65pFdifferentialand0.
95pFeachpintogroundareisolatedfromthediecapacitancesbyleadandbondwireinductances.
(6)Thisparameterisspecifiedbydesignandisnottestedinproduction.
10SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013ConverterElectricalCharacteristics(continued)ThefollowingspecificationsapplyaftercalibrationforVA=VDR=+1.
9VDC,OutV=1.
9V,VINFSR(a.
c.
coupled)=differential870mVP-P,CL=10pF,Differential,a.
c.
coupledSinewaveInputClock,fCLK=500MHzat0.
5VP-Pwith50%dutycycle,VBG=Floating,Non-ExtendedControlMode,SDRMode,REXT=3300±0.
1%,AnalogSignalSourceImpedance=100ΩDifferential.
BoldfacelimitsapplyforTA=TMINtoTMAX.
AllotherlimitsTA=25°C,unlessotherwisenoted.
See(1)(2)UnitsSymbolParameterConditionsTypical(3)Limits(3)(Limits)CHANNEL-TO-CHANNELCHARACTERISTICSOffsetErrorMatch1LSBPositiveFull-ScaleErrorMatchZerooffsetselectedinControlRegister1LSBNegativeFull-ScaleErrorMatchZerooffsetselectedinControlRegister1LSBPhaseMatching(I,Q)FIN=1.
0GHz<1DegreeCLOCKINPUTCHARACTERISTICS0.
4VP-P(min)SineWaveClock0.
62.
0VP-P(max)VIDDifferentialClockInputLevel0.
4VP-P(min)SquareWaveClock0.
62.
0VP-P(max)IIInputCurrentVIN=0orVIN=VA±1ADifferential0.
02pFCINInputCapacitance(7)(8)Eachinputtoground1.
5pFDIGITALCONTROLPINCHARACTERISTICSVIHLogicHighInputVoltageSee(9)0.
85xVAV(min)VILLogicLowInputVoltageSee(9)0.
15xVAV(max)CINInputCapacitance(8)(10)Eachinputtoground1.
2pFDIGITALOUTPUTCHARACTERISTICS400mVP-P(min)Measureddifferentially,OutV=VA,VBG710=Floating,(11)920mVP-P(max)VODLVDSDifferentialOutputVoltage280mVP-P(min)Measureddifferentially,OutV=GND,510VBG=Floating,(11)720mVP-P(max)ChangeinLVDSOutputSwingΔVODIFF±1mVBetweenLogicLevelsVOSOutputOffsetVoltage,seeFigure3VBG=Floating800mVVOSOutputOffsetVoltage,seeFigure3VBG=VA(11)1200mVOutputOffsetVoltageChangeBetweenΔVOS±1mVLogicLevelsIOSOutputShortCircuitCurrentOutput+&Output-connectedto0.
8V±4mAZODifferentialOutputImpedance100OhmsVOHCal_RunHighleveloutputIOH=-400uA(9)1.
651.
5VVOLCal_RunLowleveloutputIOH=400uA(9)0.
150.
3VPOWERSUPPLYCHARACTERISTICSPD=Low340408mA(max)IAAnalogSupplyCurrentPD=High1.
8mAPD=Low112157mA(max)IDROutputDriverSupplyCurrentPD=High0.
012mA(7)Theanalogandclockinputcapacitancesarediecapacitancesonly.
Additionalpackagecapacitancesof0.
65pFdifferentialand0.
95pFeachpintogroundareisolatedfromthediecapacitancesbyleadandbondwireinductances.
(8)Thisparameterisspecifiedbydesignandisnottestedinproduction.
(9)Thisparameterisspecifiedbydesignand/orcharacterizationandisnottestedinproduction.
(10)Thedigitalcontrolpincapacitancesarediecapacitancesonly.
Additionalpackagecapacitanceof1.
6pFeachpintogroundareisolatedfromthediecapacitancesbyleadandbondwireinductances.
(11)TyingVBGtothesupplyrailwillincreasetheoutputoffsetvoltage(VOS)by400mV(typical),asshownintheVOSspecificationabove.
TyingVBGtothesupplyrailwillalsoaffectthedifferentialLVDSoutputvoltage(VOD),causingittoincreaseby40mV(typical).
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comConverterElectricalCharacteristics(continued)ThefollowingspecificationsapplyaftercalibrationforVA=VDR=+1.
9VDC,OutV=1.
9V,VINFSR(a.
c.
coupled)=differential870mVP-P,CL=10pF,Differential,a.
c.
coupledSinewaveInputClock,fCLK=500MHzat0.
5VP-Pwith50%dutycycle,VBG=Floating,Non-ExtendedControlMode,SDRMode,REXT=3300±0.
1%,AnalogSignalSourceImpedance=100ΩDifferential.
BoldfacelimitsapplyforTA=TMINtoTMAX.
AllotherlimitsTA=25°C,unlessotherwisenoted.
See(1)(2)UnitsSymbolParameterConditionsTypical(3)Limits(3)(Limits)PD=Low0.
81.
0W(max)PDPowerConsumptionPD=High3.
5mWChangeinFullScaleErrorwithchangePSRR1D.
C.
PowerSupplyRejectionRatio30dBinVAfrom1.
8Vto2.
0VPSRR2A.
C.
PowerSupplyRejectionRatio248MHz,50mVP-PridingonVA51dBACELECTRICALCHARACTERISTICSfCLK1MaximumInputClockFrequency500MHz(min)fCLK2MinimumInputClockFrequency200MHz200MHz≤Inputclockfrequency≤80020%(min)InputClockDutyCycle50MHz(12)80%(max)tCLInputClockLowTimeSee(12)500400ps(min)tCHInputClockHighTimeSee(12)500400ps(min)45%(min)DCLKDutyCycleSee(12)5055%(max)tRSResetSetupTimeSee(12)150pstRHResetHoldTimeSee(12)250psSynchronizingEdgetoDCLKOutputtSDtOD+tOSKDelayCLK±CyclestRPWResetPulseWidthSee(13)4(min)tLHTDifferentialLowtoHighTransitionTime10%to90%,CL=2.
5pF250pstHLTDifferentialHightoLowTransitionTime10%to90%,CL=2.
5pF250ps50%ofDCLKtransitionto50%ofDatatOSKDCLKtoDataOutputSkewtransition,SDRMode±50ps(max)andDDRMode,0°DCLK(12)tSUDatatoDCLKSet-UpTimeDDRMode,90°DCLK(12)1.
7nstHDCLKtoDataHoldTimeDDRMode,90°DCLK(12)1.
9nstADSampling(Aperture)DelayInputCLK+FalltoAcquisitionofData1.
3nstAJApertureJitter0.
4psrmsInputClocktoDataOutputDelay(in50%ofInputClocktransitionto50%oftOD3.
1nsadditiontoPipelineDelay)DatatransitionDOutputs13PipelineDelay(Latency)(13)(14)CLK±CyclesDdOutputs14DifferentialVINstepfrom±1.
2Vto0VtoOverRangeRecoveryTime1CLK±CyclegetaccurateconversionPDlowtoRatedAccuracyConversiontWU500ns(Wake-UpTime)fSCLKSerialClockFrequencySee(12)100MHztSSUDatatoSerialClockSetupTimeSee(12)2.
5ns(min)tSHDatatoSerialClockHoldTimeSee(12)1ns(min)SerialClockLowTime4ns(min)SerialClockHighTime4ns(min)tCALCalibrationCycleTime1.
4x105CLK±Cycles(12)Thisparameterisspecifiedbydesignand/orcharacterizationandisnottestedinproduction.
(13)Thisparameterisspecifiedbydesignandisnottestedinproduction.
(14)TheADC08500hastwoLVDSoutputbuses,whicheachclockdataoutatonehalfthesamplerate.
Thedataateachbusisclockedoutatonehalfthesamplerate.
Thesecondbus(D0throughD7)hasapipelinelatencythatisoneclockcyclelessthanthelatencyofthefirstbus(Dd0throughDd7)12SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013ConverterElectricalCharacteristics(continued)ThefollowingspecificationsapplyaftercalibrationforVA=VDR=+1.
9VDC,OutV=1.
9V,VINFSR(a.
c.
coupled)=differential870mVP-P,CL=10pF,Differential,a.
c.
coupledSinewaveInputClock,fCLK=500MHzat0.
5VP-Pwith50%dutycycle,VBG=Floating,Non-ExtendedControlMode,SDRMode,REXT=3300±0.
1%,AnalogSignalSourceImpedance=100ΩDifferential.
BoldfacelimitsapplyforTA=TMINtoTMAX.
AllotherlimitsTA=25°C,unlessotherwisenoted.
See(1)(2)UnitsSymbolParameterConditionsTypical(3)Limits(3)(Limits)CLK±CyclestCAL_LCALPinLowTimeSeeFigure11(13)80(min)CLK±CyclestCAL_HCALPinHighTimeSeeFigure11(13)80(min)CalDly=LowCLK±Cycles225SeeSelf-Calibration,Figure11,(15)(min)CalibrationdelaydeterminedbyCalDlytCalDly(pin127)CalDly=HighCLK±Cycles231SeeSelf-Calibration,Figure11,(15)(max)(15)TyingVBGtothesupplyrailwillincreasetheoutputoffsetvoltage(VOS)by400mV(typical),asshownintheVOSspecificationabove.
TyingVBGtothesupplyrailwillalsoaffectthedifferentialLVDSoutputvoltage(VOD),causingittoincreaseby40mV(typical).
SpecificationDefinitionsAPERTURE(SAMPLING)DELAYistheamountofdelay,measuredfromthesamplingedgeoftheCLKinput,afterwhichthesignalpresentattheinputpinissampledinsidethedevice.
APERTUREJITTER(tAJ)isthevariationinaperturedelayfromsampletosample.
Aperturejittershowsupasinputnoise.
BitErrorRate(B.
E.
R.
)istheprobabilityoferrorandisdefinedastheprobablenumberofworderrorsontheADCoutputperunitoftimedividedbythenumberofwordsseeninthatamountoftime.
AB.
E.
R.
of10-18correspondstoastatisticalerrorinonewordabouteveryfour(4)years.
CLOCKDUTYCYCLEistheratioofthetimethattheclockwaveformisatalogichightothetotaltimeofoneclockperiod.
DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB.
Measuredatsamplerate=500MSPSwitha1MHzinputsinewave.
EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionRatio,orSINAD.
ENOBisdefinedas(SINAD1.
76)/6.
02andsaysthattheconverterisequivalenttoaperfectADCofthis(ENOB)numberofbits.
FULLPOWERBANDWIDTH(FPBW)isameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput.
GAINERRORisthedeviationfromtheidealslopeofthetransferfunction.
ItcanbecalculatedfromOffsetandFull-ScaleErrors:PositiveGainError=OffsetErrorPositiveFull-ScaleErrorNegativeGainError=(OffsetErrorNegativeFull-ScaleError)GainError=NegativeFull-ScaleErrorPositiveFull-ScaleError=PositiveGainError+NegativeGainErrorINTEGRALNON-LINEARITY(INL)isameasureofworstcasedeviationoftheADCtransferfunctionfromanidealstraightlinedrawnthroughtheADCtransferfunction.
Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevaluestep.
Thebestfitmethodisused.
INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalspectralcomponentsasaresultoftwosinusoidalfrequenciesbeingappliedtotheADCinputatthesametime.
Itisdefinedastheratioofthepowerinthesecondandthirdorderintermodulationproductstothepowerinoneoftheoriginalfrequencies.
IMDisusuallyexpressedindBFS.
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comLSB(LEASTSIGNIFICANTBIT)isthebitthathasthesmallestvalueorweightofallbits.
ThisvalueisVFS/2nwhereVFSisthedifferentialfull-scaleamplitudeVINassetbytheFSRinput"n"istheADCresolutioninbits,whichis8fortheADC08500.
(1)LVDSDIFFERENTIALOUTPUTVOLTAGE(VOD)istheabsolutevalueofthedifferencebetweentheVD+&VD-outputs;eachmeasuredwithrespecttoGround.
Figure3.
LVDSOUTPUTOFFSETVOLTAGE(VOS)isthemidpointbetweentheD+andD-pinsoutputvoltagereferencedtoground.
i.
e.
,[(VD+)+(VD-)]/2.
MISSINGCODESarethoseoutputcodesthatareskippedandwillneverappearattheADCoutputs.
Thesecodescannotbereachedwithanyinputvalue.
MSB(MOSTSIGNIFICANTBIT)isthebitthathasthelargestvalueorweight.
Itsvalueisonehalfoffullscale.
NEGATIVEFULL-SCALEERROR(NFSE)isameasureofhowfarthefirstcodetransitionisfromtheideal1/2LSBaboveadifferential-VIN/2.
FortheADC08500thereferencevoltageisassumedtobeideal,sothiserrorisacombinationoffull-scaleerrorandreferencevoltageerror.
OFFSETERROR(VOFF)isameasureofhowfarthemid-scalepointisfromtheidealzerovoltagedifferentialinput.
OffsetError=ActualInputcausingaverageof8ksamplestoresultinanaveragecodeof127.
5.
OUTPUTDELAY(tOD)isthetimedelayafterthefallingedgeofDCLKbeforethedataupdateispresentattheoutputpins.
OVER-RANGERECOVERYTIMEisthetimerequiredafterthedifferentialinputvoltagesgoesfrom±1.
2Vto0Vfortheconvertertorecoverandmakeaconversionwithitsratedaccuracy.
PIPELINEDELAY(LATENCY)isthenumberofclockcyclesbetweeninitiationofconversionandwhenthatdataispresentedtotheoutputdriverstage.
Newdataisavailableateveryclockcycle,butthedatalagstheconversionbythePipelineDelayplusthetOD.
POSITIVEFULL-SCALEERROR(PFSE)isameasureofhowfarthelastcodetransitionisfromtheideal1-1/2LSBbelowadifferential+VIN/2.
FortheADC08500thereferencevoltageisassumedtobeideal,sothiserrorisacombinationoffull-scaleerrorandreferencevoltageerror.
POWERSUPPLYREJECTIONRATIO(PSRR)canbeoneoftwospecifications.
PSRR1(DCPSRR)istheratioofthechangeinfull-scaleerrorthatresultsfromapowersupplyvoltagechangefrom1.
8Vto2.
0V.
PSRR2(ACPSRR)isameasureofhowwellana.
c.
signalridinguponthepowersupplyisrejectedfromtheoutputandismeasuredwitha248MHz,50mVP-Psignalridinguponthepowersupply.
Itistheratiooftheoutputamplitudeofthatsignalattheoutputtoitsamplitudeonthepowersupplypin.
PSRRisexpressedindB.
SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignalattheoutputtothermsvalueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,notincludingharmonicsord.
c.
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comSNAS373E–MAY2007–REVISEDAPRIL2013SIGNALTONOISEPLUSDISTORTION(S/(N+D)orSINAD)istheratio,expressedindB,ofthermsvalueoftheinputsignalattheoutputtothermsvalueofalloftheotherspectralcomponentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.
c.
SPURIOUS-FREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthermsvaluesoftheinputsignalattheoutputandthepeakspurioussignal,whereaspurioussignalisanysignalpresentintheoutputspectrumthatisnotpresentattheinput,excludingd.
c.
TOTALHARMONICDISTORTION(THD)istheratioexpressedindB,ofthermstotalofthefirstnineharmoniclevelsattheoutputtothelevelofthefundamentalattheoutput.
THDiscalculatedaswhereAf1istheRMSpowerofthefundamental(output)frequencyAf2throughAf10aretheRMSpowerofthefirst9harmonicfrequenciesintheoutputspectrum.
(2)–SecondHarmonicDistortion(2ndHarm)isthedifference,expressedindB,betweentheRMSpowerintheinputfrequencyseenattheoutputandthepowerinits2ndharmoniclevelattheoutput.
–ThirdHarmonicDistortion(3rdHarm)isthedifferenceexpressedindBbetweentheRMSpowerintheinputfrequencyseenattheoutputandthepowerinits3rdharmoniclevelattheoutput.
TransferCharacteristicFigure4.
Input/OutputTransferCharacteristicCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comTESTCIRCUITDIAGRAMSTimingDiagramsFigure5.
ADC08500Timing—SDRClockingFigure6.
ADC08500Timing—DDRClockingFigure7.
SerialInterfaceTiming16SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013Figure8.
ClockResetTiminginDDRModeFigure9.
ClockResetTiminginSDRModewithOUTEDGELowFigure10.
ClockResetTiminginSDRModewithOUTEDGEHighCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comFigure11.
SelfCalibrationandOn-CommandCalibrationTiming18SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013TypicalPerformanceCharacteristicsVA=VDR=1.
9V,fCLK=500MHz,TA=25°Cunlessotherwisestated.
INLvs.
CODEINLvs.
TEMPERATUREFigure12.
Figure13.
DNLvs.
CODEDNLvs.
TEMPERATUREFigure14.
Figure15.
POWERCONSUMPTIONvs.
SAMPLERATEENOBvs.
TEMPERATUREFigure16.
Figure17.
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comTypicalPerformanceCharacteristics(continued)VA=VDR=1.
9V,fCLK=500MHz,TA=25°Cunlessotherwisestated.
ENOBvs.
SUPPLYVOLTAGEENOBvs.
INPUTFREQUENCYFigure18.
Figure19.
SNRvs.
TEMPERATURESNRvs.
SUPPLYVOLTAGEFigure20.
Figure21.
SNRvs.
INPUTFREQUENCYTHDvs.
TEMPERATUREFigure22.
Figure23.
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comSNAS373E–MAY2007–REVISEDAPRIL2013TypicalPerformanceCharacteristics(continued)VA=VDR=1.
9V,fCLK=500MHz,TA=25°Cunlessotherwisestated.
THDvs.
SUPPLYVOLTAGETHDvs.
INPUTFREQUENCYFigure24.
Figure25.
SFDRvs.
TEMPERATURESFDRvs.
SUPPLYVOLTAGEFigure26.
Figure27.
SFDRvs.
INPUTFREQUENCYSpectralResponseatfIN=98MHzFigure28.
Figure29.
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comTypicalPerformanceCharacteristics(continued)VA=VDR=1.
9V,fCLK=500MHz,TA=25°Cunlessotherwisestated.
SpectralResponseatfIN=248MHzFULLPOWERBANDWIDTHFigure30.
Figure31.
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comSNAS373E–MAY2007–REVISEDAPRIL2013FUNCTIONALDESCRIPTIONTheADC08500isaversatileA/DConverterwithaninnovativearchitecturepermittingveryhighspeedoperation.
Thecontrolsavailableeasetheapplicationofthedevicetocircuitsolutions.
OptimumperformancerequiresadherencetotheprovisionsdiscussedhereandintheApplicationsInformationSection.
Whileitisgenerallypoorpracticetoallowanactivepintofloat,pins4and14oftheADC08500aredesignedtobeleftfloatingwithoutjeopardy.
Inalldiscussionsthroughoutthisdatasheet,wheneverafunctioniscalledbyallowingapintofloat,connectingthatpintoapotentialofonehalftheVAsupplyvoltagewillhavethesameeffectasallowingittofloat.
OVERVIEWTheADC08500usesacalibratedfoldingandinterpolatingarchitecturethatachieves7.
5effectivebits.
Theuseoffoldingamplifiersgreatlyreducesthenumberofcomparatorsandpowerconsumption.
Interpolationreducesthenumberoffront-endamplifiersrequired,minimizingtheloadontheinputsignalandfurtherreducingpowerrequirements.
Inadditiontootherthings,on-chipcalibrationreducestheINLbowoftenseenwithfoldingarchitectures.
Theresultisanextremelyfast,highperformance,lowpowerconverter.
Theanaloginputsignalthatiswithintheconverter'sinputvoltagerangeisdigitizedtoeightbitsatspeedsof200MSPSto500MSPS,typical.
Differentialinputvoltagesbelownegativefull-scalewillcausetheoutputwordtoconsistofallzeroes.
Differentialinputvoltagesabovepositivefull-scalewillcausetheoutputwordtoconsistofallones.
EitheroftheseconditionsattheinputwillcausetheOR(OutofRange)outputtobeactivated.
ThissingleORoutputindicateswhentheoutputcodefromoneorbothofthechannelsisbelownegativefullscaleorabovepositivefullscale.
Theconverterhasa1:2demultiplexerthatfeedstwoLVDSoutputbuses.
ThedataonthesebusesprovideanoutputwordrateoneachbusathalftheADCsamplingrateandmustbeinterleavedbytheusertoprovideoutputwordsatthefullconversionrate.
Theoutputlevelsmaybeselectedtobenormalorreduced.
Usingreducedlevelssavespowerbutcouldresultinerroneousdatacaptureofsomeorallofthebits,especiallyathighersampleratesandinmarginallydesignedsystems.
Self-CalibrationAself-calibrationisperformeduponpower-upandcanalsobeinvokedbytheuseruponcommand.
Calibrationtrimsthe100analoginputdifferentialterminationresistorandminimizesfull-scaleerror,offseterror,DNLandINL,resultinginmaximizingSNR,THD,SINAD(SNDR)andENOB.
Internalbiascurrentsarealsosetwiththecalibrationprocess.
Allofthisistruewhetherthecalibrationisperformeduponpoweruporisperformeduponcommand.
Runningtheselfcalibrationisanimportantpartofthischip'sfunctionalityandisrequiredinordertoobtainadequateperformance.
Inadditiontotherequirementtoberunatpower-up,selfcalibrationmustbere-runwheneverthesenseoftheFSRpinischanged.
Forbestperformance,werecommendthatselfcalibrationberun20secondsormoreafterapplicationofpowerandwhenevertheoperatingtemperaturechangessignificantly,accordingtotheparticularsystemdesignrequirements.
SeeOn-CommandCalibrationformoreinformation.
Calibrationcannotbeinitiatedorrunwhilethedeviceisinthepower-downmode.
SeePowerDownforinformationontheinteractionbetweenPowerDownandCalibration.
Innormaloperation,calibrationisperformedjustafterapplicationofpowerandwheneveravalidcalibrationcommandisgiven,whichisholdingtheCALpinlowforatleasttCAL_Lclockcycles,thenholdithighforatleastanothertCAL_HclockcyclesasdefinedintheConverterElectricalCharacteristics.
ThetimetakenbythecalibrationprocedureisspecifiedastCALinConverterElectricalCharacteristics.
HoldingtheCALpinhighuponpowerupwillpreventthecalibrationprocessfromrunninguntiltheCALpinexperiencestheabove-mentionedtCAL_LclockcyclesfollowedbytCAL_Hclockcycles.
CalDly(pin127)isusedtoselectoneoftwodelaytimesaftertheapplicationofpowerbeforethestartofcalibration.
ThiscalibrationdelaytimeisdepedentonthesettingoftheCalDlypinandisspecifiedastCalDlyintheConverterElectricalCharacteristics.
Thesedelayvaluesallowthepowersupplytocomeupandstabilizebeforecalibrationtakesplace.
IfthePDpinishighuponpower-up,thecalibrationdelaycounterwillbedisableduntilthePDpinisbroughtlow.
Therefore,holdingthePDpinhighduringpowerupwillfurtherdelaythestartofthepower-upcalibrationcycle.
ThebestsettingoftheCalDlypindependsuponthepower-onsettlingtimeofthepowersupply.
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comCalibrationOperationNotes:Duringthecalibrationcycle,theORoutputmaybeactiveasaresultofthecalibrationalgorithm.
AlldataontheoutputpinsandtheORoutputareinvalidduringthecalibrationcycle.
Duringthepower-upcalibrationandduringtheon-commandcalibration,allclocksarehaltedonchip,includinginternalclocksandDCLK,whiletheinputterminationresistoristrimmedtoavaluethatisequaltoREXT/33.
Thisistoreducenoiseduringtheinputresistorcalibrationportionofthecalibrationcycle.
Thisexternalresistorislocatedbetweenpin32andground.
REXTmustbe3300±0.
1%.
Withthisvalue,theinputterminationresistoristrimmedtobe100.
BecauseREXTisalsousedtosetthepropercurrentfortheTrackandHoldamplifier,forthepreamplifiersandforthecomparators,othervaluesofREXTshouldnotbeused.
BecausetheDCLKoutputishaltedduringcalibration,itisrecommendedthatthisDCLKoutputnotbeusedasasystemclock.
TheCalRunoutputishighwheneverthecalibrationprocedureisrunning.
Thisistruewhetherthecalibrationisdoneatpower-uporon-command.
AcquiringtheInputDataisacquiredatthefallingedgeofCLK+(pin18)andthedigitalequivalentofthatdataisavailableatthedigitaloutputs13clockcycleslaterfortheDoutputbusand14clockcycleslaterfortheDdoutputbus.
ThereisanadditionalinternaldelaycalledtODbeforethedataisavailableattheoutputs.
SeetheTimingDiagramsTimingDiagram.
TheADC08500willconvertaslongastheclocksignalispresent.
Thefullydifferentialcomparatordesignandtheinnovativedesignofthesample-and-holdamplifier,togetherwithselfcalibration,enablesaveryflatSINAD/ENOBresponsebeyond500MHz.
TheADC08500outputdatasignalingisLVDSandtheoutputformatisoffsetbinary.
ControlModesMuchoftheusercontrolcanbeaccomplishedwithseveralcontrolpinsthatareprovided.
Examplesincludeinitiationofthecalibrationcycle,powerdownmodeandfullscalerangesetting.
However,theADC08500alsoprovidesanExtendedControlmodewherebyaserialinterfaceisusedtoaccessregister-basedcontrolofseveraladvancedfeatures.
TheExtendedControlmodeisnotintendedtobeenabledanddisableddynamically.
Rather,theuserisexpectedtoemployeitherthenormalcontrolmodeortheExtendedControlmodeatalltimes.
WhenthedeviceisintheExtendedControlmode,pin-basedcontrolofseveralfeaturesisreplacedwithregister-basedcontrolandthosepin-basedcontrolsaredisabled.
ThesepinsareOutV(pin3),OutEdge/DDR(pin4),FSR(pin14)andCalDly(pin127).
SeeNORMAL/EXTENDEDCONTROLfordetailsontheExtendedControlmode.
TheAnalogInputsTheADC08500mustbedrivenwithadifferentialinputsignal.
Operationwithasingle-endedsignalisnotrecommended.
Itisimportantthattheinputseitherbea.
c.
coupledtotheinputswiththeVCMOpingrounded,ord.
c.
coupledwiththeVCMOpinleftfloating.
AninputcommonmodevoltageequaltotheVCMOoutputmustbeprovidedwhend.
c.
couplingisused.
Theinputfull-scalerangeisprogrammableinthenormalmodebysettingalevelonpin14(FSR)asdefinedinbythespecificationVINintheConverterElectricalCharacteristics.
Thefull-scalerangesettingoperatesequallyonbothADCs.
IntheExtendedControlmode,programmingtheInputFull-ScaleVoltageAdjustregisterallowstheinputfull-scalerangetobeadjustedasdescribedinREGISTERDESCRIPTIONandTHEANALOGINPUT.
ClockingTheADC08500mustbedrivenwithana.
c.
coupled,differentialclocksignal.
THECLOCKINPUTSdescribestheuseoftheclockinputpins.
AdifferentialLVDSoutputclockisavailableforuseinlatchingtheADCoutputdataintowhateverreceivesthatdata.
TheADC08500offerstwooptionsforoutputclocking.
TheseoptionsincludeachoiceofwhichDCLKedgetheoutputdatatransitionsonandachoiceofSingleDataRate(SDR)orDoubleDataRate(DDR)outputs.
24SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013TheADC08500alsohastheoptiontouseadutycyclecorrectedclockreceiveraspartoftheinputclockcircuit.
ThisfeatureisenabledbydefaultandprovidesimprovedADCclocking.
ThiscircuitryallowstheADCtobeclockedwithasignalsourcehavingadutycycleratioof20/80%(worstcase).
OutEdgeSettingTohelpeasedatacaptureintheSDRmode,theoutputdatamaybecausedtotransitiononeitherthepositiveorthenegativeedgeoftheoutputdataclock(DCLK).
ThisischosenwiththeOutEdgeinput(pin4).
AhighontheOutEdgeinputcausestheoutputdatatotransitionontherisingedgeofDCLK,whilegroundingthisinputcausestheoutputtotransitiononthefallingedgeofDCLK.
SeeOutputEdgeSynchronization.
DoubleDataRateAchoiceofsingledatarate(SDR)ordoubledatarate(DDR)outputisoffered.
WithsingledataratetheDCLKfrequencyisthesameasthedatarateofthetwooutputbuses.
WithdoubledataratetheDCLKfrequencyishalfthedatarateanddataissenttotheoutputsonbothDCLKedges.
DDRclockingisenabledinnon-ExtendedControlmodebyallowingpin4tofloat.
TheLVDSOutputsThedataoutputs,theOutOfRange(OR)andDCLK,areLVDS.
Outputcurrentsourcesprovide3mAofoutputcurrenttoadifferential100OhmloadwhentheOutVinput(pin14)ishighor2.
2mAwhentheOutVinputislow.
ForshortLVDSlinesandlownoisesystems,satisfactoryperformancemayberealizedwiththeOutVinputlow,whichresultsinlowerpowerconsumption.
IftheLVDSlinesarelongand/orthesysteminwhichtheADC08500isusedisnoisy,itmaybenecessarytotietheOutVpinhigh.
TheLVDSdataoutputhaveatypicalcommonmodevoltageof800mVwhentheVBGpinisunconnectedandfloating.
Thiscommonmodevoltagecanbeincreasedto1.
2VbytyingtheVBGpintoVAifahighercommonmodeisrequired.
NOTETyingtheVBGpintoVAwillalsoincreasethedifferentialLVDSoutputvoltagebyupto40mV.
PowerDownTheADC08500isintheactivestatewhenthePowerDownpin(PD)islow.
WhenthePDpinishigh,thedeviceisinthepowerdownmode,theoutputpinsareputintoahighimpedancestateandthedevicepowerconsumptionisreducedtoaminimallevel.
Uponreturntonormaloperation,thepipelinewillcontainmeaninglessinformation.
IfthePDinputisbroughthighwhileacalibrationisrunning,thedevicewillnotgointopowerdownuntilthecalibrationsequenceiscomplete.
However,ifpowerisappliedandPDisalreadyhigh,thedevicewillnotbeginthecalibrationsequenceuntilthePDinputgoeslow.
Ifamanualcalibrationisrequestedwhilethedeviceispowereddown,thecalibrationwillnotbeginatall.
Thatis,themanualcalibrationinputiscompletelyignoredinthepowerdownstate.
NORMAL/EXTENDEDCONTROLTheADC08500maybeoperatedinoneoftwomodes.
Inthesimpler"normal"controlmode,theuseraffectsavailableconfigurationandcontrolofthedevicethroughseveralcontrolpins.
The"extendedcontrolmode"providesadditionalconfigurationandcontroloptionsthroughaserialinterfaceandasetof3registers.
Thetwocontrolmodesareselectedwithpin14(FSR/ECE:ExtendedControlEnable).
Thechoiceofcontrolmodesisrequiredtobeafixedselectionandisnotintendedtobeswitcheddynamicallywhilethedeviceisoperational.
Table1showshowseveralofthedevicefeaturesareaffectedbythecontrolmodechosen.
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FeaturesandModesFeatureNormalControlModeExtendedControlModeSelectedwithnDEintheConfigurationDDRClockingselectedwithpin4floating.
Register(Addr-1h;bit-10).
WhenthedeviceSDRorDDRClockingSDRclockingselectedwhenpin4notisinDDRmode,address1h,bit-8mustbefloating.
setto0b.
SelectedwithDCPintheConfigurationDDRClockPhaseNotSelectable(0°PhaseOnly)Register(Addr-1h;bit-11).
SDRDatatransitionswithrisingedgeofSDRDatatransitionswithrisingorfallingSelectedwithOEintheConfigurationDCLK+whenpin4ishighandonfallingDCLKedgeRegister(Addr-1h;bit-8).
edgewhenlow.
NormaldifferentialdataandDCLKamplitudeSelectedwiththeOVintheConfigurationLVDSoutputlevelselectedwhenpin3ishighandreducedRegister(Addr-1h;bit-9).
amplitudeselectedwhenlow.
Shortdelayselectedwhenpin127islowandPower-OnCalibrationDelayShortdelayonly.
longerdelayselectedwhenhigh.
Upto512stepadjustmentsoveranominalNormalinputfull-scalerangeselectedwhenrangespecifiedinREGISTERFull-ScaleRangepin14ishighandreducedrangewhenlow.
DESCRIPTION.
SelectedusingtheInputSelectedrangeappliestobothchannels.
Full-ScaleAdjustregister(Addr-3h;bits-7thru15).
512stepsofadjustmentusingtheInputInputOffsetAdjustNotpossibleOffsetregister(Addr-2h;bits-7thru15)asspecifiedinREGISTERDESCRIPTION.
ThedefaultstateoftheExtendedControlModeissetuponpower-onreset(internallyperformedbythedevice)andisshowninTable2.
Table2.
ExtendedControlModeOperation(Pin14Floating)FeatureExtendedControlModeDefaultStateSDRorDDRClockingDDRClockingDDRClockPhaseDatachangeswithDCLKedge(0°phase)NormalamplitudeLVDSOutputAmplitude(710mVP-P)CalibrationDelayShortDelayFull-ScaleRange700mVnominalforbothchannelsInputOffsetAdjustNoadjustmentforeitherchannelTHESERIALINTERFACENOTEDuringtheinitialwriteusingtheserialinterface,all3userregistersmustbewrittenwithdesiredordefaultvalues.
Onceallregistershavebeenwrittenonce,otherdesiredsettingscanbeloaded.
The3-pinserialinterfaceisenabledonlywhenthedeviceisintheExtendedControlmode.
ThepinsofthisinterfaceareSerialClock(SCLK),SerialData(SDATA)andSerialInterfaceChipSelect(SCS).
Threewriteonlyregistersareaccessiblethroughthisserialinterface.
SCS:Thissignalshouldbeassertedlowwhileaccessingaregisterthroughtheserialinterface.
SetupandholdtimeswithrespecttotheSCLKmustbeobserved.
SCLK:Serialdatainputisacceptedattherisingedgeofthissignal.
ThereisnominimumfrequencyrequirementforSCLK.
SDATA:Eachregisteraccessrequiresaspecific32-bitpatternatthisinput.
Thispatternconsistsofaheader,registeraddressandregistervalue.
ThedataisshiftedinMSBfirst.
SetupandholdtimeswithrespecttotheSCLKmustbeobserved.
SeeFigure7.
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comSNAS373E–MAY2007–REVISEDAPRIL2013EachRegisteraccessconsistsof32bits,asshowninFigure7oftheTimingDiagrams.
Thefixedheaderpatternis000000000001(elevenzerosfollowedbya1).
Theloadingsequenceissuchthata"0"isloadedfirst.
These12bitsformtheheader.
Thenext4bitsaretheaddressoftheregisterthatistobewrittentoandthelast16bitsarethedatawrittentotheaddressedregister.
TheaddressesofthevariousregistersareindicatedinTable3.
RefertoREGISTERDESCRIPTIONforinformationonthedatatobewrittentotheregisters.
Subsequentregisteraccessesmaybeperformedimmediately,startingwiththe33rdSCLK.
ThismeansthattheSCSinputdoesnothavetobede-assertedandassertedagainbetweenregisteraddresses.
Itispossible,althoughnotrecommended,tokeeptheSCSinputpermanentlyenabled(atalogiclow)whenusingextendedcontrol.
NOTETheSerialInterfaceshouldnotbewrittentowhencalibratingtheADC.
Doingsowillimpairtheperformanceofthedeviceuntilitisre-calibratedcorrectly.
ProgrammingtheserialregisterswillalsoreducedynamicperformanceoftheADCforthedurationoftheregisteraccesstime.
Table3.
RegisterAddresses4-BitAddressLoadingSequence:A3loadedafterFixedHeaderPattern,A0loadedlastA3A2A1A0HexRegisterAddressed00000hReserved00011hConfiguration00102hInputOffsetInputFull-ScaleVoltage00113hAdjust01004hReserved01015hReserved01106hReserved01117hReserved10008hReserved10019hReserved1010AhReserved1011BhReserved1100ChReserved1101DhReserved1110EhReserved1111FhReservedREGISTERDESCRIPTIONThreewrite-onlyregistersprovideseveralcontrolandconfigurationoptionsintheExtendedControlMode.
TheseregistershavenoeffectwhenthedeviceisintheNormalControlMode.
EachregisterdescriptionbelowalsoshowsthePower-OnReset(POR)stateofeachcontrolbit.
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ConfigurationRegisterAddr:1h(0001b)Wonly(0xB2FF)D15D14D13D12D11D10D9D8101DCSDCPnDEOVOED7D6D5D4D3D2D1D011111111Bit15Mustbesetto1bBit14Mustbesetto0bBit13Mustbesetto1bBit12DCS:DutyCycleStabilizer.
Whenthisbitissetto1b,adutycyclestabilizationcircuitisappliedtotheclockinput.
Whenthisbitissetto0bthestabilizationcircuitisdisabled.
Bit11DCP:DDRClockPhase.
ThisbitonlyhasaneffectintheDDRmode.
Whenthisbitissetto0b,theDCLKedgesaretime-alignedwiththedatabusedges("0°Phase").
Whenthisbitissetto1b,theDCLKedgesareplacedinthemiddleofthedatabit-cells("90°Phase"),usingtheone-halfspeedDCLKshowninFigure6asthephasereference.
PORState:0bBit10nDE:DDREnable.
Whenthisbitissetto0b,databusclockingfollowstheDDR(DualDataRate)modewherebyadatawordisoutputwitheachrisingandfallingedgeofDCLK.
Whenthisbitissettoa1b,databusclockingfollowstheSDR(singledatarate)modewherebyeachdatawordisoutputwitheithertherisingorfallingedgeofDCLK,asdeterminedbytheOutEdgebit.
PORState:0bBit9OV:OutputVoltage.
ThisbitdeterminestheLVDSoutputs'voltageamplitudeandhasthesamefunctionastheOutVpinthatisusedinthenormalcontrolmode.
Whenthisbitissetto1b,thestandardoutputamplitudeof710mVP-Pisused.
Whenthisbitissetto0b,thereducedoutputamplitudeof510mVP-Pisused.
PORState:1bBit8OE:OutputEdge.
ThisbitselectstheDCLKedgewithwhichthedatawordstransitionintheSDRmodeandhasthesameeffectastheOutEdgepininthenormalcontrolmode.
Whenthisbitis1b,thedataoutputschangewiththerisingedgeofDCLK+.
Whenthisbitis0b,thedataoutputchangewiththefallingedgeofDCLK+.
PORState:0bBits7:0Mustbesetto1b.
Table5.
InputOffsetAddr:2h(0010b)Wonly(0x007F)D15D14D13D12D11D10D9D8(MSB)OffsetValue(LSB)D7D6D5D4D3D2D1D0Sign1111111Bits15:8OffsetValue.
TheinputoffsetoftheI-ChannelADCisadjustedlinearlyandmonotonicallybythevalueinthisfield.
00hprovidesanominalzerooffset,whileFFhprovidesanominal45mVofoffset.
Thus,eachcodestepprovides0.
176mVofoffset.
PORState:00000000bBit7Signbit.
0bgivespositiveoffset,1bgivesnegativeoffsetresultingintotaloffsetadjustmentof±45mV.
PORState:0bBit6:0Mustbesetto1b28SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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InputFull-ScaleVoltageAdjustAddr:3h(0011b)Wonly(0x807F)D15D14D13D12D11D10D9D8(MSB)AdjustValueD7D6D5D4D3D2D1D0(LSB)1111111Bit15:7FullScaleVoltageAdjustValue.
Theinputfull-scalevoltageoftheI-ChannelADCisadjustedlinearlyandmonotonicallyfromthenominal700mVP-Pdifferentialbythevalueinthisfield.
000000000560mVP-P100000000700mVP-P111111111840mVP-PForbestperformance,itisrecommendedthatthevalueinthisfieldbelimitedtotherangeof011000000bto111000000b.
i.
e.
,limittheamountofadjustmentto±15%.
Theremaining±5%headroomallowsfortheADC'sownfullscalevariation.
AgainadjustmentdoesnotrequireADCre-calibration.
PORState:100000000b(noadjustment)Bits6:0Mustbesetto1bNoteRegardingExtendedModeOffsetCorrectionWhenusingtheInputchannelOffsetAdjustregister,thefollowinginformationshouldbenoted.
Foroffsetvaluesof+00000000and-00000000,theactualoffsetisnotthesame.
Bychangingonlythesignbitinthiscase,anoffsetstepinthedigitaloutputcodeofabout1/10thofanLSBisexperienced.
ThisisshownmoreclearlyintheFigurebelow.
Figure32.
ExtendedModeOffsetBehaviorMULTIPLEADCSYNCHRONIZATIONTheADC08500hasthecapabilitytopreciselyresetitssamplingclockinputtoDCLKoutputrelationshipasdeterminedbytheuser-suppliedDCLK_RSTpulse.
ThisallowsmultipleADCsinasystemtohavetheirDCLK(anddata)outputstransitionatthesametimewithrespecttothesharedCLKinputthatalltheADCsuseforsampling.
TheDCLK_RSTsignalmustobservesometimingrequirementsthatareshowninFigure8,Figure9,andFigure10oftheTimingDiagrams.
TheDCLK_RSTpulsemustbeofaminimumwidthanditsde-assertionedgemustobservesetupandholdtimeswithrespecttotheCLKinputrisingedge.
ThesetimingspecificationsarelistedastRH,tRS,andtRPWintheConverterElectricalCharacteristicsConverterElectricalCharacteristics.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comTheDCLK_RSTsignalcanbeassertedasynchronoustotheinputclock.
IfDCLK_RSTisasserted,theDCLKoutputisheldinadesignatedstate.
ThestateinwhichDCLKisheldduringtheresetperiodisdeterminedbythemodeofoperation(SDR/DDR)andthesettingoftheOutputEdgeconfigurationpinorbit.
(RefertoFigure8,Figure9,andFigure10fortheDCLKresetconditions).
Therefore,dependinguponwhentheDCLK_RSTsignalisasserted,theremaybeanarrowpulseontheDCLKlineduringthisresetevent.
WhentheDCLK_RSTsignalisde-assertedinsynchronizationwiththeCLKrisingedge,thenextCLKfallingedgesynchronizestheDCLKoutputwiththoseofotherADC08500sinthesystem.
TheDCLKoutputisenabledagainafteraconstantdelaywhichisequaltotheCLKinputtoDCLKoutputdelay(tAD).
Thedevicealwaysexhibitsthisdelaycharacteristicinnormaloperation.
TheDCLK_RSTpinshouldNOTbebroughthighwhilethecalibrationprocessisrunning(whileCalRunishigh).
Doingsocouldcauseadigitalglitchinthedigitalcircuitry,resultingincorruptionandinvalidationofthecalibration.
ApplicationsInformationTHEREFERENCEVOLTAGEThevoltagereferencefortheADC08500isderivedfroma1.
254Vbandgapreferencewhichismadeavailableatpin31,VBG,foruserconvenience.
Thisoutputhasanoutputcurrentcapabilityof±100μAandshouldbebufferedifmorecurrentthanthisisrequired.
Theinternalbandgap-derivedreferencevoltagehasanominalvalueofVIN,asdeterminedbytheFSRpinanddescribedinTheAnalogInputs.
Thereisnoprovisionfortheuseofanexternalreferencevoltage,butthefull-scaleinputvoltagecanbeadjustedthroughaConfigurationRegisterintheExtendedControlmode,asexplainedinNORMAL/EXTENDEDCONTROL.
Differentialinputsignalsuptothechosenfull-scalelevelwillbedigitizedto8bits.
Signalexcursionsbeyondthefull-scalerangewillbeclippedattheoutput.
TheselargesignalexcursionswillalsoactivatetheORoutputforthetimethatthesignalisoutofrange.
SeeOutOfRange(OR)Indication.
OneextrafeatureoftheVBGpinisthatitcanbeusedtoraisethecommonmodevoltageleveloftheLVDSoutputs.
Theoutputoffsetvoltage(VOS)istypically800mVwhentheVBGpinisusedasanoutputorleftunconnected.
ToraisetheLVDSoffsetvoltagetoatypicalvalueof1200mVtheVBGpincanbeconnecteddirectlytothesupplyrails.
THEANALOGINPUTTheanaloginputisadifferentialonetowhichthesignalsourcemaybea.
c.
coupledord.
c.
coupled.
Inthenormalmode,thefull-scaleinputrangeisselectedusingtheFSRpinasspecifiedintheConverterElectricalCharacteristics.
IntheExtendedControlmode,thefull-scaleinputrangeisselectedbyprogrammingtheFull-ScaleVoltageAdjustregisterthroughtheSerialInterface.
Forbestperformancewhenadjustingtheinputfull-scalerangeintheExtendedControl,refertoREGISTERDESCRIPTIONforguidelinesonlimitingtheamountofadjustment.
Table7givestheinputtooutputrelationshipwiththeFSRpinhighwhenthenormal(non-extended)modeisused.
WiththeFSRpingrounded,themillivoltvaluesinTable7arereducedto75%ofthevaluesindicated.
IntheExtendedControlMode,thesevalueswillbedeterminedbythefullscalerangeandoffsetsettingsintheControlRegisters.
Table7.
DIFFERENTIALINPUTTOOUTPUTRELATIONSHIP(Non-ExtendedControlMode,FSRHigh)VIN+VINOutputCodeVCM217.
5mVVCM+217.
5mV00000000VCM109mVVCM+109mV0100000001111111/VCMVCM10000000VCM+109mVVCM109mV11000000VCM+217.
5mVVCM217.
5mV1111111130SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013ThebufferedanaloginputssimplifythetaskofdrivingtheseinputsandtheRCpolethatisgenerallyusedatsamplingADCinputsisnotrequired.
IfitisdesiredtouseanamplifiercircuitbeforetheADC,usecareinchoosinganamplifierwithadequatenoiseanddistortionperformanceandadequategainatthefrequenciesusedfortheapplication.
Notethataprecised.
c.
commonmodevoltagemustbepresentattheADCinputs.
Thiscommonmodevoltage,VCMO,isprovidedon-chipwhena.
c.
inputcouplingisusedandtheinputsignalisa.
c.
coupledtotheADC.
Whentheinputsarea.
c.
coupled,theVCMOoutputmustbegrounded,asshowninFigure33.
Thiscausestheon-chipVCMOvoltagetobeconnectedtotheinputsthroughon-chip50k-Ohmresistors.
Figure33.
DifferentialInputDriveWhenthed.
c.
coupledmodeisused,acommonmodevoltagemustbeprovidedatthedifferentialinputs.
ThiscommonmodevoltageshouldtracktheVCMOoutputpin.
NotethattheVCMOoutputpotentialwillchangewithtemperature.
Thecommonmodeoutputofthedrivingdeviceshouldtrackthischange.
Full-scaledistortionperformancefallsoffrapidlyastheinputcommonmodevoltagedeviatesfromVCMO.
Thisisadirectresultofusingaverylowsupplyvoltagetominimizepower.
Keeptheinputcommonvoltagewithin50mVofVCMO.
Performanceisasgoodinthed.
c.
coupledmodeasitisinthea.
c.
coupledmode,providedtheinputcommonmodevoltageatbothanaloginputsremainwithin50mVofVCMO.
HandlingSingle-EndedInputSignalsThereisnoprovisionfortheADC08500toadequatelyprocesssingle-endedinputsignals.
Thebestwaytohandlesingle-endedsignalsistoconvertthemtodifferentialsignalsbeforepresentingthemtotheADC.
a.
c.
CoupledInputTheeasiestwaytoaccomplishsingle-endeda.
c.
inputtodifferentiala.
c.
signalisbyusinganappropriatebalun,asshowninFigure34.
Figure34.
Single-EndedtoDifferentialsignalconversionusingabalunFigure34isagenericdepictionofasingle-endedtodifferentialsignalconversionusingabalun.
Thecircuitryspecifictothebalunwilldependuponthetypeofbalunselectedandtheoverallboardlayout.
Itisrecommendedthatthesystemdesignercontactthemanufacturerofthebaluntheyhaveselectedtoaidindesigningthebestperformingsingle-endedtodifferentialconversioncircuitusingthatparticularbalun.
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Therearespecificbalunparametersofwhichthesystemdesignershouldbemindful.
AdesignershouldmatchtheimpedanceoftheiranalogsourcetotheADC08500'son-chip100differentialinputterminationresistor.
TherangeofthisinputterminationresistorisdescribedintheelectricaltableasthespecificationRIN.
Also,thephaseandamplitudebalanceareimportant.
Thelowestpossiblephaseandamplitudeimbalanceisdesiredwhenselectingabalun.
Thephaseimbalanceshouldbenomorethan±2.
5°andtheamplitudeimbalanceshouldbelimitedtolessthan1dBatthedesiredinputfrequencyrange.
Finally,whenselectingabalun,theVSWR(VoltageStandingWaveRatio),bandwidthandinsertionlossofthebalunshouldalsobeconsidered.
TheVSWRaidsindeterminingtheoveralltransmissionlineterminationcapabilityofthebalunwheninterfacingtotheADCinput.
TheinsertionlossshouldbeconsideredsothatthesignalatthebalunoutputiswithinthespecifiedinputrangeoftheADCasdescribedintheConverterElectricalCharacteristicsasthespecificationVIN.
d.
c.
CoupledInputWhend.
c.
couplingtotheADC08500analoginputsisrequired,single-endedtodifferentialconversionmaybeeasilyaccomplishedwiththeLMH6555.
AnexampleofthistypeofcircuitisshowninFigure35.
Insuchapplications,theLMH6555performsthetaskofsingle-endedtodifferentialconversionwhiledeliveringlowdistortionandnoise,aswellasoutputbalance,thatsupportstheoperationoftheADC08500.
ConnectingtheADC08500VCMOpintotheVCM_REFpinoftheLMH6555,throughanappropriatebuffer,willensurethatthecommonmodeinputvoltageisasneededforoptimumperformanceoftheADC08500.
TheLMV321waschosentobufferVCMOforitslowvoltageoperationandreasonableoffsetvoltage.
BesurethatthecurrentdrawnfromtheVCMOoutputdoesnotexceed100μA.
Figure35.
ExampleofServicingtheAnalogInputwithVCMOInFigure35,RADJ-andRADJ+areusedtoadjustthedifferentialoffsetthatcanbemeasuredattheADCinputsVIN+/VIN-.
AnunadjustedpositiveoffsetwithreferencetoVIN-greaterthan|15mV|shouldbereducedwitharesistorintheRADJ-position.
Likewise,anunadjustednegativeoffsetwithreferencetoVIN-greaterthan|15mV|shouldbereducedwitharesistorintheRADJ+position.
Table8givessuggestedRADJ-andRADJ+valuesforvariousunadjusteddifferentialoffsetstobringtheVIN+/VIN-offsetbacktowithin|15mV|.
Table8.
D.
C.
CoupledOffsetAdjustmentUnadjustedOffsetReadingResistorValue0mVto10mVnoresistorneeded11mVto30mV20.
0k31mVto50mV10.
0k51mVto70mV6.
81k71mVto90mV4.
75k91mVto110mV3.
92k32SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013OutOfRange(OR)IndicationWhentheconversionresultisclippedtheOutofRangeoutputisactivatedsuchthatOR+goeshighandOR-goeslow.
Thisoutputisactiveaslongasaccuratedataoneitherorbothofthebuseswouldbeoutsidetherangeof00htoFFh.
Full-ScaleInputRangeAswithallA/DConverters,theinputrangeisdeterminedbythevalueoftheADC'sreferencevoltage.
ThereferencevoltageoftheADC08500isderivedfromaninternalband-gapreference.
TheFSRpincontrolstheeffectivereferencevoltageoftheADC08500suchthatthedifferentialfull-scaleinputrangeattheanaloginputsisanormalamplitudewiththeFSRpinhigh,orareducedamplitudewithFSRpinlowasdefinedbythespecificationVINintheConverterElectricalCharacteristics.
BestSNRisobtainedwithFSRhigh,butbetterdistortionandSFDRareobtainedwiththeFSRpinlow.
THECLOCKINPUTSTheADC08500hasdifferentialLVDSclockinputs,CLK+andCLK-,whichmustbedrivenwithana.
c.
coupled,differentialclocksignal.
AlthoughtheADC08500istestedanditsperformanceisensuredwithadifferential500MHzclock,ittypicallywillfunctionwellwithclockfrequenciesindicatedintheConverterElectricalCharacteristics.
Theclockinputsareinternallyterminatedandbiased.
TheclocksignalmustbecapacitivelycoupledtotheclockpinsasindicatedinFigure36.
OperationuptothesampleratesindicatedintheConverterElectricalCharacteristicsistypicallypossibleifthemaximumambienttemperaturesindicatedarenotexceeded.
Operatingathighersampleratesthanindicatedforthegivenambienttemperaturemayresultinreduceddevicereliabilityandproductlifetime.
Thisisbecauseofthehigherpowerconsumptionanddietemperaturesathighsamplerates.
Importantalsoforreliabilityisproperthermalmanagement.
SeeThermalManagement.
Figure36.
Differential(LVDS)ClockConnectionThedifferentialClocklinepairshouldhaveacharacteristicimpedanceof100andbeterminatedattheclocksourceinthat(100)characteristicimpedance.
Theclocklineshouldbeasshortandasdirectaspossible.
TheADC08500clockinputisinternallyterminatedwithanuntrimmed100resistor.
Insufficientclocklevelswillresultinpoordynamicperformance.
Excessivelyhighclocklevelscouldcauseachangeintheanaloginputoffsetvoltage.
Toavoidtheseproblems,keeptheclocklevelwithintherangespecifiedasVIDintheConverterElectricalCharacteristics.
ThelowandhightimesoftheinputclocksignalcanaffecttheperformanceofanyA/DConverter.
TheADC08500featuresadutycycleclockcorrectioncircuitwhichcanmaintainperformanceovertemperature.
TheADCwillmeetitsperformancespecificationiftheinputclockhighandlowtimesaremaintainedwithinthedutycyclerangeasspecifiedintheConverterElectricalCharacteristics.
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comHighspeed,highperformanceADCssuchastheADC08500requireaverystableclocksignalwithminimumphasenoiseorjitter.
ADCjitterrequirementsaredefinedbytheADCresolution(numberofbits),maximumADCinputfrequencyandtheinputsignalamplituderelativetotheADCinputfullscalerange.
Themaximumjitter(thesumofthejitterfromallsources)allowedtopreventajitter-inducedreductioninSNRisfoundtobetJ(MAX)=(VIN(P-P)/VINFSR)x(1/(2(N+1)xπxfIN))wheretJ(MAX)isthermstotalofalljittersourcesinsecondsVIN(P-P)isthepeak-to-peakanaloginputsignalVINFSRisthefull-scalerangeoftheADC"N"istheADCresolutioninbitsandfINisthemaximuminputfrequency,inHertz,attheADCanaloginput.
(3)NotethatthemaximumjitterdescribedaboveistheRSSsumofthejitterfromallsources,includingthatintheADCclock,thataddedbythesystemtotheADCclockandinputsignalsandthataddedbytheADCitself.
SincetheeffectivejitteraddedbytheADCisbeyondusercontrol,thebesttheusercandoistokeepthesumoftheexternallyaddedclockjitterandthejitteraddedbytheanalogcircuitrytotheanalogsignaltoaminimum.
InputclockamplitudesabovethosespecifiedintheConverterElectricalCharacteristicsConverterElectricalCharacteristicsmayresultinincreasedinputoffsetvoltage.
Thiswouldcausetheconvertertoproduceanoutputcodeotherthantheexpected127/128whenbothinputpinsareatthesamepotential.
CONTROLPINSSixcontrolpins(withouttheuseoftheserialinterface)provideawiderangeofpossibilitiesintheoperationoftheADC08500andfacilitateitsuse.
ThesecontrolpinsprovideFull-ScaleInputRangesetting,SelfCalibration,CalibrationDelay,OutputEdgeSynchronizationchoice,LVDSOutputLevelchoiceandaPowerDownfeature.
Full-ScaleInputRangeSettingTheinputfull-scalerangecanbeselectedwiththeFSRcontrolinput(pin14)inthenormalmodeofoperation.
TheisspecifiedasVINintheConverterElectricalCharacteristics.
Intheextendedcontrolmode,theinputfull-scalerangemaybeprogrammedusingtheFull-ScaleAdjustVoltageregister.
SeeTHEANALOGINPUTformoreinformation.
SelfCalibrationTheADC08500self-calibrationmustberuntoachievespecifiedperformance.
Thecalibrationprocedureisrunuponpower-upandcanberunanytimeoncommand.
Thecalibrationprocedureisexactlythesamewhetherthereisaclockpresentuponpoweruporiftheclockbeginssometimeafterapplicationofpower.
TheCalRunoutputindicatorishighwhileacalibrationisinprogress.
Itisimportantthatnodigitalactivitytakeplaceonanyofthedigitalinputlinesduringthecalibrationprocess,exceptthattheremustbeastable,constantfrequencyCLKsignalpresentandthatSCLKmaybeactiveiftheEnhancedModeisselected.
Specifically,noneofthefollowingactionsareallowedduringthecalibrationprocess:ChangingOUTVChangingOutEdgeorSDATAsenseChangingbetweenSDRandDDRChangingFSEorECEChangingDCLK_RSTChangingSCSRaisingPDhighRaisingCALhighDoinganyoftheseactionscancausefaultycalibration.
Power-OnCalibrationPower-oncalibrationbeginsafteratimedelayfollowingtheapplicationofpower.
ThistimedelayisdeterminedbythesettingofCalDly,asdescribedinCalibrationDelay,below.
34SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013ThecalibrationprocesswillbenotbeperformediftheCALpinishighatpowerup.
Inthiscase,thecalibrationcyclewillnotbeginuntiltheon-commandcalibrationconditionsaremet.
TheADC08500willfunctionwiththeCALpinheldhighatpowerup,butnocalibrationwillbedoneandperformancewillbeimpaired.
Amanualcalibration,however,maybeperformedafterpoweringupwiththeCALpinhigh.
SeeOn-CommandCalibration.
Theinternalpower-oncalibrationcircuitrycomesupinanunknownlogicstate.
Iftheclockisnotrunningatpowerupandthepoweroncalibrationcircuitryisactive,itwillholdtheanalogcircuitryinpowerdownandthepowerconsumptionwilltypicallybelessthan200mW.
Thepowerconsumptionwillbenormalaftertheclockstarts.
On-CommandCalibrationToinitiateanon-commandcalibration,bringtheCALpinhighforaminimumoftCAL_HinputclockcyclesafterithasbeenlowforaminimumoftCAL_Linputclockcycles.
HoldingtheCALpinhighuponpowerupwillpreventexecutionofpower-oncalibrationuntiltheCALpinislowforaminimumoftCAL_Linputclockcycles,thenbroughthighforaminimumofanothertCAL_Hinputclockcycles.
ThecalibrationcyclewillbegintCAL_HinputclockcyclesaftertheCALpinisthusbroughthigh.
TheCalRunsignalshouldbemonitoredtodeterminewhenthecalibrationcyclehascompleted.
TheminimumtCAL_HandtCAL_Linputclockcyclesequencesarerequiredtoensurethatrandomnoisedoesnotcauseacalibrationtobeginwhenitisnotdesired.
AsmentionedinSelf-Calibrationforbestperformance,aselfcalibrationshouldbeperformed20secondsormoreafterpowerupandrepeatedwhentheoperatingtemperaturechangessignificantlyaccordingtotheparticularsystemperformancerequirements.
ENOBdropsslightlyasjunctiontemperatureincreasesandexecutinganewselfcalibrationcyclewillessentiallyeliminatethechange.
DuringaPower-Oncalibrationcycle,boththeADCandtheinputterminationresistorarecalibrated.
Asdynamicperformancechangesslightlywithjunctiontemperature,anOn-CommandcalibrationcanbeexecutedtobringtheperformanceoftheADCinline.
CalibrationDelayTheCalDlyinput(pin127)isusedtoselectoneoftwodelaytimesaftertheapplicationofpowertothestartofcalibration,asdescribedinSelf-Calibration.
Thecalibrationdelayvaluesallowthepowersupplytocomeupandstabilizebeforecalibrationtakesplace.
Withnodelayorinsufficientdelay,calibrationwouldbeginbeforethepowersupplyisstabilizedatitsoperatingvalueandresultinnon-optimalcalibrationcoefficients.
IfthePDpinishighuponpower-up,thecalibrationdelaycounterwillbedisableduntilthePDpinisbroughtlow.
Therefore,holdingthePDpinhighduringpowerupwillfurtherdelaythestartofthepower-upcalibrationcycle.
ThebestsettingoftheCalDlypindependsuponthepower-onsettlingtimeofthepowersupply.
NotethatthecalibrationdelayselectionisnotpossibleintheExtendedControlmodeandtheshortdelaytimeisused.
OutputEdgeSynchronizationDCLKsignalsareavailabletohelplatchtheconverteroutputdataintoexternalcircuitry.
Theoutputdatacanbesynchronizedwitheitheredgeoftheseclocksignals.
Thatis,theoutputdatatransitioncanbesettooccurwitheithertherisingedgeorthefallingedgeoftheDCLKsignal,sothateitheredgeofthatclocksignalcanbeusedtolatchtheoutputdataintothereceivingcircuit.
WhenOutEdge(pin4)ishigh,theoutputdataissynchronizedwith(changeswith)therisingedgeoftheDCLK+(pin82).
WhenOutEdgeislow,theoutputdataissynchronizedwiththefallingedgeofDCLK+.
AttheveryhighspeedsofwhichtheADC08500iscapable,slightdifferencesinthelengthsoftheclockanddatalinescanmeanthedifferencebetweensuccessfulanderroneousdatacapture.
TheOutEdgepinisusedtocapturedataontheDCLKedgethatbestsuitstheapplicationcircuitandlayout.
LVDSOutputLevelControlTheoutputlevelcanbesettooneoftwolevelswithOutV(pin3).
ThestrengthoftheoutputdriversisgreaterwithOutVhigh.
WithOutVlowthereislesspowerconsumptionintheoutputdrivers,buttheloweroutputlevelmeansdecreasednoiseimmunity.
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comForshortLVDSlinesandlownoisesystems,satisfactoryperformancemayberealizedwiththeFSRinputlow.
IftheLVDSlinesarelongand/orthesysteminwhichtheADC08500isusedisnoisy,itmaybenecessarytotietheFSRpinhigh.
PowerDownFeatureThePowerDownpin(PD)suspendsdeviceoperationandputstheADC08500intoaminimumpowerconsumptionstate.
SeePowerDownfordetailsonthepowerdownfeature.
Thedigitaldata(+/-)outputpinsareputintoahighimpedancestatewhenthePDpinishigh.
Uponreturntonormaloperation,thepipelinewillcontainmeaninglessinformationandmustbeflushed.
IfthePDinputisbroughthighwhileacalibrationisrunning,thedevicewillnotgointopowerdownuntilthecalibrationsequenceiscomplete.
However,ifpowerisappliedandPDisalreadyhigh,thedevicewillnotbeginthecalibrationsequenceuntilthePDinputgoeslow.
Ifamanualcalibrationisrequestedwhilethedeviceispowereddown,thecalibrationwillnotbeginatall.
Thatis,themanualcalibrationinputiscompletelyignoredinthepowerdownstate.
THEDIGITALOUTPUTSTheADC08500demultiplexestheoutputdataoftheADContotwoLVDSoutputbuses.
TheresultsofsuccessiveconversionsstartedontheoddfallingedgesoftheCLK+pinareavailableononeofthetwoLVDSbuses,whiletheresultsofconversionsstartedontheevenfallingedgesoftheCLK+pinareavailableontheotherLVDSbus.
Thismeansthat,thewordrateateachLVDSbusis1/2theADC08500inputclockrateandthetwobusesmustbemultiplexedtoobtaintheentire0.
5GSPSconversionresult.
Sincetheminimumrecommendedinputclockrateforthisdeviceis200MSPS,theeffectiveratecanbereducedtoaslowas100MSPSbyusingtheresultsavailableonjustoneofthethetwoLVDSbusesanda200MHzinputclock,decimatingthe200MSPSdatabytwo.
ThereisoneLVDSoutputclockpair(DCLK+/-)availableforusetolatchtheLVDSoutputsonallbuses.
WhetherthedataissentattherisingorfallingedgeofDCLKisdeterminedbythesenseoftheOutEdgepin,asdescribedinOutputEdgeSynchronization.
DDR(DoubleDataRate)clockingcanalsobeused.
InthismodeawordofdataispresentedwitheachedgeofDCLK,reducingtheDCLKfrequencyto1/4theinputclockfrequency.
SeeTESTCIRCUITDIAGRAMSfordetails.
TheOutVpinisusedtosettheLVDSdifferentialoutputlevels.
SeeLVDSOutputLevelControl.
TheoutputformatisOffsetBinary.
Accordingly,afull-scaleinputlevelwithVIN+positivewithrespecttoVINwillproduceanoutputcodeofallones,afull-scaleinputlevelwithVINpositivewithrespecttoVIN+willproduceanoutputcodeofallzerosandwhenVIN+andVINareequal,theoutputcodewillvarybetweencodes127and128.
POWERCONSIDERATIONSA/Dconvertersdrawsufficienttransientcurrenttocorrupttheirownpowersuppliesifnotadequatelybypassed.
A33Fcapacitorshouldbeplacedwithinaninch(2.
5cm)oftheA/Dconverterpowerpins.
A0.
1FcapacitorshouldbeplacedascloseaspossibletoeachVApin,preferablywithinone-halfcentimeter.
Leadlesschipcapacitorsarepreferredbecausetheyhavelowleadinductance.
TheVAandVDRsupplypinsshouldbeisolatedfromeachothertopreventanydigitalnoisefrombeingcoupledintotheanalogportionsoftheADC.
Aferritechoke,suchastheJWMillerFB20009-3B,isrecommendedbetweenthesesupplylineswhenacommonsourceisusedforthem.
ThePowerSupplyAsisthecasewithallhighspeedconverters,theADC08500shouldbeassumedtohavelittlepowersupplynoiserejection.
AnypowersupplyusedfordigitalcircuitryinasystemwherealotofdigitalpowerisbeingconsumedshouldnotbeusedtosupplypowertotheADC08500.
TheADCsuppliesshouldbethesamesupplyusedforotheranalogcircuitry,ifnotadedicatedsupply.
36SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013Becauseswitchingpowersuppliesproduceringingenergyatfrequenciesmuchhigherthantheirswitchingrate,whichcanimpactthenoiseperformanceofhighfrequencysystems,theuseofsuchsuppliesisnotrecommendedinhighfrequencysystems.
However,realizingthatlinearsuppliesmaynotbepractical,itisimportantthatcarebeexercisedintheplacementandlayoutofanyswitchingsupplies.
ApplicationNoteAN-1149(LiteratureNumberSNVA021)canhelp.
TheADC08500isspecifiedtooperatewithasupplyvoltageof1.
9V±0.
1V.
Itisveryimportanttonotethat,whilethisdevicewillfunctionwithslightlyhighersupplyvoltages,thesehighersupplyvoltagesmayreduceproductlifetime.
Nopinshouldeverhaveavoltageonitthatisinexcessofthesupplyvoltageorbelowgroundbymorethan150mV,notevenonatransientbasis.
Thiscanbeaproblemuponapplicationofpowerandpowershut-down.
Besurethatthesuppliestocircuitsdrivinganyoftheinputpins,analogordigital,donotcomeupanyfasterthandoesthevoltageattheADC08500powerpins.
TheAbsoluteMaximumRatingsshouldbestrictlyobserved,evenduringpowerupandpowerdown.
Apowersupplythatproducesavoltagespikeatturn-onand/orturn-offofpowercandestroytheADC08500.
ThecircuitofFigure37willprovidesupplyovershootprotection.
Manylinearregulatorswillproduceoutputspikingatpower-onunlessthereisaminimumloadprovided.
Activedevicesdrawverylittlecurrentuntiltheirsupplyvoltagesreachafewhundredmillivolts.
Theresultcanbeaturn-onspikethatcandestroytheADC08500,unlessaminimumloadisprovidedforthesupply.
The100resistorattheregulatoroutputprovidesaminimumoutputcurrentduringpower-uptoensurethereisnoturn-onspiking.
InthecircuitofFigure37,anLM317linearregulatorissatisfactoryifitsinputsupplyvoltageis4Vto5V.
Ifa3.
3Vsupplyisused,anLM1086linearregulatorisrecommended.
Figure37.
Non-SpikingPowerSupplyTheoutputdriversshouldhaveasupplyvoltage,VDR,thatiswithintherangespecifiedintheOperatingRatingstable.
ThisvoltageshouldnotexceedtheVAsupplyvoltage.
Ifthepowerisappliedtothedevicewithoutaclocksignalpresent,thecurrentdrawnbythedevicemightbebelow200mA.
ThisisbecausetheADC08500getsresetthroughclockedlogicanditsinitialstateisrandom.
Iftheresetlogiccomesupinthe"on"state,itwillcausemostoftheanalogcircuitrytobepowereddown,resultinginlessthan100mAofcurrentdraw.
ThiscurrentisgreaterthanthepowerdowncurrentbecausenotalloftheADCispowereddown.
Thedevicecurrentwillbenormalaftertheclockisestablished.
ThermalManagementTheADC08500iscapableofimpressivespeedsandperformanceatverylowpowerlevelsforitsspeed.
However,thepowerconsumptionisstillhighenoughtorequireattentiontothermalmanagement.
Forreliabilityreasons,thedietemperatureshouldbekepttoamaximumof130°C.
Thatis,TA(ambienttemperature)plusADCpowerconsumptiontimesθJA(junctiontoambientthermalresistance)shouldnotexceed130°C.
Thisisnotaproblemiftheambienttemperatureiskepttoamaximumof+85°CasspecifiedintheOperatingRatingssection.
PleasenotethatthefollowingaregeneralrecommendationsformountingexposedpaddevicesontoaPCB.
ThisshouldbeconsideredthestartingpointinPCBandassemblyprocessdevelopment.
Itisrecommendedthattheprocessbedevelopedbaseduponpastexperienceinpackagemounting.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback37ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comThepackageoftheADC08500hasanexposedpadonitsbackthatprovidestheprimaryheatremovalpathaswellasexcellentelectricalgroundingtotheprintedcircuitboard.
ThelandpatterndesignforleadattachmenttothePCBshouldbethesameasforaconventionalHLQFP,buttheexposedpadmustbeattachedtotheboardtoremovethemaximumamountofheatfromthepackage,aswellastoensurebestproductparametricperformance.
Tomaximizetheremovalofheatfromthepackage,athermallandpatternmustbeincorporatedonthePCboardwithinthefootprintofthepackage.
Theexposedpadofthedevicemustbesoldereddowntoensureadequateheatconductionoutofthepackage.
Thelandpatternforthisexposedpadshouldbeatleastaslargeasthe5x5mmoftheexposedpadofthepackageandbelocatedsuchthattheexposedpadofthedeviceisentirelyoverthatthermallandpattern.
Thisthermallandpatternshouldbeelectricallyconnectedtoground.
Aclearanceofatleast0.
5mmshouldseparatethislandpatternfromthemountingpadsforthepackagepins.
Figure38.
RecommendedPackageLandPatternSincealargeapertureopeningmayresultinpoorrelease,theapertureopeningshouldbesubdividedintoanarrayofsmalleropenings,similartothelandpatternofFigure38.
Tominimizejunctiontemperature,itisrecommendedthatasimpleheatsinkbebuiltintothePCB.
Thisisdonebyincludingacopperareaofabout2squareinches(6.
5squarecm)ontheoppositesideofthePCB.
Thiscopperareamaybeplatedorsoldercoatedtopreventcorrosion,butshouldnothaveaconformalcoating,whichcouldprovidesomethermalinsulation.
Thermalviasshouldbeusedtoconnectthesetopandbottomcopperareas.
Thesethermalviasactas"heatpipes"tocarrythethermalenergyfromthedevicesideoftheboardtotheoppositesideoftheboardwhereitcanbemoreeffectivelydissipated.
Theuseof9to16thermalviasisrecommended.
Thethermalviasshouldbeplacedona1.
2mmgridspacingandhaveadiameterof0.
30to0.
33mm.
TheseviasshouldbebarrelplatedtoavoidsolderwickingintotheviasduringthesolderingprocessasthiswickingcouldcausevoidsinthesolderbetweenthepackageexposedpadandthethermallandonthePCB.
Suchvoidscouldincreasethethermalresistancebetweenthedeviceandthethermallandontheboard,whichwouldcausethedevicetorunhotter.
Ifitisdesiredtomonitordietemperature,atemperaturesensormaybemountedontheheatsinkareaoftheboardnearthethermalvias.
.
AllowforathermalgradientbetweenthetemperaturesensorandtheADC08500dieofθJ-PADtimestypicalpowerconsumption=2.
8x1.
6=4.
5°C.
Allowingfora5.
5°C(includinganextra1°C)temperaturedropfromthedietothetemperaturesensor,then,wouldmeanthatmaintainingamaximumpadtemperaturereadingof124.
5°Cwillensurethatthedietemperaturedoesnotexceed130°C,assumingthattheexposedpadoftheADC08500isproperlysoldereddownandthethermalviasareadequate.
(Theinaccuracyofthetemperaturesensorisadditionaltotheabovecalculation).
LAYOUTANDGROUNDINGPropergroundingandroutingofallsignalsareessentialtoensureaccurateconversion.
Asinglegroundplaneshouldbeusedinsteadofsplittingthegroundplaneintoanaloganddigitalareas.
38SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013Sincedigitalswitchingtransientsarecomposedlargelyofhighfrequencycomponents,theskineffecttellsusthattotalgroundplanecopperweightwillhavelittleeffectuponthelogic-generatednoise.
Totalsurfaceareaismoreimportantthanistotalgroundplanevolume.
Couplingbetweenthetypicallynoisydigitalcircuitryandthesensitiveanalogcircuitrycanleadtopoorperformancethatmayseemimpossibletoisolateandremedy.
Thesolutionistokeeptheanalogcircuitrywellseparatedfromthedigitalcircuitry.
Highpowerdigitalcomponentsshouldnotbelocatedonornearanylinearcomponentorpowersupplytraceorplanethatservicesanalogormixedsignalcomponentsastheresultingcommonreturncurrentpathcouldcausefluctuationintheanaloginput"ground"returnoftheADC,causingexcessivenoiseintheconversionresult.
Generally,weassumethatanaloganddigitallinesshouldcrosseachotherat90°toavoidgettingdigitalnoiseintotheanalogpath.
Inhighfrequencysystems,however,avoidcrossinganaloganddigitallinesaltogether.
ClocklinesshouldbeisolatedfromALLotherlines,analogANDdigital.
Thegenerallyaccepted90°crossingshouldbeavoidedasevenalittlecouplingcancauseproblemsathighfrequencies.
Bestperformanceathighfrequenciesisobtainedwithastraightsignalpath.
Theanaloginputshouldbeisolatedfromnoisysignaltracestoavoidcouplingofspurioussignalsintotheinput.
ThisisespeciallyimportantwiththelowleveldriverequiredoftheADC08500.
Anyexternalcomponent(e.
g.
,afiltercapacitor)connectedbetweentheconverter'sinputandgroundshouldbeconnectedtoaverycleanpointintheanaloggroundplane.
Allanalogcircuitry(inputamplifiers,filters,etc.
)shouldbeseparatedfromanydigitalcomponents.
DYNAMICPERFORMANCETheADC08500isa.
c.
testedanditsdynamicperformanceisensured.
Tomeetthepublishedspecificationsandavoidjitter-inducednoise,theclocksourcedrivingtheCLKinputmustexhibitlowrmsjitter.
Theallowablejitterisafunctionoftheinputfrequencyandtheinputsignallevel,asdescribedinTHECLOCKINPUTSItisgoodpracticetokeeptheADCclocklineasshortaspossible,tokeepitwellawayfromanyothersignalsandtotreatitasatransmissionline.
Othersignalscanintroducejitterintotheclocksignal.
Theclocksignalcanalsointroducenoiseintotheanalogpathifnotisolatedfromthatpath.
Bestdynamicperformanceisobtainedwhentheexposedpadatthebackofthepackagehasagoodconnectiontoground.
Thisisbecausethispathfromthedietogroundisalowerimpedancethanofferedbythepackagepins.
USINGTHESERIALINTERFACETheADC08500maybeoperatedinthenon-extendedcontrol(non-SerialInterface)modeorintheextendedcontrolmode.
Table9andTable10describethefunctionsofpins3,4,14and127inthenon-extendedcontrolmodeandtheextendedcontrolmode,respectively.
Non-ExtendedControlModeOperationNon-extendedcontrolmodeoperationmeansthattheSerialInterfaceisnotactiveandallcontrollablefunctionsarecontrolledwithvariouspinsettings.
Thatis,thefull-scalerange,thepoweroncalibrationdelay,theoutputvoltageandtheinputcoupling(a.
c.
ord.
c.
).
Thenon-extendedcontrolmodeisusedbysettingpin14highorlow,asopposedtolettingitfloat.
Table9indicatesthepinfunctionsoftheADC08500inthenon-extendedcontrolmode.
Table9.
Non-ExtendedControlModeOperation(Pin14HighorLow)PinLowHighFloating3ReducedVODNormalVODn/a4OutEdge=NegOutEdge=PosDDR127CalDlyShortCalDlyLongn/aExtended14ReducedVINNormalVINControlModeCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback39ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comPin3canbeeitherhighorlowinthenon-extendedcontrolmode.
Pin14mustnotbeleftfloatingtoselectthismode.
SeeNORMAL/EXTENDEDCONTROLformoreinformation.
Pin4canbehighorloworcanbeleftfloatinginthenon-extendedcontrolmode.
Inthenon-extendedcontrolmode,pin4highorlowdefinestheedgeatwhichtheoutputdatatransitions.
SeeOutputEdgeSynchronizationformoreinformation.
Ifthispinisfloating,theoutputclock(DCLK)isaDDR(DoubleDataRate)clock(seeDoubleDataRate)andtheoutputedgesynchronizationisirrelevantsincedataisclockedoutonbothDCLKedges.
40SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500ADC08500www.
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comSNAS373E–MAY2007–REVISEDAPRIL2013Pin127inthenon-extendedcontrolmodesetsthecalibrationdelay.
Pin127isnotdesignedtoremainfloating.
Table10.
ExtendedControlModeOperation(Pin14Floating)PinFunction3SCLK(SerialClock)4SDATA(SerialData)127SCS(SerialInterfaceChipSelect)COMMONAPPLICATIONPITFALLSFailuretowriteallregisterlocationswhenusingextendedcontrolmode.
Whenusingtheserialinterface,all3userregistersmustbewrittenatleastoncewiththedefaultordesiredvaluesbeforecalibrationandsubsequentuseoftheADC.
Onceallregistershavebeenwrittenonce,otherdesiredsettingscanbeloaded.
Drivingtheinputs(analogordigital)beyondthepowersupplyrails.
Fordevicereliability,noinputshouldgomorethan150mVbelowthegroundpinsor150mVabovethesupplypins.
Exceedingtheselimitsonevenatransientbasismaynotonlycausefaultyorerraticoperation,butmayimpairdevicereliability.
Itisnotuncommonforhighspeeddigitalcircuitstoexhibitundershootthatgoesmorethanavoltbelowground.
Controllingtheimpedanceofhighspeedlinesandterminatingtheselinesintheircharacteristicimpedanceshouldcontrolovershoot.
CareshouldbetakennottooverdrivetheinputsoftheADC08500.
Suchpracticemayleadtoconversioninaccuraciesandeventodevicedamage.
Incorrectanaloginputcommonmodevoltageinthed.
c.
coupledmode.
AsdiscussedinTheAnalogInputsandTHEANALOGINPUT,theInputcommonmodevoltagemustremainwithin50mVoftheVCMOoutput,whichhasavariabilitywithtemperaturethatmustalsobetracked.
Distortionperformancewillbedegradediftheinputcommonmodevoltageismorethan50mVfromVCMO.
Usinganinadequateamplifiertodrivetheanaloginput.
UsecarewhenchoosingahighfrequencyamplifiertodrivetheADC08500asmanyhighspeedamplifierswillhavehigherdistortionthanwilltheADC08500,resultinginoverallsystemperformancedegradation.
DrivingtheVBGpintochangethereferencevoltage.
AsmentionedinTHEREFERENCEVOLTAGE,thereferencevoltageisintendedtobefixedbyFSRpinorFull-ScaleVoltageAdjustregistersettings.
Overdrivingthispinwillnotchangethefullscalevalue,butcanotherwiseupsetoperation.
Drivingtheclockinputwithanexcessivelyhighlevelsignal.
TheADCclocklevelshouldnotexceedtheleveldescribedintheOperatingRatingsTableortheinputoffsetcouldchange.
Inadequateclocklevels.
AsdescribedinTHECLOCKINPUTS,insufficientclocklevelscanresultinpoorperformance.
Excessiveclocklevelscouldresultintheintroductionofaninputoffset.
Usingaclocksourcewithexcessivejitter,usinganexcessivelylongclocksignaltrace,orhavingothersignalscoupledtotheclocksignaltrace.
Thiswillcausethesamplingintervaltovary,causingexcessiveoutputnoiseandareductioninSNRperformance.
Failuretoprovideadequateheatremoval.
AsdescribedinThermalManagement,itisimportanttoprovideadequateheatremovaltoensuredevicereliability.
Thiscanbedoneeitherwithadequateairflowortheuseofasimpleheatsinkbuiltintotheboard.
Thebacksidepadshouldbegroundedforbestperformance.
Copyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback41ProductFolderLinks:ADC08500ADC08500SNAS373E–MAY2007–REVISEDAPRIL2013www.
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comREVISIONHISTORYChangesfromRevisionD(April2013)toRevisionEPageChangedlayoutofNationalDataSheettoTIformat4142SubmitDocumentationFeedbackCopyright2007–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC08500PACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesADC08500CIYB/NOPBACTIVEHLQFPNNB12860RoHS&GreenSNLevel-3-260C-168HR-40to85ADC08500CIYB(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
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