29.www.165aa.com

TAS5721www.
ti.
comSLOS739–JULY2012DigitalAudioPowerAmplifierwithEQ,DRC,2.
1Support,andHeadphone/LineDriverCheckforSamples:TAS57211FEATURES23AudioInput/Output–AutomaticSampleRateDetection–10Wx2into8ΩWithPVDD=24V–ThermalandShort-CircuitProtection–8Wx2+12Wx1into8WithPVDD=24–WidePVDDSupplyRange(4.
5Vto24V)VAPPLICATIONS–Supports2.
0,SingleDevice2.
1,andMonoModesLED/LCDTVs,Soundbar,DockingStations,PCSpeakers–Supports8-kHzto48-kHzSampleRate(LJ/RJ/I2S)OutputPowervs.
PVDDin2.
0Mode–IntegratedDirectPathHeadphoneAmplifierand2VRMSLineDriverAudio/PWMProcessing–IndependentChannelVolumeControlsWith24-dBtoMutein0.
5dBSteps–SeparateDynamicRangeControlforSatelliteandSubChannels–21ProgrammableBiquadsforSpeakerEQ–ProgrammableTwo-BandDynamicRangeControl–Supportfor3DEffectsGeneralFeatures–I2CSerialControlInterfaceOperationalWithoutMCLK–ConfigurableI2CAddress(0x34or0x36)1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2DirectPath,FilterProaretrademarksofTexasInstruments.
3I2CisatrademarkofPhilipsSemiconductorCorp.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2012,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
TAS5721SLOS739–JULY2012www.
ti.
comThesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
DESCRIPTIONTheTAS5721isanefficient,digital-inputaudioamplifierfordriving2.
0speakersystemsconfiguredasabridgetiedload(BTL),2.
1systemswithtwosatellitespeakersandonesubwoofer,orinPBTLsystemsdrivingasinglespeakerconfiguredasaparallelbridgetiedload(PBTL).
OneserialdatainputallowsprocessingofuptotwodiscreteaudiochannelsandseamlessintegrationtomostdigitalaudioprocessorsandMPEGdecoders.
Thedeviceacceptsawiderangeofinputdataformatsandsamplerates.
Afullyprogrammabledatapathroutesthesechannelstotheinternalspeakerdrivers.
TheTAS5721isaslave-onlydevice,receivingallclocksfromexternalsources.
TheTAS5721operateswithaPWMcarrierfrequencybetweena384-kHzswitchingrateanda288-KHzswitchingrate,dependingontheinputsamplerate.
Oversampling,combinedwithafourth-ordernoiseshaper,providesaflatnoisefloorandexcellentdynamicrangefrom20Hzto20kHz.
AnintegratedgroundcenteredDirectPathcombinationheadphoneamplifierand2VRMSlinedriverisintegratedintheTAS5721.
Figure1.
DAPProcessStructure2SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012PINASSIGNMENTANDDESCRIPTIONSPinOutPINTYPE(1)TERMINATIONDESCRIPTIONNAMENO.
ADR/FAULT20DI/DO-DualfunctionterminalwhichsetstheLSBoftheI2Caddressto0ifpulledtoGND,1ifpulledtoDVDD.
IfconfiguredtobeafaultoutputbythemethodsdescribedinICAddressSelectionandFaultOutput,thisterminalispulledlowwhenaninternalfaultoccurs.
Apull-uporpull-downresistorisrequired,asisshownintheTypicalApplicationCircuitDiagrams.
AGND36P-Groundreferenceforanalogcircuitry(2)AVDD19P-PowersupplyforinternalanalogcircuitryAVDD_REG118P-VoltageregulatorderivedfromAVDDsupply(3)AVDD_REG237P-VoltageregulatorderivedfromAVDDsupply(3)BSTRPx3,42,46,P-Connectionpointsforthebootstrapcapacitors,whichareusedtocreatea47powersupplyforthehigh-sidegatedriveofthedeviceDGND35P-Groundreferencefordigitalcircuitry(2)DR_CN12P-NegativeterminalforcapacitorconnectionusedinheadphoneamplifierandlinedriverchargepumpDR_CP13P-PositiveterminalforcapacitorconnectionusedinheadphoneamplifierandlinedriverchargepumpDR_INx7,10AI-InputforchannelAorBofheadphoneamplifierorlinedriver(1)TYPE:A=analog;D=3.
3-Vdigital;P=power/ground/decoupling;I=input;O=output(2)Thisterminalshouldbeconnectedtothesystemground(3)Thisterminalisprovidedasaconnectionpointforfilteringcapacitorsforthissupplyandmustnotbeusedtopoweranyexternalcircuitry.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comPinOut(continued)DR_OUTx8,9AO-OutputforchannelAorBofheadphoneamplifierorlinedriverDR_SD39DI-Placestheheadphoneamplifier/linedriverinshutdownwhenpulledlow.
DR_VSS11P-NegativesupplygeneratedbychargepumpforgroundcenteredheadphoneandlinedriveroutputDRVDD14P-PowersupplyforinternalheadphoneandlinedrivercircuitryDVDD34P-PowersupplyfortheinternaldigitalcircuitryDVDD_REG24P-VoltageregulatorderivedfromDVDDsupply(3)GVDD_REG40P-VoltageregulatorderivedfromPVDDsupply(3)LRCLK26DIPulldownWordselectclockforthedigitalsignalthatisactiveontheinputdatalineoftheserialportMCLK21DIPulldownMasterclockusedforinternalclocktreeandsub-circuitandstatemachineclockingNC31--Notconnectedinsidethedevice(allnoconnectterminalsshouldbeconnectedtoground)OSC_GND23P-Groundreferenceforoscillatorcircuitry(thisterminalshouldbeconnectedtothesystemground)OSC_RES22AO-ConnectionpointforoscillatortrimresistorPDN25DIPullupQuickpowerdownofthedevicethatisuseduponanunexpectedlossofPVDDorDVDDpowersupplyinordertoquicklytransitiontheoutputsofthespeakeramplifiertoa50/50dutycycle.
Thisquickpowerdownfeatureavoidstheaudibleanamoliesthatwouldoccurasaresultoflossofeitherofthesupplies.
Ifthispinisusedtoplacethedeviceintoquickpowerdownmode,theRSTpinofthedevicemustbetoggledbeforethedeviceisbroughtoutofquickpowerdown.
PGND1P-Groundreferenceforpowerdevicecircuitry(4)PLL_FLTM16AI/AO-NegativeconnectionpointforthePLLloopfiltercomponentsPLL_FLTP17AI/AO-PositiveconnectionpointforthePLLloopfiltercomponentsPLL_GND15P-GroundreferenceforPLLcircuitry(thisterminalshouldbeconnectedtothesystemground)PowerPAD-P-ThermalandgroundpadthatprovidesbothanelectricalconnectiontothegroundplaneandathermalpathtothePCBforheatdissipation.
Thispadmustbegroundedtothesystemground.
PVDD4,41P-PowersupplyforinternalpowercircuitryRST32DIPullupPlacesthedeviceinresetwhenpulledlowSCL30DI-I2CserialcontrolportclockSCLK27DIPulldownBitclockforthedigitalsignalthatisactiveontheinputdatalineoftheserialdataportSDA29DI/DO-I2CserialcontrolportdataSDIN28DIPulldownDatalinetotheserialdataportSPK_OUTx2,43,45,AO-Speakeramplifieroutputs48SSTIMER38AI-Connectionpointforthecapacitorthatisusedbytheramptimingcircuit,asdescribedinOutputModeandMUXSelectionTEST15DO-UsedbyTIfortestingduringdeviceproduction(thisterminalmustbeleftfloating)TEST26DO-UsedbyTIfortestingduringdeviceproduction(thisterminalmustbeleftfloating)TEST333DI-UsedbyTIfortestingduringdeviceproduction(thisterminalmustbeconnectedtoGND)(4)Thisterminalshouldbeconnectedtothesystemground4SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012TYPICALAPPLICATIONCIRCUITSFigure2.
TypicalApplicationCircuitforMono(PBTL)ConfigurationCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comFigure3.
TypicalApplicationDiagramfor2.
0Configuration6SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012Figure4.
TypicalApplicationDiagramfor2.
1ConfigurationCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
ti.
comABSOLUTEMAXIMUMRATINGSOveroperatingfree-airtemperaturerange(unlessotherwisenoted).
(1)VALUEUNITDVDD,AVDD,DRVDD–0.
3to3.
6VSupplyvoltagePVDD–0.
3to30VDR_INx–0.
3toDRVDD+6VV3.
3-Vdigitalinput–0.
5toDVDD+0.
5Inputvoltage5-Vtolerant(2)digitalinput(exceptMCLK)–0.
5toDVDD+2.
5(3)V5-VtolerantMCLKinput–0.
5toAVDD+2.
5(3)SPK_OUTxtoGND32(4)VBSTRPxtoGND39(4)VOperatingfree-airtemperature0to85°CStoragetemperaturerange,Tstg–40to125°C(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
ThesearestressratingsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditionsisnotimplied.
Exposuretoabsolute-maximumconditionsforextendedperiodsmayaffectdevicereliability.
(2)5-VtolerantinputsarePDN,RST,SCLK,LRCLK,MCLK,SDIN,SDA,andSCL.
(3)Maximumpinvoltageshouldnotexceed6V.
(4)DCvoltage+peakACwaveformmeasuredatthepinshouldbebelowtheallowedlimitforallconditions.
RECOMMENDEDOPERATINGCONDITIONSMINNOMMAXUNITxVDDDigital,analog,headphonesupply33.
33.
6VvoltagePVDDHalf-bridgesupplyvoltage826.
4(1)VVIHHigh-levelinputvoltage5-Vtolerant2VVILLow-levelinputvoltage5-Vtolerant0.
8VTAOperatingambienttemperaturerange085°CTJ(2)Operatingjunctiontemperaturerange0125°CRSPKMinimumSupportedSpeaker(SE,BTL,andOutputfilter:L=15μH,C=330nF48ImpedancePBTL)MinimumoutputinductanceLo(BTL)Output-filterinductance10μHundershort-circuitconditionRHPHeadphonemodeloadimpedance1632ΩRLDLine-divermodeloadimpedance0.
610kΩ(1)ForoperationatPVDDlevelsgreaterthan18V,themodulationlimitmustbesetto93.
8%viathecontrolportregister0x10.
(2)Continuousoperationabovetherecommendedjunctiontemperaturemayresultinreducedreliabilityand/orlifetimeofthedevice.
ELECTRICALCHARACTERISTICSI/OPinCharacteristicsPVDD=18V,AVDD=DRVDD=DVDD=3.
3V,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
PARAMETERTESTCONDITIONSMINTYPMAXUNITIOH=–4mAVOHHigh-leveloutputvoltage2.
4DVDD=AVDD=3VADR/FAULTandSDAVIOL=4mAVOLLow-leveloutputvoltage0.
5DVDD=AVDD=3VVIVIH;DVDD=IIHHigh-levelinputcurrent75AVDD=3.
6V8SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012I/OPinCharacteristics(continued)PVDD=18V,AVDD=DRVDD=DVDD=3.
3V,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
PARAMETERTESTCONDITIONSMINTYPMAXUNITNormalmode48703.
3Vsupplyvoltage(DVDD,IDD3.
3VsupplycurrentmAReset(RST=low,PDNAVDD)2138=high,DR_SD=low)tw(RST)Pulseduration,RSTactiveRST100μstd(I2C_ready)TimebeforetheI2Cportisable12mscommunicateafterRSTgoeshighNOTE:Onpowerup,itisrecommendedthattheTAS5721RSTbeheldLOWforatleast100μsafterDVDDhasreached3V.
NOTE:IfRSTisassertedLOWwhilePDNisLOW,thenRSTmustcontinuetobeheldLOWforatleast100μsafterPDNisdeasserted(HIGH).
Figure5.
ResetTimingMasterClockCharacteristics(1)PVDD=18V,AVDD=DRVDD=DVDD=3.
3V,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
PARAMETERTESTCONDITIONSMINTYPMAXUNITfMCLKMCLKfrequency2.
822424.
576MHzMCLKdutycycle40%50%60%tr(MCLK)/tf(MCLK)Rise/falltimeforMCLK5ns(1)Forclocksrelatedtotheserialaudioport,pleaseseeSerialAudioPortTimingCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comI2CSerialControlPortRequirementsandSpecificationsPVDD=18V,AVDD=DRVDD=DVDD=3.
3V,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
PARAMETERTESTCONDITIONSMINMAXUNITfSCLFrequency,SCLNowaitstates400kHztw(H)Pulseduration,SCLhigh0.
6μstw(L)Pulseduration,SCLlow1.
3μstrRisetime,SCLandSDA300nstfFalltime,SCLandSDA300nstsu1Setuptime,SDAtoSCL100nsth1Holdtime,SCLtoSDA0nst(buf)Busfreetimebetweenstopandstartconditions1.
3μstsu2Setuptime,SCLtostartcondition0.
6μsth2Holdtime,startconditiontoSCL0.
6μstsu3Setuptime,SCLtostopcondition0.
6μsCLLoadcapacitanceforeachbusline400pFFigure6.
SCLandSDATimingFigure7.
StartandStopConditionsTiming10SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012SerialAudioPortTimingPVDD=18V,AVDD=DRVDD=DVDD=3.
3V,audioinputsignal=1kHzsinewave,BTL,ADmode,fS=48kHz,RSPK=8,AES17filter,fPWM=384kHz,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
TESTPARAMETERMINTYPMAXUNITCONDITIONSfSCLKINFrequency,SCLK32*fS,48*fS,64*fSCL=30pF1.
02412.
288MHztsu1Setuptime,LRCLKtoSCLKrisingedge10nsth1Holdtime,LRCLKfromSCLKrisingedge10nstsu2Setuptime,SDINtoSCLKrisingedge10nsth2Holdtime,SDINfromSCLKrisingedge10nsLRCLKfrequency84848kHzSCLKdutycycle40%50%60%LRCLKdutycycle40%50%60%SCLKSCLKrisingedgesbetweenLRCLKrisingedges3264edgest(edge)SCLKLRCLKclockedgewithrespecttothefallingedgeofSCLK–1/41/4periodtr/tfRise/falltimeforSCLK/LRCLK8nsLRCLKallowabledriftbeforeLRCLKreset4MCLKPeriodsFigure8.
SerialAudioPortTimingCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comSpeakerAmplifierCharacteristicsTA=25°C,PVDD=18V,AVDD=DRVDD=DVDD=3.
3V,audioinputsignal=1kHzsinewave,BTL,ADmode,fS=48kHz,RSPK=8,AES17filter,fPWM=384kHz,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
PARAMETERTESTCONDITIONSMINTYPMAXUNITPVDD=18V,RSPK=8Ω,1-kHzinputsignal10PVDD=12V,RSPK=8Ω,10%THD+N,1-kHz8.
8inputsignalPoweroutputperchannelofPVDD=12V,RSPK=8Ω,7%THD+N,1-kHzinputPoSPK8.
3speakeramplifierwhenusedinsignal(BTL)BTLmode(1)PVDD=8V,RSPK=8Ω,10%THD+N,1-kHzinput4signalPVDD=8V,RSPK=8Ω,7%THD+N,1-kHzinput3.
8signalWPVDD=12V,RSPK=4Ω,1010%THD+N,1-kHzinputsignalPoweroutputperchannelofPoSPKPVDD=12V,RSPK=4Ω,speakeramplifierwhenusedin10(PBTL)7%THD+N,1-kHzinputsignalPBTLmode(1)PVDD=18V,RSPK=4Ω,101-kHzinputsignalPVDD=12V,RSPK=4Ω,4.
3Poweroutputperchannelof10%THD+N,1-kHzinputsignalPoSPKspeakeramplifierwhenusedin(SE)PVDD=24V,RSPK=4Ω,SEmode(1)5.
510%THD+N,1-kHzinputsignalPVDD=18V,PO=1W0.
07Totalharmonicdistortion+THD+NPVDD=12V,PO=1W0.
11%noisePVDD=8V,PO=1W0.
2ICNIdlechannelnoiseA-weighted61μVPO=1W,f=1kHz(BDMode),PVDD=24V58dBCrosstalkPO=1W,f=1kHz(ADMode),PVDD=24V48dBA-weighted,f=1kHz,maximumpoweratTHD025/22.
05/44.
1-kHzdatarate±2%352.
8fPWMOutputswitchingfrequencykHz48/24/12/8/16/32-kHzdatarate±2%384Normalmode3250IPVDDSupplycurrentNoload(PVDD)mAReset(RST=low,PDN=58high)Drain-to-sourceresistance(forrDS(on)eachoftheLow-SideandHigh-TJ=25°C,includesmetallizationresistance200mΩSideDevices)InternalpulldownresistorattheConnectedwhendriversareinthehigh-impedanceRPD3kΩoutputofeachhalf-bridgestatetoprovidebootstrapcapacitorcharge.
(1)Powerlevelsarethermallylimited.
(2)SNRiscalculatedrelativeto0-dBFSinputlevel.
12SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012HeadphoneAmplifierandLineDriverCharacteristicsTA=25°C,PVDD=18V,AVDD=DRVDD=DVDD=3.
3V,audioinputsignal=1kHzsinewave,BTL,ADmode,fS=48kHz,RSPK=8,AES17filter,fPWM=384kHz,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
PARAMETERTESTCONDITIONSMINTYPMAXUNITPoHPPoweroutputperchannelofDRVDD=3.
3V(RHP=32;THD=1%)50mWheadphoneamplifierAVDRGainforheadphoneamplifierandlineAdjustablethroughRinandRfb-dBdriverSNRHPSignal-to-noiseratio(headphonemode)Rhp=32101dBSNRLDSignal-to-noiseratio(linedrivermode)2-VRMSoutput105dBProtectionCharacteristicsTA=25°C,PVDD=18V,AVDD=DRVDD=DVDD=3.
3V,audioinputsignal=1kHzsinewave,BTL,ADmode,fS=48kHz,RSPK=8,AES17filter,fPWM=384kHz,externalcomponentsperTypicalApplicationCircuitdiagrams,andinaccordancewithrecommendedoperatingconditions(unlessotherwisespecified).
PARAMETERTESTCONDITIONSMINTYPMAXUNITVuvp(fall)UndervoltageprotectionlimitPVDDfalling4VVuvp(rise)UndervoltageprotectionlimitPVDDrising4.
1VOTEOvertemperatureerrorthreshold150°CΔOTEVariationinovertemperaturedetectioncircuit±15°CIOCEOvercurrentlimitprotectionthreshold3.
0AtOCEOvercurrentresponsetime150nsTHERMALCHARACTERISTICSTAS5721THERMALMETRIC(1)DCAUNITS48PINSθJAJunction-to-ambientthermalresistance(2)27.
9θJCtopJunction-to-case(top)thermalresistance(3)20.
7θJBJunction-to-boardthermalresistance(4)13°C/WψJTJunction-to-topcharacterizationparameter(5)0.
3ψJBJunction-to-boardcharacterizationparameter(6)6.
7θJCbotJunction-to-case(bottom)thermalresistance(7)1.
1(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
(2)Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,high-Kboard,asspecifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a.
(3)Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.
NospecificJEDEC-standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
(4)Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCBtemperature,asdescribedinJESD51-8.
(5)Thejunction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofadeviceinarealsystemandisextractedfromthesimulationdataforobtainingθJA,usingaproceduredescribedinJESD51-2a(sections6and7).
(6)Thejunction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofadeviceinarealsystemandisextractedfromthesimulationdataforobtainingθJA,usingaproceduredescribedinJESD51-2a(sections6and7).
(7)Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.
NospecificJEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
SpacerCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comTYPICALPERFORMANCECHARACTERISTICSSPACERSPACERSPACERSPACEROUTPUTPOWEROUTPUTPOWERvsvsPVDDIN2.
1MODEPVDDINPBTLMODEFigure9.
Figure10.
SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsFREQUENCYIN2.
0MODEWITHPVDD=12VFREQUENCYin2.
0MODEWITHPVDD=18VFigure11.
Figure12.
14SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012TYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsFREQUENCYIN2.
0MODEWITHPVDD=24VFEQUENCYIN2.
1MODEWITHPVDD=12VFigure13.
Figure14.
SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsFREQUENCYIN2.
1MODEWITHPVDD=18VFREQUENCYIN2.
1MODEWITHPVDD=24VFigure15.
Figure16.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comTYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsFREQUENCYINPBTLMODEWITHPVDD=12VFREQUENCYINPBTLMODEWITHPVDD=18VFigure17.
Figure18.
SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISE2.
0IDLECHANNELNOISEvsvsFREQUENCYINPBTLMODEWITHPVDD=24VPVDDFigure19.
Figure20.
16SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012TYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACER2.
1IDLECHANNELNOISEPBTLIDLECHANNELNOISEvsvsPVDDPVDDFigure21.
Figure22.
SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsOUTPUTPOWERIN2.
0MODEWITHPVDD=12VOUTPUTPOWERIN2.
0MODEWITHPVDD=18VFigure23.
Figure24.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comTYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsOUTPUTPOWERIN2.
0MODEWITHPVDD=24VOUTPUTPOWERIN2.
1MODEWITHPVDD=12VFigure25.
Figure26.
SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsOUTPUTPOWERIN2.
1MODEWITHPVDD=18VOUTPUTPOWERIN2.
1MODEWITHPVDD=24VFigure27.
Figure28.
18SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012TYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsOUTPUTPOWERINPBTLMODEWITHPVDD=12VOUTPUTPOWERINPBTLMODEWITHPVDD=18VFigure29.
Figure30.
SPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISEEFFICIENCYvsvsOUTPUTPOWERINPBTLMODEWITHPVDD=24VOUTPUTPOWERIN2.
0MODEAllchannelsdrivenFigure31.
Figure32.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comTYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACEREFFICIENCYEFFICIENCYvsvsOUTPUTPOWERIN2.
1MODEOUTPUTPOWERIN2.
1MODEAllchannelsdrivenAllchannelsdrivenFigure33.
Figure34.
SPACERSPACERSPACERSPACEREFFICIENCYEFFICIENCYvsvsOUTPUTPOWERINPBTLMODEOUTPUTPOWERINPBTLMODEAllchannelsdrivenAllchannelsdrivenFigure35.
Figure36.
20SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012TYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACERCROSSTALKCROSSTALKvsvsFREQUENCYIN2.
0MODEFREQUENCYIN2.
0MODEFigure37.
Figure38.
SPACERSPACERSPACERSPACERCROSSTALKCROSSTALKvsvsFREQUENCYIN2.
0MODEFREQUENCYIN2.
0MODEFigure39.
Figure40.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comTYPICALPERFORMANCECHARACTERISTICS(continued)SPACERSPACERSPACERSPACERCROSSTALKCROSSTALKvsvsFREQUENCYIN2.
1MODEFREQUENCYIN2.
1MODEFigure41.
Figure42.
SPACERSPACERSPACERSPACERCROSSTALKCROSSTALKvsvsFREQUENCYIN2.
1MODEFREQUENCYIN2.
1MODEFigure43.
Figure44.
22SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012HEADPHONETYPICALCHARACTERISTICSSPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISETOTALHARMONICDISTORTION+NOISEvsvsFREQUENCYHEADPHONEWITHDRVDD=3.
3VFREQUENCYHEADPHONEWITHDRVDD=3.
3VFigure45.
Figure46.
SPACERSPACERTOTALHARMONICDISTORTION+NOISEvsOUTPUTPOWERHEADPHONEWITHDRVDD=3.
3VFigure47.
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comLINEDRIVERTYPICALCHARACTERISTICSSPACERSPACERSPACERSPACERTOTALHARMONICDISTORTION+NOISECROSSTALKvsvsOUTPUTVOLTAGEHEADPHONEWITHDRVDD=3.
3VFREQUENCYHEADPHONEWITHDRVDD=3.
3VFigure48.
Figure49.
SPACERSPACERSPACERSPACERCROSSTALKCROSSTALKvsvsFREQUENCYHEADPHONEWITHDRVDD=3.
3VFREQUENCYHEADPHONEWITHDRVDD=3.
3VFigure50.
Figure51.
24SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012SerialControlInterfaceRegisterSummaryNO.
OFDEFAULTSUBADDRESSREGISTERNAMECONTENTSBYTESVALUEAuindicatesunusedbits.
0x00Clockcontrolregister1Descriptionshowninsubsequentsection0x6C0x01DeviceIDregister1Descriptionshowninsubsequentsection0x000x02Errorstatusregister1Descriptionshowninsubsequentsection0x000x03Systemcontrolregister11Descriptionshowninsubsequentsection0xA00x04Serialdatainterface1Descriptionshowninsubsequentsection0x05register0x05Systemcontrolregister21Descriptionshowninsubsequentsection0x400x06Softmuteregister1Descriptionshowninsubsequentsection0x000x07Mastervolume1Descriptionshowninsubsequentsection0xFF(mute)0x08Channel1vol1Descriptionshowninsubsequentsection0x30(0dB)0x09Channel2vol1Descriptionshowninsubsequentsection0x30(0dB)0x0AChannel3vol1Descriptionshowninsubsequentsection0x30(0dB)0x0B–0x0D1Reserved(1)0x0EVolumeconfiguration1Descriptionshowninsubsequentsection0x91register0x0F1Reserved(1)0x10Modulationlimitregister1Descriptionshowninsubsequentsection0x020x11ICdelaychannel11Descriptionshowninsubsequentsection0xAC0x12ICdelaychannel21Descriptionshowninsubsequentsection0x540x13ICdelaychannel31Descriptionshowninsubsequentsection0xAC0x14ICdelaychannel41Descriptionshowninsubsequentsection0x540x15–0x181Reserved(1)0x19PWMchannelshutdown1Descriptionshowninsubsequentsection0x30groupregister0x1AStart/stopperiodregister1Descriptionshowninsubsequentsection0x0F0x1BOscillatortrimregister1Descriptionshowninsubsequentsection0x820x1CBKND_ERRregister1Descriptionshowninsubsequentsection0x020x1D–0x1F1Reserved(1)0x20InputMUXregister4Descriptionshowninsubsequentsection0x000177720x21Ch4sourceselectregister4Descriptionshowninsubsequentsection0x000043030x22–0x244Reserved(1)0x25PWMMUXregister4Descriptionshowninsubsequentsection0x010213450x26–0x284Reserved(1)0x29ch1_bq[0]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x2Ach1_bq[1]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x00000000(1)Reservedregistersshouldnotbeaccessed.
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comNO.
OFDEFAULTSUBADDRESSREGISTERNAMECONTENTSBYTESVALUE0x2Bch1_bq[2]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x2Cch1_bq[3]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x2Dch1_bq[4]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x2Ech1_bq[5]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x2Fch1_bq[6]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x30ch2_bq[0]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x31ch2_bq[1]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x32ch2_bq[2]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x33ch2_bq[3]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x0000000026SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012NO.
OFDEFAULTSUBADDRESSREGISTERNAMECONTENTSBYTESVALUE0x34ch2_bq[4]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x35ch2_bq[5]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x36ch2_bq[6]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x37–0x394Reserved(2)0x3ADRC1ae(3)8u[31:26],ae[25:0]0x00800000DRC1(1–ae)u[31:26],(1–ae)[25:0]0x000000000x3BDRC1aa8u[31:26],aa[25:0]0x00800000DRC1(1–aa)u[31:26],(1–aa)[25:0]0x000000000x3CDRC1ad8u[31:26],ad[25:0]0x00800000DRC1(1–ad)u[31:26],(1–ad)[25:0]0x000000000x3DDRC2ae8u[31:26],ae[25:0]0x00800000DRC2(1–ae)u[31:26],(1–ae)[25:0]0x000000000x3EDRC2aa8u[31:26],aa[25:0]0x00800000DRC2(1–aa)u[31:26],(1–aa)[25:0]0x000000000x3FDRC2ad8u[31:26],ad[25:0]0x00800000DRC2(1–ad)u[31:26],(1–ad)[25:0]0x000000000x40DRC1-T4T1[31:0](9.
23format)0xFDA214900x41DRC1-K4u[31:26],K1[25:0]0x038421090x42DRC1-O4u[31:26],O1[25:0]0x000842100x43DRC2-T4T2[31:0](9.
23format)0xFDA214900x44DRC2-K4u[31:26],K2[25:0]0x038421090x45DRC2-O4u[31:26],O2[25:0]0x000842100x46DRCcontrol4Descriptionshowninsubsequentsection0x000000000x47–0x4F4Reserved(2)0x50Bankswitchcontrol4Descriptionshowninsubsequentsection0x0F7080000x51Ch1outputmixer12Ch1outputmix1[2]0x00800000Ch1outputmix1[1]0x00000000Ch1outputmix1[0]0x000000000x52Ch2outputmixer12Ch2outputmix2[2]0x00800000Ch2outputmix2[1]0x00000000Ch2outputmix2[0]0x00000000(2)Reservedregistersshouldnotbeaccessed.
(3)aestandsfor∝ofenergyfilter,aastandsfor∝ofattackfilterandadstandsfor∝ofdecayfilterand1-∝=ω.
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comNO.
OFDEFAULTSUBADDRESSREGISTERNAMECONTENTSBYTESVALUE0x53Ch1inputmixer16Ch1inputmixer[3]0x00800000Ch1inputmixer[2]0x00000000Ch1inputmixer[1]0x00000000Ch1inputmixer[0]0x008000000x54Ch2inputmixer16Ch2inputmixer[3]0x00800000Ch2inputmixer[2]0x00000000Ch2inputmixer[1]0x00000000Ch2inputmixer[0]0x008000000x55Channel3inputmixer12Channel3inputmixer[2]0x00800000Channel3inputmixer[1]0x00000000Channel3inputmixer[0]0x000000000x56Outputpost-scale4u[31:26],post[25:0]0x008000000x57Outputpre-scale4u[31:26],pre[25:0](9.
17format)0x000200000x58ch1BQ[7]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x59ch1BQ[8]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x5ASubchannelBQ[0]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x5BSubchannelBQ[1]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x5Cch2BQ[7]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x5Dch2BQ[8]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x000000000x5Epseudo_ch2BQ[0]20u[31:26],b0[25:0]0x00800000u[31:26],b1[25:0]0x00000000u[31:26],b2[25:0]0x00000000u[31:26],a1[25:0]0x00000000u[31:26],a2[25:0]0x0000000028SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012NO.
OFDEFAULTSUBADDRESSREGISTERNAMECONTENTSBYTESVALUE0x5F4Reserved(4)0x60Channel4(subchannel)8Ch4outputmixer[1]0x00000000outputmixerCh4outputmixer[0]0x008000000x61Channel4(subchannel)8Ch4inputmixer[1]0x00400000inputmixerCh4inputmixer[0]0x004000000x62IDFpostscale4Post-IDFattenuationregister0x000000800x63–0xF7Reserved(4)0x000000000xF8Deviceaddressenable4WriteF9A5A5A5inthisregistertoenablewriteto0x00000000registerdeviceaddressupdate(0xF9)0xF9DeviceaddressUpdate4u[31:8],NewDevId[7:1],ZERO[0](NewDevId0X00000036Register(7:1)definesthenewdeviceaddress0xFA–0xFF4Reserved(4)0x00000000(4)Reservedregistersshouldnotbeaccessed.
AllDAPcoefficientsare3.
23formatunlessspecifiedotherwise.
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comDETAILEDREGISTERDESCRIPTIONSCLOCKCONTROLREGISTER(0x00)TheclocksanddataratesareautomaticallydeterminedbytheTAS5721.
Theclockcontrolregistercontainstheauto-detectedclockstatus.
BitsD7–D5reflectthesamplerate.
BitsD4–D2reflecttheMCLKfrequency.
Thedeviceacceptsa64fSor32fSSCLKrateforallMCLKratios,butacceptsa48fSSCLKrateforMCLKratiosof192fSand384fSonly.
Table1.
ClockControlRegister(0x00)D7D6D5D4D3D2D1D0FUNCTION000fS=32-kHzsamplerate001Reserved(1)010Reserved(1)011fS=44.
1/48-kHzsamplerate(2)100fs=16-kHzsamplerate101fs=22.
05/24-kHzsamplerate110fs=8-kHzsamplerate111fs=11.
025/12-kHzsamplerate–––000––MCLKfrequency=64*fS(3)–––001––MCLKfrequency=128*fS(3)–––010––MCLKfrequency=192*fS(4)–––011––MCLKfrequency=256*fS(2)(5)–––100––MCLKfrequency=384*fS–––101––MCLKfrequency=512*fS–––110––Reserved(1)–––111––Reserved(1)0–Reserved(1)(2)0Reserved(1)(2)(1)Reservedregistersshouldnotbeaccessed.
(2)Defaultvaluesareinbold.
(3)Onlyavailablefor44.
1-kHzand48-kHzrates.
(4)Rateonlyavailablefor32/44.
1/48-kHzsamplerates(5)Notavailableat8kHzDEVICEIDREGISTER(0x01)ThedeviceIDregistercontainstheIDcodeforthefirmwarerevisionTable2.
DeviceIDRegister(0x01)D7D6D5D4D3D2D1D0FUNCTION00000000Identificationcode30SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012ERRORSTATUSREGISTER(0x02)Theerrorbitsarestickyandarenotclearedbythehardware.
Thismeansthatthesoftwaremustcleartheregister(writezeroes)andthenreadthemtodetermineiftheyarepersistenterrors.
ErrorDefinitions:MCLKError:MCLKfrequencyischanging.
ThenumberofMCLKsperLRCLKischanging.
SCLKError:ThenumberofSCLKsperLRCLKischanging.
LRCLKError:LRCLKfrequencyischanging.
FrameSlip:LRCLKphaseisdriftingwithrespecttointernalframesync.
Table3.
ErrorStatusRegister(0x02)D7D6D5D4D3D2D1D0FUNCTION1MCLKerror–1PLLautolockerror––1SCLKerror–––1––––LRCLKerror––––1–––Frameslip1––Clipindicator1–Overcurrent,overtemperature,overvoltageorundervoltageerrors0Reserved0000000–Noerrors(1)(1)Defaultvaluesareinbold.
SYSTEMCONTROLREGISTER1(0x03)Thesystemcontrolregister1hasseveralfunctions:BitD7:If0,thedc-blockingfilterforeachchannelisdisabled.
If1,thedc-blockingfilter(–3dBcutoff<1Hz)foreachchannelisenabled(default).
BitD5:If0,usesoftunmuteonrecoveryfromclockerror.
Thisisaslowrecovery.
Unmutetakesthesametimeasthevolumerampdefinedinregister0x0E.
If1,usehardunmuteonrecoveryfromclockerror(default).
Thisisafastrecovery,asinglestepvolumerampBitsD1–D0:Selectde-emphasisTable4.
SystemControlRegister1(0x03)D7D6D5D4D3D2D1D0FUNCTION0PWMhigh-pass(dcblocking)disabled1PWMhigh-pass(dcblocking)enabled(1)–0Reserved(1)––0Softunmuteonrecoveryfromclockerror––1Hardunmuteonrecoveryfromclockerror(1)–––0––––Reserved(1)––––0–––Reserved(1)0––Reserved(1)00Node-emphasis(1)01De-emphasisforfS=32kHz10De-emphasisforfS=44.
1kHz11De-emphasisforfS=48kHz(1)Defaultvaluesareinbold.
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comSERIALDATAINTERFACEREGISTER(0x04)AsshowninTable5,theTAS5721supportsnineserialdatamodes.
Thedefaultis24-bit,I2Smode,Table5.
SerialDataInterfaceControlRegister(0x04)FormatRECEIVESERIALDATAWORDD7–D4D3D2D1D0INTERFACEFORMATLENGTHRight-justified1600000000Right-justified2000000001Right-justified2400000010I2S160000011I2S2000000100I2S(1)2400000101Left-justified1600000110Left-justified2000000111Left-justified2400001000Reserved00001001Reserved00001010Reserved00001011Reserved00001100Reserved00001101Reserved00001110Reserved00001111(1)Defaultvaluesareinbold.
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comSLOS739–JULY2012SYSTEMCONTROLREGISTER2(0x05)WhenbitD6issetlow,thesystemexitsallchannelshutdownandstartsplayingaudio;otherwise,theoutputsareshutdown(hardmute).
Table6.
SystemControlRegister2(0x05)D7D6D5D4D3D2D1D0FUNCTION0Mid-Zrampdisabled(1)1Mid-Zrampenabled–0Exitall-channelshutdown(normaloperation)–1Enterall-channelshutdown(hardmute)(1)0––2.
0mode[2.
0BTL](1)1––2.
1mode[2SE+1BTL]0–ADR/FAULTpinisconfiguredastoserveasanaddressinputonly(1)1–ADR/FAULTpinisconfiguredasfaultoutput––000––0Reserved(1)(1)Defaultvaluesareinbold.
SOFTMUTEREGISTER(0x06)Writinga1toanyofthefollowingbitssetstheoutputoftherespectivechannelto50%dutycycle(softmute).
Table7.
SoftMuteRegister(0x06)D7D6D5D4D3D2D1D0FUNCTION00000–––Reserved(1)0––Softunmutechannel3(1)1––Softmutechannel30–Softunmutechannel2(1)1–Softmutechannel20Softunmutechannel1(1)1Softmutechannel1(1)Defaultvaluesareinbold.
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comVOLUMEREGISTERS(0x07,0x08,0x09,0x0A)Stepsizeis0.
5dBMastervolume–0x07(defaultismute)Channel-1volume–0x08(defaultis0dB)Channel-2volume–0x09(defaultis0dB)Channel-3volume–0x0A(defaultis0dB)Table8.
VolumeRegisters(0x07,0x08,0x09,0x0A)DDDDDDDDFUNCTION765432100000000024dB001100000dB(defaultforindividualchannelvolume)(1)11111110–103dB11111111Softmute(defaultforthemastervolume)(1)(1)Defaultvaluesareinbold.
VOLUMECONFIGURATIONREGISTER(0x0E)BitsVolumeslewrate(UsedtocontrolvolumechangeandMUTEramprates).
ThesebitscontroltheD2–D0:numberofstepsinavolumeramp.
VolumestepsoccurataratethatdependsonthesamplerateoftheI2Sdataasfollows:SampleRate(KHz)ApproximateRampRate8/16/32125us/step11.
025/22.
05/44.
190.
7us/step12/24/4883.
3us/stepTable9.
VolumeControlRegister(0x0E)D7D6D5D4D3D2D1D0FUNCTION1––10–––Reserved(1)–0Subchannel(ch4)volume=ch1volume(2)(1)–1Subchannelvolume=register0x0A(2)––0Ch3volume=ch2volume(1)––1Ch3volume=register0x0A000Volumeslew512steps(43-msvolumeramptimeat48kHz)001Volumeslew1024steps(85-msvolumeramptimeat48kHz)(1)010Volumeslew2048steps(171-msvolumeramptimeat48kHz)011Volumeslew256steps(21-msvolumeramptimeat48kHz)1XXReserved(1)Defaultvaluesareinbold.
(2)Bits6:5canbechangedonlywhenvolumeisinMUTE[mastervolume=MUTE(register0x07=0xFF)].
34SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012MODULATIONLIMITREGISTER(0x10)ThemodulationlimitisthemaximumdutycycleofthePWMoutputwaveform.
ItisimportanttonotethatforanyapplicationswithPVDDgreaterthan18V,themaximummodulationindexmustbesetto93.
8%.
Table10.
ModulationLimitRegister(0x10)D7D6D5D4D3D2D1D0MODULATIONLIMIT00099.
2%00198.
4%01097.
7%(1)01196.
9%10096.
1%10195.
3%11094.
5%11193.
8%00000–––RESERVED(1)Defaultvaluesareinbold.
INTERCHANNELDELAYREGISTERS(0x11,0x12,0x13,and0x14)InternalPWMchannels1,2,1,and2aremappedintoregisters0x11,0x12,0x13,and0x14.
Table11.
ChannelInterchannelDelayRegisterFormatSUBADDRESSD7D6D5D4D3D2D1D0Delay=(value)*4DCLKs0x11101011––Defaultvalueforchannel1(1)0x12010101––Defaultvalueforchannel2(1)0x13101011––Defaultvalueforchannel1(1)0x14010101––Defaultvalueforchannel2(1)RANGEOFVALUESFOR0x11-0x14000000––Minimumabsolutedelay,0DCLKcycles011111––Maximumpositivedelay,31*4DCLKcycles100000––Maximumnegativedelay,–32*4DCLKcycles00RESERVED(1)Defaultvaluesareinbold.
TheICDsettingshavehighimpactonaudioperformance(forexample,dynamicrange,THD+N,crosstalk,andsoforth).
Therefore,appropriateICDsettingsmustbeused.
Bydefault,thedevicehasICDsettingsforADmode.
IfusedinBDmode,thenupdatetheseregistersbeforecomingoutofall-channelshutdown.
REGISTERADMODEBDMODE0x11ACB80x1254600x13ACA00x145448Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback35ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comPWMSHUTDOWNGROUPREGISTER(0x19)SettingsofthisregisterdeterminewhichPWMchannelsareactive.
Thevalueshouldbe0x30forBTLmodeand0x3AforPBTLmode.
Thedefaultvalueofthisregisteris0x30.
ThefunctionalityofthisregisteristiedtothestateofbitD6inthesystemcontrolregister.
Thisregisterdefineswhichchannelsbelongtotheshutdowngroup(SDG).
Ifa1issetintheshutdowngroupregister,thatparticularchannelisnotstartedfollowinganexitoutofall-channelshutdowncommand(ifbitD6issetto0insystemcontrolregister2,0x05).
Table12.
ShutdownGroupRegisterD7D6D5D4D3D2D1D0FUNCTION0Reserved(1)–0Reserved(1)––1Reserved(1)–––1––––Reserved(1)––––0–––PWMchannel4doesnotbelongtoshutdowngroup.
(1)––––1–––PWMchannel4belongstoshutdowngroup.
0––PWMchannel3doesnotbelongtoshutdowngroup.
(1)1––PWMchannel3belongstoshutdowngroup.
0–PWMchannel2doesnotbelongtoshutdowngroup.
(1)1–PWMchannel2belongstoshutdowngroup.
0PWMchannel1doesnotbelongtoshutdowngroup.
(1)1PWMchannel1belongstoshutdowngroup.
(1)Defaultvaluesareinbold.
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comSLOS739–JULY2012START/STOPPERIODREGISTER(0x1A)Thisregisterisusedtocontrolthesoft-startandsoft-stopperiodfollowinganenter/exitallchannelshutdowncommandorchangeinthePDNstate.
Thishelpsreducepopsandclicksatstart-upandshutdown.
ThetimesareonlyapproximateandvarydependingondeviceactivitylevelandI2Sclockstability.
Table13.
Start/StopPeriodRegister(0x1A)D7D6D5D4D3D2D1D0FUNCTION0SSTIMERenabled(1)1SSTIMERdisabled–00Reserved(1)–––00–––No50%dutycyclestart/stopperiod–––0100016.
5-ms50%dutycyclestart/stopperiod–––0100123.
9-ms50%dutycyclestart/stopperiod–––0101031.
4-ms50%dutycyclestart/stopperiod–––0101140.
4-ms50%dutycyclestart/stopperiod–––0110053.
9-ms50%dutycyclestart/stopperiod–––0110170.
3-ms50%dutycyclestart/stopperiod–––0111094.
2-ms50%dutycyclestart/stopperiod–––01111125.
7-ms50%dutycyclestart/stopperiod(1)–––10000164.
6-ms50%dutycyclestart/stopperiod–––10001239.
4-ms50%dutycyclestart/stopperiod–––10010314.
2-ms50%dutycyclestart/stopperiod–––10011403.
9-ms50%dutycyclestart/stopperiod–––10100538.
6-ms50%dutycyclestart/stopperiod–––10101703.
1-ms50%dutycyclestart/stopperiod–––10110942.
5-ms50%dutycyclestart/stopperiod–––101111256.
6-ms50%dutycyclestart/stopperiod–––110001728.
1-ms50%dutycyclestart/stopperiod–––110012513.
6-ms50%dutycyclestart/stopperiod–––110103299.
1-ms50%dutycyclestart/stopperiod–––110114241.
7-ms50%dutycyclestart/stopperiod–––111005655.
6-ms50%dutycyclestart/stopperiod–––111017383.
7-ms50%dutycyclestart/stopperiod–––111109897.
3-ms50%dutycyclestart/stopperiod–––1111113,196.
4-ms50%dutycyclestart/stopperiod(1)Defaultvaluesareinbold.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback37ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comOSCILLATORTRIMREGISTER(0x1B)TheTAS5721PWMprocessorcontainsaninternaloscillatortosupportautodetectofI2Sclockrates.
Thisreducessystemcostbecauseanexternalreferenceisnotrequired.
TIrecommendsareferenceresistorvalueofthatshownintheTypicalApplicationCircuitDiagrams.
Thecircuitthatusesthisresistorshouldbecalibratedortrimmedaftereachtimethedeviceisreset.
Writing0x00toregister0x1Benablesthetrimthatwasprogrammedatthefactory.
Itisimportanttonotethatafterwritingthevalue0x00tothetrimregister,theregisterwillreporthevalue0xC0,toindicatethetrimprocessiscomplete.
Table14.
OscillatorTrimRegister(0x1B)D7D6D5D4D3D2D1D0FUNCTION1Reserved(1)–0Oscillatortrimnotdone(read-only)(1)–1Oscillatortrimdone(readonly)––0000––Reserved(1)0–Selectfactorytrim(Writea0toselectfactorytrim;defaultis1.
)1–Factorytrimdisabled(1)0Reserved(1)(1)Defaultvaluesareinbold.
BKND_ERRREGISTER(0x1C)Whenabackenderrorsignalisreceivedfromtheinternalpowerstage,thepowerstageisresetstoppingallPWMactivity.
Subsequently,themodulatorwaitsapproximatelyforthetimelistedinTable15beforeattemptingtorestartthepowerstage.
Table15.
BKND_ERRRegister(0x1C)(1)D7D6D5D4D3D2D1D0FUNCTION0000000XReserved––––0010Setback-endresetperiodto299ms(2)––––0011Setback-endresetperiodto449ms––––0100Setback-endresetperiodto598ms––––0101Setback-endresetperiodto748ms––––0110Setback-endresetperiodto898ms––––0111Setback-endresetperiodto1047ms––––1000Setback-endresetperiodto1197ms––––1001Setback-endresetperiodto1346ms––––101XSetback-endresetperiodto1496ms––––11XX(1)Thisregistercanbewrittenonlywithanon-reservedvalue.
Alsothisregistercanbeonlybewrittenonceafterthedeviceisreset.
Ifadifferentvalueisdesired,thedevicemustberesetbeforechanging0x1Cagain.
(2)Defaultvaluesareinbold.
38SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012INPUTMULTIPLEXERREGISTER(0x20)Thisregistercontrolsthemodulationscheme(ADorBDmode)aswellastheroutingofI2Saudiototheinternalchannels.
Table16.
InputMultiplexerRegister(0x20)D31D30D29D28D27D26D25D24FUNCTION00000---Reserved(1)0PolarityofCh3isnotinverted1PolarityofCh3isinverted0PolarityofCh2isnotinverted1PolarityofCh2isinverted0PolarityofCh1isnotinverted1PolarityofCh1isinvertedD23D22D21D20D19D18D17D16FUNCTION0Channel-1ADmode(1)1Channel-1BDmode–000––––SDIN-Ltochannel1(1)–001––––SDIN-Rtochannel1–010––––Reserved–011––––Reserved–100––––Reserved–101––––Reserved–110––––Ground(0)tochannel1–111––––Reserved––––0–––Channel2ADmode(1)––––1–––Channel2BDmode000SDIN-Ltochannel2001SDIN-Rtochannel2(1)010Reserved011Reserved100Reserved101Reserved110Ground(0)tochannel2111ReservedD15D14D13D12D11D10D9D8FUNCTION01110111Reserved(1)D7D6D5D4D3D2D1D0FUNCTION0Subchannelin2.
1mode,ADmodulation1Subchannelin2.
1mode,BDmodulation0111-010Reserved(1)(1)Defaultvaluesareinbold.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback39ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comCHANNEL4SOURCESELECTREGISTER(0x21)Thisregisterselectsthechannel4source.
Table17.
SubchannelControlRegister(0x21)D31D30D29D28D27D26D25D24FUNCTION00000000Reserved(1)D23D22D21D20D19D18D17D16FUNCTION00000000Reserved(1)D15D14D13D12D11D10D9D8FUNCTION0100001Reserved(1)0(L+R)/21Left-channelpost-BQ(1)D7D6D5D4D3D2D1D0FUNCTION00000011Reserved(1)(1)Defaultvaluesareinbold.
PWMOUTPUTMUXREGISTER(0x25)ThisDAPoutputmuxselectswhichinternalPWMchannelisoutputtotheexternalpins.
Anychannelcanbeoutputtoanyexternaloutputpin.
BitsD21–D20:SelectswhichPWMchannelisoutputtoOUT_ABitsD17–D16:SelectswhichPWMchannelisoutputtoOUT_BBitsD13–D12:SelectswhichPWMchannelisoutputtoOUT_CBitsD09–D08:SelectswhichPWMchannelisoutputtoOUT_DNotethatchannelsareencodedsothatchannel1=0x00,channel2=0x01,…,channel4=0x03.
Seefordetails.
Table18.
PWMOutputMuxRegister(0x25)D31D30D29D28D27D26D25D24FUNCTION00000001Reserved(1)D23D22D21D20D19D18D17D16FUNCTION00Reserved(1)––00––––MultiplexPWM1toOUT_A(1)––01––––MultiplexPWM2toOUT_A––10––––MultiplexPWM3toOUT_A––11––––MultiplexPWM4toOUT_A––––00––Reserved(1)00MultiplexPWM1toOUT_B01MultiplexPWM2toOUT_B10MultiplexPWM3toOUT_B(1)11MultiplexPWM4toOUT_BD15D14D13D12D11D10D9D8FUNCTION00Reserved(1)––00––––MultiplexPWM1toOUT_C––01––––MultiplexPWM2toOUT_C(1)(1)Defaultvaluesareinbold.
40SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012Table18.
PWMOutputMuxRegister(0x25)(continued)––10––––MultiplexPWM3toOUT_C––11––––MultiplexPWM4toOUT_C––––00––Reserved(1)00MultiplexPWM1toOUT_D01MultiplexPWM2toOUT_D10MultiplexPWM3toOUT_D11MultiplexPWM4toOUT_D(1)D7D6D5D4D3D2D1D0FUNCTION01000101Reserved(1)DRCCONTROL(0x46)EachDRCcanbeenabledindependentlyusingtheDRCcontrolregister.
TheDRCsaredisabledbydefault.
Table19.
DRCControlRegisterD31D30D29D28D27D26D25D24FUNCTION00000000Reserved(1)D23D22D21D20D19D18D17D16FUNCTION00000000Reserved(1)D15D14D13D12D11D10D9D8FUNCTION00000000Reserved(1)D7D6D5D4D3D2D1D0FUNCTION00Reserved(1)––0Disablecomplementary(1–H)low-passfiltergeneration(1)––1Enablecomplementary(1–H)low-passfiltergeneration–––0–––––––1––––00Reserved(1)0–DRC2turnedOFF(1)1–DRC2turnedON0DRC1turnedOFF(1)1DRC1turnedON(1)Defaultvaluesareinbold.
BANKSWITCHANDEQCONTROL(0x50)ThebankswitchingfeatureisdescribedindetailinsectionBANKSWITCHING.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback41ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comTable20.
BankSwitchingCommandD31D30D29D28D27D26D25D24FUNCTION032kHz,doesnotusebank3(1)132kHz,usesbank3–0Reserved(1)––0Reserved(1)–––0––––44.
1/48kHz,doesnotusebank3(1)–––1––––44.
1/48kHz,usesbank3––––0–––16kHz,doesnotusebank3––––1–––16kHz,usesbank3(1)0––22.
025/24kHz,doesnotusebank31––22.
025/24kHz,usesbank3(1)0–8kHz,doesnotusebank31–8kHz,usesbank3(1)011.
025kHz/12,doesnotusebank3111.
025/12kHz,usesbank3(1)D23D22D21D20D19D18D17D16FUNCTION032kHz,doesnotusebank2(1)132kHz,usesbank2–1Reserved(1)––1Reserved(1)–––0––––44.
1/48kHz,doesnotusebank2–––1––––44.
1/48kHz,usesbank2(1)––––0–––16kHz,doesnotusebank2(1)––––1–––16kHz,usesbank20––22.
025/24kHz,doesnotusebank2(1)1––22.
025/24kHz,usesbank20–8kHz,doesnotusebank2(1)1–8kHz,usesbank2011.
025/12kHz,doesnotusebank2(1)111.
025/12kHz,usesbank2D15D14D13D12D11D10D9D8FUNCTION032kHz,doesnotusebank1132kHz,usesbank1(1)–0Reserved(1)––0Reserved(1)–––0––––44.
1/48kHz,doesnotusebank1(1)–––1––––44.
1/48kHz,usesbank1––––0–––16kHz,doesnotusebank1(1)––––1–––16kHz,usesbank10––22.
025/24kHz,doesnotusebank1(1)1––22.
025/24kHz,usesbank10–8kHz,doesnotusebank1(1)1–8kHz,usesbank1011.
025/12kHz,doesnotusebank1(1)111.
025/12kHz,usesbank1(1)Defaultvaluesareinbold.
42SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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BankSwitchingCommand(continued)D7D6D5D4D3D2D1D0FUNCTION0EQON1EQOFF(bypassBQ0-7ofchannels1and2)–0Reserved(2)––0Ignorebank-mappinginbitsD31–D8.
Usedefaultmapping.
(2)1Usebank-mappinginbitsD31–D8.
–––0––––LandRcanbewrittenindependently.
(2)LandRaregangedforEQbiquads;awritetoleft-channelBQisalso–––1––––writtentoright-channelBQ.
(0x29–0x2Fisgangedto0x30–0x36.
Also0x58–0x5Bisgangedto0x5C–0x5F)––––0–––Reserved(2)Nobankswitching.
AllconfigurationoftheBiQuadsareapplied000directlytotheDAP(2)001Configurebank1(32kHzbydefault)010Configurebank2(44.
1/48kHzbydefault)011Configurebank3(othersampleratesbydefault)100Automaticbankselection101Reserved11XReserved(2)Defaultvaluesareinbold.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback43ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comDETAILEDDESCRIPTIONANDTHEORYOFOPERATIONPOWERSUPPLYTofacilitatesystemdesign,theTAS5721needsonlya3.
3-VsupplyinadditiontothePVDDpower-stagesupply.
TherequiredsequencingofthepowersuppliesisshownintheRecommendedUseModelsection.
Aninternalvoltageregulatorprovidessuitablevoltagelevelsforthegatedrivecircuitry.
Additionally,allcircuitryrequiringafloatingvoltagesupply,forexample,thehigh-sidegatedrive,isaccommodatedbybuilt-inbootstrapcircuitryrequiringonlyafewexternalcapacitors.
Inordertoprovidegoodelectricalandacousticalcharacteristics,thePWMsignalpathfortheoutputstageisdesignedasidentical,independenthalf-bridges.
Forthisreason,eachhalf-bridgehasseparatebootstrappins(BSTRPx)andpower-stagesupplypins(PVDD).
Thegatedrivevoltage(GVDD_REG)isderivedfromthePVDDvoltage.
Specialattentionshouldbepaidtoplacingalldecouplingcapacitorsasclosetotheirassociatedpinsaspossible.
Ingeneral,inductancebetweenthepower-supplypinsanddecouplingcapacitorsmustbeavoided.
Foraproperlyfunctioningbootstrapcircuit,asmallceramiccapacitormustbeconnectedfromeachbootstrappin(BSTRPx)tothepower-stageoutputpin(SPK_OUTx).
Whenthepower-stageoutputislow,thebootstrapcapacitorischargedthroughaninternaldiodeconnectedbetweenthegate-driveregulatoroutputpin(GVDD_X)andthebootstrappin.
Whenthepower-stageoutputishigh,thebootstrapcapacitorpotentialisshiftedabovetheoutputpotentialandthusprovidesasuitablevoltagesupplyforthehigh-sidegatedriver.
AsshownintheTypicalApplicationCircuitssection,itisrecommendedtouseceramiccapacitors,forthebootstrapsupplypins.
Thesecapacitorsensuresufficientenergystorage,evenduringminimalPWMdutycycles,tokeepthehigh-sidepowerstageFET(LDMOS)fullyturnedonduringtheremainingpartofthePWMcycle.
Specialattentionshouldbepaidtothepower-stagepowersupply;thisincludescomponentselection,PCBplacement,androuting.
Asindicated,eachhalf-bridgehasindependentpower-stagesupplypins(PVDD).
Foroptimalelectricalperformance,EMIcompliance,andsystemreliability,itisimportantthateachPVDDpinisdecoupledwithaceramiccapacitorplacedascloseaspossibletoeachsupplypin,asshownintheTypicalApplicationCircuitssection.
TheTAS5721isfullyprotectedagainsterroneouspower-stageturn-onduetoparasiticgatecharging.
I2CAddressSelectionandFaultOutputADR/FAULTisaninputpinduringpowerup.
ItcanbepulledHIGHorLOWthrougharesistorasshownintheTypicalApplicationCircuitssectioninordertosettheI2Caddress.
PullingthispinHIGHthroughtheresistorresultsinsettingtheI2C7-bitaddressto0011011(0x36),andpullingitLOWthroughtheresistorresultsinsettingtheaddressto0011010(0x34).
Duringpowerup,theaddressofthedeviceislatchedin,freeinguptheADR/FAULTpintobeusedasafaultnotificationoutput.
Whenconfiguredasafaultoutput,thepinwillgolowwhenafaultoccursandwillreturntoit'sdefaultstatewhenregister0x02iscleared.
Thedevicewillpullthefaultpinlowforover-current,over-temperature,over-voltagelock-out,andunder-voltagelock-out.
DEVICEPROTECTIONSYSTEMOvercurrent(OC)ProtectionWithCurrentLimitingThedevicehasindependent,fastreactingcurrentdetectorsonallhigh-sideandlow-sidepower-stageFETs.
Thedetectoroutputsarecloselymonitoredbyaprotectionsystem.
Ifthehigh-currentconditionsituationpersists,aprotectionsystemtriggersalatchingshutdown,resultinginthepowerstagebeingsetinthehigh-impedance(Hi-Z)state.
Afterthepowerstageentersintothisstate,thepowerstagewillattempttorestartafteraperiodoftimedefinedinregister0x1C.
Ifthehigh-currentconditionpersists,thedevicewillbegintheshutdownandretrysequenceagain.
Thedevicewillreturntonormaloperationoncethefaultconditionisremoved.
Currentlimitingandovercurrentprotectionarenotindependentforhalf-bridges.
Thatis,ifthebridge-tiedloadbetweenhalf-bridgesAandBcausesanovercurrentfault,half-bridgesA,B,C,andDareshutdown.
44SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012OvertemperatureProtectionTheTAS5721hasanovertemperature-protectionsystem.
Ifthedevicejunctiontemperatureexceeds150°C(nominal),thedeviceisputintothermalshutdown,resultinginallhalf-bridgeoutputsbeingsetinthehigh-impedance(Hi-Z)stateandADR/FAULT,ifconfiguredasanoutput,beingassertedlow.
TheTAS5721recoversautomaticallyoncethetemperaturedropsapproximately30°C.
UndervoltageProtection(UVP)andPower-OnReset(POR)TheUVPandPORcircuitsoftheTAS5721fullyprotectthedeviceinanypower-up/downandbrownoutsituation.
Whilepoweringup,thePORcircuitensuresthatallcircuitsarefullyoperationalwhenthePVDDandAVDDsupplyvoltagesreach4.
1Vand2.
7V,respectively.
AlthoughPVDDandAVDDareindependentlymonitored,asupplyvoltagedropbelowtheUVPthresholdonAVDDoroneitherPVDDpinresultsinallhalf-bridgeoutputsimmediatelybeingsetinthehigh-impedance(Hi-Z)stateandADR/FAULT,ifconfiguredasanoutput,beingassertedlow.
CLOCK,AUTODETECTION,ANDPLLTheTAS5721isaslavedevice.
ItacceptsMCLK,SCLK,andLRCLK.
Thedigitalaudioprocessor(DAP)supportsallthesampleratesandMCLKratesthataredefinedintheClockControlRegistersection.
TheTAS5721checkstoverifythatSCLKisaspecificvalueof32fS,48fS,or64fS.
TheDAPonlysupportsa1*fSLRCLK.
ThetimingrelationshipoftheseclockstoSDINisshowninsubsequentsections.
TheclocksectionusesMCLKortheinternaloscillatorclock(whenMCLKisunstable,outofrange,orabsent)toproducetheinternalclock(DCLK)runningat512timesthePWMswitchingfrequency.
TheDAPcanautodetectandsettheinternalclockcontrollogictotheappropriatesettingsforallsupportedclockratesasdefinedintheclockcontrolregister.
TAS5721hasrobustclockerrorhandlingthatusesthebuilt-intrimmedoscillatorclocktoquicklydetectchanges/errors.
Oncethesystemdetectsaclockchange/error,itwillmutetheaudio(throughasinglestepmute)andthenforcePLLtooperateinareducedcapacityusingtheinternaloscillatorasareferenceclock.
Oncetheclocksarestable,thesystemwillautodetectthenewrateandreverttonormaloperation.
Duringthisprocess,thedefaultvolumewillberestoredinasinglestep(alsocalledhardunmute)bydefault.
Ifdesired,theunmutingprocesscanbeprogrammedtorampbackslowly(alsocalledsoftunmute)asdefinedinvolumeregister(0x0E).
SERIALDATAINTERFACESerialdataisinputonSDIN.
ThePWMoutputsarederivedfromSDIN.
TheTAS5721DAPacceptsserialdatain16-,20-,or24-bitleft-justified,right-justified,andI2Sserialdataformats.
PWMSectionTheTAS5721DAPdeviceusesnoise-shapingandsophisticatednon-linearcorrectionalgorithmstoachievehighpowerefficiencyandhigh-performancedigitalaudioreproduction.
TheDAPusesafourth-ordernoiseshapertoincreasedynamicrangeandSNRintheaudioband.
ThePWMsectionaccepts24-bitPCMdatafromtheDAPandoutputsuptothreePWMaudiooutputchannels.
ThePWMmodulationblockhasindividualchanneldcblockingfiltersthatcanbeenabledanddisabled.
Thefiltercutofffrequencyislessthan1Hz.
Individualchannelde-emphasisfiltersfor44.
1-and48-kHzareincludedandcanbeenabledanddisabled.
Finally,thePWMsectionhasanadjustablemaximummodulationlimitof93.
8%to99.
2%.
ItisimportanttonotethatforanyapplicationswithPVDDgreaterthan18V,themaximummodulationindexmustbesetto93.
8%.
SERIALINTERFACECONTROLANDTIMINGTheI2Smodeissetbywritingtoregister0x04.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback45ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comI2STimingI2StimingusesLRCLKtodefinewhenthedatabeingtransmittedisfortheleftchannelandwhenitisfortherightchannel.
LRCLKislowfortheleftchannelandhighfortherightchannel.
Abitclockrunningat32,48,or64*fSisusedtoclockinthedata.
ThereisadelayofonebitclockfromthetimetheLRCLKsignalchangesstatetothefirstbitofdataonthedatalines.
ThedataiswrittenMSBfirstandisvalidontherisingedgeofbitclock.
TheDAPmasksunusedtrailingdatabitpositions.
NOTE:Alldatapresentedin2s-complementformwithMSBfirst.
Figure52.
I2S64-fSFormat46SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012NOTE:Alldatapresentedin2s-complementformwithMSBfirst.
Figure53.
I2S48-fSFormatNOTE:Alldatapresentedin2s-complementformwithMSBfirst.
Figure54.
I2S32-fSFormatLeft-JustifiedLeft-justified(LJ)timingusesLRCLKtodefinewhenthedatabeingtransmittedisfortheleftchannelandwhenitisfortherightchannel.
LRCLKishighfortheleftchannelandlowfortherightchannel.
Abitclockrunningat32,48,or64*fSisusedtoclockinthedata.
ThefirstbitofdataappearsonthedatalinesatthesametimeLRCLKtoggles.
ThedataiswrittenMSBfirstandisvalidontherisingedgeofthebitclock.
TheDAPmasksunusedtrailingdatabitpositions.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback47ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comNOTE:Alldatapresentedin2s-complementformwithMSBfirst.
Figure55.
Left-Justified64-fSFormatNOTE:Alldatapresentedin2s-complementformwithMSBfirst.
Figure56.
Left-Justified48-fSFormat48SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012NOTE:Alldatapresentedin2s-complementformwithMSBfirst.
Figure57.
Left-Justified32-fSFormatRight-JustifiedRight-justified(RJ)timingusesLRCLKtodefinewhenthedatabeingtransmittedisfortheleftchannelandwhenitisfortherightchannel.
LRCLKishighfortheleftchannelandlowfortherightchannel.
Abitclockrunningat32,48,or64*fSisusedtoclockinthedata.
Thefirstbitofdataappearsonthedata8bit-clockperiods(for24-bitdata)afterLRCLKtoggles.
InRJmodetheLSBofdataisalwaysclockedbythelastbitclockbeforeLRCLKtransitions.
ThedataiswrittenMSBfirstandisvalidontherisingedgeofbitclock.
TheDAPmasksunusedleadingdatabitpositions.
Figure58.
RightJustified64-fSFormatCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback49ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comFigure59.
RightJustified48-fSFormatFigure60.
RightJustified32-fSFormat50SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012I2CSERIALCONTROLINTERFACETheTAS5721DAPhasabidirectionalinter-integratedcircuit(I2C)interfacethatiscompatiblewiththeI2Cbusprotocolandsupportsboth100-kHzand400-kHzdatatransferratesforsingleandmultiplebytewriteandreadoperations.
Thisisaslaveonlydevicethatdoesnotsupportamultimasterbusenvironmentorwaitstateinsertion.
Thecontrolinterfaceisusedtoprogramtheregistersofthedeviceandtoreaddevicestatus.
TheDAPsupportsthestandard-modeI2Cbusoperation(100kHzmaximum)andthefastI2Cbusoperation(400kHzmaximum).
TheDAPperformsallI2CoperationswithoutI2Cwaitcycles.
GeneralI2COperationTheI2Cbusemploystwosignalstocommunicatebetweenintegratedcircuitsinasystem:(data)SDAand(clock)SCL.
Dataistransferredonthebusseriallyonebitatatime.
Theaddressanddatacanbetransferredinbyte(8-bit)format,withthemostsignificantbit(MSB)transferredfirst.
Inaddition,eachbytetransferredonthebusisacknowledgedbythereceivingdevicewithanacknowledgebit.
Eachtransferoperationbeginswiththemasterdevicedrivingastartconditiononthebusandendswiththemasterdevicedrivingastopconditiononthebus.
Thebususestransitionsonthedatapin(SDA)whiletheclockishightoindicatestartandstopconditions.
Ahigh-to-lowtransitiononSDAindicatesastartandalow-to-hightransitionindicatesastop.
Normaldatabittransitionsmustoccurwithinthelowtimeoftheclockperiod.
TheseconditionsareshowninFigure61.
Themastergeneratesthe7-bitslaveaddressandtheread/write(R/W)bittoopencommunicationwithanotherdeviceandthenwaitsforanacknowledgecondition.
TheTAS5721holdsSDAlowduringtheacknowledgeclockperiodtoindicateanacknowledgment.
Whenthisoccurs,themastertransmitsthenextbyteofthesequence.
Eachdeviceisaddressedbyaunique7-bitslaveaddressplusR/Wbit(1byte).
Allcompatibledevicessharethesamesignalsthroughabidirectionalbususingawired-ANDconnection.
AnexternalpullupresistormustbeusedfortheSDAandSCLsignalstosetthehighlevelforthebus.
Figure61.
TypicalI2CSequenceThereisnolimitonthenumberofbytesthatcanbetransmittedbetweenstartandstopconditions.
Whenthelastwordtransfers,themastergeneratesastopconditiontoreleasethebus.
AgenericdatatransfersequenceisshowninFigure61.
PinADR/FAULTdefinestheI2Cdeviceaddress.
Anexternal15-kΩpulldownonthispingivesadeviceaddressof0x34anda15-kΩpullupgivesadeviceaddressof0x36.
The7-bitaddressis0011011(0x36)or0011010(0x34).
I2CDeviceAddressChangeProcedureWritetodeviceaddresschangeenableregister,0xF8withavalueof0xF9A5A5A5.
Writetodeviceregister0xF9withavalueof0x000000XX,whereXXisthenewaddress.
AnywritesafterthatshouldusethenewdeviceaddressXX.
Single-andMultiple-ByteTransfersTheserialcontrolinterfacesupportsbothsingle-byteandmultiple-byteread/writeoperationsforsubaddresses0x00to0x1F.
However,forthesubaddresses0x20to0xFF,theserialcontrolinterfacesupportsonlymultiple-byteread/writeoperations(inmultiplesof4bytes).
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback51ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comDuringmultiple-bytereadoperations,theDAPrespondswithdata,abyteatatime,startingatthesubaddressassigned,aslongasthemasterdevicecontinuestorespondwithacknowledges.
Ifaparticularsubaddressdoesnotcontain32bits,theunusedbitsarereadaslogic0.
Duringmultiple-bytewriteoperations,theDAPcomparesthenumberofbytestransmittedtothenumberofbytesthatarerequiredforeachspecificsubaddress.
Forexample,ifawritecommandisreceivedforabiquadsubaddress,theDAPexpectstoreceivefive32-bitwords.
Iffewerthanfive32-bitdatawordshavebeenreceivedwhenastopcommand(oranotherstartcommand)isreceived,thedatareceivedisdiscarded.
SupplyingasubaddressforeachsubaddresstransactionisreferredtoasrandomI2Caddressing.
TheTAS5721alsosupportssequentialI2Caddressing.
Forwritetransactions,ifasubaddressisissuedfollowedbydataforthatsubaddressandthe15subaddressesthatfollow,asequentialI2Cwritetransactionhastakenplace,andthedataforall16subaddressesissuccessfullyreceivedbytheTAS5721.
ForI2Csequentialwritetransactions,thesubaddressthenservesasthestartaddress,andtheamountofdatasubsequentlytransmitted,beforeastoporstartistransmitted,determineshowmanysubaddressesarewritten.
Aswastrueforrandomaddressing,sequentialaddressingrequiresthatacompletesetofdatabetransmitted.
Ifonlyapartialsetofdataiswrittentothelastsubaddress,thedataforthelastsubaddressisdiscarded.
However,allotherdatawrittenisaccepted;onlytheincompletedataisdiscarded.
Single-ByteWriteAsshowninFigure62,asingle-bytedatawritetransferbeginswiththemasterdevicetransmittingastartconditionfollowedbytheI2Cdeviceaddressandtheread/writebit.
Theread/writebitdeterminesthedirectionofthedatatransfer.
Forawritedatatransfer,theread/writebitwillbea0.
AfterreceivingthecorrectI2Cdeviceaddressandtheread/writebit,theDAPrespondswithanacknowledgebit.
Next,themastertransmitstheaddressbyteorbytescorrespondingtotheTAS5721internalmemoryaddressbeingaccessed.
Afterreceivingtheaddressbyte,theTAS5721againrespondswithanacknowledgebit.
Next,themasterdevicetransmitsthedatabytetobewrittentothememoryaddressbeingaccessed.
Afterreceivingthedatabyte,theTAS5721againrespondswithanacknowledgebit.
Finally,themasterdevicetransmitsastopconditiontocompletethesingle-bytedatawritetransfer.
Figure62.
Single-ByteWriteTransferMultiple-ByteWriteAmultiple-bytedatawritetransferisidenticaltoasingle-bytedatawritetransferexceptthatmultipledatabytesaretransmittedbythemasterdevicetotheDAPasshowninFigure63.
Afterreceivingeachdatabyte,theTAS5721respondswithanacknowledgebit.
Figure63.
Multiple-ByteWriteTransfer52SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012Single-ByteReadAsshowninFigure64,asingle-bytedatareadtransferbeginswiththemasterdevicetransmittingastartconditionfollowedbytheI2Cdeviceaddressandtheread/writebit.
Forthedatareadtransfer,bothawritefollowedbyareadareactuallydone.
Initially,awriteisdonetotransfertheaddressbyteorbytesoftheinternalmemoryaddresstoberead.
Asaresult,theread/writebitbecomesa0.
AfterreceivingtheTAS5721addressandtheread/writebit,TAS5721respondswithanacknowledgebit.
Inaddition,aftersendingtheinternalmemoryaddressbyteorbytes,themasterdevicetransmitsanotherstartconditionfollowedbytheTAS5721addressandtheread/writebitagain.
Thistimetheread/writebitbecomesa1,indicatingareadtransfer.
Afterreceivingtheaddressandtheread/writebit,theTAS5721againrespondswithanacknowledgebit.
Next,theTAS5721transmitsthedatabytefromthememoryaddressbeingread.
Afterreceivingthedatabyte,themasterdevicetransmitsanotacknowledgefollowedbyastopconditiontocompletethesinglebytedatareadtransfer.
Figure64.
Single-ByteReadTransferMultiple-ByteReadAmultiple-bytedatareadtransferisidenticaltoasingle-bytedatareadtransferexceptthatmultipledatabytesaretransmittedbytheTAS5721tothemasterdeviceasshowninFigure65.
Exceptforthelastdatabyte,themasterdevicerespondswithanacknowledgebitafterreceivingeachdatabyte.
Figure65.
MultipleByteReadTransferOutputModeandMUXSelectionTheTAS5721isahighlyconfigurabledevice,capableofoperatingin2.
0,SingleDevice2.
1andparallelbridgetiedload(PBTL)configurations.
Addtionally,themodulationschemecanbechangedforthechannelstooperateeitherinADorBDModulationmode.
Whilemanyconfigurationsarepossiblebecauseofthisflexibility,themajorityofusecasesuseswilloperateinoneoftheconfigurationsshownbelow.
Foreaseofuseandreducedcomplexity,thefigurebelowoutlinesboththeregistersettingsandtheoutputconfigurationsrequiredtosetthedeviceupforoperationinthesevariousmodes.
Theoutputconfigurationquickreferencetablebelowhighlightsthecontrolsthatarerequiredtoconfigurethedeviceforvariousoperationalmodes.
Pleasenotethatothercontrols,whicharenotdirectlyrelatedtotheoutputconfigurationmuxesmayalsoberequired.
Forexample,theInterChannelDelay(ICD)settingswilllikelyneedtobemodifiedtooptimizeforidlechannelnoise,cross-talk,anddistortionperformanceforeachoftheseconsiderations,inadditiontostartandstoptimeandothers.
Pleaseconsulttherespectiveregistersforthesecontrolstooptimizeforvariousotherpeformanceparametersandusecases.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback53ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comTable21.
OutputConfigurationQuickReferenceOutputModulationModeRegisterSettingsBlockDiagramConfiguration0x20[23]=00x20[19]=00x20[15:8]=0x77ADforBothOutputs0x05[7]=00x05[2]=00x25[23:8]=0x02130x1A[7:0]=0x0F2.
0(StereoBTL)0x20[23]=10x20[19]=10x20[15:8]=0x77BDforBothOutputs0x05[7]=00x05[2]=00x25[23:8]=0x02130x1A[7:0]=0x0A0x20[23]=00x20[19]=0SingleDevice2.
10x20[3]=0(StereoSingle0x05[7]=1Ended+MonoADforBothSEOutputs0x05[2]=1BTL)ADforSingleBTL0x25[23:8]=0x0132Note:IntheseOutput0x1A[7:0]=0x95described0x20[7:4]=0x7configurations,the0x21[8]=0polarityofthe0x20[25]=1signalbeingsenttoSPK_OUTBis0x20[23]=0inverted.
Forthis0x20[19]=0reason,care0x20[3]=1shouldbetakento0x05[7]=1ADforbothSEOutputsensurethatthe0x05[2]=1BDforSingleBTLspeakersare0x25[23:8]=0x0132Outputconnectedas0x1A[7:0]=0x95shownintheblock0x20[7:4]=0x7diagram.
0x21[8]=00x20[25]=10x05[7]=00x05[5]=00x05[2]=00x19[7:0]=0x3AAD0x1A[7:0]=0x0F0x20[23]=00x20[15:12]=0x70x25[23:8]=0x01231.
0MonoPBTL0x05[7]=00x05[5]=00x05[2]=00x19[7:0]=0x3ABD0x1A[7:0]=0x0A0x20[23]=10x20[15:12]=0x70x25[23:8]=0x01232.
1-ModeSupportTheTAS5721usesaspecialmid-ZrampsequencetoreduceclickandpopinSE-modeand2.
1-modeoperation.
Toenablethemid-Zramp,register0x05bitD7mustbesetto1.
Toenable2.
1mode,register0x05bitD2mustbesetto1.
TheSSTIMERpinshouldbeleftfloatinginthismode.
54SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012SupplyPumpingandPolarityInversionThehighdegreeofcorrelationbetweentheleftandrightchannelsofastereoaudiosignaldictatesthat,whentheleftaudiosignalispositive,therightaudiosignaltendstobepositiveaswell.
WhentheClassDisconfiguredforsingle-endedoperation(aswouldbethecaseforSingleDevice2.
1Operation),thisresultsinbothoutputsdrawingcurrentfromthesupplyrail"inphase".
Similarly,whentheleftaudiosignalisnegative,therightaudiosignaltendstobenegativeaswell.
Forsingle-endedoperation,bothoutputswilllikewiseforcecurrentintothegroundrail.
Thiscanleadtoaphenomenoncalled"supplypumping"inwhichthecapacitancesonthePVDDrailbegintostorecharge-raisingthevoltagelevelofPVDDaswell.
Thisnoiseinjectionontotherailisinphasewithandatasimilarfrequencyofthesignalbeingproducedbytheamplifieroutputstage.
ThisphenomenoncancauseissuesforotherdevicesattachedtothePVDDrail.
TheproblemdoesnotoccurforBTLoutputssinceoutputsofbothpolaritiesarealwayspresentforeachchannel.
Tocombatsupplypumpingin2.
1Mode,thedevicehasanintegratedspeaker-modevolumenegationfeature,which,essentiallyintroducesapolarityinversion(shiftby180°)toanyofthegivenchannels.
Bysettingthecorrectbitin0x20[31:24],itispossibletoinvertthepolarityoftheDAPchannelsthatdrivethePWMmodulatorblocks.
Thisallows,forinstance,theleftchanneltooperatewithitsdefaultpolarity,whiletherightchannelcouldhaveitspolarityinvertedtobalancecurrentflowintoandoutofthesupplies.
Thisprocedurecouldhaveanadverseimplicationonthestereoimagingoftheaudiosystembecause,ifthespeakersinthesystemareconnectedinthesamemannerastheywouldbeconnectedwhenbeingdrivenbytraditionalBTLchannels,thephaseofthesignalsbeingsenttothespeakersis180°outofphase.
Inordertopreventthisfromoccurring,thespeakeronthenegatedchannelmustbeconnected"backwards"(i.
e.
theClassDsignalforthenegatedchannelgetsconnectedtothenegativespeakerterminalandthepositiveterminalisgrounded).
Inthisway,supplypumpingisreducedwhilekeepingtheeffectivesignalpolaritythesame.
Thetableaboveincludesregistersettingswhichenablethepolarityinversion,socareshouldbetakentoadjustthepolarityofthespeakersifthisfeatureisleftenabled.
Ofcoursethisfeaturecanbeleftdisabledifdesired,providedthesupplypumpingphenomenondoesn'tcauseanyothersystemlevelissuesPBTL-ModeSupportTheTAS5721supportsparallelBTL(PBTL)modewithOUT_A/OUT_B(andOUT_C/OUT_D)connectedaftertheLCfilter.
InordertoputthepartinPBTLconfiguration,thePWMoutputmultiplexersshouldbeupdatedtosetthedeviceinPBTLmode.
OutputMuxRegister(0x25)shouldbewrittenwithavalueof0x01103245.
Also,thePWMshutdownregister(0x19)shouldbewrittenwithavalueof0x3A.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback55ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comDynamicRangeControl(DRC)TheDRCschemehasasinglethreshold,offset,andslope(allprogrammable).
ThereisonegangedDRCfortheleft/rightchannelsandoneDRCforthesubchannel.
TheDRCinput/outputdiagramisshowninFigure66.
RefertoGDEsoftwaretoolformoredescriptiononT,K,andOparameters.
Professional-qualitydynamicrangecompressionautomaticallyadjustsvolumetoflattenvolumelevel.
EachDRChasadjustablethreshold,offset,andcompressionlevels.
Programmableenergy,attack,anddecaytimeconstantsTransparentcompression:compressorscanattackfastenoughtoavoidapparentclippingbeforeengaging,anddecaytimescanbesetslowenoughtoavoidpumping.
Figure66.
DynamicRangeControlT=9.
23format,allotherDRCcoefficientsare3.
23formatFigure67.
DRCStructure56SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012BANKSWITCHINGTheTAS5721usesanapproachcalledbankswitchingtogetherwithautomaticsample-ratedetection.
Allprocessingfeaturesthatmustbechangedfordifferentsampleratesarestoredinternallyinthreebanks.
Theusercanprogramwhichsampleratesmaptoeachbank.
Bydefault,bank1isusedin32-kHzmode,bank2isusedin44.
1-or48-kHzmode,andbank3isusedforallotherrates.
Combinedwiththeclock-rateautodetectionfeature,bankswitchingallowstheTAS5721todetectautomaticallyachangeintheinputsamplerateandswitchtotheappropriatebankwithoutanyMCUintervention.
Anexternalcontrollerconfiguresbankablelocations(0x29-0x36,0x3A-0x3F,and0x58-0x5F)forallthreebanksduringtheinitializationsequence.
Ifautobankswitchingisenabled(register0x50,bits2:0),thentheTAS5721automaticallyswapsthecoefficientsforsubsequentsampleratechanges,avoidingtheneedforanyexternalcontrollerinterventionforasampleratechange.
Bydefault,bits2:0havethevalue000;indicatingthatbankswitchingisdisabled.
Inthatstate,updatestobankablelocationstakeimmediateeffect.
Awritetoregister0x50withbits2:0being001,010,or011bringsthesystemintothecoefficient-bank-updatestateupdatebank1,updatebank2,orupdatebank3,respectively.
AnysubsequentwritetobankablelocationsupdatesthecoefficientbanksstoredoutsidetheDAP.
Afterupdatingallthethreebanks,thesystemcontrollershouldissueawritetoregister0x50withbits2:0being100;thischangesthesystemstatetoautomaticbankswitchingmode.
Inautomaticbankswitchingmode,theTAS5721automaticallyswapsbanksbasedonthesamplerate.
CommandsequencesforupdatingDAPcoefficientscanbesummarizedasfollows:1.
Bankswitchingdisabled(default):DAPcoefficientwritestakeimmediateeffectandarenotinfluencedbysubsequentsampleratechanges.
ORBankswitchingenabled:(a)Updatebank-1mode:Write"001"tobits2:0ofreg0x50.
Loadthe32kHzcoefficients.
(b)Updatebank-2mode:Write"010"tobits2:0ofreg0x50.
Loadthe48kHzcoefficients.
(c)Updatebank-3mode:Write"011"tobits2:0ofreg0x50.
Loadtheothercoefficients.
(d)Enableautomaticbankswitchingbywriting"100"tobits2:0ofreg0x50.
26-Bit3.
23NumberFormatAllmixergaincoefficientsare26-bitcoefficientsusinga3.
23numberformat.
Numbersformattedas3.
23numbersmeansthatthereare3bitstotheleftofthedecimalpointand23bitstotherightofthedecimalpoint.
ThisisshowninFigure68.
Figure68.
3.
23FormatCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback57ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comThedecimalvalueofa3.
23formatnumbercanbefoundbyfollowingtheweightingshowninFigure68.
Ifthemostsignificantbitislogic0,thenumberisapositivenumber,andtheweightingshownyieldsthecorrectnumber.
Ifthemostsignificantbitisalogic1,thenthenumberisanegativenumber.
Inthiscaseeverybitmustbeinverted,a1addedtotheresult,andthentheweightingshowninFigure69appliedtoobtainthemagnitudeofthenegativenumber.
Figure69.
ConversionWeightingFactors—3.
23FormattoFloatingPointGaincoefficients,enteredviatheI2Cbus,mustbeenteredas32-bitbinarynumbers.
Theformatofthe32-bitnumber(4-byteor8-digithexadecimalnumber)isshowninFigure70Figure70.
Alignmentof3.
23Coefficientin32-BitI2CWordTable22.
SampleCalculationfor3.
23FormatdBLinearDecimalHex(3.
23Format)018,388,6080080000051.
778279414,917,28800E39EA8–50.
56234134,717,2600047FACCXL=10(X/20)D=8,388,608*LH=dec2hex(D,8)Table23.
SampleCalculationfor9.
17FormatdBLinearDecimalHex(9.
17Format)01131,0722000051.
77231,99738A3D–50.
5673,40011EB8XL=10(X/20)D=131,072*LH=dec2hex(D,8)58SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012RecommendedUseModelFigure71.
RecommendedCommandSequenceCopyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback59ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comFigure72.
PowerLossSequenceRecommendedCommandSequencesInitializationSequenceUsethefollowingsequencetopower-upandinitializethedevice:1.
HoldalldigitalinputslowandrampupAVDD/DVDDtoatleast3V.
2.
InitializedigitalinputsandPVDDsupplyasfollows:DriveRST=0,PDN=1,andotherdigitalinputstotheirdesiredstatewhileensuringthatallarenevermorethan2.
5VaboveAVDD/DVDD.
Waitatleast100s,driveRST=1,andwaitatleastanother13.
5ms.
RampupPVDDtoatleast8Vwhileensuringthatitremainsbelow6Vforatleast100safterAVDD/DVDDreaches3V.
Thenwaitatleastanother10s.
3.
Trimoscillator(write0x00toregister0x1B)andwaitatleast50ms.
4.
ConfiguretheDAPviaI2C(seeUsers'sGuidefortypicalvalues).
5.
Configureremainingregisters.
6.
Exitshutdown(sequencedefinedbelow).
NormalOperationThefollowingaretheonlyeventssupportedduringnormaloperation:1.
Writestomaster/channelvolumeregisters.
2.
Writestosoftmuteregister.
3.
Enterandexitshutdown(sequencedefinedbelow).
Note:Event3isnotsupportedfor240ms+1.
3*tstartaftertrimfollowingAVDD/DVDDpowerupramp(wheretstartis300mswhenmid-Zrampisenabledandisotherwisespecifiedbyregister0x1A).
60SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012ShutdownSequenceEnter:1.
Write0x40toregister0x05.
2.
Waitatleast1ms+1.
3*tstop(wheretstopisspecifiedbyregister0x1A).
3.
Ifdesired,reconfigurebyreturningtostep4ofinitializationsequence.
Exit:1.
Write0x00toregister0x05(exitshutdowncommandmaynotbeservicedforasmuchas240msaftertrimfollowingAVDD/DVDDpowerupramp).
2.
Waitatleast1ms+1.
3*tstart(wheretstartis300mswhenmid-Zrampisenabledandisotherwisespecifiedbyregister0x1A).
3.
Proceedwithnormaloperation.
Power-DownSequenceUsethefollowingsequencetopowerdownthedeviceanditssupplies:1.
Iftimepermits,entershutdown(sequencedefinedabove);else,incaseofsuddenpowerloss,assertPDN=0andwaitatleast2ms.
2.
AssertRST=0.
3.
DrivedigitalinputslowandrampdownPVDDsupplyasfollows:DrivealldigitalinputslowafterRSThasbeenlowforatleast2s.
RampdownPVDDwhileensuringthatitremainsabove8VuntilRSThasbeenlowforatleast2s.
4.
RampdownAVDD/DVDDwhileensuringthatitremainsabove3VuntilPVDDisbelow6Vandthatitisnevermorethan2.
5Vbelowthedigitalinputs.
USINGHEADPHONEAMPLIFIERORLINEDRIVERINTAS5721Thisdevicehasastereooutputwhichcanbeusedasalinedriveroraheadphonedriverthatcanoutput2-Vrmsstereo.
Anaudiosystemcanbesetupfordifferentapplicationsusingthisdevice.
USINGHEADPHONEAMPLIFIERINTAS5721ThedevicecanberepresentedasshowninFigure73:analoginputs(single-ended)asDR_INA(pin7)andDR_INB(pin10)withtheoutputsDR_OUTA(pin8)andDR_OUTB(pin9).
Figure73.
Headphone/LineDriverwithAnalogInputDR_SDpincanbeusedtoturnONorOFFtheheadphoneamplifierandlinedriver.
Speakerchannelsareindependentofheadphoneandlinedriverinthismode.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback61ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comUSINGLINEDRIVERAMPLIFIERINTAS5721Single-supplyheadphoneandlinedriveramplifierstypicallyrequiredc-blockingcapacitors.
ThetopdrawinginFigure74illustratestheconventionallinedriveramplifierconnectiontotheloadandoutputsignal.
DCblockingcapacitorsforheadphoneampsareoftenlargeinvalue,andamutecircuitisneededduringpoweruptominimizeclickandpopforbothheadphoneandlinedriver.
TheoutputcapacitorsandmutecircuitsconsumePCBareaandincreasecostofassembly,andcanreducethefidelityoftheaudiooutputsignal.
Figure74.
ConventionalandDirectPathHPandLineDriverTheDirectPathamplifierarchitectureoperatesfromasinglesupplybutmakesuseofaninternalchargepumptoprovideanegativevoltagerail.
CombiningtheuserprovidedpositiverailandthenegativerailgeneratedbytheIC,thedeviceoperatesinwhatiseffectivelyasplitsupplymode.
Theoutputvoltagesarenowcenteredatzerovoltswiththecapabilitytoswingtothepositiverailornegativerail,combiningthiswiththebuiltinclickandpopreductioncircuit,theDirectPathamplifierrequiresnooutputdcblockingcapacitors.
ThebottomblockdiagramandwaveformofFigure74illustratetheground-referencedheadphoneandlinedriverarchitecture.
ThisisthearchitectureoftheTAS5721.
COMPONENTSELECTIONChargePumpThechargepumpflyingcapacitorservestotransferchargeduringthegenerationofthenegativesupplyvoltage.
ThecapacitorconnectedtotheDR_VSSpinmustbeatleastequaltothechargepumpcapacitorinordertoallowmaximumchargetransfer.
LowESRcapacitorsareanidealselection,andavalueof1Fistypical.
Capacitorvaluesthataresmallerthan1FarenotrecommendedfortheDR_VSSpinastheywilllimitthenegativevoltageswingwhendrivinglowimpedanceloads.
62SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721TAS5721www.
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comSLOS739–JULY2012DecouplingCapacitorsTheTAS5721isaDirectPathamplifierthatrequiresadequatepowersupplydecouplingtoensurethatthenoiseandtotalharmonicdistortion(THD)arelow.
Agoodlowequivalent-series-resistance(ESR)ceramiccapacitor,typically1F,placedascloseaspossibletothedevicePVDDleadsworksbest.
PlacingthisdecouplingcapacitorclosetotheTAS5721isimportantfortheperformanceoftheamplifier.
Forfilteringlowerfrequencynoisesignals,a10Forgreatercapacitorplacedneartheaudiopoweramplifierwouldalsohelp,butitisnotrequiredinmostapplicationsbecauseofthehighPSRRofthisdevice.
PleaserefertotheTAS5721fortherecommendedlayoutforthesecomponents.
GainSettingResistorsRangesThegainsettingresistors,RinandRfb,mustbechosensothatnoise,stabilityandinputcapacitorsizeoftheTAS5721iskeptwithinacceptablelimits.
VoltagegainisdefinedasRfbdividedbyRin.
Selectingvaluesthataretoolowdemandsalargeinputac-couplingcapacitor,CIN.
Selectingvaluesthataretoohighincreasesthenoiseoftheamplifier.
Table24liststherecommendedresistorvaluesfordifferentgainsettings.
Table24.
RecommendedResistorValuesINPUTRESISTORFEEDBACKRESISTORDIFFERENTIALINVERTINGINPUTNONINVERTINGVALUE,RinVALUE,RfbINPUTGAINGAININPUTGAIN10kΩ10kΩ1V/V–1V/V2V/V10kΩ15kΩ1.
5V/V–1.
5V/V2.
5V/V10kΩ20kΩ2V/V–2V/V3V/V4.
7kΩ47kΩ10V/V–10V/V11V/VFigure75.
InvertingGainConfigurationInput-BlockingCapacitorsDCinput-blockingcapacitorsarerequiredtobeaddedinserieswiththeaudiosignalintotheinputpinsoftheTAS5721.
ThesecapacitorsblocktheDCportionoftheaudiosourceandallowtheTAS5721inputstobeproperlybiasedtoprovidemaximumperformance.
TheinputblockingcapacitorsalsolimittheDCgainto1,limitingtheDC-offsetvoltageattheoutput.
Thesecapacitorsformahigh-passfilterwiththeinputresistor,Rin.
ThecutofffrequencyiscalculatedusingEquation1.
Forthiscalculation,thecapacitanceusedistheinput-blockingcapacitorandtheresistanceistheinputresistorchosenfromTable24,thenthefrequencyand/orcapacitancecanbedeterminedwhenoneofthetwovaluesisgiven.
(1)UsingtheTAS5721asaSecondOrderFilterSeveralaudioDACsusedtodayrequireanexternallow-passfiltertoremoveoutofbandnoise.
ThisispossiblewiththeTAS5721asitcanbeusedlikeastandardOPAMP.
Severalfiltertopologiescanbeimplemented,bothsingleendedanddifferential.
InthefigurebelowaMultiFeedBack(MFB),withdifferentialinputandsingleendedinputisshown.
AnAC-couplingcapacitortoremoveDC-contentfromthesourceisshown.
ItservestoblockanyDCcontentfromthesourceandlowerstheDC-gainto1,helpingreducetheoutputdc-offsettoaminimum.
Copyright2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback63ProductFolderLinks:TAS5721TAS5721SLOS739–JULY2012www.
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comThecomponentvaluescanbecalculatedwiththehelpoftheTIFilterProprogramavailableontheTIwebsiteat:focus.
ti.
comFigure76.
Second-OrderActiveLow-PassFilterTheresistorvaluesshouldhavealowvalueforobtaininglownoise,butshouldalsohaveahighenoughvaluetogetasmallsizeac-couplingcap.
TheC2canbesplitintwowiththemidpointconnectedtoGND;thiscanincreasethecommon-modeattenuation.
Pop-FreePowerUpPop-freepowerupisensuredbykeepingtheDR_SDlowduringpowersupplyrampupanddown.
ThepinshouldbekeptlowuntiltheinputAC-couplingcapacitorsarefullychargedbeforeassertingtheDR_SDpinhigh,thiswayproperprechargeoftheAC-couplingcapacitorsisperformedandpop-lesspowerupisachieved.
Figure77illustratesthepreferredsequence.
Figure77.
PowerUporDownSequence64SubmitDocumentationFeedbackCopyright2012,TexasInstrumentsIncorporatedProductFolderLinks:TAS5721PACKAGEOPTIONADDENDUMwww.
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com11-Apr-2013Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinishMSLPeakTemp(3)OpTemp(°C)Top-SideMarkings(4)SamplesTAS5721DCAACTIVEHTSSOPDCA4840Green(RoHS&noSb/Br)CUNIPDAULevel-3-260C-168HR0to85TAS5721TAS5721DCARACTIVEHTSSOPDCA482000Green(RoHS&noSb/Br)CUNIPDAULevel-3-260C-168HR0to85TAS5721(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
ti.
com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)MultipleTop-SideMarkingswillbeinsideparentheses.
OnlyoneTop-SideMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireTop-SideMarkingforthatdevice.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantTAS5721DCARHTSSOPDCA482000330.
024.
48.
615.
81.
812.
024.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com10-Jul-2013PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)TAS5721DCARHTSSOPDCA482000367.
0367.
045.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com10-Jul-2013PackMaterials-Page2IMPORTANTNOTICETexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,enhancements,improvementsandotherchangestoitssemiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.
Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentandcomplete.
Allsemiconductorproducts(alsoreferredtohereinas"components")aresoldsubjecttoTI'stermsandconditionsofsalesuppliedatthetimeoforderacknowledgment.
TIwarrantsperformanceofitscomponentstothespecificationsapplicableatthetimeofsale,inaccordancewiththewarrantyinTI'stermsandconditionsofsaleofsemiconductorproducts.
TestingandotherqualitycontroltechniquesareusedtotheextentTIdeemsnecessarytosupportthiswarranty.
Exceptwheremandatedbyapplicablelaw,testingofallparametersofeachcomponentisnotnecessarilyperformed.
TIassumesnoliabilityforapplicationsassistanceorthedesignofBuyers'products.
BuyersareresponsiblefortheirproductsandapplicationsusingTIcomponents.
TominimizetherisksassociatedwithBuyers'productsandapplications,Buyersshouldprovideadequatedesignandoperatingsafeguards.
TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanypatentright,copyright,maskworkright,orotherintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIcomponentsorservicesareused.
InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservicesorawarrantyorendorsementthereof.
Useofsuchinformationmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI.
ReproductionofsignificantportionsofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandisaccompaniedbyallassociatedwarranties,conditions,limitations,andnotices.
TIisnotresponsibleorliableforsuchaltereddocumentation.
Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.
ResaleofTIcomponentsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatcomponentorservicevoidsallexpressandanyimpliedwarrantiesfortheassociatedTIcomponentorserviceandisanunfairanddeceptivebusinesspractice.
TIisnotresponsibleorliableforanysuchstatements.
Buyeracknowledgesandagreesthatitissolelyresponsibleforcompliancewithalllegal,regulatoryandsafety-relatedrequirementsconcerningitsproducts,andanyuseofTIcomponentsinitsapplications,notwithstandinganyapplications-relatedinformationorsupportthatmaybeprovidedbyTI.
Buyerrepresentsandagreesthatithasallthenecessaryexpertisetocreateandimplementsafeguardswhichanticipatedangerousconsequencesoffailures,monitorfailuresandtheirconsequences,lessenthelikelihoodoffailuresthatmightcauseharmandtakeappropriateremedialactions.
BuyerwillfullyindemnifyTIanditsrepresentativesagainstanydamagesarisingoutoftheuseofanyTIcomponentsinsafety-criticalapplications.
Insomecases,TIcomponentsmaybepromotedspecificallytofacilitatesafety-relatedapplications.
Withsuchcomponents,TI'sgoalistohelpenablecustomerstodesignandcreatetheirownend-productsolutionsthatmeetapplicablefunctionalsafetystandardsandrequirements.
Nonetheless,suchcomponentsaresubjecttotheseterms.
NoTIcomponentsareauthorizedforuseinFDAClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersofthepartieshaveexecutedaspecialagreementspecificallygoverningsuchuse.
OnlythoseTIcomponentswhichTIhasspecificallydesignatedasmilitarygradeor"enhancedplastic"aredesignedandintendedforuseinmilitary/aerospaceapplicationsorenvironments.
BuyeracknowledgesandagreesthatanymilitaryoraerospaceuseofTIcomponentswhichhavenotbeensodesignatedissolelyattheBuyer'srisk,andthatBuyerissolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsinconnectionwithsuchuse.
TIhasspecificallydesignatedcertaincomponentsasmeetingISO/TS16949requirements,mainlyforautomotiveuse.
Inanycaseofuseofnon-designatedproducts,TIwillnotberesponsibleforanyfailuretomeetISO/TS16949.
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