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1FEATURESTMS470R1A384www.
ti.
comSPNS110E–AUGUST2005–REVISEDMAY200816/32-BitRISCFlashMicrocontroller23High-PerformanceStaticCMOSTechnology–TwoSerialCommunicationInterfaces(SCIs)TMS470R1x16/32-BitRISCCore(ARM7TDMI)–224SelectableBaudRates–24-MHzSystemClock(48-MHzPipeline)–Asynchronous/IsosynchronousModes–Independent16/32-BitInstructionSet–TwoStandardCANControllers(SCC)–OpenArchitectureWithThird-PartySupport–16-MailboxCapacity–Built-InDebugModule–FullyCompliantWithCANProtocol,Version2.
0BIntegratedMemory–ClassIISerialInterfaceB(C2SIb)–384K-ByteProgramFlash–Normal10.
4Kbpsand4XMode–ThreeBanksWith18Contiguous41.
6KbpsSectors–ThreeInter-IntegratedCircuit(I2C)Modules–32K-ByteStaticRAM(SRAM)(SeeI2CNotesinTMS470R1A384SiliconOperatingFeaturesErrata,LiteratureNumberSPNZ148)–CoreSupplyVoltage(VCC):1.
71Vto2.
05V–Multi-MasterandSlaveInterfaces–I/OSupplyVoltage(VCCIO):3.
0Vto3.
6V–Upto400Kbps(FastMode)–Low-PowerModes:STANDBYandHALT–7-and10-BitAddressCapability–ExtendedIndustrialTemperatureRangeHigh-EndTimer(HET)470+SystemModule–12ProgrammableI/OChannels:–32-BitAddressSpaceDecoding–12High-ResolutionPins–BusSupervisionforMemory/Peripherals–High-ResolutionShareFeature(XOR)–AnalogWatchdog(AWD)Timer–High-EndTimerRAM–EnhancedReal-TimeInterrupt(RTI)–64-InstructionCapacity–InterruptExpansionModule(IEM)ExternalClockPrescale(ECP)Module–SystemIntegrityandFailureDetection–ProgrammableLow-FrequencyExternalDirectMemoryAccess(DMA)ControllerClock(CLK)–32ControlPacketsand16Channels12-Channel10-BitMulti-BufferedZero-PinPhase-LockedLoop(ZPLL)-BasedAnalog-to-DigitalConverter(MibADC)ClockModuleWithPrescaler–32-WordFIFOBuffer–Multiply-by-4or-8InternalZPLLOption–Single-orContinuous-ConversionModes–ZPLLBypassMode–1.
55-sMinimumSample/ConversionTimeExpansionBusModule(EBM)(PGEPackage)–CalibrationModeandSelf-TestFeatures–Supports8-and16-BitExpansionBus55DedicatedGeneral-PurposeI/O(GIO)PinsMemoryInterfaceMappingsand39AdditionalPeripheralI/Os(PGE)–40I/OExpansionBusPins14DedicatedGeneral-PurposeI/O(GIO)PinsTenCommunicationInterfaces:and39AdditionalPeripheralI/Os(PZ)–TwoSerialPeripheralInterfaces(SPIs)FlexibleInterruptHandling–255ProgrammableBaudRatesEightExternalInterrupts1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2ARM7TDMIisatrademarkofAdvancedRISCMachinesLimited(ARM).
3Allothertrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2005–2008,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comOn-ChipScan-BaseEmulationLogic,IEEE100-PinPlasticLow-ProfileQuadFlatpackStandard1149.
1(1)(JTAG)Test-AccessPort(PZSuffix)144-PinPlasticLow-ProfileQuadFlatpack(1)Thetest-accessportiscompatiblewiththeIEEEStandard1149.
1-1990,IEEEStandardTest-AccessPortandBoundary(PGESuffix)ScanArchitecturespecification.
Boundaryscanisnotsupportedonthisdevice.
TMS470R1A384144-PinPGEPackage(TopView)(WithoutExpansionBus)2SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008TMS470R1A384144-PinPGEPackage(TopView)(withExpansionBus)Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTMS470R1A384100-PinPZPackage(TopView)4SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384DESCRIPTIONTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008TheTMS470R1A384(1)devicesaremembersoftheTexasInstrumentsTMS470R1xfamilyofgeneral-purpose16/32-bitreducedinstructionsetcomputer(RISC)microcontrollers.
TheA384microcontrolleroffershighperformanceutilizingthehigh-speedARM7TDMI16/32-bitRISCcentralprocessingunit(CPU),resultinginahighinstructionthroughputwhilemaintaininggreatercodeefficiency.
TheARM7TDMI16/32-bitRISCCPUviewsmemoryasalinearcollectionofbytesnumberedupwardsfromzero.
TheA384utilizesthebig-endianformatwherethemostsignificantbyteofawordisstoredatthelowest-numberedbyteandtheleastsignificantbyteatthehighest-numberedbyte.
High-endembeddedcontrolapplicationsdemandmoreperformancefromtheircontrollerswhilemaintaininglowcosts.
TheA384RISCcorearchitectureofferssolutionstotheseperformanceandcostdemandswhilemaintaininglowpowerconsumption.
TheA384devicescontainthefollowing:ARM7TDMI16/32-bitRISCCPUTMS470R1xsystemmodule(SYS)with470+enhancements384K-byteflash32K-byteSRAMZero-pinphase-lockedloop(ZPLL)clockmoduleAnalogwatchdog(AWD)timerEnhancedreal-timeinterrupt(RTI)moduleInterruptexpansionmodule(IEM)Twoserialperipheralinterface(SPI)modulesTwoserialcommunicationsinterface(SCI)modulesTwostandardCANcontrollers(SCC)Threeinter-integratedcircuit(I2C)modulesClassIIserialinterfaceB(C2SIb)module10-bitmulti-bufferedanalog-to-digitalconverter(MibADC),with12inputchannelsHigh-endtimer(HET)controlling12I/OsExternalclockprescale(ECP)Expansionbusmodule(EBM)Upto87I/Opinsand1input-onlypin(PGEsuffixonly),upto51I/Opinsand1input-onlypin(PZsuffixonly)Thefunctionsperformedbythe470+systemmodule(SYS)include:AddressdecodingMemoryprotectionMemoryandperipheralsbussupervisionResetandabortexceptionmanagementPrioritizationforallinternalinterruptsourcesDeviceclockcontrolParallelsignatureanalysis(PSA)Theenhancedreal-timeinterrupt(RTI)moduleontheA384hastheoptiontobedrivenbytheoscillatorclock.
Thisdatasheetincludesdevice-specificinformationsuchasmemoryandperipheralselectassignment,interruptpriority,andadevicememorymap.
ForamoredetailedfunctionaldescriptionoftheSYSmodule,seetheTMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189).
TheA384memoryincludesgeneral-purposeSRAMsupportingsingle-cycleread/writeaccessesinbyte,half-word,andwordmodes.
Theflashmemoryonthisdeviceisanonvolatile,electricallyerasableandprogrammablememoryimplementedwitha32-bit-widedatabusinterface.
Theflashoperateswithasystemclockfrequencyofupto24MHz.
Wheninpipelinemode,theflashoperateswithasystemclockfrequencyofupto48MHz.
Formoredetailedinformationontheflash,seetheFlashsectionofthisdatasheetandtheTMS470R1xF05FlashReferenceGuide(literaturenumberSPNU213).
(1)Throughouttheremainderofthisdocument,theTMS470R1A384isreferredtoaseitherthefulldevicenameorasA384.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTheA384devicehastencommunicationinterfaces:twoSPIs,twoSCIs,twoSCCs,aC2SI,andthreeI2Cs.
TheSPIprovidesaconvenientmethodofserialinteractionforhigh-speedcommunicationsbetweensimilarshift-registertypedevices.
TheSCIisafull-duplex,serialI/OinterfaceintendedforasynchronouscommunicationbetweentheCPUandotherperipheralsusingthestandardnon-return-to-zero(NRZ)format.
TheSCCusesaserial,multimastercommunicationprotocolthatefficientlysupportsdistributedreal-timecontrolwithrobustcommunicationratesofupto1megabitpersecond(Mbps).
TheSCCisidealforapplicationsoperatinginnoisyandharshenvironments(e.
g.
,industrialfields)thatrequirereliableserialcommunicationormultiplexedwiring.
TheC2SIballowstheA384totransmitandreceivemessagesonaclassIInetworkfollowinganSAEJ1850(2)standard.
TheI2Cmoduleisamulti-mastercommunicationmoduleprovidinganinterfacebetweentheA384microcontrollerandanI2C-compatibledeviceviatheI2Cserialbus.
TheI2Csupportsboth100Kbpsand400Kbpsspeeds.
FormoredetailedfunctionalinformationontheSPI,SCI,andCANperipherals,seethespecificreferenceguides(literaturenumbersSPNU195,SPNU196,andSPNU197).
FormoredetailedfunctionalinformationontheI2C,seetheTMS470R1xInter-IntegratedCircuit(I2C)ReferenceGuide(literaturenumberSPNU223).
FormoredetailedfunctionalinformationontheC2SI,seetheTMS470R1xClassIISerialInterfaceB(C2SIb)ReferenceGuide(literaturenumberSPNU214).
TheHETisanadvancedintelligenttimerthatprovidessophisticatedtimingfunctionsforreal-timeapplications.
Thetimerissoftware-controlled,usingareducedinstructionset,withaspecializedtimermicromachineandanattachedI/Oport.
TheHETcanbeusedforcompare,capture,orgeneral-purposeI/O.
Itisespeciallywellsuitedforapplicationsrequiringmultiplesensorinformationanddriveactuatorswithcomplexandaccuratetimepulses.
TheHETusedinthisdeviceisthehigh-endtimerlite.
IthasfewerI/Osthantheusual32inastandardHET.
FormoredetailedfunctionalinformationontheHET,seetheTMS470R1xHigh-EndTimer(HET)ReferenceGuide(literaturenumberSPNU199).
TheA384HETperipheralcontainstheXOR-sharefeature.
ThisfeatureallowstwoadjacentHEThigh-resolutionchannelstobeXORedtogether,makingitpossibletooutputsmallerpulsesthanastandardHET.
FormoredetailedinformationontheHETXOR-sharefeature,seetheTMS470R1xHigh-EndTimer(HET)ReferenceGuide(literaturenumberSPNU199).
TheA384devicehasone10-bit-resolutionsample-and-holdMibADC.
EachoftheMibADCchannelscanbeconvertedindividuallyorcanbegroupedbysoftwareforsequentialconversionsequences.
Therearethreeseparategroupings,twoofwhichcanbetriggeredbyanexternalevent.
Eachsequencecanbeconvertedoncewhentriggeredorconfiguredforcontinuousconversionmode.
FormoredetailedfunctionalinformationontheMibADC,seetheTMS470R1xMulti-BufferedAnalog-to-DigitalConverter(MibADC)ReferenceGuide(literaturenumberSPNU206).
Thezero-pinphase-lockedloop(ZPLL)clockmodulecontainsaphase-lockedloop,aclock-monitorcircuit,aclock-enablecircuit,andaprescaler(withprescalevaluesof1–8).
ThefunctionoftheZPLListomultiplytheexternalfrequencyreferencetoahigherfrequencyforinternaluse.
TheZPLLprovidesACLKtothesystem(SYS)module.
TheSYSmodulesubsequentlyprovidessystemclock(SYSCLK),real-timeinterruptclock(RTICLK),CPUclock(MCLK),andperipheralinterfaceclock(ICLK)toallotherA384devicemodules.
FormoredetailedfunctionalinformationontheZPLL,seetheTMS470R1xZero-PinPhase-LockedLoop(ZPLL)ClockModuleReferenceGuide(literaturenumberSPNU212).
NOTE:ACLKshouldnotbeconfusedwiththeMibADCinternalclock,ADCLK.
ACLKisthecontinuoussystemclockfromanexternalresonator/crystalreference.
Theexpansionbusmodule(EBM)isastand-alonemodulethatsupportsthemultiplexingoftheGIOfunctionsandtheexpansionbusinterface.
FormoreinformationontheEBM,seetheTMS470R1xExpansionBusModule(EBM)ReferenceGuide(literaturenumberSPNU222).
TheA384devicealsohasanexternalclockprescaler(ECP)modulethat,whenenabled,outputsacontinuousexternalclock(ECLK)onaspecifiedGIOpin.
TheECLKfrequencyisauser-programmableratiooftheperipheralinterfaceclock(ICLK)frequency.
FormoredetailedfunctionalinformationontheECP,seetheTMS470R1xExternalClockPrescaler(ECP)ReferenceGuide(literaturenumberSPNU202).
(2)SAEStandardJ1850ClassBDataCommunicationNetworkInterface.
6SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384DeviceCharacteristicsTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008TheA384deviceisaderivativeoftheF05systememulationdeviceSE470R1VB8AD.
Table1identifiesallthecharacteristicsoftheA384deviceexcepttheSYSTEMandCPU,whicharegeneric.
Table1.
DeviceCharacteristicsTMS470R1A384CHARACTERISTICSCOMMENTSDEVICEDESCRIPTIONMEMORYForthenumberofmemoryselectsonthisdevice,seeTable3,TMS470R1A384MemorySelectionAssignment.
Pipeline/non-pipelineFlashispipelinecapable.
384K-byteflashTheA384RAMisimplementedinone16K-bytearrayselectedbyInternalMemory32K-byteSRAMtwomemory-selectsignals(seeTable3,TMS470R1A384MemorySelectionAssignment).
PERIPHERALSForthedevice-specificinterruptpriorityconfigurations,seeTable6,InterruptPriority(IEMandCIM).
Forthe1K-byteperipheraladdressrangesandtheirperipheralselects,seeTable4,A384Peripherals,SystemModule,andFlashBaseAddresses.
CLOCKZPLLZero-pinPLLhasnoexternalloopfilterpins.
Expansionbusmodulewith40pins.
Supports8-and16-bitExpansionBusEBMmemories,PGEpackageonly.
SeeTable7fordetails.
InthePGEpackage,PortAhas8externalpins;PortBhasonly1externalpin;PortsC,D,E,F,andGeachhave8externalpins;and55I/O(PGEsuffix)PortHhas6externalpins.
General-PurposeI/Os14I/O(PZsuffix)InthePZpackage,PortAhas8externalpins,PortBhas1externalpin,andPortHhas5externalpins.
ECPYesSCI2(3-pin)CAN(HECCand/orSCC)2SCCTwostandardCANcontrollersSPI(5pin,4pin,or3pin)2(5-pin)C2SIb1I2C3Thehigh-resolution(HR)Sharefeatureallowseven-numberedHRpinstosharethenexthigherodd-numberedHRpinstructures.
ThisHRsharingisindependentofwhetherornottheoddpinisavailableHETwithXORShare12I/Oexternally.
Ifanoddpinisavailableexternallyandshared,thentheoddpincanonlybeusedasageneral-purposeI/O.
FormoreinformationonHRSHARE,seetheTMS470R1xHigh-EndTimer(HET)ReferenceGuide(literaturenumberSPNU199).
HETRAM64-instructioncapacity10-bit12-channelBoththelogicandregistersforafull16-channelMibADCareMibADC64-wordFIFOpresent.
CoreVoltage1.
8VI/OVoltage3.
3VPins144/100PackagesPGE/PZCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comFunctionalBlockDiagramA.
GIOC[4:0],GIOD[5:0],GIOE[5:0],GIOF[7:0],andGIOH[0],whicharemultiplexedwithEBM,arenotavailableonthePZpackage.
SeeTable7forEBM-to-GIOmapping.
8SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Table2.
TerminalFunctionsTERMINALINTERNALINPUTOUTPUTPULLUP/DESCRIPTIONVOLTAGE(1)(2)CURRENT(3)NAMEPZPGEPULLDOWNHIGH-ENDTIMER(HET)HET[0]5173Timerinputcaptureoroutputcompare.
TheHET[1]5072HET[8:0,18,20,22]applicablepinscanbeHET[2]4971programmedasgeneral-purposeinput/outputHET[3]4666(GIO)pins.
Allarehigh-resolutionpins.
Thehigh-resolution(HR)SHAREfeatureallowsHET[4]4565evenHRpinstosharethenexthigheroddHRHET[5]4463pinstructures.
ThisHRsharingisindependent3.
3V2mAofwhetherornottheoddpinisavailableHET[6]69externally.
IfanoddpinisavailableexternallyHET[7]711andshared,thentheoddpincanonlybeusedHET[8]812asageneral-purposeI/O.
FormoreinformationonHRSHARE,seetheTMS470R1xHigh-EndHET[18]915Timer(HET)ReferenceGuide(literaturenumberHET[20]1218SPNU199).
HET[22]1319STANDARDCANCONTROLLER(SCC)CAN1SRX58835-Vtolerant4mASCC1receivepinorGIOpinCAN1STX59843.
3V2mASCC1transmitpinorGIOpinCAN2SRX37545-Vtolerant4mASCC2receivepinorGIOpinCAN2STX38553.
3V2mASCC2transmitpinorGIOpinCLASSIISERIALINTERFACE(C2SIB)C2SILPN14213.
3V2mAC2SIbmoduleloopbackenablepinorGIOpinC2SIRX15225-Vtolerant4mAC2SIbmodulereceivedatainputpinorGIOpinC2SIbmoduletransmitdataoutputpinorGIOC2SITX16243.
3V2mApinGENERAL-PURPOSEI/O(GIO)GIOA[0]/INT[0]99141GIOA[1]/INT[1]/ECLK96136GIOA[2]/INT[2]95134General-purposeinput/outputpins.
GIOA[7:0]/INT[7:0]areinterrupt-capablepins.
GIOA[3]/INT[3]941335-Vtolerant4mAGIOA[1]/INT[1]/ECLKpinismultiplexedwiththeGIOA[4]/INT[4]89127externalclock-outfunctionoftheexternalclockprescale(ECP)module.
GIOA[5]/INT[5]6798GIOA[6]/INT[6]5578GIOA[7]/INT[7]5679GIOB[0]/DMAREQ[0]3043GIOC[0]/EBOE-135GIOB[0],GIOC[4:0],GIOD[5:0],GIOE[7:0:],GIOC[1]/EBWR[0]-128GIOF[7:0],GIOG[7:0],andGIOH[5:0]are3.
3V2mAIPD(20A)multiplexedwiththeexpansionbusmodule.
GIOC[2]/EBWR[1]-126SeeTable7.
GIOC[3]/EBCS[5]-120GIOC[4]/EBCS[6]-119(1)PWR=power,GND=ground,REF=referencevoltage,NC=noconnect(2)AllI/Opins,exceptRST,areconfiguredasinputswhilePORRSTislowandimmediatelyafterPORRSTgoeshigh.
(3)IPD=internalpulldown,IPU=internalpullup(allinternalpullupsandpulldownsareactiveoninputpins,independentofthePORRSTstate.
)Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTable2.
TerminalFunctions(continued)TERMINALINTERNALINPUTOUTPUTPULLUP/DESCRIPTIONVOLTAGE(1)(2)CURRENT(3)NAMEPZPGEPULLDOWNGENERAL-PURPOSEI/O(GIO)(CONTINUED)GIOD[0]/EBADDR[0]-42GIOD[1]/EBADDR[1]-39GIOD[2]/EBADDR[2]-35GIOD[3]/EBADDR[3]-30GIOD[4]/EBADDR[4]-27GIOD[5]/EBADDR[5]-23GIOE[0]/EBDATA[0]-44GIOE[1]/EBDATA[1]-47GIOE[2]/EBDATA[2]-58GIOE[3]/EBDATA[3]-61GIOE[4]/EBDATA[4]-64GIOE[5]/EBDATA[5]-67GIOE[6]/EBDATA[6]-70GIOE[7]/EBDATA[7]-77GIOF[0]/EBADDR[6]/-80EBDATA[8]GIOB[0],GIOC[4:0],GIOD[5:0],GIOE[7:0:],GIOF[1]/EBADDR[7]/-82GIOF[7:0],GIOG[7:0],ANDGIOH[5:0]areEBDATA[9]3.
3V2mAIPD(20A)multiplexedwiththeexpansionbusmodule.
GIOF[2]/EBADDR[8]/-89SeeTable7.
EBDATA[10]GIOF[3]/EBADDR[9]/-90EBDATA[11]GIOF[4]/EBADDR[10]/-93EBDATA[12]GIOF[5]/EBADDR[11]/-96EBDATA[13]GIOF[6]/EBADDR[12]/-99EBDATA[14]GIOF[7]/EBADDR[13]/-100EBDATA[15]GIOG[0]/EBADDR[14]/-20EBADDR[6]GIOG[1]/EBADDR[15]/-10EBADDR[7]GIOG[2]/EBADDR[16]/-8EBADDR[8]GIOG[3]/EBADDR[17]/-6EBADDR[9]10SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384www.
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TerminalFunctions(continued)TERMINALINTERNALINPUTOUTPUTPULLUP/DESCRIPTIONVOLTAGE(1)(2)CURRENT(3)NAMEPZPGEPULLDOWNGENERAL-PURPOSEI/O(GIO)(CONTINUED)GIOG[4]/EBADDR[18]/-3EBADDR[10]GIOG[5]/EBADDR[19]/-143EBADDR[11]GIOG[6]/EBADDR[20]/-142EBADDR[12]GIOG[7]/EBADDR[21]/-140EBADDR[13]GIOB[0],GIOC[4:0],GIOD[5:0],GIOE[7:0:],GIOH[0]/EBADDR[22]/-139GIOF[7:0],GIOG[7:0],ANDGIOH[5:0]areEBADDR[14]3.
3V2mAIPD(20A)multiplexedwiththeexpansionbusmodule.
GIOH[1]/EBADDR[23]/SeeTable7.
2941EBADDR[15]GIOH[2]/EBADDR[24]/2840EBADDR[16]GIOH[3]/EBADDR[25]/2738EBADDR[17]GIOH[4]/EBADDR[26]/2637EBADDR[18]GIOH[5]/EBHOLD88125MULTI-BUFFEREDANALOG-TO-DIGITALCONVERTER(MibADC)MibADCeventinput.
CanbeprogrammedasaADEVT681013.
3V2mAGIOpin.
ADIN[0]84117ADIN[1]83116ADIN[2]82115ADIN[3]81114ADIN[4]80113ADIN[5]751083.
3VMibADCanaloginputpinsADIN[6]74107ADIN[7]73106ADIN[8]72105ADIN[9]71104ADIN[10]70103ADIN[11]69102ADREFHI761093.
3-VREFMibADCmodulehigh-voltagereferenceinputADREFLO77110GNDREFMibADCmodulelow-voltagereferenceinputVCCAD781113.
3-VPWRMibADCanalogsupplyvoltageVSSAD79112GNDMibADCanaloggroundreferenceCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTable2.
TerminalFunctions(continued)TERMINALINTERNALINPUTOUTPUTPULLUP/DESCRIPTIONVOLTAGE(1)(2)CURRENT(3)NAMEPZPGEPULLDOWNSERIALPERIPHERALINTERFACE1(SPI1)SPI1clock.
SPI1CLKcanbeprogrammedasaSPI1CLK34GIOpin.
SPI1chipenable.
CanbeprogrammedasaSPI1ENA22GIOpin.
SPI1slavechipselect.
CanbeprogrammedasSPI1SCS115-Vtolerant4mAaGIOpin.
SPI1datastream.
Slavein/masterout.
CanbeSPI1SIMO45programmedasaGIOpin.
SPI1datastream.
Slaveout/masterin.
CanbeSPI1SOMI57programmedasaGIOpin.
SERIALPERIPHERALINTERFACE2(SPI2)SPI2CLK3956SPI2clock.
CanbeprogrammedasaGIOpin.
SPI2chipenable.
CanbeprogrammedasaSPI2ENA4260GIOpin.
SPI2slavechipselect.
CanbeprogrammedasSPI2SCS43625-Vtolerant4mAaGIOpin.
SPI2datastream.
Slavein/masterout.
CanbeSPI2SIMO4159programmedasaGIOpin.
SPI2datastream.
Slaveout/masterin.
CanbeSPI2SOMI4057programmedasaGIOpin.
INTER-INTEGRATEDCIRCUIT(I2C)I2C1SDA6087I2C1serialdatapinorGIOpinI2C1SCL6188I2C1serialclockpinorGIOpinI2C2SDA6494I2C2serialdatapinorGIOpin5-Vtolerant4mAI2C2SCL6595I2C2serialclockpinorGIOpinI2C3SDA2029I2C3serialdatapinorGIOpinI2C3SCL1928I2C3serialclockpinorGIOpinZERO-PINPHASE-LOCKEDLOOP(ZPLL)OSCIN23331.
8VCrystalconnectionpinorexternalclockinputOSCOUT22322mAExternalcrystalconnectionpinEnable/disabletheZPLL.
TheZPLLcanbePLLDIS66973.
3VIPD(20A)bypassedandtheoscillatorbecomesthesystemclock.
SERIALCOMMUNICATIONSINTERFACE1(SCI1)SCI1clock.
SCI1CLKcanbeprogrammedasaSCI1CLK33483.
3V2mAGIOpin.
SCI1datareceive.
SCI1RXcanbeprogrammedSCI1RX32465-Vtolerant4mAasaGIOpin.
SCI1datatransmit.
SCI1TXcanbeprogrammedSCI1TX31453.
3V2mAasaGIOpin.
SERIALCOMMUNICATIONSINTERFACE2(SCI2)SCI2clock.
SCI2CLKcanbeprogrammedasaSCI2CLK36513.
3V2mAGIOpin.
SCI2datareceive.
SCI2RXcanbeprogrammedSCI2RX35505-Vtolerant4mAasaGIOpin.
SCI2datatransmit.
SCI2TXcanbeprogrammedSCI2TX34493.
3V2mAasaGIOpin.
12SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384www.
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TerminalFunctions(continued)TERMINALINTERNALINPUTOUTPUTPULLUP/DESCRIPTIONVOLTAGE(1)(2)CURRENT(3)NAMEPZPGEPULLDOWNSYSTEMMODULE(SYS)Bidirectionalclockout.
CLKOUTcanbeCLKOUT57813.
3V4mAprogrammedasaGIOpinortheoutputofSYSCLK,ICLK,orMCLK.
Inputmasterchippower-upreset.
ExternalVCCPORRST851183.
3VIPD(20A)monitorcircuitrymustassertapower-onreset.
Bidirectionalreset.
Theinternalcircuitrycanassertareset,andanexternalsystemresetcanassertadevicereset.
Onthispin,theoutputbufferisimplementedasRST861213.
3V4mAIPU(20A)anopendrain(driveslowonly).
Toensureanexternalresetisnotarbitrarilygenerated,TIrecommendsthatanexternalpullupresistorbeconnectedtothispin.
WATCHDOG/REAL-TIMEINTERRUPT(WD/RTI)Analogwatchdogreset.
TheAWDpinprovidesasystemresetiftheWDKEYisnotwrittenintimebythesystem,providinganexternalRCnetworkcircuitisconnected.
IftheuserisnotusingAWD,TIrecommendsthatthispinbeAWD25363.
3V4mAconnectedtogroundorpulleddowntogroundbyanexternalresistor.
FormoredetailsontheexternalRCnetworkcircuit,seetheTMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189).
TEST/DEBUG(T/D)Testclock.
TCKcontrolsthetesthardwareTCK54762mAIPD(20A)(JTAG).
Testdatain.
TDIinputsserialdatatothetestTDI52742mAIPU(20A)instructionregister,testdataregister,andprogrammabletestaddress(JTAG).
Testdataout.
TDOoutputsserialdatafromthetestinstructionregister,testdataregister,TDO53754mAIPD(20A)identificationregister,andprogrammabletestaddress(JTAG).
Testenable.
Reservedforinternaluseonly.
TIrecommendsthatthispinbeconnectedtoTEST871243.
3VIPD(20A)groundorpulleddowntogroundbyanexternalresistor.
SerialinputforcontrollingthestateoftheCPUTMS11172mAIPU(20A)testaccessport(TAP)controller(JTAG).
SerialinputforcontrollingthesecondTAP.
TITMS210162mAIPU(20A)recommendsthatthispinbeconnectedtoVCCIOorpulleduptoVCCIObyanexternalresistor.
TesthardwareresettoTAP1andTAP2.
IEEEStd1149.
1(JTAG)Boundary-ScanLogic.
TRST100144IPD(20A)TIrecommendsthatthispinbepulleddowntogroundbyanexternalresistor.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTable2.
TerminalFunctions(continued)TERMINALINTERNALINPUTOUTPUTPULLUP/DESCRIPTIONVOLTAGE(1)(2)CURRENT(3)NAMEPZPGEPULLDOWNFLASHFlashtestpad2.
Forproperoperation,thisFLTP293132NCNCpinmustnotbeconnected[noconnect(NC)].
VCCP921313.
3-VPWRFlashexternalpumpvoltage(3.
3V)SUPPLYVOLTAGECORE(1.
8V)211363319153VCC1.
8-VPWRCorelogicsupplyvoltage-92-123-130SUPPLYVOLTAGEDIGITALI/O(3.
3V)17254869VCCIO3.
3-VPWRDigitalI/Osupplyvoltage-8697137SUPPLYGROUNDCORE90149826-34-52-68VSSGNDCoresupplygroundreference4785-9162122241291813814SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384DEVICE-SPECIFICINFORMATIONMemoryTMS470R1A384www.
ti.
comSPNS110E–AUGUST2005–REVISEDMAY2008A.
Memoryaddressesareconfigurablebythesystem(SYS)modulewithintherangeof0x0000_0000to0xFFE0_0000.
B.
TheCPUregistersarenotapartofthememorymap.
Figure1.
TMS470R1A384MemoryMapCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLink(s):TMS470R1A384MemorySelectsTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comMemoryselectsallowtheusertoaddressmemoryarrays(i.
e.
,flash,RAM,andHETRAM)atuser-definedaddresses.
Eachmemoryselecthasitsownset(lowandhigh)ofmemorybaseaddressregisters(MFBAHRxandMFBALRx)that,together,definethearray'sstarting(base)address,blocksize,andprotection.
Thebaseaddressofeachmemoryselectisconfigurabletoanymemoryaddressboundarythatisamultipleofthedecodedblocksize.
Formoreinformationonhowtocontrolandconfigurethesememoryselectregisters,seethebusstructureandmemorysectionsoftheTMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189).
Forthememoryselectionassignmentsandthememoryselected,seeTable3.
Table3.
TMS470R1A384MemorySelectionAssignmentMEMORYMEMORYSELECTEDMEMORYSTATICMEMMPUMEMORYBASEADDRESSREGISTERSELECT(ALLINTERNAL)SIZE(1)CTLREGISTER0(fine)FLASHNOMFBAHR0andMFBALR0384K1(fine)FLASHNOMFBAHR1andMFBALR12(fine)RAMYESMFBAHR2andMFBALR232K(2)3(fine)RAMYESMFBAHR3andMFBALR34(fine)HETRAM1KNOMFBAHR4andMFBALR4SMCR14MB(x8)5(fine)CS[5]/GIOC[3]NOMCBAHR2andMCBALR2SMCR51MB(x16)4MB(x8)6(fine)CS[6]/GIOC[4]NOMCBAHR3andMCBALR3SMCR61MB(x16)(1)x8referstosizeofmemoryin8-bits;x16referstosizeofmemoryin16-bits.
(2)ThestartingaddressesforbothRAMmemory-selectsignalscannotbeoffsetfromeachotherbyamultipleoftheuser-definedblocksizeinthememory-baseaddressregister.
RAMTheA384devicecontains32K-bytesofinternalstaticRAMconfigurablebytheSYSmoduletobeaddressedwithintherangeof0x0000_0000to0xFFE0_0000.
ThisA384RAMisimplementedinone32K-bytearrayselectedbytwomemory-selectsignals.
NOTE:ThisA384configurationimposesanadditionalconstraintonthememorymapforRAM;thestartingaddressesforbothRAMmemoryselectscannotbeoffsetfromeachotherbythemultiplesofthesizeofthephysicalRAM(i.
e.
,32KbytesfortheA384device).
TheA384RAMisaddressedthroughmemoryselects2and3.
TheRAMcanbeprotectedbythememoryprotectionunit(MPU)portionoftheSYSmodule,allowingtheuserfinerblocksofmemoryprotectionthanisallowedbythememoryselects.
TheMPUisidealforprotectinganoperatingsystemwhileallowingaccesstothecurrenttask.
FormoredetailedinformationontheMPUportionoftheSYSmoduleandmemoryprotection,seethememorysectionoftheTMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189).
16SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008F05FlashTheF05flashmemoryisanonvolatileelectricallyerasableandprogrammablememoryimplementedwitha32-bit-widedatabusinterface.
TheF05flashhasanexternalstatemachineforprogramminganderasefunctions.
SeetheFlashReadandFlashProgramandErasesections.
FlashProtectionKeysTheA384deviceprovidesflashprotectionkeys.
Thesefour32-bitprotectionkeyspreventprogram/erase/compactionoperationsfromoccurringuntilafterthefourprotectionkeyshavebeenmatchedbytheCPUloadingthecorrectuserkeysintotheFMPKEYcontrolregister.
TheprotectionkeysontheA384arelocatedinthelast4wordsofthefirst8Ksector.
FormoredetailedinformationontheflashprotectionkeysandtheFMPKEYcontrolregister,seethe"OptionalQuadrupleProtectionKeys"and"ProgrammingtheProtectionKeys"portionsoftheTMS470R1xF05FlashReferenceGuide(literaturenumberSPNU213).
FlashReadTheA384flashmemoryisconfigurablebytheSYSmoduletobeaddressedwithintherangeof0x0000_0000to0xFFE0_0000.
Theflashisaddressedthroughmemoryselects0and1.
NOTE:Theflashexternalpumpvoltage(VCCP)isrequiredforalloperations(program,erase,andread).
FlashPipelineModeWheninpipelinemode,theflashoperateswithasystemclockfrequencyofupto48MHz(versusasystemclockfrequencyof24MHzinnormalmode).
Flashinpipelinemodeiscapableofaccessing64-bitwordsandprovidestwo32-bitpipelinedwordstotheCPU.
Also,inpipelinemodetheflashcanbereadwithnowaitstateswhenmemoryaddressesarecontiguous(aftertheinitial1-or2-wait-statereads).
NOTE:Afterasystemreset,pipelinemodeisdisabled(FMREGOPT[0]=0).
Inotherwords,theA384devicepowersupandcomesoutofresetinnon-pipelinemode.
Furthermore,settingtheflashconfigurationmodebit(GBLCTRL[4])overridespipelinemode.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLink(s):TMS470R1A384PeripheralSelectsandBaseAddressesTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comFlashProgramandEraseTheA384deviceflashcontainsthree128K-bytememoryarrays(orbanks),foratotalof384K-bytesofflash,andconsistsof18sectors.
These18sectorsaresizedasfollows:SECTORMEMORYARRAYSSEGMENTLOWADDRESSHIGHADDRESSNO.
(ORBANKS)08KBytes0x0000_00000x0000_1FFF18KBytes0x0000_20000x0000_3FFF216KBytes0x0000_40000x0000_7FFF316KBytes0x0000_80000x0000_BFFF416KBytes0x0000_C0000x0000_FFFFBANK0(128KBytes)516KBytes0x0001_00000x0001_3FFF616KBytes0x0001_40000x0001_7FFF716KBytes0x0001_80000x0001_BFFF88KBytes0x0001_C0000x0001_DFFF98Kbytes0x0001_E0000x0001_FFFF032KBytes0x0002_00000x0002_7FFF132KBytes0x0002_80000x0002_FFFFBANK1(128KBytes)232KBytes0x0003_00000x0003_7FFF332KBytes0x0003_80000x0003_FFFF032KBytes0x0004_00000x0004_7FFF132KBytes0x0004_80000x0004_FFFFBANK2(128KBytes)232KBytes0x0005_00000x0005_7FFF332KBytes0x0005_80000x0005_FFFFTheminimumsizeforaneraseoperationisonesector.
Themaximumsizeforaprogramoperationisone16-bitword.
NOTE:Theflashexternalpumpvoltage(VCCP)isrequiredforalloperations(program,erase,andread).
Executioncanoccurfromonebankwhileprogramming/erasinganyorallsectorsofanotherbank.
However,executioncannotoccurfromanysectorwithinabankthatisbeingprogrammedorerased.
NOTE:WhentheOTPsectorisenabled,therestoftheflashmemoryisdisabled.
TheOTPmemorycanonlybereadorprogrammedfromcodeexecutedoutofRAM.
Formoredetailedinformationonflashprogramanderaseoperations,seetheTMS470R1xF05FlashReferenceGuide(literaturenumberSPNU213).
HETRAMTheA384devicecontainsHETRAM.
TheHETRAMhasa64-instructioncapability.
TheHETRAMisconfigurablebytheSYSmoduletobeaddressedwithintherangeof0x0000_0000to0xFFE0_0000.
TheHETRAMisaddressedthroughmemoryselect4.
TheA384deviceuses10ofthe16peripheralselectstodecodethebaseaddressesoftheperipherals.
TheseperipheralselectsarefixedandtransparenttotheuserbecausetheyarepartofthedecodingschemeusedbytheSYSmodule.
Controlregistersfortheperipherals,SYSmodule,andflashbeginatthebaseaddressesshowninTable4.
18SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Table4.
A384Peripherals,SystemModule,andFlashBaseAddressesADDRESSRANGECONNECTINGMODULEPERIPHERALSELECTSBASEADDRESSENDINGADDRESSSYSTEM0xFFFF_FFCC0xFFFF_FFFFN/AReserved0xFFFF_FF600xFFFF_FFCBN/APSA0xFFFF_FF400xFFFF_FF5FN/ACIM0xFFFF_FF200xFFFF_FF3FN/ARTI0xFFFF_FF000xFFFF_FF1FN/ADMA0xFFFF_FE800xFFFF_FEFFN/ADEC0xFFFF_FE000xFFFF_FE7FN/AMMC0xFFFF_FD000xFFFF_FD7FN/AIEM0xFFFF_FC000xFFFF_FCFFN/AReserved0xFFFF_FB000xFFFF_FBFFN/AReserved0xFFFF_FA000xFFFF_FAFFN/ADMACMDBUFFER0xFFFF_F8000xFFFF_F9FFN/AReserved0xFFF8_00000xFFFF_F7FFN/AHET0xFFF7_FC000xFFF7_FFFFPS[0]SPI10xFFF7_F8000xFFF7_FBFFPS[1]SCI20XFFF7_F5000XFFF7_F7FFPS[2]SCI10xFFF7_F4000xFFF7_F4FFMibADC0xFFF7_F0000xFFF7_F3FFPS[3]ECP0xFFF7_EF000xFFF7_EFFFReserved0xFFF7_EE000xFFF7_EEFFPS[4]EBM0xFFF7_ED000xFFF7_EDFFGIO0xFFF7_EC000xFFF7_ECFFReserved0xFFF7_E4000xFFF7_EBFFPS[5]–PS[6]Reserved0xFFF7_E3000xFFF7_E3FFSCC20xFFF7_E2000xFFF7_E2FFPS[7]Reserved0xFFF7_E1000xFFF7_E1FFSCC10xFFF7_E0000xFFF7_E0FFReserved0xFFF7_DF000xFFF7_DFFFSCC2RAM0xFFF7_DE000xFFF7_DEFFPS[8]Reserved0xFFF7_DD000xFFF7_DDFFSCC1RAM0xFFF7_DC000xFFF7_DCFFReserved0xFFF7_DB000xFFF7_DBFFI2C30xFFF7_DA000xFFF7_DAFFPS[9]I2C20xFFF7_D9000xFFF7_D9FFI2C10xFFF7_D8000xFFF7_D8FFSPI20xFFF7_D4000xFFF7_D7FFPS[10]Reserved0xFFF7_CC000xFFF7_D3FFPS[11]–PS[12]C2SIb0xFFF7_C8000xFFF7_CBFFPS[13]Reserved0xFFF7_C0000xFFF7_C7FFPS[14]–PS[15]Reserved0xFFF0_00000xFFF7_BFFFN/AFlashControlRegisters0xFFE8_80000xFFE8_BFFFN/AMPUControlRegisters0xFFE8_40000xFFE8_4023N/ACopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLink(s):TMS470R1A384DirectMemoryAccess(DMA)TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comTheDMAcontrollertransfersdatatoandfromanyspecifiedlocationintheA384memorymap(exceptforrestrictedmemorylocationslikethesystemcontrolregistersarea).
TheDMAmanagesupto16channels,andsupportsdatatransferforbothon-chipandoff-chipmemoriesandperipherals.
TheDMAcontrollerisconnectedtoboththeCPUandperipheralbuses,enablingthesedatatransferstooccurinparallelwithCPUactivityand,thus,maximizingoverallsystemperformance.
AlthoughtheDMAcontrollerhastwopossibleconfigurationsfortheA384device,theDMAcontrollerconfigurationis32controlpacketsand16channels.
FortheA384DMArequesthardwiredconfiguration,seeTable5.
Table5.
DMARequestLinesConnections(1)MODULESDMAREQUESTINTERRUPTSOURCESDMACHANNELEBMExpansionbusDMArequestEBDMAREQ0DMAREQ[0]SPI1SPI1end-receiveSPI1DMA0DMAREQ[1]SPI1SPI1end-transmitSPI1DMA1DMAREQ[2]I2C1I2C1readI2C1DMA0DMAREQ[3]SCI1SCI1end-receiveSCI1DMA0DMAREQ[4]SCI1SCI1end-transmitSCI1DMA1DMAREQ[5]I2C1I2C1writeI2C1DMA1DMAREQ[6]SPI2SPI2end-receiveSPI2DMA0DMAREQ[7]SPI2SPI2end-transmitSPI2DMA1DMAREQ[8]I2C2/C2SIbI2C2read/C2SIbend-receiveI2C2DMA0/C2SIDMA0DMAREQ[9]I2C2/C2SIbI2C2write/C2SIbend-transmitI2C2DMA1/C2SIDMA1DMAREQ[10]I2C3I2C3readI2C3DMA0DMAREQ[11]I2C3I2C3writeI2C3DMA1DMAREQ[12]ReservedDMAREQ[13]SCI2/SPI3SCI2end-receiveSCI2DMA0DMAREQ[14]SCI2/SPI3SCI2end-transmitSCI2DMA1DMAREQ[15](1)ForDMAchannelswithmorethanoneassignedrequestsource(I2C2/C2SIb),onlyoneofthesourceslistedcanbetheDMArequestgeneratorinagivenapplication.
Thedevicehassoftwarecontroltoensurethattherearenoconflictsbetweenrequestingmodules.
Eachchannelhastwocontrolpacketsattachedtoit,allowingtheDMAtocontinuouslyloadRAMandgenerateperiodicinterruptssothatthedatacanbereadbytheCPU.
Thecontrolpacketsallowfortheinterruptenable,andthechannelsdeterminethepriorityleveloftheinterrupt.
DMAtransfersoccurinoneoftwomodes:Non-requestmode(usedwhentransferringfrommemorytomemory)Requestmode(usedwhentransferringfrommemorytoperipheral)FormoredetailedfunctionalinformationontheDMAcontroller,seetheTMS470R1xDirectMemoryAccess(DMA)ControllerReferenceGuide(literaturenumberSPNU194).
20SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384InterruptPriority(IEMtoCIM)TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008InterruptrequestsoriginatingfromtheA384peripheralmodules(i.
e.
,SPI1orSPI2,SCI1orSCI2,RTI,etc.
)areassignedtochannelswithinthe48-channelinterruptexpansionmodule(IEM)where,viaprogrammableregistermapping,thesechannelsarethenmappedtothe32-channelcentralinterruptmanager(CIM)portionoftheSYSmodule.
ProgrammingmultipleinterruptsourcesintheIEMtothesameCIMchanneleffectivelysharestheCIMchannelbetweensources.
TheCIMrequestchannelsaremaskablesothatindividualchannelscanbeselectivelydisabled.
AllinterruptrequestscanbeprogrammedintheCIMtobeofeithertype:Fastinterruptrequest(FIQ)Normalinterruptrequest(IRQ)TheCIMprioritizesinterrupts.
TheprecedencesofrequestchannelsdecreasewithascendingchannelorderintheCIM[0(highest)and31(lowest)priority].
ForIEM-to-CIMdefaultmapping,channelpriorities,andtheirassociatedmodules,seeTable6.
Table6.
InterruptPriority(IEMandCIM)DEFAULTCIMMODULESINTERRUPTSOURCESIEMCHANNELINTERRUPTLEVEL/CHANNELSPI1SPI1end-transfer/overrun00RTICOMP2interrupt11RTICOMP1interrupt22RTITAPinterrupt33SPI2SPI2end-transfer/overrun44GIOGIOinterruptA55Reserved66HETHETinterrupt177I2C1I2C1interrupt88SCI1/SCI2SCI1orSCI2errorinterrupt99SCI1SCI1receiveinterrupt1010C2SIbC2SIbinterrupt1111I2C2I2C2interrupt1212SCC2SCC2interruptA1313SCC1SCC1interruptA1414Reserved1515MibADCMibADCendeventconversion1616SCI2SCI2receiveinterrupt1717DMADMAinterrupt01818I2C3I2C3interrupt1919SCI1SCI1transmitinterrupt2020SystemSWinterrupt(SSI)2121Reserved2222HETHETinterrupt22323SCC2SCC2interruptB2424SCC1SCC1interruptB2525SCI2SCI2transmitinterrupt2626MibADCMibADCendgroup1conversion2727DMADMAInterrupt12828GIOGIOinterruptB2929MibADCMibADCendgroup2conversion3030Reserved3131Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTable6.
InterruptPriority(IEMandCIM)(continued)DEFAULTCIMMODULESINTERRUPTSOURCESIEMCHANNELINTERRUPTLEVEL/CHANNELReserved3132Reserved3133Reserved3134Reserved3135Reserved3136Reserved3137Reserved3138Reserved3139Reserved3140Reserved3141Reserved3142Reserved3143Reserved3144Reserved3145Reserved3146Reserved3147FormoredetailedfunctionalinformationontheIEM,seetheTMS470R1xInterruptExpansionModule(IEM)ReferenceGuide(literaturenumberSPNU211).
FormoredetailedfunctionalinformationontheCIM,seetheTMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189).
22SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384ExpansionBusModule(EBM)TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Theexpansionbusmodule(EBM)isastandalonemoduleusedtobondoutbothgeneral-purposeinput/outputpinsandexpansionbusinterfacepins.
Themodulesupports8-and16-bitexpansionbusmemoryinterfacemappings,aswellasmappingofthefollowingexpansionbussignals:22-bitaddressbus(EBADDR[21:0])forx8,19-bitaddressbus(EBADDR[18:0])forx168-or16-bitdatabus(EBDATA[7:0]orEBDATA[15:0])Twowritestrobes(EBWR[1:0])Twomemorychipselects(EBCS[6:5])Oneoutputenable(EBOE)Oneexternalholdsignalforinterfacingtoslowmemories(EBHOLD)Table7showsthemultiplexingofI/Osignalswiththeexpansionbusinterfacesignals.
Themappingofthesepinsvariesdependingonthememorymode.
Table7.
ExpansionBusMultiplexMapping(1)EXPANSIONBUSMODULEPINS(2)GIOx8x16GIOB[0]EBDMAREQ[0]EBDMAREQ[0]GIOC[0]EBOEEBOEGIOC[2:1]EBWR[1:0]EBWR[1:0]GIOC[4:3]EBCS[6:5]EBCS[6:5]GIOD[5:0]EBADDR[5:0]EBADDR[5:0]GIOE[7:0]EBDATA[7:0]EBDATA[7:0]GIOF[7:0]EBADDR[13:6]EBDATA[15:8]GIOG[7:0]EBADDR[21:14]EBADDR[13:6]GIOH[4:0]–EBADDR[18:14]GIOH[5]EBHOLDEBHOLD(1)ThesemappingsarecontrolledbytheEBMmuxcontrolregistersB–H(EBMXCRB–EBMXCRH)andtheEBMcontrolregister1(EBMCR1).
ForGPIOfunctions,useGIODIRx,GIODINx,GIODOUTx,GIODSETx,andGIODCLRx.
Formoredetailedinformation,seetheTMS470R1xGeneral-PurposeInput/Output(GIO)ReferenceGuide(literaturenumberSPNU192)andtheTMS470R1xExpansionBusModule(EBM)ReferenceGuide(literaturenumberSPNU222).
(2)x8referstosizeofmemoryin8-bits;x16referstosizeofmemoryin16-bits.
Table8liststhenamesoftheexpansionbusinterfacesignalsandtheirfunctions.
Table8.
ExpansionBusPinsPINDESCRIPTIONEBDMAREQExpansionbusDMArequestEBOEExpansionbusoutputenableExpansionbuswritestrobe.
EBWR[1]controlsEBWREBDATA[15:8]andEBWR[0]controlsEBDATA[7:0].
EBCSExpansionbuschipselectEBADDRExpansionbusaddressEBDATAExpansionbusdataExpansionbushold:anexternaldeviceconnectedtoEBHOLDtheexpansionbusmayassertthissignaltoaddwaitstatestoanexpansionbustransaction.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLink(s):TMS470R1A384MibADCTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comThemulti-bufferedanalog-to-digitalconverter(MibADC)acceptsananalogsignalandconvertsthesignaltoa10-bitdigitalvalue.
TheA384MibADCmodulecanfunctionintwomodes:compatibilitymode,whereitsprogrammer'smodeliscompatiblewiththeTMS470R1xADCmoduleanditsdigitalresultsarestoredindigitalresultregisters;orinbufferedmode,wherethedigitalresultregistersarereplacedwiththreeFIFObuffers,oneforeachconversiongroup[event,group1(G1),andgroup2(G2)].
Inbufferedmode,theMibADCbufferscanbeservicedbyinterruptsorbytheDMA.
NOTE:TheMibADConthisdevicedoesnotsupporttheDMA.
MibADCEventTriggerEnhancementsTheMibADCincludestwomajorenhancementsovertheevent-triggeringcapabilityoftheTMS470R1xADC.
Bothgroup1andtheeventgroupcanbeconfiguredforevent-triggeredoperation,providinguptotwoevent-triggeredgroups.
Thetriggersourceandpolaritycanbeselectedindividuallyforbothgroup1andtheeventgroupfromtheoptionsidentifiedinTable9.
Table9.
MibADCEventHookupConfigurationSOURCESELECTBITSFORG1OREVENTEVENTNO.
SIGNALPINNAME(G1SRC[1:0]OREVSRC[1:0])EVENT100ADEVTEVENT201HET18EVENT310ReservedEVENT411ReservedForgroup1,theseevent-triggeredselectionsareconfiguredviathegroup1sourceselectbits(G1SRC[1:0])intheADeventsourceregister(ADEVTSRC[5:4]).
Fortheeventgroup,theseevent-triggeredselectionsareconfiguredviatheeventgroupsourceselectbits(EVSRC[1:0])intheADeventsourceregister(ADEVTSRC[1:0]).
FormoredetailedfunctionalinformationontheMibADC,seetheTMS470R1xMulti-BufferedAnalog-to-DigitalConverter(MibADC)ReferenceGuide(literaturenumberSPNU206).
24SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384JTAGInterfaceTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Therearetwomaintestaccessports(TAPs)onthedevice:TMS470R1xCPUTAPDeviceTAPforfactorytestSomeoftheJTAGpinsaresharedamongthesetwoTAPs.
TheconnectionisshowninFigure2.
Figure2.
JTAGInterfaceCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLink(s):TMS470R1A384DocumentationSupportTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comExtensivedocumentationsupportsalloftheTMS470microcontrollerfamilygenerationofdevices.
Thetypesofdocumentationavailableincludedatasheetswithdesignspecifications,completeuser'sguidesforalldevicesanddevelopmentsupporttools,andhardwareandsoftwareapplications.
Usefulreferencedocumentationincludes:Bulletin–TMS470MicrocontrollerFamilyProductBulletin(literaturenumberSPNB086)User'sGuides–TMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189)–TMS470R1xGeneralPurposeInput/Output(GIO)ReferenceGuide(literaturenumberSPNU192)–TMS470R1xDirectMemoryAccess(DMA)ControllerReferenceGuide(literaturenumberSPNU194)–TMS470R1xSerialPeripheralInterface(SPI)ReferenceGuide(literaturenumberSPNU195)–TMS470R1xSerialCommunicationInterface(SCI)ReferenceGuide(literaturenumberSPNU196)–TMS470R1xControllerAreaNetwork(CAN)ReferenceGuide(literaturenumberSPNU197)–TMS470R1xHighEndTimer(HET)ReferenceGuide(literaturenumberSPNU199)–TMS470R1xExternalClockPrescale(ECP)ReferenceGuide(literaturenumberSPNU202)–TMS470R1xMultiBufferedAnalogtoDigital(MibADC)ReferenceGuide(literaturenumberSPNU206)–TMS470R1xZeroPinPhase-LockedLoop(ZPLL)ClockModuleReferenceGuide(literaturenumberSPNU212)–TMS470R1xF05FlashReferenceGuide(literaturenumberSPNU213)–TMS470R1xClassIISerialInterfaceB(C2SIb)ReferenceGuide(literaturenumberSPNU214)–TMS470R1xClassIISerialInterfaceA(C2SIa)ReferenceGuide(literaturenumberSPNU218)–TMS470R1xJTAGSecurityModule(JSM)ReferenceGuide(literaturenumberSPNU245)–TMS470R1xMemorySecurityModule(MSM)ReferenceGuide(literaturenumberSPNU246)–TMS470PeripheralsOverviewReferenceGuide(literaturenumberSPNU248)ErrataSheet–TMS470R1A384TMS470MicrocontrollersSiliconErrata(literaturenumberSPNZ148)26SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384DeviceandDevelopment-SupportToolNomenclatureTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Todesignatethestagesintheproductdevelopmentcycle,TIassignsprefixestothepartnumbersofallDSPdevicesandsupporttools.
EachDSPcommercialfamilymemberhasoneofthreeprefixes:TMX,TMP,orTMS(e.
g.
,TMS470R1A384).
TexasInstrumentsrecommendstwoofthreepossibleprefixdesignatorsforitssupporttools:TMDXandTMDS.
Theseprefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes(TMX/TMDX)throughfullyqualifiedproductiondevices/tools(TMS/TMDS).
Devicedevelopmentevolutionaryflow:TMXExperimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectricalspecificationsTMPFinalsilicondiethatconformstothedevice'selectricalspecificationsbuthasnotcompletedqualityandreliabilityverificationTMSFullyqualifiedproductiondeviceSupporttooldevelopmentevolutionaryflow:TMDXDevelopment-supportproductthathasnotyetcompletedTexasInstrumentsinternalqualificationtesting.
TMDSFullyqualifieddevelopment-supportproductTMXandTMPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer:"Developmentalproductisintendedforinternalevaluationpurposes.
"TMSdevicesandTMDSdevelopment-supporttoolshavebeencharacterizedfully,andthequalityandreliabilityofthedevicehavebeendemonstratedfully.
TI'sstandardwarrantyapplies.
Predictionsshowthatprototypedevices(TMXorTMP)haveagreaterfailureratethanthestandardproductiondevices.
TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheirexpectedend-usefailureratestillisundefined.
Onlyqualifiedproductiondevicesaretobeused.
Figure3illustratesthenumberingandsymbolnomenclaturefortheTMS470R1xfamily.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback27ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comFigure3.
TMS470R1xFamilyNomenclature28SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384DeviceIdentificationCodeRegisterTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Thedeviceidentificationcoderegisteridentifiesthesiliconversion,thetechnologyfamily(TF),aROMorflashdevice,andanassigneddevice-specificpartnumber(seeFigure4).
TheA384deviceidentificationcoderegistervalueis0x096F.
Figure4.
TMS470DeviceIDBitAllocationRegister[offset=FFFF_FFF0h]3116Reserved1512111093210VERSIONTFR/FPARTNUMBER111R-KR-KR-KR-KR-1R-1R-1LEGEND:R=Readonly,-K=ValueconstantafterRESET;-n=ValueafterRESETTable10.
TMS470DeviceIDBitAllocationRegisterFieldDescriptionsBitFieldValueDescription31–16ReservedReadsareundefinedandwriteshavenoeffect.
15–12VERSIONSiliconversion(revision)bitsThesebitsidentifythesiliconversionofthedevice.
Initialdeviceversionnumbersstartat0000.
11TFTechnologyfamilybitThisbitdistinguishesthetechnologyfamilycorepowersupply:03.
3VforF10/C10devices11.
8VforF05/C05devices10R/FROM/flashbitThisbitdistinguishesbetweenROMandflashdevices:0Flashdevice1ROMdevice9–3PARTNUMBERDevice-specificpartnumberbitsThesebitsidentifytheassigneddevice-specificpartnumber.
Theassigneddevice-specificpartnumberfortheA384deviceis0101101.
2–01MandatoryHighBits2,1,and0aretiedhighbydefault.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29ProductFolderLink(s):TMS470R1A384DeviceElectricalSpecificationsandTimingParametersAbsoluteMaximumRatingsDeviceRecommendedOperatingConditions(1)TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comoveroperatingfree-airtemperaturerange(1)Supplyvoltagerange:VCC(2)–0.
5Vto2.
5VSupplyvoltagerange:VCCIO,VCCAD,VCCP(flashpump)(2)–0.
5Vto4.
1VInputvoltagerange:All5V-tolerantinputpins–0.
5Vto6.
0VAllotherinputpins–0.
5Vto4.
1VInputclampcurrent,IIK:All5-Vtolerantpins,PORRST,TRST,TEST,andTCK(VIVCCAD)±10mAAllotherpins(VIVCCAD)±20mAOperatingfree-airtemperaturerange,TATversion–40°Cto105°CQversion–40°Cto125°COperatingjunctiontemperaturerange,TJ–40°Cto150°CStoragetemperaturerange,Tstg–40°Cto150°C(1)Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperatingconditions"isnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)Allvoltagevaluesarewithrespecttotheirassociatedgrounds.
(3)Thesepinsdonothaveaninternalclampdiodetoapositivesupplyvoltage.
MINNOMMAXUNITVCCDigitallogicsupplyvoltage(Core)1.
712.
05VVCCIODigitallogicsupplyvoltage(I/O)33.
33.
6VVCCADMibADCsupplyvoltage33.
33.
6VVCCPFlashpumpsupplyvoltage33.
33.
6VVSSDigitallogicsupplyground0VVSSADMibADCsupplyground–0.
10.
1VTversion–40105TAOperatingfree-airtemperature°CQversion–40125TJOperatingjunctiontemperature–40150°C(1)AllvoltagesarewithrespecttoVSS,exceptVCCAD,whichiswithrespecttoVSSAD.
30SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384ElectricalCharacteristicsTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008overrecommendedoperatingfree-airtemperaturerange(1)PARAMETERTESTCONDITIONSMINTYPMAXUNITVhysInputhysteresis0.
15VAllinputs(2)except–0.
30.
8Low-levelinputOSCINVILVvoltageOSCINonly–0.
30.
35VCCAllinputsexceptVCCIO+2High-levelinputOSCIN0.
3VIHVvoltageOSCINonly0.
65VCCVCC+0.
3InputthresholdVthAWDonly1.
351.
8VvoltageDraintosourceonRDSONAWDonly(3)VOL–0.
35VatIOL=4mA90resistanceIOL=IOLMAX0.
2VCCIOVOLLow-leveloutputvoltage(4)VIOL=3mA0.
4IOH=IOHMIN0.
8VCCIOVOHHigh-leveloutputvoltage(4)VIOH=250A2.
7IICInputclampcurrent(I/Opins)(5)VIVCCIO+0.
3–22mAIILPulldownVI=VSS–11IIHPulldownVI=VCCIO540Inputcurrent(3.
3-VIILPullupVI=VSS–40–5Ainputpins)IIHPullupVI=VCCIO–11IIAllotherpinsNopulluporpulldown–11VI=VSS–11VI=VCCIO–11Inputcurrent(5-Vtolerantinputpins)AVI=5V0.
520VI=5.
5V140RST,CLKOUT,4AWD,TDOLow-leveloutputIOLAllother3.
3VVOL=VOLMAXmAcurrent2I/O(6)5-Vtolerant4RST,CLKOUT,–4TDOHigh-leveloutputIOHAllother3.
3VVOH=VOHMIN–2mAcurrentI/O(6)5Vtolerant–4(1)Sourcecurrents(outofthedevice)arenegative,whilesinkcurrents(intothedevice)arepositive.
(2)ThisdoesnotapplytothePORRSTpin.
ForPORRSTexceptions,seetheRSTandPORRSTTimingssection.
(3)ThesevalueshelptodeterminetheexternalRCnetworkcircuit.
Formoredetails,seetheTMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189).
(4)VOLandVOHarelinearwithrespecttotheamountofloadcurrent(IOL/IOH)applied.
(5)Parameterdoesnotapplytoinput-onlyoroutput-onlypins.
(6)The2-mAbuffersonthisdevicearecalledzero-dominantbuffers.
Iftwoofthesebuffersareshortedtogetherandoneisoutputtingalowlevelandtheotherisoutputtingahighlevel,theresultingvalueisalwayslow.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback31ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comElectricalCharacteristics(continued)overrecommendedoperatingfree-airtemperaturerangePARAMETERTESTCONDITIONSMINTYPMAXUNITSYSCLK=24MHz,ICLK=15MHz,90VCC=2.
05VVCCdigitalsupplycurrentmA(operatingmode)SYSCLK=48MHz,ICLK=24MHz,115VCC=2.
05VTversion1(105°C)VCCdigitalsupplycurrentOSCIN=4MHz,ICCmA(standbymode)(7)VCC=2.
05VQversion1.
25(125°C)30°Cversion,VCC=2.
05V30VCCdigitalsupplycurrent(haltmode)(7)Tversion(105°C),VCC=2.
05V365AQversion(125°C),VCC=2.
05V550VCCIOdigitalsupplycurrentNoDCload,VCCIO=3.
6V(8)10mA(operatingmode)ICCIOVCCIOdigitalsupplycurrentNoDCload,VCCIO=3.
6V(8)15A(standbymode)VCCIOdigitalsupplycurrent(haltmode)NoDCload,VCCIO=3.
6V(8)5AVCCADsupplycurrent(operatingmode)Allfrequencies,VCCAD=3.
6V25mAICCADVCCADsupplycurrent(standbymode)NoDCload,VCCAD=3.
6V(8)10AVCCADsupplycurrent(haltmode)VCCAD=3.
6V5AVCCP=3.
6Vreadoperation25mAVCCP=3.
6Vprogramanderase70mAICCPVCCPpumpsupplycurrentVCCP=3.
6Vstandbymodeoperation(7)10AVCCP=3.
6Vhaltmodeoperation(7)5ACIInputcapacitance2pFCOOutputcapacitance3pF(7)Forflashbanks/pumpsinsleepmode.
(8)I/Opinsconfiguredasinputsoroutputswithnoload.
Allpulldowninputs≤0.
2V.
Allpullupinputs≥VCCIO–0.
2V.
32SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384ParameterMeasurementInformationTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008A.
Forthesevalues,seethe"ElectricalCharacteristicsoverRecommendedOperatingFree-AirTemperatureRange"table.
B.
Alltimingparametersmeasuredusinganexternalloadcapacitanceof150pFunlessotherwisenoted.
Figure5.
TestLoadCircuitCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback33ProductFolderLink(s):TMS470R1A384TimingParameterSymbologyTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTimingparametersymbolshavebeencreatedinaccordancewithJEDECStandard100.
Toshortenthesymbols,someofthepinnamesandotherrelatedterminologyhavebeenabbreviatedasfollows:CMCompaction,CMPCTRDReadCOCLKOUTRSTReset,RSTEREraseRXSCInRXICLKInterfaceclockSSlavemodeMMastermodeSCCSCInCLKOSC,OSCIOSCINSIMOSPInSIMOOSCOOSCOUTSOMISPInSOMIPProgram,PROGSPCSPInCLKRReadySYSSystemclockR0Readmargin0,RDMRGN0TXSCInTXR1Readmargin1,RDMRGN1Lowercasesubscriptsandtheirmeaningsare:aaccesstimerrisetimeccycletime(period)susetuptimeddelaytimettransitiontimeffalltimevvalidtimehholdtimewpulseduration(width)Thefollowingadditionallettersareusedwiththesemeanings:HHighXUnknown,changing,ordon'tcarelevelLLowZHighimpedanceVValid34SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384ExternalReferenceResonator/CrystalOscillatorClockOptionTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Theoscillatorisenabledbyconnectingtheappropriatefundamental4-20MHzresonator/crystalandloadcapacitorsacrosstheexternalOSCINandOSCOUTpinsasshowninFigure6a.
Theoscillatorisasingle-stageinverterheldinbiasbyanintegratedbiasresistor.
ThisresistorisdisabledduringleakagetestmeasurementandHALTmode.
TIstronglyencourageseachcustomertosubmitsamplesofthedevicetotheresonator/crystalvendorsforvalidation.
Thevendorsareequippedtodeterminewhatloadcapacitorswillbesttunetheirresonator/crystaltothemicrocontrollerdeviceforoptimumstart-upandoperationovertemperature/voltageextremes.
Anexternaloscillatorsourcecanbeusedbyconnectinga1.
8-VclocksignaltotheOSCINpinandleavingtheOSCOUTpinunconnected(open)asshowninFigure6b.
A.
ThevaluesofC1andC2shouldbeprovidedbytheresonator/crystalvendor.
Figure6.
Crystal/ClockConnectionCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback35ProductFolderLink(s):TMS470R1A384ZPLLANDCLOCKSPECIFICATIONSTimingRequirementsforZPLLCircuitsEnabledorDisabledSwitchingCharacteristicsOverRecommendedOperatingConditionsforClocks(1)(2)TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comMINTYPMAXUNITf(OSC)Inputclockfrequency420MHztc(OSC)Cycletime,OSCIN50nstw(OSCIL)Pulseduration,OSCINlow15nstw(OSCIH)Pulseduration,OSCINhigh15nsf(OSCRST)OSCFAILfrequency(1)53kHz(1)Causesadevicereset(specificallyaclockreset)bysettingtheRSTOSCFAIL(GLBCTRL.
15)andtheOSCFAILflag(GLBSTAT.
1)bitsequalto1.
Formoredetailedinformationonthesebitsanddeviceresets,seetheTMS470R1xSystemModuleReferenceGuide(literaturenumberSPNU189).
PARAMETERTESTCONDITIONS(3)MINMAXUNITPipelinemodeenabled48MHzf(SYS)Systemclockfrequency(4)Pipelinemodedisabled24MHzf(CONFIG)Systemclockfrequency-flashconfigmode24MHzf(ICLK)Interfaceclockfrequency24MHzf(ECLK)ExternalclockoutputfrequencyforECPmodule24MHzPipelinemodeenabled20.
8nstc(SYS)Cycletime,systemclockPipelinemodedisabled41.
6nstc(CONFIG)Cycletime,systemclock-flashconfigmode41.
6nstc(ICLK)Cycletime,interfaceclock41.
6nstc(ECLK)Cycletime,ECPmoduleexternalclockoutput41.
6ns(1)f(SYS)=M*f(OSC)/R,whereM={8},R={1,2,3,4,5,6,7,8}whenPLLDIS=0.
Risthesystem-clockdividerdeterminedbytheCLKDIVPRE[2:0]bitsintheglobalcontrolregister(GLBCTRL[2:0])andMisthePLLmultiplierdeterminedbytheMULT4bitalsointheGLBCTRLregister(GLBCTRL.
3).
f(SYS)=f(OSC)/R,whereR={1,2,3,4,5,6,7,8}whenPLLDIS=1.
f(ICLK)=f(SYS)/X,whereX={1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}.
XistheinterfaceclockdividerratiodeterminedbythePCR0[4:1]bitsintheSYSmodule.
(2)f(ECLK)=f(ICLK)/N,whereN={1to256}.
NistheECPprescalevaluedefinedbytheECPCTRL[7:0]registerbitsintheECPmodule.
(3)PipelinemodeenabledordisabledisdeterminedbytheENPIPEbit(FMREGOPT.
0).
(4)FlashVreadmustbesetto5Vtoachievemaximumsystemclockfrequency.
36SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384SwitchingCharacteristicsOverRecommendedOperatingConditionsforExternalClocks(1)(2)(3)TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008(seeFigure7andFigure8)PARAMETERTESTCONDITIONSMINMAXUNITSYSCLKorMCLK(4)0.
5tc(SYS)-tfnstw(COL)Pulseduration,CLKOUTlowICLK:Xisevenor1(5)0.
5tc(ICLK)-tfICLK:Xisoddandnot1(5)0.
5tc(ICLK)+0.
5tc(SYS)-tfSYSCLKorMCLK(4)0.
5tc(SYS)-trnstw(COH)Pulseduration,CLKOUThighICLK:Xisevenor1(5)0.
5tc(ICLK)-trICLK:Xisoddandnot1(5)0.
5tc(ICLK)-0.
5tc(SYS)-trNisevenandXisevenorodd0.
5tc(ECLK)-tfnstw(EOL)Pulseduration,ECLKlowNisoddandXiseven0.
5tc(ECLK)-tfNisoddandXisoddandnot10.
5tc(ECLK)+0.
5tc(SYS)-tfNisevenandXisevenorodd0.
5tc(ECLK)-trnstw(EOH)Pulseduration,ECLKhighNisoddandXiseven0.
5tc(ECLK)-trNisoddandXisoddandnot10.
5tc(ECLK)-0.
5tc(SYS)-tr(1)X={1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}.
XistheinterfaceclockdividerratiodeterminedbythePCR0[4:1]bitsintheSYSmodule.
(2)N={1to256}.
NistheECPprescalevaluedefinedbytheECPCTRL[7:0]registerbitsintheECPmodule.
(3)CLKOUT/ECLKpulsedurations(low/high)areafunctionoftheOSCINpulsedurationswhenPLLDISisactive.
(4)ClocksourcebitsareselectedaseitherSYSCLK(CLKCNTL[6:5]=11binary)orMCLK(CLKCNTL[6:5]=10binary).
(5)ClocksourcebitsareselectedasICLK(CLKCNTL[6:5]=01binary).
Figure7.
CLKOUTTimingDiagramFigure8.
ECLKTimingDiagramCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback37ProductFolderLink(s):TMS470R1A384RSTANDPORRSTTIMINGSTimingRequirementsforPORRSTSwitchingCharacteristicsOverRecommendedOperatingConditionsforRST(1)TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
com(seeFigure9)MINMAXUNITVCCPORLVCClowsupplylevelwhenPORRSTmustbeactiveduringpowerup0.
6VVCChighsupplylevelwhenPORRSTmustremainactiveduringpowerupandbecomeVCCPORH1.
5VactiveduringpowerdownVCCIOPORLVCCIOlowsupplylevelwhenPORRSTmustbeactiveduringpowerup1.
1VVCCIOhighsupplylevelwhenPORRSTmustremainactiveduringpowerupandbecomeVCCIOPORH2.
75VactiveduringpowerdownVILLow-levelinputvoltageafterVCCIO>VCCIOPORH0.
2VCCIOVVIL(PORRST)Low-levelinputvoltageofPORRSTbeforeVCCIO>VCCIOPORL0.
5Vtsu(PORRST)rSetuptime,PORRSTactivebeforeVCCIO>VCCIOPORLduringpowerup0mstsu(VCCIO)rSetuptime,VCCIO>VCCIOPORLbeforeVCC>VCCPORL0msth(PORRST)rHoldtime,PORRSTactiveafterVCC>VCCPORH1mstsu(PORRST)fSetuptime,PORRSTactivebeforeVCC≤VCCPORHduringpowerdown8sth(PORRST)rioHoldtime,PORRSTactiveafterVCC>VCCIOPORH1msth(PORRST)dHoldtime,PORRSTactiveafterVCC1.
1VbeforeVCC>0.
6VFigure9.
PORRSTTimingDiagramPARAMETERMINMAXUNITValidtime,RSTactiveafterPORRSTinactive4112tc(OSC)tv(RST)nsValidtime,RSTactive(allothers)8tc(SYS)Flashstart-uptime,fromRSTinactivetofetchoffirstinstructionfromflash(flashpumptfsu360tc(OSC)nsstabilizationtime)(1)SpecifiedvaluesdoNOTincluderise/falltimes.
Forriseandfalltimings,seethe"SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance"table.
38SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384JTAGSCANINTERFACETIMINGTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008(JTAGClockSpecification10-MHzand50-pFLoadonTDOOutput)MINMAXUNITtc(JTAG)Cycletime,JTAGlowandhighperiod50nstsu(TDI/TMS-TCKr)Setuptime,TDI,TMSbeforeTCKrise(TCKr)15nsth(TCKr-TDI/TMS)Holdtime,TDI,TMSafterTCKr15nsth(TCKf-TDO)Holdtime,TDOafterTCKf10nstd(TCKf-TDO)Delaytime,TDOvalidafterTCKfall(TCKf)45nsFigure10.
JTAGScanTimingsCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback39ProductFolderLink(s):TMS470R1A384OUTPUTTIMINGSSwitchingCharacteristicsforOutputTimingsversusLoadCapacitance(CL)TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
com(seeFigure11)PARAMETERMINMAXUNITCL=15pF2.
58CL=50pF514trRisetime,AWD,CLKOUT,RST,TD0/GIOC[6]nsCL=100pF923CL=150pF1332CL=15pF2.
58CL=50pF514tfFalltime,AWD,CLKOUT,TDO/GIOC[6]nsCL=100pF923CL=150pF1332CL=15pF310CL=50pF3.
512trRisetime,4-mA5-VtolerantpinsnsCL=100pF721CL=150pF928CL=15pF28CL=50pF2.
59tfFalltime,4-mA5-VtolerantpinsnsCL=100pF825CL=150pF1135CL=15pF2.
510CL=50pF6.
025trRisetime,allotheroutputpinsnsCL=100pF1245CL=150pF1865CL=15pF310CL=50pF8.
525tfFalltime,allotheroutputpinsnsCL=100pF1645CL=150pF2365Figure11.
CMOS-LevelOutputs40SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384INPUTTIMINGSTimingRequirementsforInputTimings(1)FLASHTIMINGSTimingRequirementsforProgramFlash(1)TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008(seeFigure12)MINMAXUNITtpwInputminimumpulsewidthtc(ICLK)+10ns(1)tc(ICLK)=interfaceclockcycletime=1/f(ICLK)Figure12.
CMOS-LevelInputsMINTYPMAXUNITtprog(16-bit)Halfword(16-bit)programmingtime416200stprog(Total)384K-byteprogrammingtime(2)310sterase(sector)Sectorerasetime1.
7stwecWrite/erasecyclesatTA=–40°Cto125°C50000cyclestfp(RST)FlashpumpsettlingtimefromRSTtoSLEEP72tc(SYS)nstfp(SLEEP)InitialflashpumpsettlingtimefromSLEEPtoSTANDBY72tc(SYS)tfp(STANDBY)InitialflashpumpsettlingtimefromSTANDBYtoACTIVE36tc(SYS)(1)Formoredetailedinformationontheflashcoresectors,seetheflashprogramanderasesectionofthisdatasheet.
(2)The384K-byteprogrammingtimeincludesoverheadofstatemachine.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback41ProductFolderLink(s):TMS470R1A384SPInMASTERMODETIMINGPARAMETERSSPInMasterModeExternalTimingParametersTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
com(CLOCKPHASE=0,SPInCLK=output,SPInSIMO=output,andSPInSOMI=input)(1)(2)(3)(seeFigure13)NO.
MINMAXUNIT1tc(SPC)MCycletime,SPInCLK(4)100256tc(ICLK)nstw(SPCH)MPulseduration,SPInCLKhigh(clockpolarity=0)0.
5tc(SPC)M-tr0.
5tc(SPC)M+52(5)nstw(SPCL)MPulseduration,SPInCLKlow(clockpolarity=1)0.
5tc(SPC)M-tf0.
5tc(SPC)M+5tw(SPCL)MPulseduration,SPInCLKlow(clockpolarity=0)0.
5tc(SPC)M-tf0.
5tc(SPC)M+53(5)nstw(SPCH)MPulseduration,SPInCLKhigh(clockpolarity=1)0.
5tc(SPC)M-tr0.
5tc(SPC)M+5td(SPCH-SIMO)MDelaytime,SPInCLKhightoSPInSIMOvalid(clockpolarity=0)104(5)nstd(SPCL-SIMO)MDelaytime,SPInCLKlowtoSPInSIMOvalid(clockpolarity=1)10tv(SPCL-SIMO)MValidtime,SPInSIMOdatavalidafterSPInCLKlow(clockpolarity=0)tc(SPC)M-5-tf5(5)nstv(SPCH-SIMO)MValidtime,SPInSIMOdatavalidafterSPInCLKhigh(clockpolarity=1)tc(SPC)M-5-trtsu(SOMI-SPCL)MSetuptime,SPInSOMIbeforeSPInCLKlow(clockpolarity=0)66(5)nstsu(SOMI-SPCH)MSetuptime,SPInSOMIbeforeSPInCLKhigh(clockpolarity=1)6tv(SPCL-SOMI)MValidtime,SPInSOMIdatavalidafterSPInCLKlow(clockpolarity=0)47(5)nstv(SPCH-SOMI)MValidtime,SPInSOMIdatavalidafterSPInCLKhigh(clockpolarity=1)4(1)TheMASTERbit(SPInCTRL2.
3)issetandtheCLOCKPHASEbit(SPInCTRL2.
0)iscleared.
(2)tc(ICLK)=interfaceclockcycletime=1/f(ICLK)(3)Forriseandfalltimings,seethe"SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance"table.
(4)WhentheSPIisinmastermode,thefollowingmustbetrue:ForPSvaluesfrom1to255:tc(SPC)M≥(PS+1)tc(ICLK)≥100ns,wherePSistheprescalevaluesetintheSPInCTL1[12:5]registerbits.
ForPSvaluesof0:tc(SPC)M=2tc(ICLK)≥100ns.
(5)TheactiveedgeoftheSPInCLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPInCTRL2[1]).
Figure13.
SPInMasterModeExternalTiming(CLOCKPHASE=0)42SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384SPInMasterModeExternalTimingParametersTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008(CLOCKPHASE=1,SPInCLK=output,SPInSIMO=output,andSPInSOMI=input)(1)(2)(3)(seeFigure14)NO.
MINMAXUNIT1tc(SPC)MCycletime,SPInCLK(4)100256tc(ICLK)nstw(SPCH)MPulseduration,SPInCLKhigh(clockpolarity=0)0.
5tc(SPC)M-tr0.
5tc(SPC)M+52(5)nstw(SPCL)MPulseduration,SPInCLKlow(clockpolarity=1)0.
5tc(SPC)M-tf0.
5tc(SPC)M+5tw(SPCL)MPulseduration,SPInCLKlow(clockpolarity=0)0.
5tc(SPC)M-tf0.
5tc(SPC)M+53(5)nstw(SPCH)MPulseduration,SPInCLKhigh(clockpolarity=1)0.
5tc(SPC)M-tr0.
5tc(SPC)M+5tv(SIMO-SPCH)MValidtime,SPInCLKhighafterSPInSIMOdatavalid(clockpolarity=0)0.
5tc(SPC)M-104(5)nstv(SIMO-SPCL)MValidtime,SPInCLKlowafterSPInSIMOdatavalid(clockpolarity=1)0.
5tc(SPC)M-10tv(SPCH-SIMO)MValidtime,SPInSIMOdatavalidafterSPInCLKhigh(clockpolarity=0)0.
5tc(SPC)M-5-tr5(5)nstv(SPCL-SIMO)MValidtime,SPInSIMOdatavalidafterSPInCLKlow(clockpolarity=1)0.
5tc(SPC)M-5-tftsu(SOMI-SPCH)MSetuptime,SPInSOMIbeforeSPInCLKhigh(clockpolarity=0)66(5)nstsu(SOMI-SPCL)MSetuptime,SPInSOMIbeforeSPInCLKlow(clockpolarity=1)6tv(SPCH-SOMI)MValidtime,SPInSOMIdatavalidafterSPInCLKhigh(clockpolarity=0)47(5)nstv(SPCL-SOMI)MValidtime,SPInSOMIdatavalidafterSPInCLKlow(clockpolarity=1)4(1)TheMASTERbit(SPInCTRL2.
3)issetandtheCLOCKPHASEbit(SPInCTRL2.
0)isset.
(2)tc(ICLK)=interfaceclockcycletime=1/f(ICLK)(3)Forriseandfalltimings,seethe"SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance"table.
(4)WhentheSPIisinmastermode,thefollowingmustbetrue:ForPSvaluesfrom1to255:tc(SPC)M≥(PS+1)tc(ICLK)≥100ns,wherePSistheprescalevaluesetintheSPInCTL1[12:5]registerbits.
ForPSvaluesof0:tc(SPC)M=2tc(ICLK)≥100ns.
(5)TheactiveedgeoftheSPInCLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPInCTRL2[1]).
Figure14.
SPInMasterModeExternalTiming(CLOCKPHASE=1)Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback43ProductFolderLink(s):TMS470R1A384SPInSLAVEMODETIMINGPARAMETERSSPInSlaveModeExternalTimingParametersTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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com(CLOCKPHASE=0,SPInCLK=input,SPInSIMO=input,andSPInSOMI=output)(1)(2)(3)(4)(seeFigure15)NO.
MINMAXUNIT1tc(SPC)SCycletime,SPInCLK(5)100256tc(ICLK)nstw(SPCH)SPulseduration,SPInCLKhigh(clockpolarity=0)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)2(6)nstw(SPCL)SPulseduration,SPInCLKlow(clockpolarity=1)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)tw(SPCL)SPulseduration,SPInCLKlow(clockpolarity=0)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)3(6)nstw(SPCH)SPulseduration,SPInCLKhigh(clockpolarity=1)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)Delaytime,SPInCLKhightoSPInSOMIvalidtd(SPCH-SOMI)S6+tr(clockpolarity=0)4(6)nsDelaytime,SPInCLKlowtoSPInSOMIvalidtd(SPCL-SOMI)S6+tf(clockpolarity=1)Validtime,SPInSOMIdatavalidafterSPInCLKhightv(SPCH-SOMI)Stc(SPC)S-6-tr(clockpolarity=0)5(6)nsValidtime,SPInSOMIdatavalidafterSPInCLKlowtv(SPCL-SOMI)Stc(SPC)S-6-tf(clockpolarity=1)Setuptime,SPInSIMObeforeSPInCLKlowtsu(SIMO-SPCL)S6(clockpolarity=0)6(6)nsSetuptime,SPInSIMObeforeSPInCLKhightsu(SIMO-SPCH)S6(clockpolarity=1)Validtime,SPInSIMOdatavalidafterSPInCLKlowtv(SPCL-SIMO)S6(clockpolarity=0)7(6)nsValidtime,SPInSIMOdatavalidafterSPInCLKhightv(SPCH-SIMO)S6(clockpolarity=1)(1)TheMASTERbit(SPInCTRL2.
3)isclearedandtheCLOCKPHASEbit(SPInCTRL2.
0)iscleared.
(2)IftheSPIisinslavemode,thefollowingmustbetrue:tc(SPC)S≥(PS+1)tc(ICLK),wherePS=prescalevaluesetinSPInCTL1[12:5].
(3)Forriseandfalltimings,seethe"SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance"table.
(4)tc(ICLK)=interfaceclockcycletime=1/f(ICLK)(5)WhentheSPInisinslavemode,thefollowingmustbetrue:ForPSvaluesfrom1to255:tc(SPC)S≥(PS+1)tc(ICLK)≥100ns,wherePSistheprescalevaluesetintheSPInCTL1[12:5]registerbits.
ForPSvaluesof0:tc(SPC)S=2tc(ICLK)≥100ns.
(6)TheactiveedgeoftheSPInCLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPInCTRL2[1]).
Figure15.
SPInSlaveModeExternalTiming(CLOCKPHASE=0)44SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384SPInSlaveModeExternalTimingParametersTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008(CLOCKPHASE=1,SPInCLK=input,SPInSIMO=input,andSPInSOMI=output)(1)(2)(3)(4)(seeFigure16)NO.
MINMAXUNIT1tc(SPC)SCycletime,SPInCLK(5)100256tc(ICLK)nstw(SPCH)SPulseduration,SPInCLKhigh(clockpolarity=0)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)2(6)nstw(SPCL)SPulseduration,SPInCLKlow(clockpolarity=1)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)tw(SPCL)SPulseduration,SPInCLKlow(clockpolarity=0)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)3(6)nstw(SPCH)SPulseduration,SPInCLKhigh(clockpolarity=1)0.
5tc(SPC)S-0.
25tc(ICLK)0.
5tc(SPC)S+0.
25tc(ICLK)Validtime,SPInCLKhighafterSPInSOMIdatavalidtv(SOMI-SPCH)S0.
5tc(SPC)S-6-tr(clockpolarity=0)4(6)nsValidtime,SPInCLKlowafterSPInSOMIdatavalidtv(SOMI-SPCL)S0.
5tc(SPC)S-6-tf(clockpolarity=1)Validtime,SPInSOMIdatavalidafterSPInCLKhightv(SPCH-SOMI)S0.
5tc(SPC)S-6-tr(clockpolarity=0)5(6)nsValidtime,SPInSOMIdatavalidafterSPInCLKlowtv(SPCL-SOMI)S0.
5tc(SPC)S-6-tf(clockpolarity=1)Setuptime,SPInSIMObeforeSPInCLKhightsu(SIMO-SPCH)S6(clockpolarity=0)6(6)nsSetuptime,SPInSIMObeforeSPInCLKlowtsu(SIMO-SPCL)S6(clockpolarity=1)Validtime,SPInSIMOdatavalidafterSPInCLKhightv(SPCH-SIMO)S6(clockpolarity=0)7(6)nsValidtime,SPInSIMOdatavalidafterSPInCLKlowtv(SPCL-SIMO)S6(clockpolarity=1)(1)TheMASTERbit(SPInCTRL2.
3)isclearedandtheCLOCKPHASEbit(SPInCTRL2.
0)isset.
(2)IftheSPIisinslavemode,thefollowingmustbetrue:tc(SPC)S≥(PS+1)tc(ICLK),wherePS=prescalevaluesetinSPInCTL1[12:5].
(3)Forriseandfalltimings,seethe"SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance"table.
(4)tc(ICLK)=interfaceclockcycletime=1/f(ICLK)(5)WhentheSPInisinslavemode,thefollowingmustbetrue:ForPSvaluesfrom1to255:tc(SPC)S≥(PS+1)tc(ICLK)≥100ns,wherePSistheprescalevaluesetintheSPInCTL1[12:5]registerbits.
ForPSvaluesof0:tc(SPC)S=2tc(ICLK)≥100ns.
(6)TheactiveedgeoftheSPInCLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPInCTRL2[1]).
Figure16.
SPInSlaveModeExternalTiming(CLOCKPHASE=1)Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback45ProductFolderLink(s):TMS470R1A384SCInISOSYNCHRONOUSMODETIMINGSINTERNALCLOCKTimingRequirementsforInternalClockSCInIsosynchronousMode(1)(2)(3)TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
com(seeFigure17)(BAUD+1)(BAUD+1)ISEVENORBAUD=0ISODDANDBAUD≠0UNITMINMAXMINMAXCycletime,tc(SCC)2tc(ICLK)224tc(ICLK)3tc(ICLK)(224-1)tc(ICLK)nsSCInCLKPulseduration,tw(SCCL)0.
5tc(SCC)-tf0.
5tc(SCC)+50.
5tc(SCC)+0.
5tc(ICLK)-tf0.
5tc(SCC)+0.
5tc(ICLK)nsSCInCLKlowPulseduration,tw(SCCH)0.
5tc(SCC)-tr0.
5tc(SCC)+50.
5tc(SCC)-0.
5tc(ICLK)-tr0.
5tc(SCC)-0.
5tc(ICLK)nsSCInCLKhighDelaytime,td(SCCH-TXV)SCInCLKhighto1010nsSCInTXvalidValidtime,SCInTXdatatv(TX)tc(SCC)-10tc(SCC)-10nsafterSCInCLKlowSetuptime,tsu(RX-SCCL)SCInRXbeforetc(ICLK)+tf+20tc(ICLK)+tf+20nsSCInCLKlowValidtime,SCInRXdatatv(SCCL-RX)-tc(ICLK)+tf+20-tc(ICLK)+tf+20nsafterSCInCLKlow(1)BAUD=24-bitconcatenatedvalueformedbytheSCI[H,M,L]BAUDregisters.
(2)tc(ICLK)=interfaceclockcycletime=1/f(ICLK)(3)Forriseandfalltimings,seethe"SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance"table.
A.
Datatransmission/receptioncharacteristicsforisosynchronousmodewithinternalclockingaresimilartotheasynchronousmode.
DatatransmissionoccursontheSCICLKrisingedge,anddatareceptionoccursontheSCICLKfallingedge.
Figure17.
SCInIsosynchronousModeTimingDiagramforInternalClock46SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384SCInISOSYNCHRONOUSMODETIMINGSEXTERNALCLOCKTimingRequirementsforExternalClockSCInIsosynchronousMode(1)(2)TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008(seeFigure18)MINMAXUNITtc(SCC)Cycletime,SCInCLK(3)8tc(ICLK)nstw(SCCH)Pulseduration,SCInCLKhigh0.
5tc(SCC)-0.
25tc(ICLK)0.
5tc(SCC)+0.
25tc(ICLK)nstw(SCCL)Pulseduration,SCInCLKlow0.
5tc(SCC)-0.
25tc(ICLK)0.
5tc(SCC)+0.
25tc(ICLK)nstd(SCCH-TXV)Delaytime,SCInCLKhightoSCInTXvalid2tc(ICLK)+12+trnstv(TX)Validtime,SCInTXdataafterSCInCLKlow2tc(SCC)-10nstsu(RX-SCCL)Setuptime,SCInRXbeforeSCInCLKlow0nstv(SCCL-RX)Validtime,SCInRXdataafterSCInCLKlow2tc(ICLK)+10ns(1)tc(ICLK)=interfaceclockcycletime=1/f(ICLK)(2)Forriseandfalltimings,seethe"SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance"table.
(3)WhendrivinganexternalSCInCLK,thefollowingmustbetrue:tc(SCC)≥8tc(ICLK).
A.
Datatransmission/receptioncharacteristicsforisosynchronousmodewithexternalclockingaresimilartotheasynchronousmode.
DatatransmissionoccursontheSCICLKrisingedge,anddatareceptionoccursontheSCICLKfallingedge.
Figure18.
SCInIsosynchronousModeTimingDiagramforExternalClockCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback47ProductFolderLink(s):TMS470R1A384I2CTIMINGTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comTable11belowassumestestingoverrecommendedoperatingconditions.
Table11.
I2CSignals(SDAandSCL)SwitchingCharacteristics(1)STANDARDFASTMODEMODEPARAMETERUNITMINMAXMINMAXtc(I2CCLK)Cycletime,I2Cmoduleclock7515075150nstc(SCL)Cycletime,SCL102.
5stsu(SCLH-SDAL)Setuptime,SCLhighbeforeSDAlow(forarepeatedSTARTcondition)4.
70.
6sth(SCLL-SDAL)Holdtime,SCLlowafterSDAlow(forarepeatedSTARTcondition)40.
6stw(SCLL)Pulseduration,SCLlow4.
71.
3stw(SCLH)Pulseduration,SCLhigh40.
6stsu(SDA-SCLH)Setuptime,SDAvalidbeforeSCLhigh250100nsth(SDA-SCLL)Holdtime,SDAvalidafterSCLlowForI2Cbusdevices03.
45(2)00.
9stw(SDAH)Pulseduration,SDAhighbetweenSTOPandSTARTconditions4.
71.
3stsu(SCLH-SDAH)Setuptime,SCLhighbeforeSDAhigh(forSTOPcondition)4.
00.
6stw(SP)Pulseduration,spike(mustbesuppressed)050nsCb(3)Capacitiveloadforeachbusline400400pF(1)TheI2CpinsSDAandSCLdonotfeaturefail-safeI/Obuffers.
Thesepinscouldpotentiallydrawcurrentwhenthedeviceispowereddown.
(2)Themaximumth(SDA-SCLL)forI2Cbusdevicesneedstobemetonlyifthedevicedoesnotstretchthelowperiod(tw(SCLL))oftheSCLsignal.
(3)Cb=ThetotalcapacitanceofonebuslineinpF.
A.
Adevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignal(referredtotheVIHminoftheSCLsignal)tobridgetheundefinedregionofthefallingedgeofSCL.
B.
Themaximumth(SDA-SCLL)needsonlybemetifthedevicedoesnotstretchtheLOWperiod(tw(SCLL))oftheSCLsignal.
C.
Afast-modeI2C-busdevicecanbeusedinastandard-modeI2C-bussystem,buttherequirementtsu(SDA-SCLH)≥250nsmustthenbemet.
ThiswillautomaticallybethecaseifthedevicedoesnotstretchtheLOWperiodoftheSCLsignal.
IfsuchadevicedoesstretchtheLOWperiodoftheSCLsignal,itmustoutputthenextdatabittotheSDAlinetrmax+tsu(SDA-SCLH).
D.
Cb=totalcapacitanceofonebuslineinpF.
IfmixedwithHS=modedevices,fasterfall-timesareallowed.
Figure19.
I2CTimings48SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384STANDARDCANCONTROLLER(SCC)MODETIMINGSDynamicCharacteristicsfortheCANSTXandCANSRXPinsEXPANSIONBUSMODULETIMINGExpansionBusTimingParameters,-40°C≤TJ≤150°C,3.
0V≤VCC≤3.
6VTMS470R1A384www.
ti.
comSPNS110E–AUGUST2005–REVISEDMAY2008PARAMETERMINMAXUNITtd(CANSTX)Delaytime,transmitshiftregistertoCANSTXpin(1)15nstd(CANSRX)Delaytime,CANSRXpintoreceiveshiftregister5ns(1)Thesevaluesdonotincludetherise/falltimesoftheoutputbuffer.
(seeFigure20andFigure21)MINMAXUNITtc(CO)Cycletime,CLKOUT20.
8nstd(COH-EBADV)Delaytime,CLKOUThightoEBADDRvalid21.
4nsth(COH-EBADIV)Holdtime,EBADDRinvalidafterCLKOUThigh12.
4nstd(COH-EBOE)Delaytime,CLKOUThightoEBOEfall11.
4nsth(COH-EBOEH)Holdtime,EBOEriseafterCLKOUThigh11.
4nstd(COL-EBWR)Delaytime,CLKOUTlowtowritestrobe(EBWR)low11.
3nsth(COL-EBWRH)Holdtime,EBWRhighafterCLKOUTlow11.
6nstsu(EBRDATV-COH)Setuptime,EBDATAvalidbeforeCLKOUThigh(READ)(1)15.
2nsth(COH-EBRDATIV)Holdtime,EBDATAinvalidafterCLKOUThigh(READ)(-14.
7)nstd(COL-EBWDATV)Delaytime,CLKOUTlowtoEBDATAvalid(WRITE)(2)16.
1nsth(COL-EBWDATIV)Holdtime,EBDATAinvalidafterCLKOUTlow(WRITE)14.
7nsSECONDARYTIMEStd(COH-EBCS0)Delay,CLKOUThightoEBCS0fall13.
6nsth(COH-EBCS0H)Hold,EBCS0riseafterCLKOUThigh13.
2nstsu(COH-EBHOLDL)Setuptime,EBHOLDlowtoCLKOUThigh(1)10.
9nstsu(COH-EBHOLDH)Setuptime,EBHOLDhightoCLKOUThigh(1)10.
5ns(1)Setuptimeistheminimumtimeunderworstcaseconditions.
Datawithlesssetuptimedoesnotwork.
(2)ValidafterCLKOUTgoeslowforwritecycles.
Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback49ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comFigure20.
ExpansionMemorySignalTiming-Reads50SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Figure21.
ExpansionMemorySignalTiming-WritesCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback51ProductFolderLink(s):TMS470R1A384CLASS2SERIALINTERFACEB(C2SIb)VARIABLEPULSEWIDTH(VPW)MODULATIONVPWTimingRequirementsTMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comSeeFigure22.
NORMALMODE(10.
4KBPS)4XMODE(41.
6KBPS)PARAMETERTXRXTXRXUNITMINMAXMINMAXMINMAXMINMAXSOFStartofframe19220816323948524160nsLow=0ShortPulse606834961418924nsHigh=1Low=0LongPulse1221349716330342441nsHigh=1EODEndofdata19320716423948524160nsNormalizationbit(long)1221349716330342441NBnsNormalizationbit(short)606834961418924EOFEndofframe27128924032067736080nsShort290-239-290-60-BreaknsLong758-239-758-60-Figure22.
C2SIbTimingDiagram52SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384HIGH-ENDTIMER(HET)TIMINGSMinimumPWMOutputPulseWidth:MinimumInputPulsesthatCanBeCaptured:TMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Thisisequaltoonehighresolutionclockperiod(HRP).
TheHRPisdefinedbythe6-bithighresolutionprescalefactor(hr),whichisuserdefined,givingprescalefactorsof1to64,withalinearincrementofcodes.
Therefore,theminimumPWMoutputpulsewidth=HRP(min)=hr(min)/SYSCLK=1/SYSCLKForexample,foraSYSCLKof30MHz,theminimumPWMoutputpulsewidth=1/30=33.
33nsTheinputpulsewidthmustbegreaterorequaltothelowresolutionclockperiod(LRP),i.
e.
,theHETloop(theHETprogrammustfitwithintheLRP).
TheLRPisdefinedbythe3-bitloop-resolutionprescalefactor(lr),whichisuserdefined,withapowerof2incrementofcodes.
Thatis,thevalueoflrcanbe1,2,4,8,16,or32.
Therefore,theminimuminputpulsewidth=LRP(min)=hr(min)*lr(min)/SYSCLK=1*1/SYSCLKForexample,withaSYSCLKof30MHz,theminimuminputpulsewidth=1*1/30=33.
33nsNOTE:OncetheinputpulsewidthisgreaterthanLRP,theresolutionofthemeasurementisstillHRP.
(Thatis,thecapturedvaluegivesthenumberofHRPclocksinsidethepulse.
)Abbreviations:hr=HEThighresolutiondividerate=1,2,3,.
.
.
63,64lr=HETlowresolutiondividerate=1,2,4,8,16,32Highresolutionclockperiod=HRP=hr/SYSCLKLoopresolutionclockperiod=LRP=hr*lr/SYSCLKCopyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback53ProductFolderLink(s):TMS470R1A384MULTI-BUFFEREDA-TO-DCONVERTER(MibADC)TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comThemulti-bufferedA-to-Dconverter(MibADC)hasaseparatepowerbusforitsanalogcircuitrythatenhancestheA-to-Dperformancebypreventingdigitalswitchingnoiseonthelogiccircuitry,whichcouldbepresentonVSSandVCC,fromcouplingintotheA-to-Danalogstage.
AllA-to-DspecificationsaregivenwithrespecttoADREFLOunlessotherwisenoted.
Resolution10bits(1024values)MonotonicAssuredOutputconversioncode00hto3FFh[00forVAI≤ADREFLO;3FFhforVAI≥ADREFHI]Table12.
MibADCRecommendedOperatingConditions(1)MINMAXUNITADREFHIA-to-Dhigh-voltagereferencesourceVSSADVCCADVADREFLOA-to-Dlow-voltagereferencesourceVSSADVCCADVVAIAnaloginputvoltageVSSAD–0.
3VCCAD+0.
3VAnaloginputclampcurrent(2)IAIC–22mA(VAIVCCAD+0.
3)(1)ForVCCADandVSSADrecommendedoperatingconditions,seethe"DeviceRecommendedOperatingConditions"table.
(2)InputcurrentsintoanyADCinputchanneloutsidethespecifiedlimitscouldaffectconversionresultsofotherchannels.
Table13.
OperatingCharacteristicsOverFullRangesofRecommendedOperatingConditions(1)(2)PARAMETERDESCRIPTION/CONDITIONSMINTYPMAXUNITRiAnaloginputresistanceSeeFigure23.
250500Conversion10pFCiAnaloginputcapacitanceSeeFigure23.
Sampling30pFIAILAnaloginputleakagecurrentSeeFigure23.
-11AIADREFHIADREFHIinputcurrentADREFHI=3.
6V,ADREFLO=VSSAD5mAConversionrangeoverwhichspecifiedCRADREFHI-ADREFLO33.
6VaccuracyismaintainedDifferencebetweentheactualstepwidthEDNLDifferentialnonlinearityerror±2LSBandtheidealvalue.
SeeFigure24.
MaximumdeviationfromthebeststraightlinethroughtheMibADC.
MibADCEINLIntegralnonlinearityerror±2LSBtransfercharacteristics,excludingthequantizationerror.
SeeFigure25.
MaximumvalueofthedifferenceETOTTotalerror/absoluteaccuracybetweenananalogvalueandtheideal±2LSBmidstepvalue.
SeeFigure26.
(1)VCCAD=ADREFHI(2)1LSB=(ADREFHI-ADREFLO)/210fortheMibADC54SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384Multi-BufferADCTimingRequirementsTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008Figure23.
MibADCInputEquivalentCircuitMINNOMMAXUNITtc(ADCLK)Cycletime,MibADCclock0.
05std(SH)Delaytime,sampleandholdtime1std(C)Delaytime,conversiontime0.
55std(SHC)(1)Delaytime,totalsample/holdandconversiontime1.
55s(1)Thisistheminimumsample/holdandconversiontimethatcanbeachieved.
Theseparametersaredependentonmanyfactors;formoredetails,seetheTMS470R1xMulti-BufferedAnalog-to-DigitalConverter(MibADC)ReferenceGuide(literaturenumberSPNU206).
ThedifferentialnonlinearityerrorshowninFigure24(sometimesreferredtoasdifferentiallinearity)isthedifferencebetweenanactualstepwidthandtheidealvalueof1LSB.
A.
1LSB=(ADREFHI-ADREFLO)/210Figure24.
DifferentialNonlinearity(DNL)Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback55ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
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comTheintegralnonlinearityerrorshowninFigure25(sometimesreferredtoaslinearityerror)isthedeviationofthevaluesontheactualtransferfunctionfromastraightline.
A.
1LSB=(ADREFHI-ADREFLO)/210Figure25.
IntegralNonlinearity(INL)ErrorTheabsoluteaccuracyortotalerrorofanMibADCasshowninFigure26isthemaximumvalueofthedifferencebetweenananalogvalueandtheidealmidstepvalue.
A.
1LSB=(ADREFHI-ADREFLO)/210Figure26.
AbsoluteAccuracy(Total)Error56SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384PGEThermalResistanceCharacteristicsPZThermalResistanceCharacteristicsTMS470R1A384www.
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comSPNS110E–AUGUST2005–REVISEDMAY2008PARAMETER°C/WRθJA43RθJC5PARAMETER°C/WRθJA48RθJC5Copyright2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback57ProductFolderLink(s):TMS470R1A384TMS470R1A384SPNS110E–AUGUST2005–REVISEDMAY2008www.
ti.
comRevisionHistoryThisrevisionhistoryhighlightsthechangesmadetothedevice-specificdatasheetSPNS110.
Table14.
RevisionHistorySPNS110DtoSPNS110ECorrectedthedevice-specificpartnumberfrom0100001to0101101inTable10.
SPNS110CtoSPNS110DRemovedreferencetoGIOH[5:0]inTerminalFunctionstable.
ChangedOutputCurrentforAWDterminalfrom8mAto4mAinTerminalFunctionstable.
ChangedbeginningaddressforPeripheralControlRegistersto0xFFF0_0000inFigure1.
ChangedregistervalueinDeviceIdentificationCodeRegisterChangedunitfor"VCCdigitalsupplycurrent(standbymode)"fromAtomAinElectricalCharacteristics.
SPNS110BtoSPNS110CRemovedreferencestodigitalwatchdog(DWD)onpage5.
SPNS110AtoSPNS110BRevisedtheFamilyNomenclaturedrawingtoaddQversionofthetemperaturerange.
Revised"AbsoluteMaximumRatings"tabletoaddQversionofthetemperaturerange.
Revised"DeviceRecommendedOperatingConditions"tabletoaddQversionofthetemperaturerange.
Revised"ElectricalCharacteristics"tabletoaddTandQtemperatureversionstoICCspecification.
ChangedTversionICC,standbymode,maxto1.
AddedQversionICCstandbymode,maxof1.
25.
ChangedTversionICC,haltmode,maxto365.
AddedQversionICChaltmode,maxof550.
AddednotetoPORRSTTimingDiagram.
ChangedTArangeto–40°Cto125°Contwecin"TimingRequirementsforProgramFlash"table.
AddedtwecMINvalueof50000anddeletedTYPvaluein"TimingRequirementsforProgramFlash"table.
Changedterase(sector)TYPvalueto1.
7andremovedMAXvaluein"TimingRequirementsforProgramFlash"table.
SPNS110toSPNS110ACorrectedmaxvalueforICCstandbyandhaltmodesinElectricalCharacteristicstable.
58SubmitDocumentationFeedbackCopyright2005–2008,TexasInstrumentsIncorporatedProductFolderLink(s):TMS470R1A384PACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesTMS470R1A384PGETNRNDLQFPPGE14460RoHS&GreenNIPDAULevel-3-260C-168HR470R1A384PGETTMSTMS470R1A384PZ-TNRNDLQFPPZ10090RoHS&GreenNIPDAULevel-3-260C-168HR470R1A384PZ-TTMS(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
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PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page2MECHANICALDATAMTQF017A–OCTOBER1994–REVISEDDECEMBER19961POSTOFFICEBOX655303DALLAS,TEXAS75265PGE(S-PQFP-G144)PLASTICQUADFLATPACK4040147/C10/960,27720,1737730,13NOM0,250,750,450,05MIN36SeatingPlaneGagePlane108109144SQSQ22,2021,80119,8017,50TYP20,201,351,451,60MAXM0,080°–7°0,080,50NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
FallswithinJEDECMS-026MECHANICALDATAMTQF013A–OCTOBER1994–REVISEDDECEMBER19961POSTOFFICEBOX655303DALLAS,TEXAS75265PZ(S-PQFP-G100)PLASTICQUADFLATPACK4040149/B11/9650260,13NOMGagePlane0,250,450,750,05MIN0,27512575112,00TYP0,1776100SQSQ15,8016,2013,801,351,451,60MAX14,200°–7°SeatingPlane0,080,50M0,08NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
FallswithinJEDECMS-026IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
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