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56F830016-bitDigitalSignalControllerfreescale.
com56F8335/56F8135DataSheetPreliminaryTechnicalDataMC56F8335Rev.
501/200756F8335TechnicalData,Rev.
52FreescaleSemiconductorPreliminaryDocumentRevisionHistoryVersionHistoryDescriptionofChangeRev.
0InitialReleaseRev.
1DeletedRSTOfromPinGroup2(listedafterTable10-1).
DeletedformulaforMaxAmbientOperatingTemperature(Automotive)andMaxAmbientOperatingTemperature(Industrial)inTable10-4.
AddedRoHS-complianceand"pb-free"languagetobackcover.
Rev.
2Addedinformation/correctedstateduringresetinTable2-2.
ClarifiedexternalreferencecrystalfrequencyforPLLinTable10-14byincreasingmaximumvalueto8.
4MHz.
Rev.
3Replaced"Tri-stated"withanexplanationinStateDuringResetcolumninTable2-2.
Rev.
4RevisedTable4-4toincludecorrectprogramFlashsize.
Rev.
5AddedthefollowingnotetothedescriptionoftheTMSsignalinTable2-2:Note:AlwaystietheTMSpintoVDDthrougha2.
2Kresistor.
AddedthefollowingnotetothedescriptionoftheTRSTsignalinTable2-2:Note:Fornormaloperation,connectTRSTdirectlytoVSS.
Ifthedesignistobeusedinadebuggingenvironment,TRSTmaybetiedtoVSSthrougha1Kresistor.
Pleaseseehttp://www.
freescale.
comforthemostcurrentdatasheetrevision.
56F8335TechnicalData,Rev.
5FreescaleSemiconductor3Preliminary56F8335/56F8135BlockDiagram-128LQFPQuadratureDecoder1orQuadTimerBorSP1IorGPIOCProgramControllerandHardwareLoopingUnitDataALU16x16+36-->36-BitMACThree16-bitInputRegistersFour36-bitAccumulatorsAddressGenerationUnitBitManipulationUnit16-Bit56800ECoreInterruptControllerCOP/WatchdogSCI1orGPIOD42IRQAIRQBPDBPDBXAB1XAB2XDB2CDBRSCI0orGPIOESPI0orGPIOEIPBusBridge(IPBB)DecodingPeripheralsPeripheralDeviceSelectsRWControlIPABIPWDBIPRDB2SystemBusR/WControlPABPABCDBWCDBRCDBWJTAG/EOnCEPortDigitalRegAnalogRegLowVoltageSupervisorVCAPVDDVSSVDDAVSSA54752VPP2RESETRSTO463463QuadTimerDorGPIOEQuadTimerCorGPIOEADCA45QuadratureDecoder0orQuadTimerAorGPIOCFlexCAN242ADCB44VREFTEMP_SENSE4*ExternalAddressBusSwitchExternalBusInterfaceUnit*ExternalDataBusSwitchA8-13orGPIOA0-5D7-10orGPIOF0-3GPIOB0-4orA16-20GPIOD0-5orCS2-7*BusControl6546*EMInotfunctionalinthispackage;useasGPIOpinsPLLClockGeneratorXTALEXTALCLKMODEIntegrationModuleSystemPOROSCClockresetsCLKOPWMOutputsFaultInputsPWMACurrentSenseInputsorGPIOCPWMOutputsFaultInputsPWMBCurrentSenseInputsorGPIODOCR_DIS4AD1AD04AD1AD0DataMemory4Kx16Flash4Kx16RAMMemoryProgramMemory32Kx16Flash2Kx16RAM4Kx16BootFlashControl56F8335/56F8135GeneralDescriptionNote:FeaturesinitalicsareNOTavailableinthe56F8135device.
Upto60MIPSat60MHzcorefrequencyDSPandMCUfunctionalityinaunified,C-efficientarchitecture64KBProgramFlash4KBProgramRAM8KBDataFlash8KBDataRAM8KBBootFlashUptotwo6-channelPWMmodulesFour4-channel,12-bitADCsTemperatureSensorUptotwoQuadratureDecodersFlexCANmoduleOptionalOn-ChipRegulatorTwoSerialCommunicationInterfaces(SCIs)UptotwoSerialPeripheralInterface(SPIs)Uptofourgeneral-purposeQuadTimersComputerOperatingProperly(COP)/WatchdogJTAG/EnhancedOn-ChipEmulation(OnCE)forunobtrusive,real-timedebuggingUpto49GPIOlines128-pinLQFPPackage56F8335TechnicalData,Rev.
54FreescaleSemiconductorPreliminaryPart1Overview51.
156F8335/56F8135Features51.
2DeviceDescription.
71.
3Award-WinningDevelopmentEnvironment91.
4ArchitectureBlockDiagram91.
5ProductDocumentation121.
6DataSheetConventions13Part2Signal/ConnectionDescriptions.
.
.
.
142.
1Introduction142.
2SignalPins.
17Part3On-ChipClockSynthesis(OCCS).
.
.
333.
1Introduction333.
2ExternalClockOperation.
333.
3Registers35Part4MemoryMap354.
1Introduction354.
2ProgramMap.
364.
3InterruptVectorTable374.
4DataMap414.
5FlashMemoryMap424.
6EOnCEMemoryMap.
434.
7PeripheralMemoryMappedRegisters.
.
.
444.
8FactoryProgrammedMemory.
71Part5InterruptController(ITCN)715.
1Introduction715.
2Features.
715.
3FunctionalDescription715.
4BlockDiagram735.
5OperatingModes735.
6RegisterDescriptions.
745.
7Resets99Part6SystemIntegrationModule(SIM).
.
1006.
1Introduction1006.
2Features.
1006.
3OperatingModes1016.
4OperatingModeRegister.
1016.
5RegisterDescriptions.
1026.
6ClockGenerationOverview.
1146.
7Power-DownModesOverview1156.
8StopandWaitModeDisableFunction.
.
1166.
9Resets116Part7SecurityFeatures1177.
1OperationwithSecurityEnabled.
1177.
2FlashAccessBlockingMechanisms.
.
.
.
117Part8GeneralPurposeInput/Output(GPIO)1208.
1Introduction1208.
2MemoryMaps1208.
3Configuration.
120Part9JointTestActionGroup(JTAG).
.
1259.
1JTAGInformation125Part10Specifications12610.
1GeneralCharacteristics.
12610.
2DCElectricalCharacteristics.
13010.
3ACElectricalCharacteristics.
13410.
4FlashMemoryCharacteristics.
13410.
5ExternalClockOperationTiming13510.
6PhaseLockedLoopTiming.
13510.
7CrystalOscillatorTiming13610.
8Reset,Stop,Wait,ModeSelect,andInterruptTiming13610.
9SerialPeripheralInterface(SPI)Timing.
13810.
10QuadTimerTiming14210.
11QuadratureDecoderTiming14210.
12SerialCommunicationInterface(SCI)Timing.
14310.
13ControllerAreaNetwork(CAN)Timing.
.
14410.
14JTAGTiming14410.
15Analog-to-DigitalConverter(ADC)Parameters.
14610.
16EquivalentCircuitforADCInputs14810.
17PowerConsumption149Part11Packaging15211.
156F8335PackageandPin-OutInformation15211.
256F8135PackageandPin-OutInformation155Part12DesignConsiderations16012.
1ThermalDesignConsiderations16012.
2ElectricalDesignConsiderations16112.
3PowerDistributionandI/ORingImplementation.
162Part13OrderingInformation163TableofContents56F8335/56F8135Features56F8335TechnicalData,Rev.
5FreescaleSemiconductor5PreliminaryPart1Overview1.
156F8335/56F8135Features1.
1.
1CoreEfficient16-bit56800EfamilycontrollerenginewithdualHarvardarchitectureUpto60MillionInstructionsPerSecond(MIPS)at60MHzcorefrequencySingle-cycle16*16-bitparallelMultiplier-Accumulator(MAC)Four36-bitaccumulators,includingextensionbitsArithmeticandlogicmulti-bitshifterParallelinstructionsetwithuniqueDSPaddressingmodesHardwareDOandREPloopsThreeinternaladdressbusesFourinternaldatabusesInstructionsetsupportsbothDSPandcontrollerfunctionsController-styleaddressingmodesandinstructionsforcompactcodeEfficientCcompilerandlocalvariablesupportSoftwaresubroutineandinterruptstackwithdepthlimitedonlybymemoryJTAG/EOnCEdebugprogramminginterface1.
1.
2DifferencesBetweenDevicesTable1-1outlinesthekeydifferencesbetweenthe56F8335and56F8135devices.
Table1-1DeviceDifferencesFeature56F833556F8135GuaranteedSpeed60MHz/60MIPS40MHz/40MIPSProgramRAM4KBNotAvailableDataFlash8KBNotAvailablePWM2x61x6CAN1NotAvailableQuadTimer42QuadratureDecoder2x41x4TemperatureSensor1NotAvailable56F8335TechnicalData,Rev.
56FreescaleSemiconductorPreliminary1.
1.
3MemoryNote:FeaturesinitalicsareNOTavailableinthe56F8135device.
HarvardarchitecturepermitsasmanyasthreesimultaneousaccessestoprogramanddatamemoryFlashsecurityprotectionfeatureOn-chipmemory,includingalow-cost,high-volumeFlashsolution—64KBofProgramFlash—4KBofProgramRAM—8KBofDataFlash—8KBofDataRAM—8KBofBootFlashEEPROMemulationcapability1.
1.
4PeripheralCircuitsNote:FeaturesinitalicsareNOTavailableinthe56F8135device.
PulseWidthModulatormodule:—Inthe56F8335,twoPulseWidthModulatormodules,eachwithsixPWMoutputs,threeCurrentSenseinputs,andfourFaultinputs;fault-tolerantdesignwithdeadtimeinsertion;supportsbothcenter-alignedandedge-alignedmodes—Inthe56F8135,onePulseWidthModulatormodulewithsixPWMoutputs,threeCurrentSenseinputsandthreeFaultinputs;fault-tolerantdesignwithdeadtimeinsertion;supportsbothcenter-alignedandedge-alignedmodesFour12-bit,Analog-to-DigitalConverters(ADCs),whichsupportfoursimultaneousconversionswithquad,4-pinmultiplexedinputs;ADCandPWMmodulescanbesynchronizedthroughTimerC,channels2and3QuadratureDecoder:—Inthe56F8335,twofour-inputQuadratureDecodersortwoadditionalQuadTimers—Inthe56F8135,onefour-inputQuadratureDecoder,whichworksinconjunctionwithQuadTimerATemperatureSensorcanbeconnected,ontheboard,toanyoftheADCinputstomonitortheon-chiptemperatureQuadTimer:—Inthe56F8335,fourdedicatedgeneral-purposeQuadTimerstotalingsixdedicatedpins:TimerCwithtwopinsandTimerDwithfourpins—Inthe56F8135,twoQuadTimers;TimerAandTimerCbothworkinconjunctionwithGPIOOptionalOn-ChipRegulatorFlexCAN(CANVersion2.
0B-compliant)modulewith2-pinportfortransmitandreceiveTwoSerialCommunicationInterfaces(SCIs),eachwithtwopins(orfouradditionalGPIOlines)UptotwoSerialPeripheralInterfaces(SPIs),bothwithconfigurable4-pinport(oreightadditionalGPIOlines);SPI1canalsobeusedasQuadratureDecoder1orQuadTimerBComputerOperatingProperly(COP)/WatchdogtimerTwodedicatedexternalinterruptpinsDeviceDescription56F8335TechnicalData,Rev.
5FreescaleSemiconductor7Preliminary49GeneralPurposeI/O(GPIO)pins;28pinsdedicatedtoGPIOExternalresetinputpinforhardwareresetExternalresetoutputpinforsystemresetIntegratedlow-voltageinterruptmoduleJTAG/EnhancedOn-ChipEmulation(OnCE)forunobtrusive,processorspeed-independent,real-timedebuggingSoftware-programmable,PhaseLockLoop-basedfrequencysynthesizerforthecoreclock1.
1.
5EnergyInformationFabricatedinhigh-densityCMOSwith5V-tolerant,TTL-compatibledigitalinputsOn-board3.
3Vdownto2.
6Vvoltageregulatorforpoweringinternallogicandmemories;canbedisabledOn-chipregulatorsfordigitalandanalogcircuitrytolowercostandreducenoiseWaitandStopmodesavailableADCsmartpowermanagementEachperipheralcanbeindividuallydisabledtosavepower1.
2DeviceDescriptionThe56F8335and56F8135aremembersofthe56800Ecore-basedfamilyofcontrollers.
Eachcombines,onasinglechip,theprocessingpowerofaDigitalSignalProcessor(DSP)andthefunctionalityofamicrocontrollerwithaflexiblesetofperipheralstocreateanextremelycost-effectivesolution.
Becauseoftheirlowcost,configurationflexibility,andcompactprogramcode,the56F8335and56F8135arewell-suitedformanyapplications.
Thedevicesincludemanyperipheralsthatareespeciallyusefulformotioncontrol,smartappliances,steppers,encoders,tachometers,limitswitches,powersupplyandcontrol,automotivecontrol(56F8335only),enginemanagement,noisesuppression,remoteutilitymetering,industrialcontrolforpower,lighting,andautomationapplications.
The56800EcoreisbasedonaHarvard-stylearchitectureconsistingofthreeexecutionunitsoperatinginparallel,allowingasmanyassixoperationsperinstructioncycle.
TheMCU-styleprogrammingmodelandoptimizedinstructionsetallowstraightforwardgenerationofefficient,compactDSPandcontrolcode.
TheinstructionsetisalsohighlyefficientforC/C++Compilerstoenablerapiddevelopmentofoptimizedcontrolapplications.
The56F8335and56F8135supportprogramexecutionfrominternalmemories.
Twodataoperandscanbeaccessedfromtheon-chipdataRAMperinstructioncycle.
Thesedevicesalsoprovidetwoexternaldedicatedinterruptlinesandupto49GeneralPurposeInput/Output(GPIO)lines,dependingonperipheralconfiguration.
1.
2.
156F8335FeaturesThe56F8335includes64KBofProgramFlashand8KBofDataFlash(eachprogrammablethroughtheJTAGport)with4KBofProgramRAMand8KBofDataRAM.
Atotalof8KBofBootFlashisincorporatedforeasycustomerinclusionoffield-programmablesoftwareroutinesthatcanbeusedtoprogramthemainProgramandDataFlashmemoryareas.
BothProgramandDataFlashmemoriescanbe56F8335TechnicalData,Rev.
58FreescaleSemiconductorPreliminaryindependentlybulkerasedorerasedinpages.
ProgramFlashpageerasesizeis1KB.
BootandDataFlashpageerasesizeis512bytes.
TheBootFlashmemorycanalsobeeitherbulkorpageerased.
Akeyapplication-specificfeatureofthe56F8335istheinclusionoftwoPulseWidthModulator(PWM)modules.
Thesemoduleseachincorporatethreecomplementary,individuallyprogrammablePWMsignaloutputpairs(eachmoduleisalsocapableofsupportingsixindependentPWMfunctions,foratotalof12PWMoutputs)toenhancemotorcontrolfunctionality.
Complementaryoperationpermitsprogrammabledeadtimeinsertion,distortioncorrectionviacurrentsensingbysoftware,andseparatetopandbottomoutputpolaritycontrol.
Theup-countervalueisprogrammabletosupportacontinuouslyvariablePWMfrequency.
Edge-alignedandcenter-alignedsynchronouspulsewidthcontrol(0%to100%modulation)issupported.
Thedeviceiscapableofcontrollingmostmotortypes:ACIM(ACInductionMotors);bothBDCandBLDC(BrushandBrushlessDCmotors);SRMandVRM(SwitchedandVariableReluctanceMotors);andsteppermotors.
ThePWMsincorporatefaultprotectionandcycle-by-cyclecurrentlimitingwithsufficientoutputdrivecapabilitytodirectlydrivestandardoptoisolators.
A"smoke-inhibit",write-onceprotectionfeatureforkeyparametersisalsoincluded.
ApatentedPWMwaveformdistortioncorrectioncircuitisalsoprovided.
EachPWMisdouble-bufferedandincludesinterruptcontrolstopermitintegralreloadratestobeprogrammablefrom1to16.
ThePWMmodulesprovidereferenceoutputstosynchronizetheAnalog-to-DigitalConvertersthroughtwochannelsofQuadTimerC.
The56F8335incorporatestwoQuadratureDecoderscapableofcapturingallfourtransitionsonthetwo-phaseinputs,permittinggenerationofanumberproportionaltoactualposition.
Speedcomputationcapabilitiesaccommodatebothfast-andslow-movingshafts.
AnintegratedwatchdogtimerintheQuadratureDecodercanbeprogrammedwithatime-outvaluetoalertwhennoshaftmotionisdetected.
Eachinputisfilteredtoensureonlytruetransitionsarerecorded.
ThiscontrolleralsoprovidesafullsetofstandardprogrammableperipheralsthatincludetwoSerialCommunicationsInterfaces(SCIs);twoSerialPeripheralInterfaces(SPIs);andfourQuadTimers.
AnyoftheseinterfacescanbeusedasGeneralPurposeInput/Outputs(GPIOs)ifthatfunctionisnotrequired.
AFlexControllerAreaNetwork(FlexCAN)interface(CANVersion2.
0B-compliant)andaninternalinterruptcontrollerarealsoapartofthe56F8335.
1.
2.
256F8135FeaturesThe56F8135includes64KBofProgramFlash,programmablethroughtheJTAGport,and8KBofDataRAM.
Atotalof8KBofBootFlashisincorporatedforeasycustomerinclusionoffield-programmablesoftwareroutinesthatcanbeusedtoprogramthemainProgramFlashmemoryarea.
TheProgramFlashmemorycanbeindependentlybulkerasedorerasedinpages;ProgramFlashpageerasesizeis1KB.
TheBootFlashpageerasesizeis512bytes;BootFlashmemorycanalsobeeitherbulkorpageerased.
Akeyapplication-specificfeatureofthe56F8135istheinclusionofonePulseWidthModulator(PWM)module.
Thismoduleincorporatesthreecomplementary,individuallyprogrammablePWMsignaloutputpairsandcanalsosupportsixindependentPWMfunctionstoenhancemotorcontrolfunctionality.
Complementaryoperationpermitsprogrammabledeadtimeinsertion,distortioncorrectionviacurrentsensingbysoftware,andseparatetopandbottomoutputpolaritycontrol.
Theup-countervalueisprogrammabletosupportacontinuouslyvariablePWMfrequency.
Edge-alignedandcenter-alignedsynchronouspulsewidthcontrol(0%to100%modulation)issupported.
Thedeviceiscapableofcontrollingmostmotortypes:ACIM(ACInductionMotors);bothBDCandBLDC(BrushandBrushlessAward-WinningDevelopmentEnvironment56F8335TechnicalData,Rev.
5FreescaleSemiconductor9PreliminaryDCmotors);SRMandVRM(SwitchedandVariableReluctanceMotors);andsteppermotors.
ThePWMincorporatesfaultprotectionandcycle-by-cyclecurrentlimitingwithsufficientoutputdrivecapabilitytodirectlydrivestandardoptoisolators.
A"smoke-inhibit",write-onceprotectionfeatureforkeyparametersisalsoincluded.
ApatentedPWMwaveformdistortioncorrectioncircuitisalsoprovided.
ThePWMisdouble-bufferedandincludesinterruptcontrolstopermitintegralreloadratestobeprogrammablefrom1to16.
ThePWMmoduleprovidesreferenceoutputstosynchronizetheAnalog-to-DigitalConvertersthroughtwochannelsofQuadTimerC.
The56F8135incorporatesaQuadratureDecodercapableofcapturingallfourtransitionsonthetwo-phaseinputs,permittinggenerationofanumberproportionaltoactualposition.
Speedcomputationcapabilitiesaccommodatebothfast-andslow-movingshafts.
AnintegratedwatchdogtimerintheQuadratureDecodercanbeprogrammedwithatime-outvaluetoalertwhennoshaftmotionisdetected.
Eachinputisfilteredtoensureonlytruetransitionsarerecorded.
ThiscontrolleralsoprovidesafullsetofstandardprogrammableperipheralsthatincludetwoSerialCommunicationsInterfaces(SCIs);twoSerialPeripheralInterfaces(SPIs);andtwoQuadTimers.
AnyoftheseinterfacescanbeusedasGeneralPurposeInput/Outputs(GPIOs)ifthatfunctionisnotrequired.
Aninternalinterruptcontrollerisalsoapartofthe56F8135.
1.
3Award-WinningDevelopmentEnvironmentProcessorExpertTM(PE)providesaRapidApplicationDesign(RAD)toolthatcombineseasy-to-usecomponent-basedsoftwareapplicationcreationwithanexpertknowledgesystem.
TheCodeWarriorIntegratedDevelopmentEnvironmentisasophisticatedtoolforcodenavigation,compiling,anddebugging.
Acompletesetofevaluationmodules(EVMs)anddevelopmentsystemcardswillsupportconcurrentengineering.
Together,PE,CodeWarriorandEVMscreateacomplete,scalabletoolssolutionforeasy,fast,andefficientdevelopment.
1.
4ArchitectureBlockDiagramNote:FeaturesinitalicsareNOTavailableinthe56F8135deviceandareshadedinthefollowingfigures.
The56F8335/56F8135architectureisshowninFigure1-1andFigure1-2.
Figure1-1illustrateshowthe56800EsystembusescommunicatewithinternalmemoriesandtheIPBusBridge.
Table1-2liststheinternalbusesinthe56800Earchitectureandprovidesabriefdescriptionoftheirfunction.
Figure1-2showstheperipheralsandcontrolblocksconnectedtotheIPBusBridge.
Thefiguresdonotshowtheon-boardregulatorandpowerandgroundsignals.
TheyalsodonotshowthemultiplexingbetweenperipheralsorthededicatedGPIOs.
PleaseseePart2,Signal/ConnectionDescriptions,toseewhichsignalsaremultiplexedwiththoseofotherperipherals.
AlsoshowninFigure1-2areconnectionsbetweenthePWM,TimerCandADCblocks.
TheseconnectionsallowthePWMand/orTimerCtocontrolthetimingofthestartofADCconversions.
TheTimerCchannelindicatedcangenerateperiodicstart(SYNC)signalstotheADCtostartitsconversions.
Inanotheroperatingmode,thePWMloadinterrupt(SYNCoutput)signalisroutedinternallytotheTimerCinputchannelasindicated.
Thetimercanthenbeusedtointroduceacontrollabledelaybeforegeneratingitsoutputsignal.
ThetimeroutputthentriggerstheADC.
Tofullyunderstandthisinteraction,pleaseseethe56F8300PeripheralUser'sManualforclarificationontheoperationofallthreeoftheseperipherals.
56F8335TechnicalData,Rev.
510FreescaleSemiconductorPreliminaryFigure1-1SystemBusInterfacesNote:FlashmemoriesareencapsulatedwithintheFlashMemory(FM)Module.
FlashcontrolisaccomplishedbytheI/OtotheFMovertheperipheralbus,whilereadsandwritesarecompletedbetweenthecoreandtheFlashmemories.
Note:TheprimarydataRAMportis32bitswide.
Otherdataportsare16bits.
56800EProgramFlashProgramRAMDataRAMEMI*DataFlashIPBusBridgeBootFlashFlashMemoryModule*EMInotfunctionalinthispackage;sinceonlypartoftheaddress/databusisbondedout,useasGPIOpinsNOTavailableonthe56F8135device.
JTAG/EOnCE511pdb_m[15:0]4pab[20:0]cdbw[31:0]xab2[23:0]xab1[23:0]cdbr_m[31:0]xdb2_m[15:06AddressDataControlCHIPTAPControllerTAPLinkingModuleExternalJTAGPortToFlashControlLogicIPBusArchitectureBlockDiagram56F8335TechnicalData,Rev.
5FreescaleSemiconductor11PreliminaryFigure1-2PeripheralSubsystemTimerATimerCTimerDSPI1ADCBADCAFlexCANGPIOASPI0SCI0SCI1InterruptControllerTo/FromIPBusBridgePWMAPWMBQuadratureDecoder0Note:ADCAandADCBusethesamevoltagereferencecircuitwithVREFH,VREFP,VREFMID,VREFN,andVREFLOpins.
GPIOBGPIOCGPIODGPIOEGPIOFTimerBQuadratureDecoder1TEMP_SENSENOTavailableonthe56F8135device.
Low-VoltageInterruptSystemPORCOPResetRESETPOR&LVISIMCOP21313CLKGEN(OSC/PLL)444SYNCOutputSYNCOutput2ch3ich2ich3och2o881224IPBus56F8335TechnicalData,Rev.
512FreescaleSemiconductorPreliminary1.
5ProductDocumentationThedocumentslistedinTable1-3arerequiredforacompletedescriptionandproperdesignwiththe56F8335and56F8135devices.
DocumentationisavailablefromlocalFreescaledistributors,Freescalesemiconductorsalesoffices,FreescaleLiteratureDistributionCenters,oronlineathttp://www.
freescale.
com.
Table1-2BusSignalNamesNameFunctionProgramMemoryInterfacepdb_m[15:0]Programdatabusforinstructionwordfetchesorreadoperations.
cdbw[15:0]Primarycoredatabususedforprogrammemorywrites.
(Onlythese16bitsofthecdbw[31:0]busareusedforwritestoprogrammemory.
)pab[20:0]Programmemoryaddressbus.
Dataisreturnedonpdb_mbus.
PrimaryDataMemoryInterfaceBuscdbr_m[31:0]Primarycoredatabusformemoryreads.
Addressedviaxab1bus.
cdbw[31:0]Primarycoredatabusformemorywrites.
Addressedviaxab1bus.
xab1[23:0]Primarydataaddressbus.
Capableofaddressingbytes1,words,andlongdatatypes.
Dataiswrittenoncdbwandreturnedoncdbr_m.
Alsousedtoaccessmemory-mappedI/O.
1.
Byteaccessescanonlyoccurinthebottomhalfofthememoryaddressspace.
TheMSBoftheaddresswillbeforcedto0.
SecondaryDataMemoryInterfacexdb2_m[15:0]Secondarydatabususedforsecondarydataaddressbusxab2inthedualmemoryreads.
xab2[23:0]Secondarydataaddressbususedforthesecondoftwosimultaneousaccesses.
Capableofaddressingonlywords.
Dataisreturnedonxdb2_m.
PeripheralInterfaceBusIPBus[15:0]Peripheralbusaccessesallon-chipperipheralsregisters.
ThisbusoperatesatthesameclockrateasthePrimaryDataMemoryandthereforegeneratesnodelayswhenaccessingtheprocessor.
Writedataisobtainedfromcdbw.
Readdataisprovidedtocdbr_m.
Table1-3ChipDocumentationTopicDescriptionOrderNumberDSP56800EReferenceManualDetaileddescriptionofthe56800Efamilyarchitecture,16-bithybridcontrollercoreprocessor,andtheinstructionsetDSP56800ERM56F8300PeripheralUserManualDetaileddescriptionofperipheralsofthe56F8300familyofdevicesMC56F8300UM56F8300SCI/CANBootloaderUserManualDetaileddescriptionoftheSCI/CANBootloaders56F8300familyofdevicesMC56F83xxBLUM56F8335/56F8135TechnicalDataSheetElectricalandtimingspecifications,pindescriptions,devicespecificperipheralinformationandpackagedescriptions(thisdocument)MC56F8335ErrataDetailsanychipissuesthatmightbepresentMC56F8335EMC56F8135EDataSheetConventions56F8335TechnicalData,Rev.
5FreescaleSemiconductor13Preliminary1.
6DataSheetConventionsThisdatasheetusesthefollowingconventions:OVERBARThisisusedtoindicateasignalthatisactivewhenpulledlow.
Forexample,theRESETpinisactivewhenlow.
"asserted"Ahightrue(activehigh)signalishighoralowtrue(activelow)signalislow.
"deasserted"Ahightrue(activehigh)signalisloworalowtrue(activelow)signalishigh.
Examples:Signal/SymbolLogicStateSignalStateVoltage11.
ValuesforVIL,VOL,VIH,andVOHaredefinedbyindividualproductspecifications.
PINTrueAssertedVIL/VOLPINFalseDeassertedVIH/VOHPINTrueAssertedVIH/VOHPINFalseDeassertedVIL/VOL56F8335TechnicalData,Rev.
514FreescaleSemiconductorPreliminaryPart2Signal/ConnectionDescriptions2.
1IntroductionTheinputandoutputsignalsofthe56F8335and56F8135areorganizedintofunctionalgroups,asdetailedinTable2-2andasillustratedinFigure2-1.
InTable2-2,eachtablerowdescribesthesignalorsignalspresentonapin.
Table2-1FunctionalGroupPinAllocationsFunctionalGroupNumberofPinsinPackage56F833556F8135Power(VDDorVDDA)99PowerOptionControl11Ground(VSSorVSSA)66SupplyCapacitors1&VPP1.
Iftheon-chipregulatorisdisabled,theVCAPpinsserveas2.
5VVDD_COREpowerinputs66PLLandClock44BusControl66InterruptandProgramControl44PulseWidthModulator(PWM)Ports2613SerialPeripheralInterface(SPI)Port044SerialPeripheralInterface(SPI)Port1—4QuadratureDecoderPort022.
Alternately,canfunctionasQuadTimerpinsorGPIO44QuadratureDecoderPort133.
PinsinthissectioncanfunctionasQuadTimer,SPI1,orGPIO4—SerialCommunicationsInterface(SCI)Ports44CANPorts2—Analog-to-DigitalConverter(ADC)Ports2121TimerModulePorts64JTAG/EnhancedOn-ChipEmulation(EOnCE)55TemperatureSense1—DedicatedGPIO(AddressBus=11;DataBus=44)4.
EMInotfunctionalinthesepackages;useasGPIOpins.
Note:SeeTable1-1for56F8135functionaldifferences.
2828Introduction56F8335TechnicalData,Rev.
5FreescaleSemiconductor15PreliminaryFigure2-156F8335SignalsIdentifiedbyFunctionalGroup1(128-PinLQFP)1.
Alternatepinfunctionalityisshowninparenthesis;pindirection/typeshownisthedefaultfunctionality.
VDD_IOVDDA_OSC_PLLVSSVSSA_ADCOtherSupplyPortsPLLandClock*ExternalAddressBusorGPIO*ExternalDataBus*ExternalBusControlSCI0orGPIOESCI1orGPIOJTAG/EOnCEPort51711VCAP1-VCAP4VPP1&VPP242PowerPowerPowerGroundGround111A8-A13(GPIOA0-5)D7-D10(GPIOF0-3)GPIOD0-5(CS2-7)TXD1(GPIOD6)RXD1(GPIOD7)QuadratureDecoder0orQuadTimerAorGPIOPHASEB0(TA1,GPIOC5)INDEX0(TA2,GPIOC6)HOME0(TA3,GPIOC7)ISA0-2(GPIOC8-10)FAULTB0-3PWMB0-5ANA0-7TD0-3(GPIOE10-13)IRQAIRQBRESETRSTOSPI0orGPIOQuadratureDecoder1orQuadTimerBorSPI1orGPIOTemperatureSensor654111111111633854GPIOB0-4(A16-20)6EXTALXTALCLKO171111TXD0(GPIOE0)RXD0(GPIOE1)TCKTMSTDITDOTRSTSCLK0(GPIOE4)MOSI0(GPIOE5)MISO0(GPIOE6)SS0(GPIOE7)PHASEB1(TB1,MOSI1,GPIOC1)INDEX1(TB2,MISO1,GPIOC2)HOME1(TB3,SS1,GPIOC3)PWMA0-5FAULTA0-3ISB0-2(GPIOD10-12)ANB0-7CAN_RXCAN_TXTC0-1(GPIOE8-9)PWMAPWMBADCBADCACANInterrupt/ProgramControlPHASEA1(TB0,SCLK1,GPIOC0)641111111111111111111146481121111VREFCLKMODE1TEMP_SENSE1*EMInotfunctionalinthispackage;useasGPIOpinsOCR_DISVDDA_ADC156F8335PHASEA0(TA0,GPIOC4)QuadTimerCandDorGPIO56F8335TechnicalData,Rev.
516FreescaleSemiconductorPreliminaryFigure2-256F8135SignalsIdentifiedbyFunctionalGroup1(128-PinLQFP)1.
Alternatepinfunctionalityisshowninparenthesis;pindirection/typeshownisthedefaultfunctionality.
VDD_IOVDDA_OSC_PLLVSSVSSA_ADCOtherSupplyPortsPLLandClock*ExternalAddressBusorGPIO*ExternalDataBus*ExternalBusControlSCI0orGPIOESCI1orGPIOJTAG/EOnCEPort51711VCAP1-VCAP4VPP1&VPP242PowerPowerPowerGroundGround111A8-A13(GPIOA0-5)D7-D10(GPIOF0-3)GPIOD0-5(CS2-7)TXD1(GPIOD6)RXD1(GPIOD7)QuadratureDecoder0orQuadTimerAorGPIOPHASEB0(TA1,GPIOC5)INDEX0(TA2,GPIOC6)HOME0(TA3,GPIOC7)(GPIOC8-10)FAULTB0-3PWMB0-5ANA0-7(GPIOE10-13)IRQAIRQBRESETRSTOSPI0orGPIOSPI1orGPIO65411111111133854GPIOB0-4(A16-20)6EXTALXTALCLKO171111TXD0(GPIOE0)RXD0(GPIOE1)TCKTMSTDITDOTRSTSCLK0(GPIOE4)MOSI0(GPIOE5)MISO0(GPIOE6)SS0(GPIOE7)(MOSI1,GPIOC1)(MISO1,GPIOC2)(SS1,GPIOC3)ISB0-2(GPIOD10-12)ANB0-7TC0-1(GPIOE8-9)GPIOPWMBADCBADCAInterrupt/ProgramControl(SCLK1,GPIOC0)641111111111111111111164821111VREFCLKMODE1*EMInotfunctionalinthispackage;useasGPIOpinsOCR_DISVDDA_ADC156F8135PHASEA0(TA0,GPIOC4)QUADTimerCorGPIOSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor17Preliminary2.
2SignalPinsAfterreset,eachpinisconfiguredforitsprimaryfunction(listedfirst).
Anyalternatefunctionalitymustbeprogrammed.
EMIisnotfunctionalinthispackage;sinceonlypartoftheaddress/databusisbondedout,useasGPIOpins.
Note:SignalsinitalicsareNOTavailableinthe56F8135device.
Ifthe"StateDuringReset"listsmorethanonestateforapin,thefirststateistheactualresetstate.
Otherstatesshowtheresetconditionofthealternatefunction,whichyougetifthealternatepinfunctionisselectedwithoutchangingtheconfigurationofthealternateperipheral.
Forexample,theA8/GPIOA0pinshowsthatitistri-statedduringreset.
IftheGPIOA_PERischangedtoselecttheGPIOfunctionofthepin,itwillbecomeaninputifnootherregistersarechanged.
Table2-2SignalandPackageInformationforthe128-PinLQFPSignalNamePinNo.
TypeStateDuringResetSignalDescriptionVDD_IO4SupplyI/OPower—Thispinsupplies3.
3VpowertothechipI/OinterfaceandalsotheProcessorcorethroughttheon-chipvoltageregulator,ifitisenabled.
VDD_IO14VDD_IO25VDD_IO36VDD_IO62VDD_IO76VDD_IO112VDDA_ADC94SupplyADCPower—Thispinsupplies3.
3VpowertotheADCmodules.
Itmustbeconnectedtoacleananalogpowersupply.
VDDA_OSC_PLL72SupplyOscillatorandPLLPower—Thispinsupplies3.
3VpowertotheOSCandtotheinternalregulatorthatinturnsuppliesthePhaseLockedLoop.
Itmustbeconnectedtoacleananalogpowersupply.
VSS3SupplyGround—ThesepinsprovidegroundforchiplogicandI/Odrivers.
VSS21VSS35VSS59VSS6556F8335TechnicalData,Rev.
518FreescaleSemiconductorPreliminaryVSSA_ADC95SupplyADCAnalogGround—ThispinsuppliesananaloggroundtotheADCmodules.
OCR_DIS71InputInputOn-ChipRegulatorDisable—TiethispintoVSStoenabletheon-chipregulatorTiethispintoVDDtodisabletheon-chipregulatorThispinisintendedtobeastaticDCsignalfrompower-uptoshutdown.
Donottrytotogglethispinforpowersavingsduringoperation.
VCAP149SupplySupplyVCAP1-4—WhenOCR_DISistiedtoVSS(regulatorenabled),connecteachpintoa2.
2μForgreaterbypasscapacitorinordertobypassthecorelogicvoltageregulator,requiredforproperchipoperation.
WhenOCR_DISistiedtoVDD(regulatordisabled),thesepinsbecomeVDD_COREandshouldbeconnectedtoaregulated2.
5Vpowersupply.
Note:Thisbypassisrequiredevenifthechipispoweredwithanexternalsupply.
VCAP2122VCAP375VCAP413VPP1119InputInputVPP1-2—Thesepinsshouldbeleftunconnectedasanopencircuitfornormalfunctionality.
VPP25CLKMODE79InputInputClockInputModeSelection—ThisinputdeterminesthefunctionoftheXTALandEXTALpins.
1=ExternalclockinputonXTALisusedtodirectlydrivetheinputclockofthechip.
TheEXTALpinshouldbegrounded.
0=AcrystalorceramicresonatorshouldbeconnectedbetweenXTALandEXTAL.
EXTAL74InputInputExternalCrystalOscillatorInput—Thisinputcanbeconnectedtoan8MHzexternalcrystal.
TiethispinlowifXTALisdrivenbyanexternalclocksource.
XTAL73Input/OutputChip-drivenCrystalOscillatorOutput—Thisoutputconnectstheinternalcrystaloscillatoroutputtoanexternalcrystal.
Ifanexternalclockisused,XTALmustbeusedastheinputandEXTALconnectedtoGND.
Theinputclockcanbeselectedtoprovidetheclockdirectlytothecore.
Thisinputclockcanalsobeselectedastheinputclockfortheon-chipPLL.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor19PreliminaryCLKO6OutputInreset,outputisdisabledClockOutput—Thispinoutputsabufferedclocksignal.
UsingtheSIMCLKOSelectRegister(SIM_CLKOSR),thispincanbeprogrammedasanyofthefollowing:disabled,CLK_MSTR(systemclock),IPBusclock,oscillatoroutput,prescalerclockandpostscalerclock.
Othersignalsarealsoavailablefortestpurposes.
SeePart6.
5.
7fordetails.
A8(GPIOA0)15OutputSchmittInput/OutputInreset,outputisdisabled,pull-upisenabledAddressBus—A8-A13specifysixoftheaddresslinesforexternalprogramordatamemoryaccesses.
DependinguponthestateoftheDRVbitintheEMIbuscontrolregister(BCR),A8-A13andEMIcontrolsignalsaretri-statedwhentheexternalbusisinactive.
PortAGPIO—ThesesixGPIOpinscanbeindividuallyprogrammedasinputoroutputpins.
Afterreset,thesepinsdefaulttoaddressbusfunctionalityandmustbeprogrammedasGPIO.
Todeactivatetheinternalpull-upresistor,cleartheappropriateGPIObitintheGPIOA_PURregister.
Example:GPIOA0,clearbit0intheGPIOA_PURregister.
Note:Primaryfunctionisnotavailableinthispackageconfiguration;GPIOfunctionmustbeusedinstead.
A9(GPIOA1)16A10(GPIOA2)17A11(GPIOA3)18A12(GPIOA4)19A13(GPIOA5)20GPIOB0(A16)27SchmittInput/OutputOutputInput,pull-upenabledPortBGPIO—ThesefourGPIOpinscanbeindividuallyprogrammedasaninputoroutputpin.
AddressBus—A16-A19specifyfouroftheaddresslinesforexternalprogramordatamemoryaccesses.
DependinguponthestateoftheDRVbitintheEMIbuscontrolregister(BCR),A16-A19andEMIcontrolsignalsaretri-statedwhentheexternalbusisinactive.
Afterreset,thedefaultstateisGPIO.
Todeactivatetheinternalpull-upresistor,clearbit0intheGPIOB_PURregister.
Example:GPIOB1,clearbit1intheGPIOB_PURregister.
GPIOB1(A17)28GPIOB2(A18)29GPIOB3(A19)30Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescription56F8335TechnicalData,Rev.
520FreescaleSemiconductorPreliminaryGPIOB4(A20)(prescaler_clock)31SchmittInput/OutputOutputOutputInput,pull-upenabledPortBGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
AddressBus—A20specifiesoneoftheaddresslinesforexternalprogramordatamemoryaccesses.
DependinguponthestateoftheDRVbitintheEMIbuscontrolregister(BCR),A20andEMIcontrolsignalsaretri-statedwhentheexternalbusisinactive.
ClockOutput—canbeusedtomonitortheprescaler_clockonGPIOB4.
Afterreset,thedefaultstateisGPIO.
Thispincanalsobeusedtoviewtheprescaler_clock.
Inthesecases,theGPIOB_PERcanbeusedtodisabletheGPIO.
TheCLKOSRregisterintheSIMcanthenbeusedtochoosebetweenaddressandclockfunctions;seePart6.
5.
7fordetails.
Todeactivatetheinternalpull-upresistor,clearbit4intheGPIOB_PURregister.
D7(GPIOF0)22Input/OutputInput/OutputInreset,outputisdisabled,pull-upisenabledDataBus—D7-D10specifypartofthedataforexternalprogramordatamemoryaccesses.
DependinguponthestateoftheDRVbitintheEMIbuscontrolregister(BCR),D7-D10aretri-statedwhentheexternalbusisinactivePortFGPIO—ThesefourGPIOpinscanbeindividuallyprogrammedasinputoroutputpins.
Afterreset,thesepinsdefaulttodatabusfunctionalityandshouldbeprogrammedasGPIO.
Todeactivatetheinternalpull-upresistor,cleartheappropriateGPIObitintheGPIOF_PURregister.
Example:GPIOF0,clearbit0intheGPIOF_PURregister.
Note:Primaryfunctionisnotavailableinthispackageconfiguration;GPIOfunctionmustbeusedinstead.
D8(GPIOF1)23D9(GPIOF2)24D10(GPIOF3)26Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor21PreliminaryGPIOD0(CS2)42Input/OutputOutputInput,pull-upenabledPortDGPIO—ThesesixGPIOpinscanbeindividuallyprogrammedasinputoroutputpins.
ChipSelect—CS2-CS7maybeprogrammedwithintheEMImoduletoactaschipselectsforspecificareasoftheexternalmemorymap.
DependinguponthestateoftheDRVbitintheEMIbuscontrolregister(BCR),CS2-CS7aretri-statedwhentheexternalbusisinactive.
Afterreset,thesepinsareconfiguredasGPIO.
Todeactivatetheinternalpull-upresistor,cleartheappropriateGPIObitintheGPIOD_PURregister.
Example:GPIOD0,clearbit0intheGPIOD_PURregister.
GPIOD1(CS3)43GPIOD2(CS4)44GPIOD3(CS5)45GPIOD4(CS6)46GPIOD5(CS7)47TXD0(GPIOE0)7OutputInput/OutputInreset,outputisdisabled,pull-upisenabledTransmitData—SCI0transmitdataoutputPortEGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisSCIoutput.
Todeactivatetheinternalpull-upresistor,clearbit0intheGPIOE_PURregister.
RXD0(GPIOE1)8InputInput/OutputInput,pull-upenabledReceiveData—SCI0receivedatainputPortEGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisSCIoutput.
Todeactivatetheinternalpull-upresistor,clearbit1intheGPIOE_PURregister.
TXD1(GPIOD6)40OutputInput/OutputInreset,outputisdisabled,pull-upisenabledTransmitData—SCI1transmitdataoutputPortDGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisSCIoutput.
Todeactivatetheinternalpull-upresistor,clearbit6intheGPIOD_PURregister.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescription56F8335TechnicalData,Rev.
522FreescaleSemiconductorPreliminaryRXD1(GPIOD7)41InputInput/OutputInput,pull-upenabledReceiveData—SCI1receivedatainputPortDGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisSCIinput.
Todeactivatetheinternalpull-upresistor,clearbit7intheGPIOD_PURregister.
TCK115SchmittInputInput,pulledlowinternallyTestClockInput—ThisinputpinprovidesagatedclocktosynchronizethetestlogicandshiftserialdatatotheJTAG/EOnCEport.
Thepinisconnectedinternallytoapull-downresistor.
TMS116SchmittInputInput,pulledhighinternallyTestModeSelectInput—ThisinputpinisusedtosequencetheJTAGTAPcontroller'sstatemachine.
ItissampledontherisingedgeofTCKandhasanon-chippull-upresistor.
Todeactivatetheinternalpull-upresistor,settheJTAGbitintheSIM_PUDRregister.
Note:AlwaystietheTMSpintoVDDthrougha2.
2Kresistor.
TDI117SchmittInputInput,pulledhighinternallyTestDataInput—ThisinputpinprovidesaserialinputdatastreamtotheJTAG/EOnCEport.
ItissampledontherisingedgeofTCKandhasanon-chippull-upresistor.
Todeactivatetheinternalpull-upresistor,settheJTAGbitintheSIM_PUDRregister.
TDO118OutputInreset,outputisdisabled,pull-upisenabledTestDataOutput—Thistri-stateableoutputpinprovidesaserialoutputdatastreamfromtheJTAG/EOnCEport.
Itisdrivenintheshift-IRandshift-DRcontrollerstates,andchangesonthefallingedgeofTCK.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor23PreliminaryTRST114SchmittInputInput,pulledhighinternallyTestReset—Asaninput,alowsignalonthispinprovidesaresetsignaltotheJTAGTAPcontroller.
Toensurecompletehardwarereset,TRSTshouldbeassertedwheneverRESETisasserted.
TheonlyexceptionoccursinadebuggingenvironmentwhenahardwaredeviceresetisrequiredandtheJTAG/EOnCEmodulemustnotbereset.
Inthiscase,assertRESET,butdonotassertTRST.
Todeactivatetheinternalpull-upresistor,settheJTAGbitintheSIM_PUDRregister.
Note:Fornormaloperation,connectTRSTdirectlytoVSS.
Ifthedesignistobeusedinadebuggingenvironment,TRSTmaybetiedtoVSSthrougha1Kresistor.
PHASEA0(TA0)(GPIOC4)127SchmittInputSchmittInput/OutputSchmittInput/OutputInput,pull-upenabledPhaseA—QuadratureDecoder0,PHASEAinputTA0—TimerA,Channel0PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisPHASEA0.
Todeactivatetheinternalpull-upresistor,clearbit4oftheGPIOC_PURregister.
PHASEB0(TA1)(GPIOC5)128SchmittInputSchmittInput/OutputSchmittInput/OutputInput,pull-upenabledPhaseB—QuadratureDecoder0,PHASEBinputTA1—TimerA,Channel1PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisPHASEB0.
Todeactivatetheinternalpull-upresistor,clearbit5oftheGPIOC_PURregister.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescription56F8335TechnicalData,Rev.
524FreescaleSemiconductorPreliminaryINDEX0(TA2)(GPIOC6)1SchmittInputSchmittInput/OutputSchmittInput/OutputInput,pull-upenabledIndex—QuadratureDecoder0,INDEXinputTA2—TimerA,Channel2PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisINDEX0.
Todeactivatetheinternalpull-upresistor,clearbit6oftheGPIOC_PURregister.
HOME0(TA3)(GPIOC7)2SchmittInputSchmittInput/OutputSchmittInput/OutputInput,pull-upenabledHome—QuadratureDecoder0,HOMEinputTA3—TimerA,Channel3PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisHOME0.
Todeactivatetheinternalpull-upresistor,clearbit7oftheGPIOC_PURregister.
SCLK0(GPIOE4)124SchmittInput/OutputSchmittInput/OutputInput,pull-upenabledSPI0SerialClock—Inthemastermode,thispinservesasanoutput,clockingslavedlisteners.
Inslavemode,thispinservesasthedataclockinput.
PortEGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisSCLK0.
Todeactivatetheinternalpull-upresistor,clearbit4intheGPIOE_PURregister.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor25PreliminaryMOSI0(GPIOE5)126Input/OutputInput/OutputInreset,outputisdisabled,pull-upisenabledSPI0MasterOut/SlaveIn—Thisserialdatapinisanoutputfromamasterdeviceandaninputtoaslavedevice.
ThemasterdeviceplacesdataontheMOSIlineahalf-cyclebeforetheclockedgetheslavedeviceusestolatchthedata.
PortEGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisMOSI0.
Todeactivatetheinternalpull-upresistor,clearbit5intheGPIOE_PURregister.
MISO0(GPIOE6)125Input/OutputInput/OutputInput,pull-upenabledSPI0MasterIn/SlaveOut—Thisserialdatapinisaninputtoamasterdeviceandanoutputfromaslavedevice.
TheMISOlineofaslavedeviceisplacedinthehigh-impedancestateiftheslavedeviceisnotselected.
TheslavedeviceplacesdataontheMISOlineahalf-cyclebeforetheclockedgethemasterdeviceusestolatchthedata.
PortEGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisMISO0.
Todeactivatetheinternalpull-upresistor,clearbit6intheGPIOE_PURregister.
SS0(GPIOE7)123InputInput/OutputInput,pull-upenabledSPI0SlaveSelect—SS0isusedinslavemodetoindicatetotheSPImodulethatthecurrenttransferistobereceived.
PortEGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Afterreset,thedefaultstateisSS0.
Todeactivatetheinternalpull-upresistor,clearbit7intheGPIOE_PURregister.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescription56F8335TechnicalData,Rev.
526FreescaleSemiconductorPreliminaryPHASEA1(TB0)(SCLK1)(GPIOC0)9SchmittInputSchmittInput/OutputSchmittInput/OutputSchmittInput/OutputInput,pull-upenabledPhaseA1—QuadratureDecoder1,PHASEAinputfordecoder1.
TB0—TimerB,Channel0SPI1SerialClock—Inthemastermode,thispinservesasanoutput,clockingslavedlisteners.
Inslavemode,thispinservesasthedataclockinput.
ToactivatetheSPIfunction,setthePHSA_ALTbitintheSIM_GPSregister.
Fordetails,seePart6.
5.
8.
PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Inthe56F8335,thedefaultstateafterresetisPHASEA1.
Inthe56F8135,thedefaultstateisnotoneofthefunctionsofferedandmustbereconfigured.
Todeactivatetheinternalpull-upresistor,clearbit0intheGPIOC_PURregister.
PHASEB1(TB1)(MOSI1)(GPIOC1)10SchmittInputSchmittInput/OutputSchmittInput/OutputSchmittInput/OutputInput,pull-upenabledPhaseB1—QuadratureDecoder1,PHASEBinputfordecoder1.
TB1—TimerB,Channel1SPI1MasterOut/SlaveIn—Thisserialdatapinisanoutputfromamasterdeviceandaninputtoaslavedevice.
ThemasterdeviceplacesdataontheMOSIlineahalf-cyclebeforetheclockedgetheslavedeviceusestolatchthedata.
ToactivatetheSPIfunction,setthePHSB_ALTbitintheSIM_GPSregister.
Fordetails,seePart6.
5.
8.
PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Inthe56F8335,thedefaultstateafterresetisPHASEB1.
Inthe56F8135,thedefaultstateisnotoneofthefunctionsofferedandmustbereconfigured.
Todeactivatetheinternalpull-upresistor,clearbit1intheGPIOC_PURregister.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor27PreliminaryINDEX1(TB2)(MISO1)(GPIOC2)11SchmittInputSchmittInput/OutputSchmittInput/OutputSchmittInput/OutputInput,pull-upenabledIndex1—QuadratureDecoder1,INDEXinputTB2—TimerB,Channel2SPI1MasterIn/SlaveOut—Thisserialdatapinisaninputtoamasterdeviceandoutputfromaslavedevice.
TheMISOlineofaslavedeviceisplacedinthehigh-impedancestateiftheslavedeviceisnotselected.
TheslavedeviceplacesdataontheMISOlineahalf-cyclebeforetheclockedgethemasterdeviceusestolatchthedata.
ToactivatetheSPIfunction,settheINDEX_ALTbitintheSIM_GPSregister.
SeePart6.
5.
8fordetails.
PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasaninputoroutputpin.
Inthe56F8335,thedefaultstateafterresetisINDEX1.
Inthe56F8135,thedefaultstateisnotoneofthefunctionsofferedandmustbereconfigured.
Todeactivatetheinternalpull-upresistor,clearbit2intheGPIOC_PURregister.
HOME1(TB3)(SS1)(GPIOC3)12SchmittInputSchmittInput/OutputSchmittInputSchmittInput/OutputInput,pull-upenabledHome—QuadratureDecoder1,HOMEinputTB3—TimerB,Channel3SPI1SlaveSelect—Inthemastermode,thispinisusedtoarbitratemultiplemasters.
Inslavemode,thispinisusedtoselecttheslave.
ToactivatetheSPIfunction,settheHOME_ALTbitintheSIM_GPSregister.
SeePart6.
5.
8fordetails.
PortCGPIO—ThisGPIOpincanbeindividuallyprogrammedasinputoroutputpin.
Inthe56F8335,thedefaultstateafterresetisHOME1.
Inthe56F8135,thedefaultstateisnotoneofthefunctionsofferedandmustbereconfigured.
Todeactivatetheinternalpull-upresistor,clearbit3intheGPIOC_PURregister.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescription56F8335TechnicalData,Rev.
528FreescaleSemiconductorPreliminaryPWMA058OutputInreset,outputisdisabled,pull-upisenabledPWMA0-5—ThesearesixPWMAoutputpins.
PWMA160PWMA261PWMA363PWMA464PWMA566ISA0(GPIOC8)104SchmittInputSchmittInput/OutputInput,pull-upenabledISA0-2—Thesethreeinputcurrentstatuspinsareusedfortop/bottompulsewidthcorrectionincomplementarychanneloperationforPWMA.
PortCGPIO—TheseGPIOpinscanbeindividuallyprogrammedasinputoroutputpins.
Inthe56F8335,thesepinsdefaulttoISAfunctionality.
Inthe56F8135,thedefaultstateisnotoneofthefunctionsofferedandmustbereconfigured.
Todeactivatetheinternalpull-upresistor,cleartheappropriatebitoftheGPIOC_PURregister.
SeePart6.
5.
6fordetails.
ISA1(GPIOC9)105ISA2(GPIOC10)106FAULTA067SchmittInputInput,pull-upenabledFAULTA0-2—ThesethreefaultinputpinsareusedfordisablingselectedPWMAoutputsincaseswherefaultconditionsoriginateoff-chip.
Todeactivatetheinternalpull-upresistor,setthePWMA0bitintheSIM_PUDRregister.
SeePart6.
5.
6fordetails.
FAULTA168FAULTA269FAULTA370SchmittInputInput,pull-upenabledFAULTA3—ThisfaultinputpinisusedfordisablingselectedPWMAoutputsincaseswherefaultconditionsoriginateoff-chip.
Todeactivatetheinternalpull-upresistor,setthePWMA1bitintheSIM_PUDRregister.
SeePart6.
5.
6fordetails.
PWMB032OutputInreset,outputisdisabled,pull-upisenabledPWMB0-5—SixPWMBoutputpins.
PWMB133PWMB234PWMB337PWMB438PWMB539Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor29PreliminaryISB0(GPIOD10)48SchmittInputSchmittInput/OutputInput,pull-upenabledISB0-2—Thesethreeinputcurrentstatuspinsareusedfortop/bottompulsewidthcorrectionincomplementarychanneloperationforPWMB.
PortDGPIO—TheseGPIOpinscanbeindividuallyprogrammedasinputoroutputpins.
Atreset,thesepinsdefaulttoISBfunctionality.
Todeactivatetheinternalpull-upresistor,cleartheappropriatebitoftheGPIOD_PURregister.
SeePart6.
5.
6fordetails.
ISB1(GPIOD11)50ISB2(GPIOD12)51FAULTB054SchmittInputInput,pull-upenabledFAULTB0-3—ThesefourfaultinputpinsareusedfordisablingselectedPWMBoutputsincaseswherefaultconditionsoriginateoff-chip.
Todeactivatetheinternalpull-upresistor,setthePWMBbitintheSIM_PUDRregister.
SeePart6.
5.
6fordetails.
FAULTB155FAULTB256FAULTB357ANA080InputAnalogInputANA0-3—AnaloginputstoADCA,channel0ANA181ANA282ANA383ANA484InputAnalogInputANA4-7—AnaloginputstoADCA,channel1ANA585ANA686ANA787VREFH93InputAnalogInputVREFH—AnalogReferenceVoltageHigh.
VREFHmustbelessthanorequaltoVDDA_ADC.
VREFP92Input/OutputAnalogInput/OutputVREFP,VREFMID&VREFN—Internalpinsforvoltagereferencewhicharebroughtoff-chipsothattheycanbebypassed.
Connecttoa0.
1μFlowESRcapacitor.
VREFMID91VREFN90VREFLO89InputAnalogInputVREFLO—AnalogReferenceVoltageLow.
Thisshouldnormallybeconnectedtoalow-noiseVSSA.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescription56F8335TechnicalData,Rev.
530FreescaleSemiconductorPreliminaryANB096InputAnalogInputANB0-3—AnaloginputstoADCB,channel0ANB197ANB298ANB399ANB4100InputAnalogInputANB4-7—AnaloginputstoADCB,channel1ANB5101ANB6102ANB7103TEMP_SENSE88OutputAnalogOutputTemperatureSenseDiode—Thissignalconnectstoanon-chipdiodethatcanbeconnectedtooneoftheADCinputsandisusedtomonitorthetemperatureofthedie.
Mustbebypassedwitha0.
01μFcapacitor.
CAN_RX121SchmittInputInput,pull-upenabledFlexCANReceiveData—ThisistheCANinput.
Thispinhasaninternalpull-upresistor.
Todeactivatetheinternalpull-upresistor,settheCANbitintheSIM_PUDRregister.
CAN_TX120OpenDrainOutputOpenDrainOutputFlexCANTransmitData—CANoutputwithinternalpull-upenableatreset.
**Note:Ifapinisconfiguredasopendrainoutputmode,internalpull-upwillautomaticallybedisabledwhenitoutputslow.
Internalpull-upwillbeenabledunlessithasbeenmanuallydisabledbyclearingthecorrespondingbitinthePURENregisteroftheGPIOmodule,whenitoutputshigh.
Ifapinisconfiguredaspush-pulloutputmode,internalpull-upwillautomaticallybedisabled,whetheritoutputsloworhigh.
TC0(GPIOE8)111SchmittInput/OutputSchmittInput/OutputInput,pull-upenabledTC0-1—TimerC,Channels0and1PortEGPIO—TheseGPIOpinscanbeindividuallyprogrammedasinputoroutputpins.
Atreset,thesepinsdefaulttoTimerfunctionality.
Todeactivatetheinternalpull-upresistor,cleartheappropriatebitoftheGPIOE_PURregister.
SeePart6.
5.
6fordetails.
TC1(GPIOE9)113Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionSignalPins56F8335TechnicalData,Rev.
5FreescaleSemiconductor31PreliminaryTD0(GPIOE10)107SchmittInput/OutputSchmittInput/OutputInput,pull-upenabledTD0-TD3—TimerD,Channels0,1,2and3PortEGPIO—TheseGPIOpinscanbeindividuallyprogrammedasinputoroutputpins.
Atreset,thesepinsdefaulttoTimerfunctionality.
Todeactivatetheinternalpull-upresistor,cleartheappropriatebitoftheGPIOE_PURregister.
SeePart6.
5.
6fordetails.
TD1(GPIOE11)108TD2(GPIOE12)109TD3(GPIOE13)110IRQA52SchmittInputInput,pull-upenabledExternalInterruptRequestAandB—TheIRQAandIRQBinputsareasynchronousexternalinterruptrequestsduringStopandWaitmodeoperation.
Duringotheroperatingmodes,theyaresynchronizedexternalinterruptrequests,whichindicateanexternaldeviceisrequestingservice.
Theycanbeprogrammedtobelevel-sensitiveornegative-edgetriggered.
Todeactivatetheinternalpull-upresistor,settheIRQbitintheSIM_PUDRregister.
SeePart6.
5.
6fordetails.
IRQB53RESET78SchmittInputInput,pull-upenabledReset—Thisinputisadirecthardwareresetontheprocessor.
WhenRESETisassertedlow,thedeviceisinitializedandplacedintheresetstate.
ASchmitttriggerinputisusedfornoiseimmunity.
Theinternalresetsignalwillbedeassertedsynchronouswiththeinternalclocksafterafixednumberofinternalclocks.
Toensurecompletehardwarereset,RESETandTRSTshouldbeassertedtogether.
TheonlyexceptionoccursinadebuggingenvironmentwhenahardwaredeviceresetisrequiredandtheJTAG/EOnCEmodulemustnotbereset.
Inthiscase,assertRESET,butdonotassertTRST.
Note:TheinternalPower-OnResetwillassertoninitialpower-up.
Todeactivatetheinternalpull-upresistor,settheRESETbitintheSIM_PUDRregister.
SeePart6.
5.
6.
fordetails.
RSTO77OutputOutputResetOutput—Thisoutputreflectstheinternalresetstateofthechip.
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescription56F8335TechnicalData,Rev.
532FreescaleSemiconductorPreliminaryEXTBOOTInternalGroundSchmittInputInput,pull-upenabledExternalBoot—ThisinputistiedtoVDDtoforcethedevicetobootfromoff-chipmemory(assumingthattheon-chipFlashmemoryisnotinasecurestate).
Otherwise,itistiedtoground.
Fordetails,seeTable4-4.
Note:Whenthispinistiedlow,thecustomerbootsoftwareshoulddisabletheinternalpull-upresistorbysettingtheXBOOTbitoftheSIM_PUDR;seePart6.
5.
6.
Note:Thispinisinternallytiedlow(toVSS).
EMI_MODEInternalGroundSchmittInputInput,pull-upenabledExternalMemoryMode—ThisdevicewillbootfrominternalFlashmemoryundernormaloperation.
ThisfunctionisalsoaffectedbyEXTBOOTandtheFlashsecuritymode;seeTable4-4fordetails.
Note:Whenthispinistiedlow,thecustomerbootsoftwareshoulddisabletheinternalpull-upresistorbysettingtheEMI_MODEbitoftheSIM_PUDR;seePart6.
5.
6.
Note:Thispinisinternallytiedlow(toVSS).
Table2-2SignalandPackageInformationforthe128-PinLQFP(Continued)SignalNamePinNo.
TypeStateDuringResetSignalDescriptionIntroduction56F8335TechnicalData,Rev.
5FreescaleSemiconductor33PreliminaryPart3On-ChipClockSynthesis(OCCS)3.
1IntroductionRefertotheOCCSchapterofthe56F8300PeripheralUserManualforafulldescriptionoftheOCCS.
ThematerialcontainedhereidentifiesthespecificfeaturesoftheOCCSdesign.
Figure3-1showsthespecificOCCSblockdiagramtoreferenceintheOCCSchapterofthe56F8300PeripheralUserManual.
Figure3-1OCCSBlockDiagram3.
2ExternalClockOperationThesystemclockcanbederivedfromanexternalcrystal,ceramicresonator,oranexternalsystemclocksignal.
Togenerateareferencefrequencyusingtheinternaloscillator,areferencecrystalorceramicresonatormustbeconnectedbetweentheEXTALandXTALpins.
3.
2.
1CrystalOscillatorTheinternaloscillatorisdesignedtointerfacewithaparallel-resonantcrystalresonatorinthefrequencyrangespecifiedfortheexternalcrystalinTable10-15.
ArecommendedcrystaloscillatorcircuitisshowninFigure3-2.
Followthecrystalsupplier'srecommendationswhenselectingacrystal,sincecrystalparametersdeterminethecomponentvaluesrequiredtoprovidemaximumstabilityandreliablestart-up.
ThecrystalandassociatedcomponentsshouldbemountedasnearaspossibletotheEXTALandXTALMUXEXTALXTALFEEDBACKLCKPrescalerCLKPostscalerCLKFOUT/2CrystalOSCLossofReferenceClockDetectorLockDetectorZSRCBusInterface&ControlFOUTFREFPLLDBPLLCODPLLCIDBusInterfaceLossofReferenceClockInterruptSYS_CLK2SourcetoSIMMUXCLKMODE÷2Prescaler÷(1,2,4,8)Postscaler÷(1,2,4,8)MSTR_OSCPLLx(1to128)56F8335TechnicalData,Rev.
534FreescaleSemiconductorPreliminarypinstominimizeoutputdistortionandstart-upstabilizationtime.
Figure3-2ConnectingtoaCrystalOscillatorNote:TheOCCS_COHLbitmustbesetto1whenacrystaloscillatorisused.
TheresetconditionontheOCCS_COHLbitis0.
PleaseseetheCOHLbitintheOscillatorControl(OSCTL)register,discussedinthe56F8300PeripheralUser'sManual.
3.
2.
2CeramicResonator(Default)Itisalsopossibletodrivetheinternaloscillatorwithaceramicresonator,assumingtheoverallsystemdesigncantoleratethereducedsignalintegrity.
AtypicalceramicresonatorcircuitisshowninFigure3-3.
Refertothesupplier'srecommendationswhenselectingaceramicresonatorandassociatedcomponents.
TheresonatorandcomponentsshouldbemountedasnearaspossibletotheEXTALandXTALpins.
Figure3-3ConnectingaCeramicResonatorNote:TheOCCS_COHLbitmustbesetto0whenaceramicresonatorisused.
TheresetconditionontheOCCS_COHLbitis0.
PleaseseetheCOHLbitintheOscillatorControl(OSCTL)register,discussedinthe56F8300PeripheralUser'sManual.
3.
2.
3ExternalClockSourceTherecommendedmethodofconnectinganexternalclockisillustratedinFigure3-4.
TheexternalclocksourceisconnectedtoXTALandtheEXTALpinisgrounded.
SetOCCS_COHLbithighwhenusinganexternalclocksourceaswell.
SampleExternalCrystalParameters:Rz=750KΩNote:Iftheoperatingtemperaturerangeislimitedtobelow85oC(105oCjunction),thenRz=10MegΩCLKMODE=0CrystalFrequency=4-8MHz(optimizedfor8MHz)EXTALEXTALXTALXTALRZRZCL1CL2EXTALXTALRzSampleExternalCeramicResonatorParameters:Rz=750KΩEXTALXTALRzC1CL1CL2C2ResonatorFrequency=4-8MHz(optimizedfor8MHz)3Terminal2TerminalCLKMODE=0Registers56F8335TechnicalData,Rev.
5FreescaleSemiconductor35PreliminaryFigure3-4ConnectinganExternalClockSignalRegister3.
3RegistersWhenreferringtotheregisterdefinitionsfortheOCCSinthe56F8300PeripheralUserManual,usetheregisterdefinitionswithouttheinternalRelaxationOscillator,sincethe56F8335/56F8135devicesdoNOTcontainthisoscillator.
Part4MemoryMap4.
1IntroductionThe56F8335and56F8135devicesare16-bitmotor-controlchipsbasedonthe56800Ecore.
ThesepartsuseaHarvard-stylearchitecturewithtwoindependentmemoryspacesforDataandProgram.
On-chipRAMandFlashmemoriesareusedinbothspaces.
Thissectionprovidesmemorymapsfor:ProgramAddressSpace,includingtheInterruptVectorTableDataAddressSpace,includingtheEOnCEMemoryandPeripheralMemoryMapsOn-chipmemorysizesforeachdevicearesummarizedinTable4-1.
Flashmemories'restrictionsareidentifiedinthe"UseRestrictions"columnofTable4-1.
Note:DataFlashandProgramRAMareNOTavailableonthe56F8135device.
Table4-1ChipMemoryConfigurationsOn-ChipMemory56F833556F8135UseRestrictionsProgramFlash64KB64KBErase/ProgramviaFlashinterfaceunitandwordwritestoCDBWXTALEXTALExternalVSSClockNote:Whenusinganexternalclockingsourcewiththisconfiguration,theinput"CLKMODE"shouldbehighandCOHLbitintheOSCTLregistershouldbesetto1.
56F8335TechnicalData,Rev.
536FreescaleSemiconductorPreliminary4.
2ProgramMapTheProgrammemorymapislocatedinTable4-4.
Theoperatingmodecontrolbits(MAandMB)intheOperatingModeRegister(OMR)controltheProgrammemorymap.
Atreset,thesebitsaresetasindicatedinTable4-2.
EXT_BOOT=EMI_MODE=0andcannotbechangedinthe56F8335or56F8135.
Afterreset,theOMRMAbitcanbechangedandwillhaveaneffectontheP-spacememorymap,asshowninTable4-3.
ChangingtheOMRMBbitwillhavenoeffect.
DataFlash8KB—Erase/ProgramviaFlashinterfaceunitandwordwritestoCDBW.
DataFlashcanbereadviaeitherCDBRorXDB2,butnotbybothsimultaneouslyProgramRAM4KB—NoneDataRAM8KB8KBNoneProgramBootFlash8KB8KBErase/ProgramviaFlashInterfaceunitandwordwritestoCDBWTable4-2OMRMB/MAValueatReset11.
Informationinshadedareasnotapplicableto56F8335/56F8135.
OMRMB=FlashSecuredState2,32.
Thisbitisonlyconfiguredatreset.
IftheFlashsecuredstatechanges,thiswillnotbereflectedinMBuntilthenextreset.
3.
ChangingMBinsoftwarewillnotaffectFlashmemorysecurity.
OMRMA=EXTBOOTPinChipOperatingMode00Mode0–InternalBoot;EMIisconfiguredtouse16addresslines;FlashMemoryissecured;externalP-spaceisnotallowed;theEOnCEisdisabled01Notvalid;cannotbootexternallyiftheFlashissecuredandwillactuallyconfigureto00state10Mode0–InternalBoot;EMIisconfiguredtouse16addresslines11Mode1–ExternalBoot;FlashMemoryisnotsecured;EMIconfigurationisdeterminedbythestateoftheEMI_MODEpinTable4-3ChangingOMRMAValueDuringNormalOperationOMRMAChipOperatingMode0UseinternalP-spacememorymapconfiguration11UseexternalP-spacememorymapconfiguration–IfMB=0atreset,changingthisbithasnoeffect.
Table4-1ChipMemoryConfigurationsOn-ChipMemory56F833556F8135UseRestrictionsInterruptVectorTable56F8335TechnicalData,Rev.
5FreescaleSemiconductor37PreliminaryTable4-4showsthememorymapoptionsofthe56F8335/56F8135.
Thetworightcolumnscannotbeused,sincetheEMIpinsarenotprovidedinthepackage;therefore,onlytheMode0columnisrelevant.
Note:ProgramRAMisNOTavailableonthe56F8135device.
1.
CannotbeusedsinceMA=EXTBOOT=0andtheEMIisnotavailable;informationinshadedareasnotapplicableto56F8335/56F8135.
2.
Thismodeprovidesmaximumcompatibilitywith56F80xpartswhileoperatingexternally.
3.
"EMI_MODE=0",EMI_MODEpinistiedtogroundatbootup.
4.
"EMI_MODE=1",EMI_MODEpinistiedtoVDDatbootup.
5.
Notaccessibleinthispart,sincetheEMIisnotfullypinnedoutinthispackage;informationinshadedareasnotapplicableto56F8335/56F8135.
4.
3InterruptVectorTableTable4-5providestheresetandinterruptprioritystructure,includingon-chipperipherals.
Thetableisorganizedwithhigher-priorityvectorsatthetopandlower-priorityinterruptslowerinthetable.
Thepriorityofaninterruptcanbeassignedtodifferentlevels,asindicated,allowingsomecontrolover1.
Settingthisbitcancauseunpredictableresultsandisnotrecommended,sincetheEMIisnotfunctionalinthispackage.
Table4-4ProgramMemoryMapatResetBegin/EndAddressMode0(MA=0)Mode11(MA=1)InternalBootExternalBootInternalBoot16-BitExternalAddressBusEMI_MODE=02,316-BitExternalAddressBusEMI_MODE=1420-BitExternalAddressBusP:$1FFFFFP:$100000ExternalProgramMemory5ExternalProgramMemory5ExternalProgramMemory5P:$0FFFFFP:$030000ExternalProgramRAM5COPResetAddress=020002BootLocation=020000P:$02FFFFP:$02F800On-ChipProgramRAM4KBOn-ChipProgramRAM4KBP:$02F7FFP:$021000Reserved116KBP:$020FFFP:$020000BootFlash8KBCOPResetAddress=020002BootLocation=020000BootFlash8KB(NotUsedforBootinthisMode)P:$01FFFFP:$018000ExternalProgramRAM5Reserved64KBP:$017FFFP:$010000InternalProgramFlash64KBP:$00FFFFP:$008000Reserved64KBExternalProgramRAM5COPResetAddress=000002BootLocation=000000P:$007FFFP:$000000InternalProgramFlash64KB56F8335TechnicalData,Rev.
538FreescaleSemiconductorPreliminaryinterruptpriorities.
Alllevel3interruptswillbeservicedbeforelevel2,andsoon.
Foraselectedprioritylevel,thelowestvectornumberhasthehighestpriority.
ThelocationofthevectortableisdeterminedbytheVectorBaseAddress(VBA)register.
PleaseseePart5.
6.
11fortheresetvalueoftheVBA.
Insomeconfigurations,theresetaddressandCOPresetaddresswillcorrespondtovector0and1oftheinterruptvectortable.
Intheseinstances,thefirsttwolocationsinthevectortablemustcontainbranchorJMPinstructions.
AllotherentriesmustcontainJSRinstructions.
Note:PWMA,FlexCAN,QuadratureDecoder1,andQuadTimersBandDareNOTavailableonthe56F8135device.
Table4-5InterruptVectorTableContents1PeripheralVectorNumberPriorityLevelVectorBaseAddress+InterruptFunctionReservedforResetOverlay2ReservedforCOPResetOverlay2core23P:$04IllegalInstructioncore33P:$06SWInterrupt3core43P:$08HWStackOverflowcore53P:$0AMisalignedLongWordAccesscore61-3P:$0COnCEStepCountercore71-3P:$0EOnCEBreakpointUnit0Reservedcore91-3P:$12OnCETraceBuffercore101-3P:$14OnCETransmitRegisterEmptycore111-3P:$16OnCEReceiveRegisterFullReservedcore142P:$1CSWInterrupt2core151P:$1ESWInterrupt1core160P:$20SWInterrupt0core170-2P:$22IRQAcore180-2P:$24IRQBReservedLVI200-2P:$28LowVoltageDetector(powersense)PLL210-2P:$2APLLFM220-2P:$2CFMAccessErrorInterruptFM230-2P:$2EFMCommandCompleteInterruptVectorTable56F8335TechnicalData,Rev.
5FreescaleSemiconductor39PreliminaryFM240-2P:$30FMCommand,dataandaddressBuffersEmptyReservedFLEXCAN260-2P:$34FLEXCANBusOffFLEXCAN270-2P:$36FLEXCANErrorFLEXCAN280-2P:$38FLEXCANWakeUpFLEXCAN290-2P:$3AFLEXCANMessageBufferInterruptGPIOF300-2P:$3CGPIOFGPIOE310-2P:$3EGPIOEGPIOD320-2P:$40GPIODGPIOC330-2P:$42GPIOCGPIOB340-2P:$44GPIOBGPIOA350-2P:$46GPIOAReservedSPI1380-2P:$4CSPI1ReceiverFullSPI1390-2P:$4ESPI1TransmitterEmptySPI0400-2P:$50SPI0ReceiverFullSPI0410-2P:$52SPI0TransmitterEmptySCI1420-2P:$54SCI1TransmitterEmptySCI1430-2P:$56SCI1TransmitterIdleReservedSCI1450-2P:$5ASCI1ReceiverErrorSCI1460-2P:$5CSCI1ReceiverFullTable4-5InterruptVectorTableContents1(Continued)PeripheralVectorNumberPriorityLevelVectorBaseAddress+InterruptFunction56F8335TechnicalData,Rev.
540FreescaleSemiconductorPreliminaryDEC1470-2P:$5EQuadratureDecoder#1HomeSwitchorWatchdogDEC1480-2P:$60QuadratureDecoder#1INDEXPulseDEC0490-2P:$62QuadratureDecoder#0HomeSwitchorWatchdogDEC0500-2P:$64QuadratureDecoder#0INDEXPulseReservedTMRD520-2P:$68TimerD,Channel0TMRD530-2P:$6ATimerD,Channel1TMRD540-2P:$6CTimerD,Channel2TMRD550-2P:$6ETimerD,Channel3TMRC560-2P:$70TimerC,Channel0TMRC570-2P:$72TimerC,Channel1TMRC580-2P:$74TimerC,Channel2TMRC590-2P:$76TimerC,Channel3TMRB600-2P:$78TimerB,Channel0TMRB610-2P:$7ATimerB,Channel1TMRB620-2P:$7CTimerB,Channel2TMRB630-2P:$7ETimerB,Channel3TMRA640-2P:$80TimerA,Channel0TMRA650-2P:$82TimerA,Channel1TMRA660-2P:$84TimerA,Channel2TMRA670-2P:$86TimerA,Channel3SCI0680-2P:$88SCI0TransmitterEmptySCI0690-2P:$8ASCI0TransmitterIdleReservedSCI0710-2P:$8ESCI0ReceiverErrorSCI0720-2P:$90SCI0ReceiverFullADCB730-2P:$92ADCBConversionCompete/EndofScanADCA740-2P:$94ADCAConversionComplete/EndofScanADCB750-2P:$96ADCBZeroCrossingorLimitErrorADCA760-2P:$98ADCAZeroCrossingorLimitErrorPWMB770-2P:$9AReloadPWMBPWMA780-2P:$9CReloadPWMAPWMB790-2P:$9EPWMBFaultTable4-5InterruptVectorTableContents1(Continued)PeripheralVectorNumberPriorityLevelVectorBaseAddress+InterruptFunctionDataMap56F8335TechnicalData,Rev.
5FreescaleSemiconductor41Preliminary4.
4DataMapNote:DataFlashisNOTavailableonthe56F8135device.
PWMA800-2P:$A0PWMAFaultcore81-1P:$A2SWInterruptLP1.
Twowordsareallocatedforeachentryinthevectortable.
Thisdoesnotallowthefulladdressrangetobereferencedfromthevectortable,providingonly19bitsofaddress.
2.
IftheVBAissetto$0200(orVBA=0000forMode1,EMI_MODE=0),thefirsttwolocationsofthevectortablearethechipresetaddresses;therefore,theselocationsarenotinterruptvectors.
Table4-6DataMemoryMap1,21.
Informationinshadedareasnotapplicableto56F8335/56F8135.
2.
Alladdressesare16-bitWordaddresses,notbyteaddresses.
Begin/EndAddressEX=033.
IntheOperationModeRegister.
EX=144.
SettingEX=1isnotrecommendedinthe56F8335/56F8135,sincetheEMIisnotfunctionalinthispackage.
X:$FFFFFFX:$FFFF00EOnCE256locationsallocatedEOnCE256locationsallocatedX:$FFFEFFX:$010000ExternalMemoryExternalMemoryX:$00FFFFX:$00F000On-ChipPeripherals4096locationsallocatedOn-ChipPeripherals4096locationsallocatedX:$00EFFFX:$002000ExternalMemoryExternalMemoryX:$001FFFX:$001000On-ChipDataFlash8KBX:$000FFFX:$000000On-ChipDataRAM8KB55.
TheDataRAMisorganizedasa2Kx32-bitmemorytoallowsingle-cycle,long-wordoperations.
Table4-5InterruptVectorTableContents1(Continued)PeripheralVectorNumberPriorityLevelVectorBaseAddress+InterruptFunction56F8335TechnicalData,Rev.
542FreescaleSemiconductorPreliminary4.
5FlashMemoryMapFigure4-1illustratestheFlashMemory(FM)maponthesystembus.
TheFlashMemoryisdividedintothreefunctionalblocks.
TheProgramandbootmemoriesresideontheProgramMemorybuses.
Theyarecontrolledbyonesetofbankedregisters.
DataMemoryFlashresidesontheDataMemorybusesandiscontrolledseparatelybyitsownsetofbankedregisters.
ThetopninewordsoftheProgramMemoryFlasharetreatedasspecialmemorylocations.
ThecontentofthesewordsisusedtocontroltheoperationoftheFlashController.
BecausethesewordsarepartoftheFlashMemorycontent,theirstateismaintainedduringpower-downandreset.
Duringchipinitialization,thecontentofthesememorylocationsisloadedintoFlashMemorycontrolregisters,detailedintheFlashMemorychapterofthe56F8300PeripheralUserManual.
Theseconfigurationparametersarelocatedbetween$00_FFF7and$00_FFFF.
Figure4-1FlashArrayMemoryMapsTable4-7showsthepageandsectorsizesusedwithineachFlashmemoryblockonthechip.
Note:DataFlashisNOTavailableonthe56F8135device.
Table4-7.
FlashMemoryPartitionsFlashSizeSectorsSectorSizePageSizeProgramFlash64KB162Kx16bits512x16bitsBOOT_FLASH_START=$02_0000BOOT_FLASH_START+$1FFFBlock0OddBlock0EvenPROG_FLASH_START+$00_FFFF.
.
.
8KBBootReservedConfigureFieldPROG_FLASH_START+$00_FFF7PROG_FLASH_START+$00_FFF664KBPROG_FLASH_START=$00_0000FM_PROG_MEM_TOP=$00_FFFFBLOCK0Odd(2Bytes)$00_0003BLOCK0Even(2Bytes)$00_0002BLOCK0Odd(2Bytes)$00_0001BLOCK0Even(2Bytes)$00_0000FM_BASE+$14BankedRegistersUnbankedRegisters8KBFM_BASE+$00DATA_FLASH_START+$0FFFDATA_FLASH_START+$0000DataMemoryProgramMemoryNote:DataFlashisNOTavailableinthe56F8135device.
EOnCEMemoryMap56F8335TechnicalData,Rev.
5FreescaleSemiconductor43PreliminaryPleaseseethe56F8300PeripheralUserManualforadditionalFlashinformation.
4.
6EOnCEMemoryMapDataFlashDataFlash8KB16256x16bits256x16bitsBootFlash8KB41Kx16bits256x16bitsTable4-8EOnCEMemoryMapAddressRegisterAcronymRegisterNameReservedX:$FFFF8AOESCRExternalSignalControlRegisterReservedX:$FFFF8EOBCNTRBreakpointUnit[0]CounterReservedX:$FFFF90OBMSK(32bits)Breakpoint1Unit[0]MaskRegisterX:$FFFF91—Breakpoint1Unit[0]MaskRegisterX:$FFFF92OBAR2(32bits)Breakpoint2Unit[0]AddressRegisterX:$FFFF93—Breakpoint2Unit[0]AddressRegisterX:$FFFF94OBAR1(24bits)Breakpoint1Unit[0]AddressRegisterX:$FFFF95—Breakpoint1Unit[0]AddressRegisterX:$FFFF96OBCR(24bits)BreakpointUnit[0]ControlRegisterX:$FFFF97—BreakpointUnit[0]ControlRegisterX:$FFFF98OTB(21-24bits/stage)TraceBufferRegisterStagesX:$FFFF99—TraceBufferRegisterStagesX:$FFFF9AOTBPR(8bits)TraceBufferPointerRegisterX:$FFFF9BOTBCRTraceBufferControlRegisterX:$FFFF9COBASE(8bits)PeripheralBaseAddressRegisterX:$FFFF9DOSRStatusRegisterX:$FFFF9EOSCNTR(24bits)InstructionStepCounterX:$FFFF9F—InstructionStepCounterX:$FFFFA0OCR(bits)ControlRegisterReservedX:$FFFFFCOCLSR(8bits)CoreLock/UnlockStatusRegisterX:$FFFFFDOTXRXSR(8bits)TransmitandReceiveStatusandControlRegisterTable4-7.
FlashMemoryPartitionsFlashSizeSectorsSectorSizePageSize56F8335TechnicalData,Rev.
544FreescaleSemiconductorPreliminary4.
7PeripheralMemoryMappedRegistersOn-chipperipheralregistersarepartofthedatamemorymaponthe56800Eseries.
TheselocationsmaybeaccessedwiththesameaddressingmodesusedforordinaryDatamemory,exceptallperipheralregistersshouldberead/writtenusingwordaccessesonly.
Table4-9summarizesbaseaddressesforthesetofperipheralsonthe56F8335and56F8135devices.
Peripheralsarelistedinorderofthebaseaddress.
Thefollowingtableslistalloftheperipheralregistersrequiredtocontroloraccesstheperipherals.
Note:FeaturesinitalicsareNOTavailableinthe56F8135device.
X:$FFFFFEOTX/ORX(32bits)TransmitRegister/ReceiveRegisterX:$FFFFFFOTX1/ORX1TransmitRegisterUpperWordReceiveRegisterUpperWordTable4-9DataMemoryPeripheralBaseAddressMapSummaryPeripheralPrefixBaseAddressTableNumberExternalMemoryInterfaceEMIX:$00F0204-10TimerATMRAX:$00F0404-11TimerBTMRBX:$00F0804-12TimerCTMRCX:$00F0C04-13TimerDTMRDX:$00F1004-14PWMAPWMAX:$00F1404-15PWMBPWMBX:$00F1604-16QuadratureDecoder0DEC0X:$00F1804-17QuadratureDecoder1DEC1X:$00F1904-18ITCNITCNX:$00F1A04-19ADCAADCAX:$00F2004-20ADCBADCBX:$00F2404-21TemperatureSensorTSENSORX:$00F2704-22SCI#0SCI0X:$00F2804-23SCI#1SCI1X:$00F2904-24SPI#0SPI0X:$00F2A04-25SPI#1SPI1X:$00F2B04-26COPCOPX:$00F2C04-27PLL,OSCCLKGENX:$00F2D04-28GPIOPortAGPIOAX:$00F2E04-29GPIOPortBGPIOBX:$00F3004-30Table4-8EOnCEMemoryMap(Continued)AddressRegisterAcronymRegisterNamePeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor45PreliminaryGPIOPortCGPIOCX:$00F3104-31GPIOPortDGPIODX:$00F3204-32GPIOPortEGPIOEX:$00F3304-33GPIOPortFGPIOFX:$00F3404-34SIMSIMX:$00F3504-35PowerSupervisorLVIX:$00F3604-36FMFMX:$00F4004-37FlexCANFCX:$00F8004-38Table4-9DataMemoryPeripheralBaseAddressMapSummary(Continued)PeripheralPrefixBaseAddressTableNumber56F8335TechnicalData,Rev.
546FreescaleSemiconductorPreliminaryTable4-10ExternalMemoryIntegrationRegistersAddressMap(EMI_BASE=$00F020)RegisterAcronymAddressOffsetRegisterDescriptionResetValuesCSBAR0$0ChipSelectBaseAddressRegister00x0004=64KsinceEXTBOOT=EMI_MODE=0Thistableaddedtoprovidecompleteinformation,butthisperipheralisnotfunctionalinthe56F8335/56F8135packageCSBAR1$1ChipSelectBaseAddressRegister10x0004=64KsinceEMI_MODE=0CSBAR2$2ChipSelectBaseAddressRegister2CSBAR3$3ChipSelectBaseAddressRegister3CSBAR4$4ChipSelectBaseAddressRegister4CSBAR5$5ChipSelectBaseAddressRegister5CSBAR6$6ChipSelectBaseAddressRegister6CSBAR7$7ChipSelectBaseAddressRegister7CSOR0$8ChipSelectOptionRegister0CSOR1$9ChipSelectOptionRegister1CSOR2$AChipSelectOptionRegister2CSOR3$BChipSelectOptionRegister3CSOR4$CChipSelectOptionRegister4CSOR5$DChipSelectOptionRegister5CSOR6$EChipSelectOptionRegister6CSOR7$FChipSelectOptionRegister7CSTC0$10ChipSelectTimingControlRegister0CSTC1$11ChipSelectTimingControlRegister1CSTC2$12ChipSelectTimingControlRegister2CSTC3$13ChipSelectTimingControlRegister3CSTC4$14ChipSelectTimingControlRegister4CSTC5$15ChipSelectTimingControlRegister5CSTC6$16ChipSelectTimingControlRegister6CSTC7$17ChipSelectTimingControlRegister7BCR$18BusControlRegisterTable4-11QuadTimerARegistersAddressMap(TMRA_BASE=$00F040)RegisterAcronymAddressOffsetRegisterDescriptionTMRA0_CMP1$0CompareRegister1TMRA0_CMP2$1CompareRegister2TMRA0_CAP$2CaptureRegisterTMRA0_LOAD$3LoadRegisterTMRA0_HOLD$4HoldRegisterPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor47PreliminaryTMRA0_CNTR$5CounterRegisterTMRA0_CTRL$6ControlRegisterTMRA0_SCR$7StatusandControlRegisterTMRA0_CMPLD1$8ComparatorLoadRegister1TMRA0_CMPLD2$9ComparatorLoadRegister2TMRA0_COMSCR$AComparatorStatusandControlRegisterReservedTMRA1_CMP1$10CompareRegister1TMRA1_CMP2$11CompareRegister2TMRA1_CAP$12CaptureRegisterTMRA1_LOAD$13LoadRegisterTMRA1_HOLD$14HoldRegisterTMRA1_CNTR$15CounterRegisterTMRA1_CTRL$16ControlRegisterTMRA1_SCR$17StatusandControlRegisterTMRA1_CMPLD1$18ComparatorLoadRegister1TMRA1_CMPLD2$19ComparatorLoadRegister2TMRA1_COMSCR$1AComparatorStatusandControlRegisterReservedTMRA2_CMP1$20CompareRegister1TMRA2_CMP2$21CompareRegister2TMRA2_CAP$22CaptureRegisterTMRA2_LOAD$23LoadRegisterTMRA2_HOLD$24HoldRegisterTMRA2_CNTR$25CounterRegisterTMRA2_CTRL$26ControlRegisterTMRA2_SCR$27StatusandControlRegisterTMRA2_CMPLD1$28ComparatorLoadRegister1TMRA2_CMPLD2$29ComparatorLoadRegister2TMRA2_COMSCR$2AComparatorStatusandControlRegisterReservedTable4-11QuadTimerARegistersAddressMap(Continued)(TMRA_BASE=$00F040)RegisterAcronymAddressOffsetRegisterDescription56F8335TechnicalData,Rev.
548FreescaleSemiconductorPreliminaryTMRA3_CMP1$30CompareRegister1TMRA3_CMP2$31CompareRegister2TMRA3_CAP$32CaptureRegisterTMRA3_LOAD$33LoadRegisterTMRA3_HOLD$34HoldRegisterTMRA3_CNTR$35CounterRegisterTMRA3_CTRL$36ControlRegisterTMRA3_SCR$37StatusandControlRegisterTMRA3_CMPLD1$38ComparatorLoadRegister1TMRA3_CMPLD2$39ComparatorLoadRegister2TMRA3_COMSCR$3AComparatorStatusandControlRegisterTable4-12QuadTimerBRegistersAddressMap(TMRB_BASE=$00F080)QuadTimerBisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionTMRB0_CMP1$0CompareRegister1TMRB0_CMP2$1CompareRegister2TMRB0_CAP$2CaptureRegisterTMRB0_LOAD$3LoadRegisterTMRB0_HOLD$4HoldRegisterTMRB0_CNTR$5CounterRegisterTMRB0_CTRL$6ControlRegisterTMRB0_SCR$7StatusandControlRegisterTMRB0_CMPLD1$8ComparatorLoadRegister1TMRB0_CMPLD2$9ComparatorLoadRegister2TMRB0_COMSCR$AComparatorStatusandControlRegisterReservedTMRB1_CMP1$10CompareRegister1TMRB1_CMP2$11CompareRegister2TMRB1_CAP$12CaptureRegisterTMRB1_LOAD$13LoadRegisterTMRB1_HOLD$14HoldRegisterTMRB1_CNTR$15CounterRegisterTable4-11QuadTimerARegistersAddressMap(Continued)(TMRA_BASE=$00F040)RegisterAcronymAddressOffsetRegisterDescriptionPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor49PreliminaryTMRB1_CTRL$16ControlRegisterTMRB1_SCR$17StatusandControlRegisterTMRB1_CMPLD1$18ComparatorLoadRegister1TMRB1_CMPLD2$19ComparatorLoadRegister2TMRB1_COMSCR$1AComparatorStatusandControlRegisterReservedTMRB2_CMP1$20CompareRegister1TMRB2_CMP2$21CompareRegister2TMRB2_CAP$22CaptureRegisterTMRB2_LOAD$23LoadRegisterTMRB2_HOLD$24HoldRegisterTMRB2_CNTR$25CounterRegisterTMRB2_CTRL$26ControlRegisterTMRB2_SCR$27StatusandControlRegisterTMRB2_CMPLD1$28ComparatorLoadRegister1TMRB2_CMPLD2$29ComparatorLoadRegister2TMRB2_COMSCR$2AComparatorStatusandControlRegisterReservedTMRB3_CMP1$30CompareRegister1TMRB3_CMP2$31CompareRegister2TMRB3_CAP$32CaptureRegisterTMRB3_LOAD$33LoadRegisterTMRB3_HOLD$34HoldRegisterTMRB3_CNTR$35CounterRegisterTMRB3_CTRL$36ControlRegisterTMRB3_SCR$37StatusandControlRegisterTMRB3_CMPLD1$38ComparatorLoadRegister1TMRB3_CMPLD2$39ComparatorLoadRegister2TMRB3_COMSCR$3AComparatorStatusandControlRegisterTable4-12QuadTimerBRegistersAddressMap(Continued)(TMRB_BASE=$00F080)QuadTimerBisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescription56F8335TechnicalData,Rev.
550FreescaleSemiconductorPreliminaryTable4-13QuadTimerCRegistersAddressMap(TMRC_BASE=$00F0C0)RegisterAcronymAddressOffsetRegisterDescriptionTMRC0_CMP1$0CompareRegister1TMRC0_CMP2$1CompareRegister2TMRC0_CAP$2CaptureRegisterTMRC0_LOAD$3LoadRegisterTMRC0_HOLD$4HoldRegisterTMRC0_CNTR$5CounterRegisterTMRC0_CTRL$6ControlRegisterTMRC0_SCR$7StatusandControlRegisterTMRC0_CMPLD1$8ComparatorLoadRegister1TMRC0_CMPLD2$9ComparatorLoadRegister2TMRC0_COMSCR$AComparatorStatusandControlRegisterReservedTMRC1_CMP1$10CompareRegister1TMRC1_CMP2$11CompareRegister2TMRC1_CAP$12CaptureRegisterTMRC1_LOAD$13LoadRegisterTMRC1_HOLD$14HoldRegisterTMRC1_CNTR$15CounterRegisterTMRC1_CTRL$16ControlRegisterTMRC1_SCR$17StatusandControlRegisterTMRC1_CMPLD1$18ComparatorLoadRegister1TMRC1_CMPLD2$19ComparatorLoadRegister2TMRC1_COMSCR$1AComparatorStatusandControlRegisterReservedTMRC2_CMP1$20CompareRegister1TMRC2_CMP2$21CompareRegister2TMRC2_CAP$22CaptureRegisterTMRC2_LOAD$23LoadRegisterTMRC2_HOLD$24HoldRegisterTMRC2_CNTR$25CounterRegisterTMRC2_CTRL$26ControlRegisterTMRC2_SCR$27StatusandControlRegisterTMRC2_CMPLD1$28ComparatorLoadRegister1PeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor51PreliminaryTMRC2_CMPLD2$29ComparatorLoadRegister2TMRC2_COMSCR$2AComparatorStatusandControlRegisterReservedTMRC3_CMP1$30CompareRegister1TMRC3_CMP2$31CompareRegister2TMRC3_CAP$32CaptureRegisterTMRC3_LOAD$33LoadRegisterTMRC3_HOLD$34HoldRegisterTMRC3_CNTR$35CounterRegisterTMRC3_CTRL$36ControlRegisterTMRC3_SCR$37StatusandControlRegisterTMRC3_CMPLD1$38ComparatorLoadRegister1TMRC3_CMPLD2$39ComparatorLoadRegister2TMRC3_COMSCR$3AComparatorStatusandControlRegisterTable4-14QuadTimerDRegistersAddressMap(TMRD_BASE=$00F100)QuadTimerDisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionTMRD0_CMP1$0CompareRegister1TMRD0_CMP2$1CompareRegister2TMRD0_CAP$2CaptureRegisterTMRD0_LOAD$3LoadRegisterTMRD0_HOLD$4HoldRegisterTMRD0_CNTR$5CounterRegisterTMRD0_CTRL$6ControlRegisterTMRD0_SCR$7StatusandControlRegisterTMRD0_CMPLD1$8ComparatorLoadRegister1TMRD0_CMPLD2$9ComparatorLoadRegister2TMRD0_COMSCR$AComparatorStatusandControlRegisterReservedTMRD1_CMP1$10CompareRegister1TMRD1_CMP2$11CompareRegister2Table4-13QuadTimerCRegistersAddressMap(Continued)(TMRC_BASE=$00F0C0)RegisterAcronymAddressOffsetRegisterDescription56F8335TechnicalData,Rev.
552FreescaleSemiconductorPreliminaryTMRD1_CAP$12CaptureRegisterTMRD1_LOAD$13LoadRegisterTMRD1_HOLD$14HoldRegisterTMRD1_CNTR$15CounterRegisterTMRD1_CTRL$16ControlRegisterTMRD1_SCR$17StatusandControlRegisterTMRD1_CMPLD1$18ComparatorLoadRegister1TMRD1_CMPLD2$19ComparatorLoadRegister2TMRD1_COMSCR$1AComparatorStatusandControlRegisterReservedTMRD2_CMP1$20CompareRegister1TMRD2_CMP2$21CompareRegister2TMRD2_CAP$22CaptureRegisterTMRD2_LOAD$23LoadRegisterTMRD2_HOLD$24HoldRegisterTMRD2_CNTR$25CounterRegisterTMRD2_CTRL$26ControlRegisterTMRD2_SCR$27StatusandControlRegisterTMRD2_CMPLD1$28ComparatorLoadRegister1TMRD2_CMPLD2$29ComparatorLoadRegister2TMRD2_COMSCR$2AComparatorStatusandControlRegisterReservedTMRD3_CMP1$30CompareRegister1TMRD3_CMP2$31CompareRegister2TMRD3_CAP$32CaptureRegisterTMRD3_LOAD$33LoadRegisterTMRD3_HOLD$34HoldRegisterTMRD3_CNTR$35CounterRegisterTMRD3_CTRL$36ControlRegisterTMRD3_SCR$37StatusandControlRegisterTMRD3_CMPLD1$38ComparatorLoadRegister1TMRD3_CMPLD2$39ComparatorLoadRegister2TMRD3_COMSCR$3AComparatorStatusandControlRegisterTable4-14QuadTimerDRegistersAddressMap(Continued)(TMRD_BASE=$00F100)QuadTimerDisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor53PreliminaryTable4-15PulseWidthModulatorARegistersAddressMap(PWMA_BASE=$00F140)PWMAisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionPWMA_PMCTL$0ControlRegisterPWMA_PMFCTL$1FaultControlRegisterPWMA_PMFSA$2FaultStatusAcknowledgeRegisterPWMA_PMOUT$3OutputControlRegisterPWMA_PMCNT$4CounterRegisterPWMA_PWMCM$5CounterModuloRegisterPWMA_PWMVAL0$6ValueRegister0PWMA_PWMVAL1$7ValueRegister1PWMA_PWMVAL2$8ValueRegister2PWMA_PWMVAL3$9ValueRegister3PWMA_PWMVAL4$AValueRegister4PWMA_PWMVAL5$BValueRegister5PWMA_PMDEADTM$CDeadTimeRegisterPWMA_PMDISMAP1$DDisableMappingRegister1PWMA_PMDISMAP2$EDisableMappingRegister2PWMA_PMCFG$FConfigureRegisterPWMA_PMCCR$10ChannelControlRegisterPWMA_PMPORT$11PortRegisterPWMA_PMICCR$12PWMInternalCorrectionControlRegisterTable4-16PulseWidthModulatorBRegistersAddressMap(PWMB_BASE=$00F160)RegisterAcronymAddressOffsetRegisterDescriptionPWMB_PMCTL$0ControlRegisterPWMB_PMFCTL$1FaultControlRegisterPWMB_PMFSA$2FaultStatusAcknowledgeRegisterPWMB_PMOUT$3OutputControlRegisterPWMB_PMCNT$4CounterRegisterPWMB_PWMCM$5CounterModuloRegisterPWMB_PWMVAL0$6ValueRegister0PWMB_PWMVAL1$7ValueRegister156F8335TechnicalData,Rev.
554FreescaleSemiconductorPreliminaryPWMB_PWMVAL2$8ValueRegister2PWMB_PWMVAL3$9ValueRegister3PWMB_PWMVAL4$AValueRegister4PWMB_PWMVAL5$BValueRegister5PWMB_PMDEADTM$CDeadTimeRegisterPWMB_PMDISMAP1$DDisableMappingRegister1PWMB_PMDISMAP2$EDisableMappingRegister2PWMB_PMCFG$FConfigureRegisterPWMB_PMCCR$10ChannelControlRegisterPWMB_PMPORT$11PortRegisterPWMB_PMICCR$12PWMInternalCorrectionControlRegisterTable4-17QuadratureDecoder0RegistersAddressMap(DEC0_BASE=$00F180)RegisterAcronymAddressOffsetRegisterDescriptionDEC0_DECCR$0DecoderControlRegisterDEC0_FIR$1FilterIntervalRegisterDEC0_WTR$2WatchdogTime-outRegisterDEC0_POSD$3PositionDifferenceCounterRegisterDEC0_POSDH$4PositionDifferenceCounterHoldRegisterDEC0_REV$5RevolutionCounterRegisterDEC0_REVH$6RevolutionHoldRegisterDEC0_UPOS$7UpperPositionCounterRegisterDEC0_LPOS$8LowerPositionCounterRegisterDEC0_UPOSH$9UpperPositionHoldRegisterDEC0_LPOSH$ALowerPositionHoldRegisterDEC0_UIR$BUpperInitializationRegisterDEC0_LIR$CLowerInitializationRegisterDEC0_IMR$DInputMonitorRegisterTable4-16PulseWidthModulatorBRegistersAddressMap(Continued)(PWMB_BASE=$00F160)RegisterAcronymAddressOffsetRegisterDescriptionPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor55PreliminaryTable4-18QuadratureDecoder1RegistersAddressMap(DEC1_BASE=$00F190)QuadratureDecoder1isNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionDEC1_DECCR$0DecoderControlRegisterDEC1_FIR$1FilterIntervalRegisterDEC1_WTR$2WatchdogTime-outRegisterDEC1_POSD$3PositionDifferenceCounterRegisterDEC1_POSDH$4PositionDifferenceCounterHoldRegisterDEC1_REV$5RevolutionCounterRegisterDEC1_REVH$6RevolutionHoldRegisterDEC1_UPOS$7UpperPositionCounterRegisterDEC1_LPOS$8LowerPositionCounterRegisterDEC1_UPOSH$9UpperPositionHoldRegisterDEC1_LPOSH$ALowerPositionHoldRegisterDEC1_UIR$BUpperInitializationRegisterDEC1_LIR$CLowerInitializationRegisterDEC1_IMR$DInputMonitorRegisterTable4-19InterruptControlRegistersAddressMap(ITCN_BASE=$00F1A0)RegisterAcronymAddressOffsetRegisterDescriptionIPR0$0InterruptPriorityRegister0IPR1$1InterruptPriorityRegister1IPR2$2InterruptPriorityRegister2IPR3$3InterruptPriorityRegister3IPR4$4InterruptPriorityRegister4IPR5$5InterruptPriorityRegister5IPR6$6InterruptPriorityRegister6IPR7$7InterruptPriorityRegister7IPR8$8InterruptPriorityRegister8IPR9$9InterruptPriorityRegister956F8335TechnicalData,Rev.
556FreescaleSemiconductorPreliminaryVBA$AVectorBaseAddressRegisterFIM0$BFastInterruptMatchRegister0FIVAL0$CFastInterruptVectorAddressLow0RegisterFIVAH0$DFastInterruptVectorAddressHigh0RegisterFIM1$EFastInterruptMatchRegister1FIVAL1$FFastInterruptVectorAddressLow1RegisterFIVAH1$10FastInterruptVectorAddressHigh1RegisterIRQP0$11IRQPendingRegister0IRQP1$12IRQPendingRegister1IRQP2$13IRQPendingRegister2IRQP3$14IRQPendingRegister3IRQP4$15IRQPendingRegister4IRQP5$16IRQPendingRegister5ReservedICTL$1DInterruptControlRegisterTable4-20Analog-to-DigitalConverterRegistersAddressMap(ADCA_BASE=$00F200)RegisterAcronymAddressOffsetRegisterDescriptionADCA_CR1$0ControlRegister1ADCA_CR2$1ControlRegister2ADCA_ZCC$2ZeroCrossingControlRegisterADCA_LST1$3ChannelListRegister1ADCA_LST2$4ChannelListRegister2ADCA_SDIS$5SampleDisableRegisterADCA_STAT$6StatusRegisterADCA_LSTAT$7LimitStatusRegisterADCA_ZCSTAT$8ZeroCrossingStatusRegisterADCA_RSLT0$9ResultRegister0ADCA_RSLT1$AResultRegister1ADCA_RSLT2$BResultRegister2ADCA_RSLT3$CResultRegister3ADCA_RSLT4$DResultRegister4Table4-19InterruptControlRegistersAddressMap(Continued)(ITCN_BASE=$00F1A0)RegisterAcronymAddressOffsetRegisterDescriptionPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor57PreliminaryADCA_RSLT5$EResultRegister5ADCA_RSLT6$FResultRegister6ADCA_RSLT7$10ResultRegister7ADCA_LLMT0$11LowLimitRegister0ADCA_LLMT1$12LowLimitRegister1ADCA_LLMT2$13LowLimitRegister2ADCA_LLMT3$14LowLimitRegister3ADCA_LLMT4$15LowLimitRegister4ADCA_LLMT5$16LowLimitRegister5ADCA_LLMT6$17LowLimitRegister6ADCA_LLMT7$18LowLimitRegister7ADCA_HLMT0$19HighLimitRegister0ADCA_HLMT1$1AHighLimitRegister1ADCA_HLMT2$1BHighLimitRegister2ADCA_HLMT3$1CHighLimitRegister3ADCA_HLMT4$1DHighLimitRegister4ADCA_HLMT5$1EHighLimitRegister5ADCA_HLMT6$1FHighLimitRegister6ADCA_HLMT7$20HighLimitRegister7ADCA_OFS0$21OffsetRegister0ADCA_OFS1$22OffsetRegister1ADCA_OFS2$23OffsetRegister2ADCA_OFS3$24OffsetRegister3ADCA_OFS4$25OffsetRegister4ADCA_OFS5$26OffsetRegister5ADCA_OFS6$27OffsetRegister6ADCA_OFS7$28OffsetRegister7Table4-20Analog-to-DigitalConverterRegistersAddressMap(Continued)(ADCA_BASE=$00F200)RegisterAcronymAddressOffsetRegisterDescription56F8335TechnicalData,Rev.
558FreescaleSemiconductorPreliminaryADCA_POWER$29PowerControlRegisterADCA_CAL$2AADCCalibrationRegisterTable4-21Analog-to-DigitalConverterRegistersAddressMap(ADCB_BASE=$00F240)RegisterAcronymAddressOffsetRegisterDescriptionADCB_CR1$0ControlRegister1ADCB_CR2$1ControlRegister2ADCB_ZCC$2ZeroCrossingControlRegisterADCB_LST1$3ChannelListRegister1ADCB_LST2$4ChannelListRegister2ADCB_SDIS$5SampleDisableRegisterADCB_STAT$6StatusRegisterADCB_LSTAT$7LimitStatusRegisterADCB_ZCSTAT$8ZeroCrossingStatusRegisterADCB_RSLT0$9ResultRegister0ADCB_RSLT1$AResultRegister1ADCB_RSLT2$BResultRegister2ADCB_RSLT3$CResultRegister3ADCB_RSLT4$DResultRegister4ADCB_RSLT5$EResultRegister5ADCB_RSLT6$FResultRegister6ADCB_RSLT7$10ResultRegister7ADCB_LLMT0$11LowLimitRegister0ADCB_LLMT1$12LowLimitRegister1ADCB_LLMT2$13LowLimitRegister2ADCB_LLMT3$14LowLimitRegister3ADCB_LLMT4$15LowLimitRegister4ADCB_LLMT5$16LowLimitRegister5ADCB_LLMT6$17LowLimitRegister6ADCB_LLMT7$18LowLimitRegister7ADCB_HLMT0$19HighLimitRegister0ADCB_HLMT1$1AHighLimitRegister1Table4-20Analog-to-DigitalConverterRegistersAddressMap(Continued)(ADCA_BASE=$00F200)RegisterAcronymAddressOffsetRegisterDescriptionPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor59PreliminaryADCB_HLMT2$1BHighLimitRegister2ADCB_HLMT3$1CHighLimitRegister3ADCB_HLMT4$1DHighLimitRegister4ADCB_HLMT5$1EHighLimitRegister5ADCB_HLMT6$1FHighLimitRegister6ADCB_HLMT7$20HighLimitRegister7ADCB_OFS0$21OffsetRegister0ADCB_OFS1$22OffsetRegister1ADCB_OFS2$23OffsetRegister2ADCB_OFS3$24OffsetRegister3ADCB_OFS4$25OffsetRegister4ADCB_OFS5$26OffsetRegister5ADCB_OFS6$27OffsetRegister6ADCB_OFS7$28OffsetRegister7ADCB_POWER$29PowerControlRegisterADCB_CAL$2AADCCalibrationRegisterTable4-22TemperatureSensorRegisterAddressMap(TSENSOR_BASE=$00F270)TemperatureSensorisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionTSENSOR_CNTL$0ControlRegisterTable4-23SerialCommunicationInterface0RegistersAddressMap(SCI0_BASE=$00F280)RegisterAcronymAddressOffsetRegisterDescriptionSCI0_SCIBR$0BaudRateRegisterTable4-21Analog-to-DigitalConverterRegistersAddressMap(Continued)(ADCB_BASE=$00F240)RegisterAcronymAddressOffsetRegisterDescription56F8335TechnicalData,Rev.
560FreescaleSemiconductorPreliminarySCI0_SCICR$1ControlRegisterReservedSCI0_SCISR$3StatusRegisterSCI0_SCIDR$4DataRegisterTable4-24SerialCommunicationInterface1RegistersAddressMap(SCI1_BASE=$00F290)RegisterAcronymAddressOffsetRegisterDescriptionSCI1_SCIBR$0BaudRateRegisterSCI1_SCICR$1ControlRegisterReservedSCI1_SCISR$3StatusRegisterSCI1_SCIDR$4DataRegisterTable4-25SerialPeripheralInterface0RegistersAddressMap(SPI0_BASE=$00F2A0)RegisterAcronymAddressOffsetRegisterDescriptionSPI0_SPSCR$0StatusandControlRegisterSPI0_SPDSR$1DataSizeRegisterSPI0_SPDRR$2DataReceiveRegisterSPI0_SPDTR$3DataTransmitterRegisterTable4-26SerialPeripheralInterface1RegistersAddressMap(SPI1_BASE=$00F2B0)RegisterAcronymAddressOffsetRegisterDescriptionSPI1_SPSCR$0StatusandControlRegisterSPI1_SPDSR$1DataSizeRegisterSPI1_SPDRR$2DataReceiveRegisterSPI1_SPDTR$3DataTransmitterRegisterTable4-23SerialCommunicationInterface0RegistersAddressMap(Continued)(SCI0_BASE=$00F280)RegisterAcronymAddressOffsetRegisterDescriptionPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor61PreliminaryTable4-27ComputerOperatingProperlyRegistersAddressMap(COP_BASE=$00F2C0)RegisterAcronymAddressOffsetRegisterDescriptionCOPCTL$0ControlRegisterCOPTO$1Time-OutRegisterCOPCTR$2CounterRegisterTable4-28ClockGenerationModuleRegistersAddressMap(CLKGEN_BASE=$00F2D0)RegisterAcronymAddressOffsetRegisterDescriptionPLLCR$0ControlRegisterPLLDB$1Divide-ByRegisterPLLSR$2StatusRegisterReservedSHUTDOWN$4ShutdownRegisterOSCTL$5OscillatorControlRegisterTable4-29GPIOARegistersAddressMap(GPIOA_BASE=$00F2E0)RegisterAcronymAddressOffsetRegisterDescriptionResetValueGPIOA_PUR$0Pull-upEnableRegister0x3FFFGPIOA_DR$1DataRegister0x0000GPIOA_DDR$2DataDirectionRegister0x0000GPIOA_PER$3PeripheralEnableRegister0x3FFFGPIOA_IAR$4InterruptAssertRegister0x0000GPIOA_IENR$5InterruptEnableRegister0x0000GPIOA_IPOLR$6InterruptPolarityRegister0x0000GPIOA_IPR$7InterruptPendingRegister0x0000GPIOA_IESR$8InterruptEdge-SensitiveRegister0x0000GPIOA_PPMODE$9Push-PullModeRegister0x3FFFGPIOA_RAWDATA$ARawDataInputRegister—56F8335TechnicalData,Rev.
562FreescaleSemiconductorPreliminaryTable4-30GPIOBRegistersAddressMap(GPIOB_BASE=$00F300)RegisterAcronymAddressOffsetRegisterDescriptionResetValueGPIOB_PUR$0Pull-upEnableRegister0x00FFGPIOB_DR$1DataRegister0x0000GPIOB_DDR$2DataDirectionRegister0x0000GPIOB_PER$3PeripheralEnableRegister0x0000GPIOB_IAR$4InterruptAssertRegister0x0000GPIOB_IENR$5InterruptEnableRegister0x0000GPIOB_IPOLR$6InterruptPolarityRegister0x0000GPIOB_IPR$7InterruptPendingRegister0x0000GPIOB_IESR$8InterruptEdge-SensitiveRegister0x0000GPIOB_PPMODE$9Push-PullModeRegister0x00FFGPIOB_RAWDATA$ARawDataInputRegister—Table4-31GPIOCRegistersAddressMap(GPIOC_BASE=$00F310)RegisterAcronymAddressOffsetRegisterDescriptionResetValueGPIOC_PUR$0Pull-upEnableRegister0x07FFGPIOC_DR$1DataRegister0x0000GPIOC_DDR$2DataDirectionRegister0x0000GPIOC_PER$3PeripheralEnableRegister0x07FFGPIOC_IAR$4InterruptAssertRegister0x0000GPIOC_IENR$5InterruptEnableRegister0x0000GPIOC_IPOLR$6InterruptPolarityRegister0x0000GPIOC_IPR$7InterruptPendingRegister0x0000GPIOC_IESR$8InterruptEdge-SensitiveRegister0x0000GPIOC_PPMODE$9Push-PullModeRegister0x07FFGPIOC_RAWDATA$ARawDataInputRegister—PeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor63PreliminaryTable4-32GPIODRegistersAddressMap(GPIOD_BASE=$00F320)RegisterAcronymAddressOffsetRegisterDescriptionResetValueGPIOD_PUR$0Pull-upEnableRegister0x1FFFGPIOD_DR$1DataRegister0x0000GPIOD_DDR$2DataDirectionRegister0x0000GPIOD_PER$3PeripheralEnableRegister0x1FC0GPIOD_IAR$4InterruptAssertRegister0x0000GPIOD_IENR$5InterruptEnableRegister0x0000GPIOD_IPOLR$6InterruptPolarityRegister0x0000GPIOD_IPR$7InterruptPendingRegister0x0000GPIOD_IESR$8InterruptEdge-SensitiveRegister0x0000GPIOD_PPMODE$9Push-PullModeRegister0x1FFFGPIOD_RAWDATA$ARawDataInputRegister—Table4-33GPIOERegistersAddressMap(GPIOE_BASE=$00F330)RegisterAcronymAddressOffsetRegisterDescriptionResetValueGPIOE_PUR$0Pull-upEnableRegister0x3FFFGPIOE_DR$1DataRegister0x0000GPIOE_DDR$2DataDirectionRegister0x0000GPIOE_PER$3PeripheralEnableRegister0x3FFFGPIOE_IAR$4InterruptAssertRegister0x0000GPIOE_IENR$5InterruptEnableRegister0x0000GPIOE_IPOLR$6InterruptPolarityRegister0x0000GPIOE_IPR$7InterruptPendingRegister0x0000GPIOE_IESR$8InterruptEdge-SensitiveRegister0x0000GPIOE_PPMODE$9Push-PullModeRegister0x3FFFGPIOE_RAWDATA$ARawDataInputRegister—56F8335TechnicalData,Rev.
564FreescaleSemiconductorPreliminaryTable4-34GPIOFRegistersAddressMap(GPIOF_BASE=$00F340)RegisterAcronymAddressOffsetRegisterDescriptionResetValueGPIOF_PUR$0Pull-upEnableRegister0xFFFFGPIOF_DR$1DataRegister0x0000GPIOF_DDR$2DataDirectionRegister0x0000GPIOF_PER$3PeripheralEnableRegister0xFFFFGPIOF_IAR$4InterruptAssertRegister0x0000GPIOF_IENR$5InterruptEnableRegister0x0000GPIOF_IPOLR$6InterruptPolarityRegister0x0000GPIOF_IPR$7InterruptPendingRegister0x0000GPIOF_IESR$8InterruptEdge-SensitiveRegister0x0000GPIOF_PPMODE$9Push-PullModeRegister0xFFFFGPIOF_RAWDATA$ARawDataInputRegister—Table4-35SystemIntegrationModuleRegistersAddressMap(SIM_BASE=$00F350)RegisterAcronymAddressOffsetRegisterDescriptionSIM_CONTROL$0ControlRegisterSIM_RSTSTS$1ResetStatusRegisterSIM_SCR0$2SoftwareControlRegister0SIM_SCR1$3SoftwareControlRegister1SIM_SCR2$4SoftwareControlRegister2SIM_SCR3$5SoftwareControlRegister3SIM_MSH_ID$6MostSignificantHalfJTAGIDSIM_LSH_ID$7LeastSignificantHalfJTAGIDSIM_PUDR$8Pull-upDisableRegisterReservedSIM_CLKOSR$AClockOutSelectRegisterSIM_GPS$BQuadDecoder1/TimerB/SPI1SelectRegisterSIM_PCE$CPeripheralClockEnableRegisterSIM_ISALH$DI/OShortAddressLocationHighRegisterSIM_ISALL$EI/OShortAddressLocationLowRegisterPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor65PreliminaryTable4-36PowerSupervisorRegistersAddressMap(LVI_BASE=$00F360)RegisterAcronymAddressOffsetRegisterDescriptionLVI_CONTROL$0ControlRegisterLVI_STATUS$1StatusRegisterTable4-37FlashModuleRegistersAddressMap(FM_BASE=$00F400)RegisterAcronymAddressOffsetRegisterDescriptionFMCLKD$0ClockDividerRegisterFMMCR$1ModuleControlRegisterReservedFMSECH$3SecurityHighHalfRegisterFMSECL$4SecurityLowHalfRegisterReservedReservedFMPROT$10ProtectionRegister(Banked)FMPROTB$11ProtectionBootRegister(Banked)ReservedFMUSTAT$13UserStatusRegister(Banked)FMCMD$14CommandRegister(Banked)ReservedReservedFMOPT0$1A16-BitInformationOptionRegister0HottemperatureADCreadingofTemperatureSensor;valuesetduringfactorytestFMOPT1$1B16-BitInformationOptionRegister1NotusedFMOPT2$1C16-BitInformationOptionRegister2RoomtemperatureADCreadingofTemperatureSensor;valuesetduringfactorytest56F8335TechnicalData,Rev.
566FreescaleSemiconductorPreliminaryTable4-38FlexCANRegistersAddressMap(FC_BASE=$00F800)FlexCANisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionFCMCR$0ModuleConfigurationRegisterReservedFCCTL0$3ControlRegister0RegisterFCCTL1$4ControlRegister1RegisterFCTMR$5Free-RunningTimerRegisterFCMAXMB$6MaximumMessageBufferConfigurationRegisterReservedFCRXGMASK_H$8ReceiveGlobalMaskHighRegisterFCRXGMASK_L$9ReceiveGlobalMaskLowRegisterFCRX14MASK_H$AReceiveBuffer14MaskHighRegisterFCRX14MASK_L$BReceiveBuffer14MaskLowRegisterFCRX15MASK_H$CReceiveBuffer15MaskHighRegisterFCRX15MASK_L$DReceiveBuffer15MaskLowRegisterReservedFCSTATUS$10ErrorandStatusRegisterFCIMASK1$11InterruptMasks1RegisterFCIFLAG1$12InterruptFlags1RegisterFCR/T_ERROR_CNTRS$13ReceiveandTransmitErrorCountersRegisterReservedReservedReservedFCMB0_CONTROL$40MessageBuffer0Control/StatusRegisterFCMB0_ID_HIGH$41MessageBuffer0IDHighRegisterFCMB0_ID_LOW$42MessageBuffer0IDLowRegisterFCMB0_DATA$43MessageBuffer0DataRegisterFCMB0_DATA$44MessageBuffer0DataRegisterFCMB0_DATA$45MessageBuffer0DataRegisterFCMB0_DATA$46MessageBuffer0DataRegisterReservedFCMSB1_CONTROL$48MessageBuffer1Control/StatusRegisterFCMSB1_ID_HIGH$49MessageBuffer1IDHighRegisterPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor67PreliminaryFCMSB1_ID_LOW$4AMessageBuffer1IDLowRegisterFCMB1_DATA$4BMessageBuffer1DataRegisterFCMB1_DATA$4CMessageBuffer1DataRegisterFCMB1_DATA$4DMessageBuffer1DataRegisterFCMB1_DATA$4EMessageBuffer1DataRegisterReservedFCMB2_CONTROL$50MessageBuffer2Control/StatusRegisterFCMB2_ID_HIGH$51MessageBuffer2IDHighRegisterFCMB2_ID_LOW$52MessageBuffer2IDLowRegisterFCMB2_DATA$53MessageBuffer2DataRegisterFCMB2_DATA$54MessageBuffer2DataRegisterFCMB2_DATA$55MessageBuffer2DataRegisterFCMB2_DATA$56MessageBuffer2DataRegisterReservedFCMB3_CONTROL$58MessageBuffer3Control/StatusRegisterFCMB3_ID_HIGH$59MessageBuffer3IDHighRegisterFCMB3_ID_LOW$5AMessageBuffer3IDLowRegisterFCMB3_DATA$5BMessageBuffer3DataRegisterFCMB3_DATA$5CMessageBuffer3DataRegisterFCMB3_DATA$5DMessageBuffer3DataRegisterFCMB3_DATA$5EMessageBuffer3DataRegisterReservedFCMB4_CONTROL$60MessageBuffer4Control/StatusRegisterFCMB4_ID_HIGH$61MessageBuffer4IDHighRegisterFCMB4_ID_LOW$62MessageBuffer4IDLowRegisterFCMB4_DATA$63MessageBuffer4DataRegisterFCMB4_DATA$64MessageBuffer4DataRegisterFCMB4_DATA$65MessageBuffer4DataRegisterFCMB4_DATA$66MessageBuffer4DataRegisterReservedFCMB5_CONTROL$68MessageBuffer5Control/StatusRegisterFCMB5_ID_HIGH$69MessageBuffer5IDHighRegisterFCMB5_ID_LOW$6AMessageBuffer5IDLowRegisterTable4-38FlexCANRegistersAddressMap(Continued)(FC_BASE=$00F800)FlexCANisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescription56F8335TechnicalData,Rev.
568FreescaleSemiconductorPreliminaryFCMB5_DATA$6BMessageBuffer5DataRegisterFCMB5_DATA$6CMessageBuffer5DataRegisterFCMB5_DATA$6DMessageBuffer5DataRegisterFCMB5_DATA$6EMessageBuffer5DataRegisterReservedFCMB6_CONTROL$70MessageBuffer6Control/StatusRegisterFCMB6_ID_HIGH$71MessageBuffer6IDHighRegisterFCMB6_ID_LOW$72MessageBuffer6IDLowRegisterFCMB6_DATA$73MessageBuffer6DataRegisterFCMB6_DATA$74MessageBuffer6DataRegisterFCMB6_DATA$75MessageBuffer6DataRegisterFCMB6_DATA$76MessageBuffer6DataRegisterReservedFCMB7_CONTROL$78MessageBuffer7Control/StatusRegisterFCMB7_ID_HIGH$79MessageBuffer7IDHighRegisterFCMB7_ID_LOW$7AMessageBuffer7IDLowRegisterFCMB7_DATA$7BMessageBuffer7DataRegisterFCMB7_DATA$7CMessageBuffer7DataRegisterFCMB7_DATA$7DMessageBuffer7DataRegisterFCMB7_DATA$7EMessageBuffer7DataRegisterReservedFCMB8_CONTROL$80MessageBuffer8Control/StatusRegisterFCMB8_ID_HIGH$81MessageBuffer8IDHighRegisterFCMB8_ID_LOW$82MessageBuffer8IDLowRegisterFCMB8_DATA$83MessageBuffer8DataRegisterFCMB8_DATA$84MessageBuffer8DataRegisterFCMB8_DATA$85MessageBuffer8DataRegisterFCMB8_DATA$86MessageBuffer8DataRegisterReservedFCMB9_CONTROL$88MessageBuffer9Control/StatusRegisterFCMB9_ID_HIGH$89MessageBuffer9IDHighRegisterTable4-38FlexCANRegistersAddressMap(Continued)(FC_BASE=$00F800)FlexCANisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionPeripheralMemoryMappedRegisters56F8335TechnicalData,Rev.
5FreescaleSemiconductor69PreliminaryFCMB9_ID_LOW$8AMessageBuffer9IDLowRegisterFCMB9_DATA$8BMessageBuffer9DataRegisterFCMB9_DATA$8CMessageBuffer9DataRegisterFCMB9_DATA$8DMessageBuffer9DataRegisterFCMB9_DATA$8EMessageBuffer9DataRegisterReservedFCMB10_CONTROL$90MessageBuffer10Control/StatusRegisterFCMB10_ID_HIGH$91MessageBuffer10IDHighRegisterFCMB10_ID_LOW$92MessageBuffer10IDLowRegisterFCMB10_DATA$93MessageBuffer10DataRegisterFCMB10_DATA$94MessageBuffer10DataRegisterFCMB10_DATA$95MessageBuffer10DataRegisterFCMB10_DATA$96MessageBuffer10DataRegisterReservedFCMB11_CONTROL$98MessageBuffer11Control/StatusRegisterFCMB11_ID_HIGH$99MessageBuffer11IDHighRegisterFCMB11_ID_LOW$9AMessageBuffer11IDLowRegisterFCMB11_DATA$9BMessageBuffer11DataRegisterFCMB11_DATA$9CMessageBuffer11DataRegisterFCMB11_DATA$9DMessageBuffer11DataRegisterFCMB11_DATA$9EMessageBuffer11DataRegisterReservedFCMB12_CONTROL$A0MessageBuffer12Control/StatusRegisterFCMB12_ID_HIGH$A1MessageBuffer12IDHighRegisterFCMB12_ID_LOW$A2MessageBuffer12IDLowRegisterFCMB12_DATA$A3MessageBuffer12DataRegisterFCMB12_DATA$A4MessageBuffer12DataRegisterFCMB12_DATA$A5MessageBuffer12DataRegisterFCMB12_DATA$A6MessageBuffer12DataRegisterReservedFCMB13_CONTROL$A8MessageBuffer13Control/StatusRegisterFCMB13_ID_HIGH$A9MessageBuffer13IDHighRegisterFCMB13_ID_LOW$AAMessageBuffer13IDLowRegisterTable4-38FlexCANRegistersAddressMap(Continued)(FC_BASE=$00F800)FlexCANisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescription56F8335TechnicalData,Rev.
570FreescaleSemiconductorPreliminaryFCMB13_DATA$ABMessageBuffer13DataRegisterFCMB13_DATA$ACMessageBuffer13DataRegisterFCMB13_DATA$ADMessageBuffer13DataRegisterFCMB13_DATA$AEMessageBuffer13DataRegisterReservedFCMB14_CONTROL$B0MessageBuffer14Control/StatusRegisterFCMB14_ID_HIGH$B1MessageBuffer14IDHighRegisterFCMB14_ID_LOW$B2MessageBuffer14IDLowRegisterFCMB14_DATA$B3MessageBuffer14DataRegisterFCMB14_DATA$B4MessageBuffer14DataRegisterFCMB14_DATA$B5MessageBuffer14DataRegisterFCMB14_DATA$B6MessageBuffer14DataRegisterReservedFCMB15_CONTROL$B8MessageBuffer15Control/StatusRegisterFCMB15_ID_HIGH$B9MessageBuffer15IDHighRegisterFCMB15_ID_LOW$BAMessageBuffer15IDLowRegisterFCMB15_DATA$BBMessageBuffer15DataRegisterFCMB15_DATA$BCMessageBuffer15DataRegisterFCMB15_DATA$BDMessageBuffer15DataRegisterFCMB15_DATA$BEMessageBuffer15DataRegisterReservedTable4-38FlexCANRegistersAddressMap(Continued)(FC_BASE=$00F800)FlexCANisNOTavailableinthe56F8135deviceRegisterAcronymAddressOffsetRegisterDescriptionFactoryProgrammedMemory56F8335TechnicalData,Rev.
5FreescaleSemiconductor71Preliminary4.
8FactoryProgrammedMemoryTheBootFlashmemoryblockisprogrammedduringmanufacturingwithadefaultSerialBootloaderprogram.
TheSerialBootloaderapplicationcanbeusedtoloadauserapplicationintotheProgramandDataFlash(NOTavailableinthe56F8135)memoriesofthedevice.
The56F83xxSCI/CANBootloaderUserManual(MC56F83xxBLUM)providesdetailedinformationonthisfirmware.
Anapplicationnote,ProductionFlashProgramming(AN1973),detailshowtheSerialBootloaderprogramcanbeusedtoperformproductionFlashprogrammingoftheon-boardFlashmemoriesaswellasotherpotentialmethods.
LikealltheFlashmemoryblocks,theBootFlashcanbeerasedandprogrammedbytheuser.
TheSerialBootloaderapplicationisprogrammedasanaidtotheenduser,butisnotrequiredtobeusedormaintainedintheBootFlashmemory.
Part5InterruptController(ITCN)5.
1IntroductionTheInterruptController(ITCN)moduleisusedtoarbitratebetweenvariousinterruptrequests(IRQs),tosignaltothe56800Ecorewhenaninterruptofsufficientpriorityexists,andtowhataddresstojumpinordertoservicethisinterrupt.
5.
2FeaturesTheITCNmoduledesignincludesthesedistinctivefeatures:ProgrammableprioritylevelsforeachIRQTwoprogrammableFastInterruptsNotificationtoSIMmoduletorestartclocksoutofWaitandStopmodesDrivesinitialaddressontheaddressbusafterresetForfurtherinformation,seeTable4-5,InterruptVectorTableContents.
5.
3FunctionalDescriptionTheInterruptControllerisaslaveontheIPBus.
Itcontainsregistersallowingeachofthe82interruptsourcestobesettooneoffourprioritylevels,excludingcertaininterruptsoffixedpriority.
Next,alloftheinterruptrequestsofagivenlevelarepriorityencodedtodeterminethelowestnumericalvalueoftheactiveinterruptrequestsforthatlevel.
Withinagivenprioritylevel,0isthehighestpriority,whilenumber81isthelowest.
5.
3.
1NormalInterruptHandlingOncetheITCNhasdeterminedthataninterruptistobeservicedandwhichinterrupthasthehighestpriority,aninterruptvectoraddressisgenerated.
NormalinterrupthandlingconcatenatestheVBAandthevectornumbertodeterminethevectoraddress.
Inthisway,anoffsetisgeneratedintothevectortableforeachinterrupt.
56F8335TechnicalData,Rev.
572FreescaleSemiconductorPreliminary5.
3.
2InterruptNestingInterruptexceptionsmaybenestedtoallowanIRQofhigherprioritythanthecurrentexceptiontobeserviced.
Thefollowingtablesdefinethenestingrequirementsforeachprioritylevel.
5.
3.
3FastInterruptHandlingFastinterruptsaredescribedintheDSP56F800EReferenceManual.
Theinterruptcontrollerrecognizesfastinterruptsbeforethecoredoes.
Afastinterruptisdefined(totheITCN)by:1.
Settingthepriorityoftheinterruptaslevel2,withtheappropriatefieldintheIPRregisters2.
SettingtheFIMnregistertotheappropriatevectornumber3.
SettingtheFIVALnandFIVAHnregisterswiththeaddressofthecodeforthefastinterruptWhenaninterruptoccurs,itsvectornumberiscomparedwiththeFIM0andFIM1registervalues.
Ifamatchoccurs,anditisalevel2interrupt,theITCNhandlesitasafastinterrupt.
TheITCNtakesthevectoraddressfromtheappropriateFIVALnandFIVAHnregisters,insteadofgeneratinganaddressthatisanoffsetfromtheVBA.
ThecorethenfetchestheinstructionfromtheindicatedvectoradddressandifitisnotaJSR,thecorestartsitsfastinterrupthandling.
Table5-1InterruptMaskBitDefinitionSR[9]11.
Corestatusregisterbitsindicatingcurrentinterruptmaskwithinthecore.
SR[8]1PermittedExceptionsMaskedExceptions00Priorities0,1,2,3None01Priorities1,2,3Priority010Priorities2,3Priorities0,111Priority3Priorities0,1,2Table5-2.
InterruptPriorityEncodingIPIC_LEVEL[1:0]11.
SeeIPICfielddefinitioninPart5.
6.
30.
2CurrentInterruptPriorityLevelRequiredNestedExceptionPriority00NoInterruptorSWILPPriorities0,1,2,301Priority0Priorities1,2,310Priority1Priorities2,311Priorities2or3Priority3BlockDiagram56F8335TechnicalData,Rev.
5FreescaleSemiconductor73Preliminary5.
4BlockDiagramFigure5-1InterruptControllerBlockDiagram5.
5OperatingModesTheITCNmoduledesigncontainstwomajormodesofoperation:FunctionalModeTheITCNisinthismodebydefault.
WaitandStopModesDuringWaitandStopmodes,thesystemclocksandthe56800Ecoreareturnedoff.
TheITCNwillsignalapendingIRQtotheSystemIntegrationModule(SIM)torestarttheclocksandservicetheIRQ.
AnIRQcanonlywakeupthecoreiftheIRQisenabledpriortoenteringtheWaitorStopmode.
Also,theIRQAandIRQBsignalsautomaticallybecomelow-levelsensitiveinthesemodes,evenifthecontrolregisterbitsaresettomakethemfalling-edgesensitive.
Thisisbecausethereisnoclockavailabletodetectthefallingedge.
AperipheralwhichrequiresaclocktogenerateinterruptswillnotbeabletogenerateinterruptsduringStopmode.
TheFlexCANmodulecanwakethedevicefromStopmode,andaresetwilldojustthat,orIRQAandIRQBcanwakeitup.
PriorityLevel2->4DecodeINT1PriorityLevel2->4DecodeINT82Level082->7PriorityEncoderany0Level382->7PriorityEncoderany3INTVABIPICCONTROL77PIC_ENIACKSR[9:8]56F8335TechnicalData,Rev.
574FreescaleSemiconductorPreliminary5.
6RegisterDescriptionsAregisteraddressisthesumofabaseaddressandanaddressoffset.
Thebaseaddressisdefinedatthesystemlevelandtheaddressoffsetisdefinedatthemodulelevel.
TheITCNperipheralhas24registers.
Table5-3ITCNRegisterSummary(ITCN_BASE=$00F1A0)RegisterAcronymBaseAddress+RegisterNameSectionLocationIPR0$0InterruptPriorityRegister05.
6.
1IPR1$1InterruptPriorityRegister15.
6.
2IPR2$2InterruptPriorityRegister25.
6.
3IPR3$3InterruptPriorityRegister35.
6.
4IPR4$4InterruptPriorityRegister45.
6.
5IPR5$5InterruptPriorityRegister55.
6.
6IPR6$6InterruptPriorityRegister65.
6.
7IPR7$7InterruptPriorityRegister75.
6.
8IPR8$8InterruptPriorityRegister85.
6.
9IPR9$9InterruptPriorityRegister95.
6.
10VBA$AVectorBaseAddressRegister5.
6.
11FIM0$BFastInterrupt0MatchRegister5.
6.
12FIVAL0$CFastInterrupt0VectorAddressLowRegister5.
6.
13FIVAH0$DFastInterrupt0VectorAddressHighRegister5.
6.
14FIM1$EFastInterrupt1MatchRegister5.
6.
15FIVAL1$FFastInterrupt1VectorAddressLowRegister5.
6.
16FIVAH1$10FastInterrupt1VectorAddressHighRegister5.
6.
17IRQP0$11IRQPendingRegister05.
6.
18IRQP1$12IRQPendingRegister15.
6.
19IRQP2$13IRQPendingRegister25.
6.
20IRQP3$14IRQPendingRegister35.
6.
21IRQP4$15IRQPendingRegister45.
6.
22IRQP5$16IRQPendingRegister55.
6.
23ReservedICTL$1DInterruptControlRegister5.
6.
30RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor75PreliminaryAdd.
OffsetRegisterName1514131211109876543210$0IPR0R00BKPT_U0IPLSTPCNTIPL0000000000W$1IPR1R0000000000RX_REGIPLTX_REGIPLTRBUFIPLW$2IPR2RFMCBEIPLFMCCIPLFMERRIPLLOCKIPLLVIIPL00IRQBIPLIRQAIPLW$3IPR3RGPIODIPLGPIOEIPLGPIOFIPLFCMSGBUFIPLFCWKUPIPLFCERRIPLFCBOFFIPL00W$4IPR4RSPI0_RCVIPLSPI1_XMITIPLSPI1_RCVIPL0000GPIOAIPLGPIOBIPLGPIOCIPLW$5IPR5RDEC1_XIRQIPLDEC1_HIRQIPLSCI1_RCVIPLSCI1_RERRIPL00SCI1_TIDLIPLSCI1_XMITIPLSPI0_XMITIPLW$6IPR6RTMRC0IPLTMRD3IPLTMRD2IPLTMRD1IPLTMRD0IPL00DEC0_XIRQIPLDEC0_HIRQIPLW$7IPR7RTMRA0IPLTMRB3IPLTMRB2IPLTMRB1IPLTMRB0IPLTMRC3IPLTMRC2IPLTMRC1IPLW$8IPR8RSCI0_RCVIPLSCI0_RERRIPL00SCI0_TIDLIPLSCI0_XMITIPLTMRA3IPLTMRA2IPLTMRA1IPLW$9IPR9RPWMA_FIPLPWMB_FIPLPWMA_RLIPLPWMB_RLIPLADCA_ZCIPLABCB_ZCIPLADCA_CCIPLADCB_CCIPLW$AVBAR000VECTORBASEADDRESSW$BFIM0R000000000FASTINTERRUPT0W$CFIVAL0RFASTINTERRUPT0VECTORADDRESSLOWW$DFIVAH0R00000000000FASTINTERRUPT0VECTORADDRESSHIGHW$EFIM1R000000000FASTINTERRUPT1W$FFIVAL1RFASTINTERRUPT1VECTORADDRESSLOWW$10FIVAH1R00000000000FASTINTERRUPT1VECTORADDRESSHIGHW00000000000$11IRQP0RPENDING[16:2]1W$12IRQP1RPENDING[32:17]W$13IRQP2RPENDING[48:33]W$14IRQP3RPENDING[64:49]W$15IRQP4RPENDING[80:65]W$16IRQP5R111111111111111PEND-ING[81]WReserved$1DICTLRINTIPICVABINT_DIS1IRQBSTATEIRQASTATEIRQBEDGIRQAEDGW=Reserved56F8335TechnicalData,Rev.
576FreescaleSemiconductorPreliminaryFigure5-2ITCNRegisterMapSummary5.
6.
1InterruptPriorityRegister0(IPR0)Figure5-3InterruptPriorityRegister0(IPR0)5.
6.
1.
1Reserved—Bits15–14Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
1.
2EOnCEBreakpointUnit0InterruptPriorityLevel(BKPT_U0IPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelsforIRQs.
ThisIRQislimitedtopriorities1through3.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel110=IRQisprioritylevel211=IRQisprioritylevel35.
6.
1.
3EOnCEStepCounterInterruptPriorityLevel(STPCNTIPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities1through3.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel110=IRQisprioritylevel211=IRQisprioritylevel35.
6.
1.
4Reserved—Bits9–0Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
2InterruptPriorityRegister1(IPR1)Figure5-4InterruptPriorityRegister1(IPR1)Base+$01514131211109876543210Read00BKPT_U0IPLSTPCNTIPL0000000000WriteRESET0000000000000000Base+$11514131211109876543210Read0000000000RX_REGIPLTX_REGIPLTRBUFIPLWriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor77Preliminary5.
6.
2.
1Reserved—Bits15–6Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
2.
2EOnCEReceiveRegisterFullInterruptPriorityLevel(RX_REGIPL)—Bits5–4ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities1through3.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel110=IRQisprioritylevel211=IRQisprioritylevel35.
6.
2.
3EOnCETransmitRegisterEmptyInterruptPriorityLevel(TX_REGIPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities1through3.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel110=IRQisprioritylevel211=IRQisprioritylevel35.
6.
2.
4EOnCETraceBufferInterruptPriorityLevel(TRBUFIPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities1through3.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel110=IRQisprioritylevel211=IRQisprioritylevel356F8335TechnicalData,Rev.
578FreescaleSemiconductorPreliminary5.
6.
3InterruptPriorityRegister2(IPR2)Figure5-5InterruptPriorityRegister2(IPR2)5.
6.
3.
1FlashMemoryCommand,Data,AddressBuffersEmptyInterruptPriorityLevel(FMCBEIPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
3.
2FlashMemoryCommandCompletePriorityLevel(FMCCIPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
3.
3FlashMemoryErrorInterruptPriorityLevel(FMERRIPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
3.
4PLLLossofLockInterruptPriorityLevel(LOCKIPL)—Bits9–8ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel2Base+$21514131211109876543210ReadFMCBEIPLFMCCIPLFMERRIPLLOCKIPLLVIIPL00IRQBIPLIRQAIPLWriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor79Preliminary5.
6.
3.
5LowVoltageDetectorInterruptPriorityLevel(LVIIPL)—Bits7–6ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
3.
6Reserved—Bits5–4Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
3.
7ExternalIRQBInterruptPriorityLevel(IRQBIPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
3.
8ExternalIRQAInterruptPriorityLevel(IRQAIPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Itisdisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
4InterruptPriorityRegister3(IPR3)Figure5-6InterruptPriorityRegister3(IPR3)Base+$31514131211109876543210ReadGPIODIPLGPIOEIPLGPIOFIPLFCMSGBUFIPLFCWKUPIPLFCERRIPLFCBOFFIPL00WriteRESET000000000000000056F8335TechnicalData,Rev.
580FreescaleSemiconductorPreliminary5.
6.
4.
1GPIODInterruptPriorityLevel(GPIODIPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
4.
2GPIOEInterruptPriorityLevel(GPIOEIPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
4.
3GPIOFInterruptPriorityLevel(GPIOFIPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
4.
4FlexCANMessageBufferInterruptPriorityLevel(FCMSGBUFIPL)—Bits9–8ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
4.
5FlexCANWakeUpInterruptPriorityLevel(FCWKUPIPL)—Bits7–6ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel2RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor81Preliminary5.
6.
4.
6FlexCANErrorInterruptPriorityLevel(FCERRIPL)—Bits5–4ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
4.
7FlexCANBusOffInterruptPriorityLevel(FCBOFFIPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
4.
8Reserved—Bits1–0Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
5InterruptPriorityRegister4(IPR4)Figure5-7InterruptPriorityRegister4(IPR4)5.
6.
5.
1SPI0ReceiverFullInterruptPriorityLevel(SPI0_RCVIPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel2Base+$41514131211109876543210ReadSPI0_RCVIPLSPI1_XMITIPLSPI1_RCVIPL0000GPIOAIPLGPIOBIPLGPIOCIPLWriteRESET000000000000000056F8335TechnicalData,Rev.
582FreescaleSemiconductorPreliminary5.
6.
5.
2SPI1TransmitEmptyInterruptPriorityLevel(SPI1_XMITIPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
5.
3SPI1ReceiverFullInterruptPriorityLevel(SPI1_RCVIPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
5.
4Reserved—Bits9–6Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
5.
5GPIOAInterruptPriorityLevel(GPIOAIPL)—Bits5–4ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
5.
6GPIOBInterruptPriorityLevel(GPIOBIPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
5.
7GPIOCInterruptPriorityLevel(GPIOCIPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor83Preliminary00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
6InterruptPriorityRegister5(IPR5)Figure5-8InterruptPriorityRegister5(IPR5)5.
6.
6.
1QuadratureDecoder1INDEXPulseInterruptPriorityLevel(DEC1_XIRQIPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
6.
2QuadratureDecoder1HOMESignalTransitionorWatchdogTimerInterruptPriorityLevel(DEC1_HIRQIPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
6.
3SCI1ReceiverFullInterruptPriorityLevel(SCI1_RCVIPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel0Base+$51514131211109876543210ReadDEC1_XIRQIPLDEC1_HIRQIPLSCI1_RCVIPLSCI1_RERRIPL00SCI1_TIDLIPLSCI1_XMITIPLSPI0_XMITIPLWriteRESET000000000000000056F8335TechnicalData,Rev.
584FreescaleSemiconductorPreliminary10=IRQisprioritylevel111=IRQisprioritylevel25.
6.
6.
4SCI1ReceiverErrorInterruptPriorityLevel(SCI1_RERRIPL)—Bits9–8ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
6.
5Reserved—Bits7–6Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
6.
6SCI1TransmitterIdleInterruptPriorityLevel(SCI1_TIDLIPL)—Bits5–4ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
6.
7SCI1TransmitterEmptyInterruptPriorityLevel(SCI1_XMITIPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
6.
8SPI0TransmitterEmptyInterruptPriorityLevel(SPI0_XMITIPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel2RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor85Preliminary5.
6.
7InterruptPriorityRegister6(IPR6)Figure5-9InterruptPriorityRegister6(IPR6)5.
6.
7.
1TimerC,Channel0InterruptPriorityLevel(TMRC0IPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
7.
2TimerD,Channel3InterruptPriorityLevel(TMRD3IPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
7.
3TimerD,Channel2InterruptPriorityLevel(TMRD2IPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
7.
4TimerD,Channel1InterruptPriorityLevel(TMRD1IPL)—Bits9–8ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)Base+$61514131211109876543210ReadTMRC0IPLTMRD3IPLTMRD2IPLTMRD1IPLTMRD0IPL00DEC0_XIRQIPLDEC0_HIRQIPLWriteRESET000000000000000056F8335TechnicalData,Rev.
586FreescaleSemiconductorPreliminary01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
7.
5TimerD,Channel0InterruptPriorityLevel(TMRD0IPL)—Bits7–6ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
7.
6Reserved—Bits5–4Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
7.
7QuadratureDecoder0,INDEXPulseInterruptPriorityLevel(DEC0_XIRQIPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
7.
8QuadratureDecoder0,HOMESignalTransitionorWatchdogTimerInterruptPriorityLevel(DEC0_HIRQIPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
8InterruptPriorityRegister7(IPR7)Figure5-10InterruptPriorityRegister(IPR7)Base+$71514131211109876543210ReadTMRA0IPLTMRB3IPLTMRB2IPLTMRB1IPLTMRB0IPLTMRC3IPLTMRC2IPLTMRC1IPLWriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor87Preliminary5.
6.
8.
1TimerA,Channel0InterruptPriorityLevel(TMRA0IPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
8.
2TimerB,Channel3InterruptPriorityLevel(TMRB3IPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
8.
3TimerB,Channel2InterruptPriorityLevel(TMRB2IPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
8.
4TimerB,Channel1InterruptPriorityLevel(TMRB1IPL)—Bits9–8ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
8.
5TimerB,Channel0InterruptPriorityLevel(TMRB0IPL)—Bits7–6ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel156F8335TechnicalData,Rev.
588FreescaleSemiconductorPreliminary11=IRQisprioritylevel25.
6.
8.
6TimerC,Channel3InterruptPriorityLevel(TMRC3IPL)—Bits5–4ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
8.
7TimerC,Channel2InterruptPriorityLevel(TMRC2IPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
8.
8TimerC,Channel1InterruptPriorityLevel(TMRC1IPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
9InterruptPriorityRegister8(IPR8)Figure5-11InterruptPriorityRegister8(IPR8)5.
6.
9.
1SCI0ReceiverFullInterruptPriorityLevel(SCI0_RCVIPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel2Base+$81514131211109876543210ReadSCI0_RCVIPLSCI0_RERRIPL00SCI0_TIDLIPLSCI0_XMITIPLTMRA3IPLTMRA2IPLTMRA1IPLWriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor89Preliminary5.
6.
9.
2SCI0ReceiverErrorInterruptPriorityLevel(SCI0_RERRIPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
9.
3Reserved—Bits11–10Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
9.
4SCI0TransmitterIdleInterruptPriorityLevel(SCI0_TIDLIPL)—Bits9–8ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
9.
5SCI0TransmitterEmptyInterruptPriorityLevel(SCI0_XMITIPL)—Bits7–6ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
9.
6TimerA,Channel3InterruptPriorityLevel(TMRA3IPL)—Bits5–4ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)56F8335TechnicalData,Rev.
590FreescaleSemiconductorPreliminary01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
9.
7TimerA,Channel2InterruptPriorityLevel(TMRA2IPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
9.
8TimerA,Channel1InterruptPriorityLevel(TMRA1IPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
10InterruptPriorityRegister9(IPR9)Figure5-12InterruptPriorityRegister9(IPR9)5.
6.
10.
1PWMAFaultInterruptPriorityLevel(PWMA_FIPL)—Bits15–14ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
10.
2PWMBFaultInterruptPriorityLevel(PWMB_FIPL)—Bits13–12ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
Base+$91514131211109876543210ReadPWMA_FIPLPWMB_FIPLPWMA_RLIPLPWMB_RLIPLADCA_ZCIPLABCB_ZCIPLADCA_CCIPLADCB_CCIPLWriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor91Preliminary00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
10.
3ReloadPWMAInterruptPriorityLevel(PWMA_RLIPL)—Bits11–10ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
10.
4ReloadPWMBInterruptPriorityLevel(PWMB_RLIPL)—Bits9–8ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
10.
5ADCAZeroCrossingorLimitErrorInterruptPriorityLevel(ADCA_ZCIPL)—Bits7–6ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
10.
6ADCBZeroCrossingInterruptPriorityLevel(ADCB_ZCIPL)—Bits5–4ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel256F8335TechnicalData,Rev.
592FreescaleSemiconductorPreliminary5.
6.
10.
7ADCAConversionCompleteInterruptPriorityLevel(ADCA_CCIPL)—Bits3–2ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
10.
8ADCBConversionCompleteInterruptPriorityLevel(ADCB_CCIPL)—Bits1–0ThisfieldisusedtosettheinterruptprioritylevelforIRQs.
ThisIRQislimitedtopriorities0through2.
Theyaredisabledbydefault.
00=IRQdisabled(default)01=IRQisprioritylevel010=IRQisprioritylevel111=IRQisprioritylevel25.
6.
11VectorBaseAddressRegister(VBA)Figure5-13VectorBaseAddressRegister(VBA)5.
6.
11.
1Reserved—Bits15–13Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
11.
2InterruptVectorBaseAddress(VECTORBASEADDRESS)—Bits12–0ThecontentsofthisregisterdeterminethelocationoftheVectorAddressTable.
Thevalueinthisregisterisusedastheupper13bitsoftheinterruptVectorAddressBus(VAB[20:0]).
Thelowereightbitsaredeterminedbaseduponthehighest-priorityinterrupt.
TheyarethenappendedontoVBAbeforepresentingthefullinterruptaddresstothe56800Ecore;seePart5.
3.
1fordetails.
Base+$A1514131211109876543210Read000VECTORBASEADDRESSWriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor93Preliminary5.
6.
12FastInterrupt0MatchRegister(FIM0)Figure5-14FastInterrupt0MatchRegister(FIM0)5.
6.
12.
1Reserved—Bits15–7Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
12.
2FastInterrupt0VectorNumber(FASTINTERRUPT0)—Bits6–0ThisvaluedetermineswhichIRQwillbeaFastInterrupt0.
FastinterruptsvectordirectlytoaserviceroutinebasedonvaluesintheFastInterruptVectorAddressregisterswithouthavingtogotoajumptablefirst;seePart5.
3.
3.
IRQsusedasfastinterruptsmustbesettoprioritylevel2.
Unexpectedresultswilloccurifafastinterruptvectorissettoanyotherpriority.
Fastinterruptsautomaticallybecomethehighest-prioritylevel2interrupt,regardlessoftheirlocationintheinterrupttable,priortobeingdeclaredasfastinterrupt.
FastInterrupt0haspriorityoverFastInterrupt1.
TodeterminethevectornumberofeachIRQ,refertoTable4-5.
5.
6.
13FastInterrupt0VectorAddressLowRegister(FIVAL0)Figure5-15FastInterrupt0VectorAddressLowRegister(FIVAL0)5.
6.
13.
1FastInterrupt0VectorAddressLow(FIVAL0)—Bits15–0Thelower16bitsofthevectoraddressusedforFastInterrupt0.
ThisregisteriscombinedwithFIVAH0toformthe21-bitvectoraddressforFastInterrupt0definedintheFIM0register.
5.
6.
14FastInterrupt0VectorAddressHighRegister(FIVAH0)Figure5-16FastInterrupt0VectorAddressHighRegister(FIVAH0)5.
6.
14.
1Reserved—Bits15–5Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
Base+$B1514131211109876543210Read000000000FASTINTERRUPT0WriteRESET0000000000000000Base+$C1514131211109876543210ReadFASTINTERRUPT0VECTORADDRESSLOWWriteRESET0000000000000000Base+$D1514131211109876543210Read00000000000FASTINTERRUPT0VECTORADDRESSHIGHWriteRESET000000000000000056F8335TechnicalData,Rev.
594FreescaleSemiconductorPreliminary5.
6.
14.
2FastInterrupt0VectorAddressHigh(FIVAH0)—Bits4–0TheupperfivebitsofthevectoraddressusedforFastInterrupt0.
ThisregisteriscombinedwithFIVAL0toformthe21-bitvectoraddressforFastInterrupt0definedintheFIM0register.
5.
6.
15FastInterrupt1MatchRegister(FIM1)Figure5-17FastInterrupt1MatchRegister(FIM1)5.
6.
15.
1Reserved—Bits15–7Thisbitfieldisreservedornotimplemented.
Itisreadas0,butcannotbemodifiedbywriting.
5.
6.
15.
2FastInterrupt1VectorNumber(FASTINTERRUPT1)—Bits6–0ThisvaluedetermineswhichIRQwillbeaFastInterrupt1.
FastinterruptsvectordirectlytoaserviceroutinebasedonvaluesintheFastInterruptVectorAddressregisterswithouthavingtogotoajumptablefirst;seePart5.
3.
3.
IRQsusedasfastinterruptsmustbesettoprioritylevel2.
Unexpectedresultswilloccurifafastinterruptvectorissettoanyotherpriority.
Fastinterruptsautomaticallybecomethehighest-prioritylevel2interrupt,regardlessoftheirlocationintheinterrupttable,priortobeingdeclaredasfastinterrupt.
FastInterrupt0haspriorityoverFastInterrupt1.
TodeterminethevectornumberofeachIRQ,refertoTable4-5.
5.
6.
16FastInterrupt1VectorAddressLowRegister(FIVAL1)Figure5-18FastInterrupt1VectorAddressLowRegister(FIVAL1)5.
6.
16.
1FastInterrupt1VectorAddressLow(FIVAL1)—Bits15–0Thelower16bitsofthevectoraddressareusedforFastInterrupt1.
ThisregisteriscombinedwithFIVAH1toformthe21-bitvectoraddressforFastInterrupt1definedintheFIM1register.
5.
6.
17FastInterrupt1VectorAddressHighRegister(FIVAH1)Figure5-19FastInterrupt1VectorAddressHighRegister(FIVAH1)Base+$E1514131211109876543210Read000000000FASTINTERRUPT1WriteRESET0000000000000000Base+$F1514131211109876543210ReadFASTINTERRUPT1VECTORADDRESSLOWWriteRESET0000000000000000Base+$101514131211109876543210Read00000000000FASTINTERRUPT1VECTORADDRESSHIGHWriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor95Preliminary5.
6.
17.
1Reserved—Bits15–5Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
5.
6.
17.
2FastInterrupt1VectorAddressHigh(FIVAH1)—Bits4–0TheupperfivebitsofthevectoraddressareusedforFastInterrupt1.
ThisregisteriscombinedwithFIVAL1toformthe21-bitvectoraddressforFastInterrupt1definedintheFIM1register.
5.
6.
18IRQPending0Register(IRQP0)Figure5-20IRQPending0Register(IRQP0)5.
6.
18.
1IRQPending(PENDING)—Bits16–2ThisregistercombineswiththeotherfivetorepresentthependingIRQsforinterruptvectornumbers2through81.
0=IRQpendingforthisvectornumber1=NoIRQpendingforthisvectornumber5.
6.
18.
2Reserved—Bit0Thisbitisreservedornotimplemented.
Itisreadas1andcannotbemodifiedbywriting.
5.
6.
19IRQPending1Register(IRQP1)Figure5-21IRQPending1Register(IRQP1)5.
6.
19.
1IRQPending(PENDING)—Bits32–17ThisregistercombineswiththeotherfivetorepresentthependingIRQsforinterruptvectornumbers2through81.
0=IRQpendingforthisvectornumber1=NoIRQpendingforthisvectornumberBase+$111514131211109876543210ReadPENDING[16:2]1WriteRESET1111111111111111$Base+$121514131211109876543210ReadPENDING[32:17]WriteRESET111111111111111156F8335TechnicalData,Rev.
596FreescaleSemiconductorPreliminary5.
6.
20IRQPending2Register(IRQP2)Figure5-22IRQPending2Register(IRQP2)5.
6.
20.
1IRQPending(PENDING)—Bits48–33ThisregistercombineswiththeotherfivetorepresentthependingIRQsforinterruptvectornumbers2through81.
0=IRQpendingforthisvectornumber1=NoIRQpendingforthisvectornumber5.
6.
21IRQPending3Register(IRQP3)Figure5-23IRQPending3Register(IRQP3)5.
6.
21.
1IRQPending(PENDING)—Bits64–49ThisregistercombineswiththeotherfivetorepresentthependingIRQsforinterruptvectornumbers2through81.
0=IRQpendingforthisvectornumber1=NoIRQpendingforthisvectornumber5.
6.
22IRQPending4Register(IRQP4)Figure5-24IRQPending4Register(IRQP4)5.
6.
22.
1IRQPending(PENDING)—Bits80–65ThisregistercombineswiththeotherfivetorepresentthependingIRQsforinterruptvectornumbers2through81.
0=IRQpendingforthisvectornumberBase+$131514131211109876543210ReadPENDING[48:33]WriteRESET1111111111111111Base+$141514131211109876543210ReadPENDING[64:49]WriteRESET1111111111111111Base+$151514131211109876543210ReadPENDING[80:65]WriteRESET1111111111111111RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor97Preliminary1=NoIRQpendingforthisvectornumber5.
6.
23IRQPending5Register(IRQP5)Figure5-25IRQPendingRegister5(IRQP5)5.
6.
23.
1Reserved—Bits96–82Thisbitfieldisreservedornotimplemented.
Thebitsarereadas1andcannotbemodifiedbywriting.
5.
6.
23.
2IRQPending(PENDING)—Bit81ThisregistercombineswiththeotherfivetorepresentthependingIRQsforinterruptvectornumbers2through81.
0=IRQpendingforthisvectornumber1=NoIRQpendingforthisvectornumber5.
6.
24Reserved—Base+175.
6.
25Reserved—Base+185.
6.
26Reserved—Base+195.
6.
27Reserved—Base+1A5.
6.
28Reserved—Base+1B5.
6.
29Reserved—Base+1CBase+$161514131211109876543210Read111111111111111PEND-ING[81]WriteRESET111111111111111156F8335TechnicalData,Rev.
598FreescaleSemiconductorPreliminary5.
6.
30ITCNControlRegister(ICTL)Figure5-26ITCNControlRegister(ICTL)5.
6.
30.
1Interrupt(INT)—Bit15Thisread-onlybitreflectsthestateoftheinterrupttothe56800Ecore.
0=Nointerruptisbeingsenttothe56800Ecore1=Aninterruptisbeingsenttothe56800Ecore5.
6.
30.
2InterruptPriorityLevel(IPIC)—Bits14–13Theseread-onlybitsreflectthestateofthenewinterruptprioritylevelbitsbeingpresentedtothe56800EcoreatthetimethelastIRQwastaken.
Thisfieldisonlyupdatedwhenthe56800Ecorejumpstoanewinterruptserviceroutine.
Note:Nestedinterruptsmaycausethisfieldtobeupdatedbeforetheoriginalinterruptserviceroutinecanreadit.
00=Requirednestedexceptionprioritylevelsare0,1,2,or301=Requirednestedexceptionprioritylevelsare1,2,or310=Requirednestedexceptionprioritylevelsare2or311=Requirednestedexceptionprioritylevelis35.
6.
30.
3VectorNumber-VectorAddressBus(VAB)—Bits12–6Thisread-onlyfieldshowsthevectornumber(VAB[7:1])usedatthetimethelastIRQwastaken.
Thisfieldisonlyupdatedwhenthe56800Ecorejumpstoanewinterruptserviceroutine.
Note:Nestedinterruptsmaycausethisfieldtobeupdatedbeforetheoriginalinterruptserviceroutinecanreadit.
5.
6.
30.
4InterruptDisable(INT_DIS)—Bit5Thisbitallowsallinterruptstobedisabled.
0=Normaloperation(default)1=Allinterruptsdisabled5.
6.
30.
5Reserved—Bit4Thisbitfieldisreservedornotimplemented.
Itisreadas1andcannotbemodifiedbywriting.
Base+$1D1514131211109876543210ReadINTIPICVABINT_DIS1IRQBSTATEIRQASTATEIRQBEDGIRQAEDGWriteRESET0001000000011100Resets56F8335TechnicalData,Rev.
5FreescaleSemiconductor99Preliminary5.
6.
30.
6IRQBStatePin(IRQBSTATE)—Bit3Thisread-onlybitreflectsthestateoftheexternalIRQBpin.
5.
6.
30.
7IRQAStatePin(IRQASTATE)—Bit2Thisread-onlybitreflectsthestateoftheexternalIRQApin.
5.
6.
30.
8IRQBEdgePin(IRQBEdg)—Bit1ThisbitcontrolswhethertheexternalIRQBinterruptisedge-orlevel-sensitive.
DuringStopandWaitmodes,itisautomaticallylevel-sensitive.
0=IRQBinterruptisalow-levelsensitive(default)1=IRQBinterruptisfalling-edgesensitive.
5.
6.
30.
9IRQAEdgePin(IRQAEdg)—Bit0ThisbitcontrolswhethertheexternalIRQAinterruptisedge-orlevel-sensitive.
DuringStopandWaitmodes,itisautomaticallylevel-sensitive.
0=IRQAinterruptisalow-levelsensitive(default)1=IRQAinterruptisfalling-edgesensitive.
5.
7Resets5.
7.
1ResetHandshakeTimingTheITCNprovidesthe56800EcorewitharesetvectoraddresswheneverRESETisasserted.
TheresetvectorwillbepresenteduntilthesecondrisingclockedgeafterRESETisreleased.
5.
7.
2ITCNAfterResetAfterreset,alloftheITCNregistersareintheirdefaultstates.
ThismeansallinterruptsaredisabledexceptthecoreIRQswithfixedpriorities:IllegalInstructionSWInterrupt3HWStackOverflowMisalignedLongWordAccessSWInterrupt2SWInterrupt1SWInterrupt0SWInterruptLPTheseinterruptsareenabledattheirfixedprioritylevels.
56F8335TechnicalData,Rev.
5100FreescaleSemiconductorPreliminaryPart6SystemIntegrationModule(SIM)6.
1IntroductionTheSIMmoduleisasystemcatchallforthegluelogicthattiestogetherthesystem-on-chip.
Itcontrolsdistributionofresetsandclocksandprovidesanumberofcontrolfeatures.
Thesystemintegrationmoduleisresponsibleforthefollowingfunctions:ResetsequencingClockgeneration&distributionStop/WaitcontrolPull-upenablesforselectedperipheralsSystemstatusregistersRegistersforsoftwareaccesstotheJTAGIDofthechipEnforcingFlashsecurityThesearediscussedinmoredetailinthesectionsthatfollow.
6.
2FeaturesTheSIMhasthefollowingfeatures:Flashsecurityfeaturepreventsunauthorizedaccesstocode/datacontainedinon-chipFlashmemoryPower-savingclockgatingforperipheralThreepowermodes(Run,Wait,Stop)tocontrolpowerutilization—Stopmodeshutsdownthe56800Ecore,systemclock,peripheralclock,andPLLoperation—StopmodeentrycanoptionallydisablePLLandOscillator(lowpowervs.
fastrestart);mustbedoneexplicitly—Waitmodeshutsdownthe56800Ecoreandunnecessarysystemclockoperation—RunmodesupportsfullpartoperationControlstoenable/disablethe56800EcoreWAITandSTOPinstructionsCalculatesbasedelayforresetextensionbaseduponPORorRESEToperations.
Resetdelaywillbe3x32clocks(phasedreleaseofreset)forreset,exceptforPOR,whichis221clockcycles.
ControlsresetsequencingafterresetSoftware-initiatedresetFour16-bitregistersresetonlybyaPower-OnResetusableforgeneral-purposesoftwarecontrolSystemControlRegisterRegistersforsoftwareaccesstotheJTAGIDofthechipOperatingModes56F8335TechnicalData,Rev.
5FreescaleSemiconductor101Preliminary6.
3OperatingModesSincetheSIMisresponsiblefordistributingclocksandresetsacrossthechip,itmustunderstandthevariouschipoperatingmodesandtakeappropriateaction.
Theseare:ResetMode,whichhastwosubmodes:—PORandRESEToperationThe56800Ecoreandallperipheralsarereset.
ThisoccurswhentheinternalPORisassertedortheRESETpinisasserted.
—COPresetandsoftwareresetoperationThe56800Ecoreandallperipheralsarereset.
TheMAbitwithintheOMRisnotchanged.
Thisallowsthesoftwaretodeterminethebootmode(internalorexternalboot)tobeusedonthenextreset.
RunModeThisistheprimarymodeofoperationforthisdevice.
Inthismode,the56800Econtrolschipoperation.
DebugModeThe56800EiscontrolledviaJTAG/EOnCEwhenindebugmode.
Allperipherals,excepttheCOPandPWMs,continuetorun.
COPisdisabledandPWMoutputsareoptionallyswitchedofftodisableanymotorfrombeingdriven;seethePWMchapterinthe56F8300PeripheralUserManualfordetails.
WaitModeInWaitmode,thecoreclockandmemoryclocksaredisabled.
Optionally,theCOPcanbestopped.
Similarly,itisanoptiontoswitchoffPWMoutputstodisableanymotorfrombeingdriven.
Allotherperipheralscontinuetorun.
StopModeWheninStopmode,the56800Ecore,memoryandmostperipheralclocksareshutdown.
Optionally,theCOPandCANcanbestopped.
ForlowestpowerconsumptioninStopmode,thePLLcanbeshutdown.
ThismustbedoneexplicitlybeforeenteringStopmode,sincethereisnoautomaticmechanismforthis.
TheCAN(alongwithanynon-gatedinterrupt)iscapableofwakingthechipupfromStopmode,butisnotfullyfunctionalinStopmode.
6.
4OperatingModeRegisterFigure6-1OMRTheresetstateforMBandMAwilldependontheFlashsecuredstate.
SeePart4.
2andPart7fordetailedinformationonhowtheOperatingModeRegister(OMR)MAandMBbitsoperateinthisdevice.
ForadditionalinformationontheEXbit,seePart4.
4.
Forallotherbits,seetheDSP56F800EReferenceManual.
Note:TheOMRisnotaMemoryMapregister;itisdirectlyaccessibleincodethroughtheacronymOMR.
Bit1514131211109876543210NLCMXPSDRSAEX0MBMATypeR/WR/WR/WR/WR/WR/WR/WR/WR/WRESET00000000000000XX56F8335TechnicalData,Rev.
5102FreescaleSemiconductorPreliminary6.
5RegisterDescriptionsTable6-1SIMRegisters(SIM_BASE=$00F350)AddressOffsetAddressAcronymRegisterNameSectionLocationBase+$0SIM_CONTROLControlRegister6.
5.
1Base+$1SIM_RSTSTSResetStatusRegister6.
5.
2Base+$2SIM_SCR0SoftwareControlRegister06.
5.
3Base+$3SIM_SCR1SoftwareControlRegister16.
5.
3Base+$4SIM_SCR2SoftwareControlRegister26.
5.
3Base+$5SIM_SCR3SoftwareControlRegister36.
5.
3Base+$6SIM_MSH_IDMostSignificantHalfofJTAGID6.
5.
4Base+$7SIM_LSH_IDLeastSignificantHalfofJTAGID6.
5.
5Base+$8SIM_PUDRPull-upDisableRegister6.
5.
6ReservedBase+$ASIM_CLKOSRCLKOSelectRegister6.
5.
7Base+$BSIM_GPSGPIOPeripheralSelectRegister6.
5.
8Base+$CSIM_PCEPeripheralClockEnableRegister6.
5.
9Base+$DSIM_ISALHI/OShortAddressLocationHighRegister6.
5.
10Base+$ESIM_ISALLI/OShortAddressLocationLowRegister6.
5.
10RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor103PreliminaryFigure6-2SIMRegisterMapSummary6.
5.
1SIMControlRegister(SIM_CONTROL)Figure6-3SIMControlRegister(SIM_CONTROL)6.
5.
1.
1Reserved—Bits15–6Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
1.
2OnCEEnable(OnCEEBL)—Bit50=OnCEclockto56800EcoreenabledwhencoreTAPisenabled1=OnCEclockto56800Ecoreisalwaysenabled6.
5.
1.
3SoftwareReset(SWRST)—Bit4Thisbitisalwaysreadas0.
Writing1tothisfieldwillcausetheparttoreset.
Add.
OffsetRegisterName1514131211109876543210$0SIM_CONTROLR0000000000ONCEEBL0SWRSTSTOP_DISABLEWAIT_DISABLEW$1SIM_RSTSTSR0000000000SWRCOPREXTRPOR00W$2SIM_SCR0RFIELDW$3SIM_SCR1RFIELDW$4SIM_SCR2RFIELDW$5SIM_SCR3RFIELDW$6SIM_MSH_IDR0000000111110100W$7SIM_LSH_IDR0100000000011101W$8SIM_PUDRR0PWMA1CANEMI_MODERESETIRQXBOOTPWMBPWMA00CTRL0JTAG000WReserved$ASIM_CLKOSRR000000A23A22A21A20CLKDISCLKOSELW$BSIM_GPSR000000000000C3C2C1C0W$CSIM_PCEREMIADCBADCACANDEC1DEC0TMRDTMRCTMRBTMRASCI1SCI0SPI1SPI0PWMBPWMAW$DSIM_ISALHR11111111111111ISAL[23:22]W$ESIM_ISALLRISAL[21:6]W=ReservedBase+$01514131211109876543210Read0000000000ONCEEBLSWRSTSTOP_DISABLEWAIT_DISABLEWriteRESET000000000000000056F8335TechnicalData,Rev.
5104FreescaleSemiconductorPreliminary6.
5.
1.
4StopDisable(STOP_DISABLE)—Bits3–200=Stopmodewillbeenteredwhenthe56800EcoreexecutesaSTOPinstruction01=The56800ESTOPinstructionwillnotcauseentryintoStopmode;STOP_DISABLEcanbereprogrammedinthefuture10=The56800ESTOPinstructionwillnotcauseentryintoStopmode;STOP_DISABLEcanthenonlybechangedbyresettingthedevice11=Sameoperationas106.
5.
1.
5WaitDisable(WAIT_DISABLE)—Bits1–000=Waitmodewillbeenteredwhenthe56800EcoreexecutesaWAITinstruction01=The56800EWAITinstructionwillnotcauseentryintoWaitmode;WAIT_DISABLEcanbereprogrammedinthefuture10=The56800EWAITinstructionwillnotcauseentryintoWaitmode;WAIT_DISABLEcanthenonlybechangedbyresettingthedevice11=Sameoperationas106.
5.
2SIMResetStatusRegister(SIM_RSTSTS)BitsinthisregisteraresetuponanysystemresetandareinitializedonlybyaPower-OnReset(POR).
Areset(otherthanPOR)willonlysetbitsintheregister;bitsarenotcleared.
Onlysoftwareshouldclearthisregister.
Figure6-4SIMResetStatusRegister(SIM_RSTSTS)6.
5.
2.
1Reserved—Bits15–6Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
2.
2SoftwareReset(SWR)—Bit5When1,thisbitindicatesthatthepreviousresetoccurredasaresultofasoftwarereset(writetoSWRSTbitintheSIM_CONTROLregister).
Thisbitwillbeclearedbyanyhardwareresetorbysoftware.
Writinga0tothisbitpositionwillsetthebit,whilewritinga1tothebitwillclearit.
6.
5.
2.
3COPReset(COPR)—Bit4When1,theCOPRbitindicatestheComputerOperatingProperly(COP)timer-generatedresethasoccurred.
ThisbitwillbeclearedbyaPower-OnResetorbysoftware.
Writinga0tothisbitpositionwillsetthebit,whilewritinga1tothebitwillclearit.
6.
5.
2.
4ExternalReset(EXTR)—Bit3If1,theEXTRbitindicatesanexternalsystemresethasoccurred.
ThisbitwillbeclearedbyaPower-OnResetorbysoftware.
Writinga0tothisbitpositionwillsetthebit,whilewritinga1tothebitpositionBase+$11514131211109876543210Read0000000000SWRCOPREXTRPOR00WriteRESET000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor105Preliminarywillclearit.
Basically,whentheEXTRbitis1,theprevioussystemresetwascausedbytheexternalRESETpinbeingassertedlow.
6.
5.
2.
5Power-OnReset(POR)—Bit2When1,thePORbitindicatesaPower-OnResetoccurredsometimeinthepast.
Thisbitcanbeclearedonlybysoftwareorbyanothertypeofreset.
Writinga0tothisbitwillsetthebit,whilewritinga1tothebitpositionwillclearthebit.
Insummary,ifthebitis1,theprevioussystemresetwasduetoaPower-OnReset.
6.
5.
2.
6Reserved—Bits1–0Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
3SIMSoftwareControlRegisters(SIM_SCR0,SIM_SCR1,SIM_SCR2,andSIM_SCR3)OnlySIM_SCR0isshowninthissection.
SIM_SCR1,SIM_SCR2,andSIM_SCR3areidenticalinfunctionality.
Figure6-5SIMSoftwareControlRegister0(SIM_SCR0)6.
5.
3.
1SoftwareControlData1(FIELD)—Bits15–0ThisregisterisresetonlybythePower-OnReset(POR).
Ithasnopart-specificfunctionalityandisintendedforusebyasoftwaredevelopertocontaindatathatwillbeunaffectedbytheotherresetsources(RESETpin,softwarereset,andCOPreset).
6.
5.
4MostSignificantHalfofJTAGID(SIM_MSH_ID)Thisread-onlyregisterdisplaysthemostsignificanthalfoftheJTAGIDforthechip.
Thisregisterreads$01F4.
Figure6-6MostSignificantHalfofJTAGID(SIM_MSH_ID)6.
5.
5LeastSignificantHalfofJTAGID(SIM_LSH_ID)Thisread-onlyregisterdisplaystheleastsignificanthalfoftheJTAGIDforthechip.
Thisregisterreads$401D.
Base+$21514131211109876543210ReadFIELDWritePOR0000000000000000Base+$61514131211109876543210Read0000000111110100WriteRESET000000011111010056F8335TechnicalData,Rev.
5106FreescaleSemiconductorPreliminaryFigure6-7LeastSignificantHalfofJTAGID(SIM_LSH_ID)6.
5.
6SIMPull-upDisableRegister(SIM_PUDR)Mostofthepinsonthechiphaveon-chippull-upresistors.
PinswhichcanoperateasGPIOcanhavetheseresistorsdisabledviatheGPIOfunction.
Non-GPIOpinscanhavetheirpull-upsdisabledbysettingtheappropriatebitinthisregister.
Disablingpull-upsisdoneonaperipheral-by-peripheralbasis(forpinsnotmuxedwithGPIO).
Eachbitintheregister(seeFigure6-8)correspondstoafunctionalgroupofpins.
SeeTable2-2toidentifywhichpinscandeactivatetheinternalpull-upresistor.
Figure6-8SIMPull-upDisableRegister(SIM_PUDR)6.
5.
6.
1Reserved—Bit15Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
6.
2PWMA1—Bit14Thisbitcontrolsthepull-upresistorsontheFAULTA3pin.
6.
5.
6.
3CAN—Bit13Thisbitcontrolsthepull-upresistorsontheCAN_RXpin.
6.
5.
6.
4EMI_MODE—Bit12Thisbitcontrolsthepull-upresistorsontheEMI_MODEpin.
Note:Inthispackage,thisinputpinisdouble-bondedwiththeadjacentVSSpinandthisbitshouldbechangedtoa1inordertoreducepowerconsumption.
6.
5.
6.
5RESET—Bit11Thisbitcontrolsthepull-upresistorsontheRESETpin.
6.
5.
6.
6IRQ—Bit10Thisbitcontrolsthepull-upresistorsontheIRQAandIRQBpins.
Base+$71514131211109876543210Read0100000000011101WriteRESET0100000000011101Base+$81514131211109876543210Read0PWMA1CANEMI_MODERESETIRQXBOOTPWMBPWMA00CTRL0JTAG000WriteRESET0000000000000000RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor107Preliminary6.
5.
6.
7XBOOT—Bit9Thisbitcontrolsthepull-upresistorsontheEXTBOOTpin.
Note:Inthispackage,thisinputpinisdouble-bondedwiththeadjacentVSSpinandthisbitshouldbechangedtoa1inordertoreducepowerconsumption.
6.
5.
6.
8PWMB—Bit8Thisbitcontrolsthepull-upresistorsontheFAULTB0,FAULTB1,FAULTB2,andFAULTB3pins.
6.
5.
6.
9PWMA0—Bit7Thisbitcontrolsthepull-upresistorsontheFAULTA0,FAULTA1,andFAULTA2pins.
6.
5.
6.
10Reserved—Bit6Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
6.
11CTRL—Bit5Thisbitcontrolsthepull-upresistorsontheWRandRDpins.
6.
5.
6.
12Reserved—Bit4Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
6.
13JTAG—Bit3Thisbitcontrolsthepull-upresistorsontheTRST,TMSandTDIpins.
6.
5.
6.
14Reserved—Bit2–0Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
7CLKOSelectRegister(SIM_CLKOSR)TheCLKOselectregistercanbeusedtomultiplexoutanyoneoftheclocksgeneratedinsidetheclockgenerationandSIMmodules.
ThedefaultvalueisSYS_CLK.
Thispathhasbeenoptimizedinordertominimizeanydelayandclockdutycycledistortion.
Allotherclocksprimarilymuxedoutarefortestpurposesonly,andaresubjecttosignificantphaseshiftathighfrequencies.
TheupperfourbitsoftheGPIOBregistercanfunctionasGPIO,[A23:A20],orasadditionalclockoutputsignals.
GPIOhaspriorityandisenabled/disabledviatheGPIOB_PER.
IfGPIOB[7:4]areprogrammedtooperateasperipheraloutputs,thenthechoicebetween[A23:A20]andadditionalclockoutputsisdonehereintheCLKOSR.
ThedefaultstateisfortheperipheralfunctionofGPIOB[7:4]tobeprogrammedas[A23:A20].
Thiscanbechangedbyaltering[A23:A20],asshowninFigure6-9.
Figure6-9CLKOSelectRegister(SIM_CLKOSR)Base+$A1514131211109876543210Read000000A23A22A21A20CLKDISCLKOSELWriteRESET000000000010000056F8335TechnicalData,Rev.
5108FreescaleSemiconductorPreliminary6.
5.
7.
1Reserved—Bits15–10Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
7.
2AlternateGPIO_BPeripheralFunctionforA23(A23)—Bit90=PeripheraloutputfunctionofGPIOB[7]isdefinedtobeA[23]1=PeripheraloutputfunctionofGPIOB[7]isdefinedtobetheoscillatorclock(MSTR_OSC,seeFigure3-4)6.
5.
7.
3AlternateGPIO_BPeripheralFunctionforA22(A22)—Bit80=PeripheraloutputfunctionofGPIOB[6]isdefinedtobeA[22]1=PeripheraloutputfunctionofGPIOB[6]isdefinedtobeSYS_CLK26.
5.
7.
4AlternateGPIO_BPeripheralFunctionforA21(A21)—Bit70=PeripheraloutputfunctionofGPIOB[5]isdefinedtobeA[21]1=PeripheraloutputfunctionofGPIOB[5]isdefinedtobeSYS_CLK6.
5.
7.
5AlternateGPIO_BPeripheralFunctionforA20(A20)—Bit60=PeripheraloutputfunctionofGPIOB[4]isdefinedtobeA[20]1=PeripheraloutputfunctionofGPIOB[4]isdefinedtobetheprescalerclock(FREF,seeFigure3-4)6.
5.
7.
6ClockoutDisable(CLKDIS)—Bit50=CLKOUToutputisenabledandwilloutputthesignalindicatedbyCLKOSEL1=CLKOUTistri-stated6.
5.
7.
7CLockoutSelect(CLKOSEL)—Bits4–0SelectsclocktobemuxedoutontheCLKOpin.
00000=SYS_CLK(fromOCCS-DEFAULT)00001=Reservedforfactorytest—56800Eclock00010=Reservedforfactorytest—XRAMclock00011=Reservedforfactorytest—PFLASHoddclock00100=Reservedforfactorytest—PFLASHevenclock00101=Reservedforfactorytest—BFLASHclock00110=Reservedforfactorytest—DFLASHclock00111=Oscillatoroutput01000=Fout(fromOCCS)01001=Reservedforfactorytest—IPBclock01010=Reservedforfactorytest—Feedback(fromOCCS,thisispathtoPLL)01011=Reservedforfactorytest—Prescalerclock(fromOCCS)01100=Reservedforfactorytest—Postscalerclock(fromOCCS)01101=Reservedforfactorytest—SYS_CLK2(fromOCCS)RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor109Preliminary01110=Reservedforfactorytest—SYS_CLK_DIV201111=Reservedforfactorytest—SYS_CLK_D10000=ADCAclock10001=ADCBclock6.
5.
8GPIOPeripheralSelectRegister(SIM_GPS)TheGPIOPeripheralSelectRegistercanbeusedtomultiplexoutanyoneofthethreealternateperipheralsforGPIOC.
ThedefaultperipheralisQuadDecoder1andQuadTimerB(NOTavailableinthe56F8135device);theseperipheralsworktogether.
ThefourI/OpinsassociatedwithGPIOCcanfunctionasGPIO,QuadDecoder1/QuadTimerB,orasSPI1signals.
GPIOisnotthedefaultandisenabled/disabledviatheGPIOC_PER,asshowninFigure6-10andTable6-2.
WhenGPIOC[3:0]areprogrammedtooperateasperipheralI/O,thenthechoicebetweendecoder/timerandSPIinputs/outputsismadeintheSIM_GPSandinconjunctionwiththeQuadTimerStatusandControlRegisters(SCR).
ThedefaultstateisfortheperipheralfunctionofGPIOC[3:0]tobeprogrammedasdecoderfunctions.
Thiscanbechangedbyalteringtheappropriatecontrolsintheindicatedregisters.
Figure6-10OverallControlofPadsUsingSIM_GPSControlTable6-2ControlofPadsUsingSIM_GPSControl1PinFunctionControlRegistersCommentsGPIOC_PERGPIOC_DTRSIM_GPSQuadTimerSCRRegisterOENbitsGPIOInput00——GPIOOutput01——GPIOC_PERRegisterGPIOControlledI/OPadControlSIM_GPSRegisterQuadTimerControlledSPIControlled010156F8335TechnicalData,Rev.
5110FreescaleSemiconductorPreliminaryFigure6-11GPIOPeripheralSelectRegister(SIM_GPS)6.
5.
8.
1Reserved—Bits15–4Thisbitfieldisreservedornotimplemented.
Itisreadas0andcannotbemodifiedbywriting.
6.
5.
8.
2GPIOC3(C3)—Bit3ThisbitselectsthealternatefunctionforGPIOC3.
0=HOME1/TB3(default-see"SwitchMatrixMode"bitsoftheQuadDecoderDECCRregisterinthe56F8300PeripheralUser'sManual)1=SS16.
5.
8.
3GPIOC2(C2)—Bit2ThisbitselectsthealternatefunctionforGPIOC2.
0=INDEX1/TB2(default)1=MISO16.
5.
8.
4GPIOC1(C1)—Bit1ThisbitselectsthealternatefunctionforGPIOC1.
QuadTimerInput/QuadDecoderInput21—00Seethe"SwitchMatrixforInputstotheTimer"tableinthe56F8300PeripheralUserManualforthedefinitionoftimerinputsbasedontheQuadDecodermodeconfiguration.
QuadTimerOutput/QuadDecoderInput31—01SPIinput1—1—SeeSPIcontrolsfordeterminingthedirectionofeachoftheSPIpins.
SPIoutput1—1—1.
ThisappliestothefourpinsthatserveasQuadDecoder/QuadTimer/SPI/GPIOCfunctions.
Aseparatesetofcontrolbitsisusedforeachpin.
2.
Resetconfiguration3.
QuadDecoderpinsarealwaysinputsandfunctioninconjunctionwiththeQuadTimerpins.
Base+$B1514131211109876543210Read000000000000C3C2C1C0WriteRESET0000000000000000Table6-2ControlofPadsUsingSIM_GPSControl1PinFunctionControlRegistersCommentsGPIOC_PERGPIOC_DTRSIM_GPSQuadTimerSCRRegisterOENbitsRegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor111Preliminary0=PHASEB1/TB1(default)1=MOSI16.
5.
8.
5GPIOC0(C0)—Bit0ThisbitselectsthealternatefunctionforGPIOC0.
0=PHASEA1/TB0(default)1=SCLK16.
5.
9PeripheralClockEnableRegister(SIM_PCE)ThePeripheralClockEnableregisterisusedtoenableordisableclockstotheperipheralsasapowersavingsfeature.
Theclockscanbeindividuallycontrolledforeachperipheralonthechip.
Figure6-12PeripheralClockEnableRegister(SIM_PCE)6.
5.
9.
1ExternalMemoryInterfaceEnable(EMI)—Bit15Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
2Analog-to-DigitalConverterBEnable(ADCB)—Bit14Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
3Analog-to-DigitalConverterAEnable(ADCA)—Bit13Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
4FlexCANEnable(CAN)—Bit12Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
5Decoder1Enable(DEC1)—Bit11Eachbitcontrolsclockstotheindicatedperipheral.
Base+$C1514131211109876543210ReadEMIADCBADCACANDEC1DEC0TMRDTMRCTMRBTMRASCI1SCI0SPI1SPI0PWMBPWMAWriteRESET111111111111111156F8335TechnicalData,Rev.
5112FreescaleSemiconductorPreliminary1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
6Decoder0Enable(DEC0)—Bit10Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
7QuadTimerDEnable(TMRD)—Bit9Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
8QuadTimerCEnable(TMRC)—Bit8Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
9QuadTimerBEnable(TMRB)—Bit7Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
10QuadTimerAEnable(TMRA)—Bit6Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
11SerialCommunicationsInterface1Enable(SCI1)—Bit5Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
12SerialCommunicationsInterface0Enable(SCI0)—Bit4Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
13SerialPeripheralInterface1Enable(SPI1)—Bit3Eachbitcontrolsclockstotheindicatedperipheral.
RegisterDescriptions56F8335TechnicalData,Rev.
5FreescaleSemiconductor113Preliminary1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
14SerialPeripheralInterface0Enable(SPI0)—Bit2Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
15PulseWidthModulatorBEnable(PWMB)—Bit1Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
9.
16PulseWidthModulatorAEnable(PWMA)—Bit0Eachbitcontrolsclockstotheindicatedperipheral.
1=Clocksareenabled0=Theclockisnotprovidedtotheperipheral(theperipheralisdisabled)6.
5.
10I/OShortAddressLocationRegister(SIM_ISALHandSIM_ISALL)TheI/OShortAddressLocationregistersareusedtospecifythememoryreferencedviatheI/Oshortaddressmode.
TheI/Oshortaddressmodeallowstheinstructiontospecifythelowersixbitsofaddress;theupperaddressbitsarenotdirectlycontrollable.
Thisregistersetallowslimitedcontrolofthefulladdress,asshowninFigure6-13.
Note:Ifthisregisterissettosomethingotherthanthetopofmemory(EOnCEregisterspace)andtheEXbitintheOMRissetto1,theJTAGportcannotaccesstheon-chipEOnCEregisters,anddebugfunctionswillbeaffected.
Figure6-13I/OShortAddressDeterminationWiththisregisterset,aninterruptdrivercansettheSIM_ISALLregisterpairtopointtoitsperipheralInstructionPortion"HardCoded"AddressPortion16BitsfromSIM_ISALLRegister2BitsfromSIM_ISALHRegisterFull24-BitforShortI/OAddress6BitsfromI/OShortAddressModeInstruction56F8335TechnicalData,Rev.
5114FreescaleSemiconductorPreliminaryregistersandthenusetheI/OShortaddressingmodetoreferencethem.
TheISRshouldrestorethisregistertoitspreviouscontentspriortoreturningfrominterrupt.
Note:ThedefaultvalueofthisregistersetpointstotheEOnCEregisters.
Note:ThepipelinedelaybetweensettingthisregistersetandusingshortI/Oaddressingwiththenewvalueisthreecycles.
Figure6-14I/OShortAddressLocationHighRegister(SIM_ISALH)6.
5.
10.
1Input/OutputShortAddressLow(ISAL[23:22])—Bit1–0Thisfieldrepresentstheuppertwoaddressbitsofthe"hardcoded"I/Oshortaddress.
Figure6-15I/OShortAddressLocationLowRegister(SIM_ISAL)6.
5.
10.
2Input/OutputShortAddressLow(ISAL[21:6])—Bit15–0Thisfieldrepresentsthelower16addressbitsofthe"hardcoded"I/Oshortaddress.
6.
6ClockGenerationOverviewTheSIMusesaninternalmasterclockfromtheOCCS(CLKGEN)moduletoproducetheperipheralandsystem(coreandmemory)clocks.
Themaximummasterclockfrequencyis120MHz.
Peripheralandsystemclocksaregeneratedathalfthemasterclockfrequencyandthereforeatamaximum60MHz.
TheSIMprovidespowermodes(Stop,Wait)andclockenables(SIM_PCEregister,CLK_DIS,ONCE_EBL)tocontrolwhichclocksareinoperation.
TheOCCS,powermodes,andclockenablesprovideaflexiblemeanstomanagepowerconsumption.
Powerutilizationcanbeminimizedinseveralways.
IntheOCCS,crystaloscillator,andPLLmaybeshutdownwhennotinuse.
WhenthePLLisinuse,itsprescalerandpostscalercanbeusedtolimitPLLandmasterclockfrequency.
Powermodespermitsystemand/orperipheralclockstobedisabledwhenunused.
Clockenablesprovidethemeanstodisableindividualclocks.
Someperipheralsprovidefurthercontrolstodisableunusedsubfunctions.
RefertoPart3On-ChipClockSynthesis(OCCS),andthe56F8300PeripheralUserManualforfurtherdetails.
Base+$D1514131211109876543210Read11111111111111ISAL[23:22]WriteRESET1111111111111111Base+$E1514131211109876543210ReadISAL[21:6]WriteRESET1111111111111111Power-DownModesOverview56F8335TechnicalData,Rev.
5FreescaleSemiconductor115Preliminary6.
7Power-DownModesOverviewThe56F8335/56F8135operateinoneofthreepower-downmodes,asshowninTable6-3.
Allperipherals,excepttheCOP/watchdogtimer,runofftheIPBusclockfrequency,whichisthesameasthemainprocessorfrequencyinthisarchitecture.
ThemaximumfrequencyofoperationisSYS_CLK=60MHz.
Table6-3ClockOperationinPower-DownModesModeCoreClocksPeripheralClocksDescriptionRunActiveActiveDeviceisfullyfunctionalWaitCoreandmemoryclocksdisabledActivePeripheralsareactiveandcanproduceinterruptsiftheyhavenotbeenmaskedoff.
Interruptswillcausethecoretocomeoutofitssuspendedstateandresumenormaloperation.
Typicallyusedforpower-consciousapplications.
StopSystemclockscontinuetobegeneratedintheSIM,butmostaregatedpriortoreachingmemory,coreandperipherals.
TheonlypossiblerecoveriesfromStopmodeare:1.
CANtraffic(1stmessagewillbelost)2.
Non-clockedinterrupts3.
COPreset4.
Externalreset5.
Power-onreset56F8335TechnicalData,Rev.
5116FreescaleSemiconductorPreliminary6.
8StopandWaitModeDisableFunctionFigure6-16InternalStopDisableCircuitThe56800EcorecontainsbothSTOPandWAITinstructions.
BothputtheCPUtosleep.
ForlowestpowerconsumptioninStopmode,thePLLcanbeshutdown.
ThismustbedoneexplicitlybeforeenteringStopmode,sincethereisnoautomaticmechanismforthis.
WhenthePLLisshutdown,the56800Esystemclockmustbesetequaltotheoscillatoroutput.
Someapplicationsrequirethe56800ESTOPandWAITinstructionstobedisabled.
Todisablethoseinstructions,writetotheSIMcontrolregister(SIM_CONTROL),describedinPart6.
5.
1.
Thisprocedurecanbeoneitherapermanentortemporarybasis.
Permanentlyassignedapplicationslastonlyuntiltheirnextreset.
6.
9ResetsTheSIMsupportsfoursourcesofreset.
ThetwoasynchronoussourcesaretheexternalRESETpinandthePower-OnReset(POR).
Thetwosynchronoussourcesarethesoftwarereset,whichisgeneratedwithintheSIMitselfbywritingtotheSIM_CONTROLregister,andtheCOPreset.
Resetbeginswiththeassertionofanyoftheresetsources.
Releaseofresettovariousblocksissequencedtopermitproperoperationofthedevice.
APORresetisfirstextendedfor221clockcyclestopermitstabilizationoftheclocksource,followedbya32clockwindowinwhichSIMclockingisinitiated.
Itisthenfollowedbya32clockwindowinwhichperipheralsarereleasedtoimplementFlashsecurity,and,finally,followedbya32clockwindowinwhichthecoreisinitialized.
Aftercompletionofthedescribedresetsequence,applicationcodewillbeginexecution.
Resetsmaybeassertedasynchronously,butarealwaysreleasedinternallyonarisingedgeofthesystemclock.
D-FLOPDQCD-FLOPDQCR56800ESTOP_DISPermanentDisableReprogrammableDisableClockSelectResetDNote:WaitdisablecircuitissimilarOperationwithSecurityEnabled56F8335TechnicalData,Rev.
5FreescaleSemiconductor117PreliminaryPart7SecurityFeaturesThe56F8335/56F8135offersecurityfeaturesintendedtopreventunauthorizedusersfromreadingthecontentsoftheFlashMemory(FM)array.
TheFlashsecurityconsistsofseveralhardwareinterlocksthatblockthemeansbywhichanunauthorizedusercouldgainaccesstotheFlasharray.
However,partofthesecuritymustliewiththeuser'scode.
Anextremeexamplewouldbeuser'scodethatdumpsthecontentsoftheinternalprogram,asthiscodewoulddefeatthepurposeofsecurity.
Atthesametime,theusermayalsowishtoputa"backdoor"inhisprogram.
Asanexample,theuserdownloadsasecuritykeythroughtheSCI,allowingaccesstoaprogrammingroutinethatupdatesparametersstoredinanothersectionoftheFlash.
7.
1OperationwithSecurityEnabledOncetheuserhasprogrammedtheFlashwithhisapplicationcode,thedevicecanbesecuredbyprogrammingthesecuritybyteslocatedintheFMconfigurationfield,whichoccupiesaportionoftheFMarray.
Thesenon-volatilebyteswillkeepthepartsecuredthroughresetandthroughpower-downofthedevice.
Onlytwobyteswithinthisfieldareusedtoenableordisablesecurity.
RefertotheFlashMemorysectioninthe56F8300PeripheralUserManualforthestateofthesecuritybytesandtheresultingstateofsecurity.
WhenFlashsecuritymodeisenabledinaccordancewiththemethoddescribedintheFlashMemorymodulespecification,thedevicewilldisablethecoreEOnCEdebugcapabilities.
Normalprogramexecutionisotherwiseunaffected.
7.
2FlashAccessBlockingMechanismsThe56F8335/56F8135haveseveraloperatingfunctionalandtestmodes.
EffectiveFlashsecuritymustaddressoperatingmodeselectionandanticipatemodesinwhichtheon-chipFlashcanbecompromisedandreadwithoutexplicituserpermission.
Methodstoblocktheseareoutlinedinthenextsubsections.
7.
2.
1ForcedOperatingModeSelectionAtboottime,theSIMdeterminesinwhichfunctionalmodesthedevicewilloperate.
Theseare:UnsecuredModeSecureMode(EOnCEdisabled)WhenFlashsecurityisenabledasdescribedintheFlashMemorymodulespecification,thedevicewilldisabletheEOnCEdebuginterface.
7.
2.
2DisablingEOnCEAccessOn-chipFlashcanbereadbyissuingcommandsacrosstheEOnCEport,whichisthedebuginterfaceforthe56800Ecore.
TheTRST,TCLK,TMS,TDO,andTDIpinscompriseaJTAGinterfaceontowhichtheEOnCEportfunctionalityismapped.
Whenthedeviceboots,thechip-levelJTAGTAP(TestAccessPort)isactiveandprovidesthechip'sboundaryscancapabilityandaccesstotheIDregister.
ProperimplementationofFlashsecurityrequiresthatnoaccesstotheEOnCEportisprovidedwhensecurityisenabled.
The56800EcorehasaninputwhichdisablesreadingofinternalmemoryviatheJTAG/EOnCE.
TheFMsetsthisinputatresettoavaluedeterminedbythecontentsoftheFMsecuritybytes.
56F8335TechnicalData,Rev.
5118FreescaleSemiconductorPreliminary7.
2.
3FlashLockoutRecoveryIfauserinadvertentlyenablesFlashsecurityonthedevice,abuilt-inlockoutrecoverymechanismcanbeusedtoreenableaccesstothedevice.
Thismechanismcompletelyreasesallon-chipFlash,thusdisablingFlashsecurity.
AccesstothisrecoverymechanismisbuiltintoCodeWarriorviaaninstructioninmemoryconfiguration(.
cfg)files.
Add,oruncommentthefollowingconfigurationcommand:unlock_flash_on_connect1Formoreinformation,pleaseseeCodeWarriorMC56F83xx/DSP5685xFamilyTargetingManual.
TheLOCKOUT_RECOVERYinstructionhasanassociated7-bitDataRegister(DR)thatisusedtocontroltheclockdividercircuitwithintheFMmodule.
Thisdivider,FM_CLKDIV[6:0],isusedtocontroltheperiodoftheclockusedfortimedeventsintheFMerasealgorithm.
Thisregistermustbesetwithappropriatevaluesbeforethelockoutsequencecanbegin.
RefertotheJTAGsectionofthe56F8300PeripheralUserManualformoredetailsonsettingthisregistervalue.
ThevalueoftheJTAGFM_CLKDIV[6:0]willreplacethevalueoftheFMregisterFMCLKDthatdividesdownthesystemclockfortimedevents,asillustratedinFigure7-1.
FM_CLKDIV[6]willmaptothePRDIV8bit,andFM_CLKDIV[5:0]willmaptotheDIV[5:0]bits.
ThecombinationofPRDIV8andDIVmustdividetheFMinputclockdowntoafrequencyof150kHz-200kHz.
The"WritingtheFMCLKDRegister"sectionintheFlashMemorychapterofthe56F8300PeripheralUserManualgivesspecificequationsforcalculatingthecorrectvalues.
Figure7-1JTAGtoFMConnectionforLockoutRecoverySYS_CLKJTAGFMCLKDDIVIDER7772FM_CLKDIVFM_ERASEFlashMemoryclockinputFlashAccessBlockingMechanisms56F8335TechnicalData,Rev.
5FreescaleSemiconductor119PreliminaryTwoexamplesofFM_CLKDIVcalculationsfollow.
EXAMPLE1:Ifthesystemclockisthe8MHzcrystalfrequencybecausethePLLhasnotbeensetup,theinputclockwillbebelow12.
8MHz,soPRDIV8=FM_CLKDIV[6]=0.
UsingthefollowingequationyieldsaDIVvalueof19foraclockof200kHz,andaDIVvalueof20foraclockof190kHz.
ThistranslatesintoanFM_CLKDIV[6:0]valueof$13or$14,respectively.
EXAMPLE2:Inthisexample,thesystemclockhasbeensetupwithavalueof32MHz,makingtheFMinputclock16MHz.
Becausethatisgreaterthan12.
8MHz,PRDIV8=FM_CLKDIV[6]=1.
UsingthefollowingequationyieldsaDIVvalueof9foraclockof200kHz,andaDIVvalueof10foraclockof181kHz.
ThistranslatestoanFM_CLKDIV[6:0]valueof$49or$4A,respectively.
OncetheLOCKOUT_RECOVERYinstructionhasbeenshiftedintotheinstructionregister,theclockdividervaluemustbeshiftedintothecorresponding7-bitdataregister.
Afterthedataregisterhasbeenupdated,theusermusttransitiontheTAPcontrollerintotheRUN-TEST/IDLEstateforthelockoutsequencetocommence.
Thecontrollermustremaininthisstateuntiltheerasesequencehascompleted.
Fordetails,seetheJTAGSectioninthe56F8300PeripheralUserManual.
Note:Whenthelockoutrecoverysequencehascompleted,theusermustresetboththeJTAGTAPcontroller(byassertingTRST)andthedevice(byassertingexternalchipreset)toreturntonormalunsecuredoperation.
7.
2.
4ProductAnalysisTherecommendedmethodofunsecuringaprogrammeddeviceforproductanalysisoffieldfailuresisviathebackdoorkeyaccess.
ThecustomerwouldneedtosupplyTechnicalSupportwiththebackdoorkeyandtheprotocoltoaccessthebackdoorroutineintheFlash.
Additionally,theKEYENbitthatallowsbackdoorkeyaccessmustbeset.
Analternativemethodforperforminganalysisonasecuredhybridcontrollerwouldbetomass-eraseandreprogramtheFlashwiththeoriginalcode,buttomodifythesecuritybytes.
Toinsurethatacustomerdoesnotinadvertentlylockhimselfoutofthedeviceduringprogramming,itisrecommendedthatheprogramthebackdooraccesskeyfirst,hisapplicationcodesecond,andthesecuritybyteswithintheFMconfigurationfieldlast.
SYS_CLK(2))(<<(DIV+1)150[kHz]200[kHz]<<(DIV+1)150[kHz]200[kHz]SYS_CLK(2))(56F8335TechnicalData,Rev.
5120FreescaleSemiconductorPreliminaryPart8GeneralPurposeInput/Output(GPIO)8.
1IntroductionThissectionisintendedtosupplementtheGPIOinformationfoundinthe56F8300PeripheralUserManualandcontainsonlychip-specificinformation.
Thisinformationsupercedesthegenericinformationinthe56F8300PeripheralUserManual.
8.
2MemoryMapsThewidthoftheGPIOportdefineshowmanybitsareimplementedineachoftheGPIOregisters.
BasedonthisandthedefaultfunctionofeachoftheGPIOpins,theresetvaluesoftheGPIOx_PURandGPIOx_PERregisterschangefromporttoport.
Tables4-29through4-34definetheactualresetvaluesoftheseregisters.
8.
3ConfigurationTherearesixGPIOportsdefinedonthe56F8335/56F8135.
ThewidthofeachportandtheassociatedperipheralfunctionisshowninTable8-1andTable8-2.
ThespecificmappingofGPIOportpinsisshowninTable8-3.
Table8-156F8335GPIOPortsConfigurationGPIOPortPortWidthAvailablePinsin56F8335PeripheralFunctionResetFunctionA1466pins-EMIAddresspins-CanonlybeusedasGPIO8pins-EMIAddresspins-NotavailableinthispackageEMIAddressN/AB855pins-EMIAddresspins-CanonlybeusedasGPIO3pins-EMIAddresspins-NotavailableinthispackageGPION/AC11114pins-DEC1/TMRB/SPI14pins-DEC0/TMRA3pins-PWMAcurrentsenseDEC1/TMRBDEC0/TMRAPWMAcurrentsenseConfiguration56F8335TechnicalData,Rev.
5FreescaleSemiconductor121PreliminaryD13112pins-EMICSn4pins-EMICSn-CanonlybeusedasGPIO2pins-SCI12pins-EMICSn-Notavailableinthispackage3pins-PWMBcurrentsenseEMIChipSelectsEMIChipSelectsSCI1N/APWMBcurrentsenseE14122pins-SCI02pins-EMIAddresspins-Notavailableinthispackage4pins-SPI02pins-TMRC4pins-TMRDSCI0N/ASPI0TMRCTMRDF1644pins-EMIData-CanonlybeusedasGPIO12pins-EMIData-NotavailableinthispackageEMIDataN/ATable8-256F8135GPIOPortsConfigurationGPIOPortPortWidthAvailablePinsin56F8135PeripheralFunctionResetFunctionA1466pins-EMIAddresspins-CanonlybeusedasGPIO8pins-EMIAddresspins-NotavailableinthispackageEMIAddressN/AB855pins-EMIAddresspins-CanonlybeusedasGPIO3pins-EMIAddresspins-NotavailableinthispackageGPION/AC11114pins-SPI14pins-DEC0/TMRA3pins-DedicatedGPIODEC1/TMRBDEC0/TMRAGPIOD13116pins-EMICSn-CanonlybeusedasGPIO2pins-SCI12pins-EMICSn-Notavailableinthispackage3pins-PWMBcurrentsenseEMIChipSelectsSCI1N/APWMBcurrentsenseE14122pins-SCI02pins-EMIAddresspins-Notavailableinthispackage4pins-SPI02pins-TMRC4pins-DedicatedGPIOSCI0N/ASPI0TMRCGPIOF1644pins-EMIData-CanonlybeusedasGPIO12pins-EMIData-NotavailableinthispackageEMIDataN/ATable8-156F8335GPIOPortsConfigurationGPIOPortPortWidthAvailablePinsin56F8335PeripheralFunctionResetFunction56F8335TechnicalData,Rev.
5122FreescaleSemiconductorPreliminaryTable8-3GPIOExternalSignalsMapPinsinshadedrowsarenotavailablein56F8335/56F8135PinsinitalicsareNOTavailableinthe56F8135deviceGPIOPortGPIOBitResetFunctionFunctionalSignalPackagePin#GPIOA0PeripheralA81151PeripheralA91162PeripheralA101173PeripheralA111184PeripheralA121195PeripheralA131206N/A7N/A8N/A9N/A10N/A11N/A12N/A13N/AGPIOB0GPIOA161271GPIOA171282GPIOA181293GPIOA191304GPIOA20/Prescaler_clock315N/A6N/A7N/AConfiguration56F8335TechnicalData,Rev.
5FreescaleSemiconductor123PreliminaryGPIOC0PeripheralPHASEA1/TB0/SCLK1291PeripheralPHASEB1/TB1/PHASEB1/TB1/MOSI12102PeripheralINDEX1/TB2/MISO12113PeripheralHOME1/TB3/SS12124PeripheralPHASEA0/TA01275PeripheralPHASEB0/TA11286PeripheralINDEX0/TA217PeripheralHOME0/TA328PeripheralISA01049PeripheralISA110510PeripheralISA2106GPIOD0GPIOCS21421GPIOCS31432GPIOCS41443GPIOCS51454GPIOCS61465GPIOCS71476PeripheralTXD1407PeripheralRXD1418N/A9N/A10PeripheralISB04811PeripheralISB15012PeripheralISB251Table8-3GPIOExternalSignalsMap(Continued)Pinsinshadedrowsarenotavailablein56F8335/56F8135PinsinitalicsareNOTavailableinthe56F8135deviceGPIOPortGPIOBitResetFunctionFunctionalSignalPackagePin#56F8335TechnicalData,Rev.
5124FreescaleSemiconductorPreliminaryGPIOE0PeripheralTXD071PeripheralRXD082N/A3N/A4PeripheralSCLK01245PeripheralMOSI01266PeripheralMISO01257PeripheralSS01238PeripheralTC01119PeripheralTC111310PeripheralTD010711PeripheralTD110812PeripheralTD210913PeripheralTD3110Table8-3GPIOExternalSignalsMap(Continued)Pinsinshadedrowsarenotavailablein56F8335/56F8135PinsinitalicsareNOTavailableinthe56F8135deviceGPIOPortGPIOBitResetFunctionFunctionalSignalPackagePin#JTAGInformation56F8335TechnicalData,Rev.
5FreescaleSemiconductor125PreliminaryPart9JointTestActionGroup(JTAG)9.
1JTAGInformationPleasecontactyourFreescalemarketingrepresentativeorauthorizeddistributorfordevice/package-specificBSDLinformation.
GPIOF0PeripheralD71221PeripheralD81232PeripheralD91243PeripheralD101264N/A5N/A6N/A7N/A8N/A9N/A10N/A11N/A12N/A13N/A14N/A15N/A1.
Notusefulinresetconfigurationinthispackage-reconfigureasGPIO2.
SeePart6.
5.
8todeterminehowtoselectperipheralsfromthisset;DEC1istheselectedperipheralatresetTable8-3GPIOExternalSignalsMap(Continued)Pinsinshadedrowsarenotavailablein56F8335/56F8135PinsinitalicsareNOTavailableinthe56F8135deviceGPIOPortGPIOBitResetFunctionFunctionalSignalPackagePin#56F8335TechnicalData,Rev.
5126FreescaleSemiconductorPreliminaryPart10Specifications10.
1GeneralCharacteristicsThe56F8335/56F8135arefabricatedinhigh-densityCMOSwith5V-tolerantTTL-compatibledigitalinputs.
Theterm"5V-tolerant"referstothecapabilityofanI/Opin,builtona3.
3V-compatibleprocesstechnology,towithstandavoltageupto5.
5Vwithoutdamagingthedevice.
Manysystemshaveamixtureofdevicesdesignedfor3.
3Vand5Vpowersupplies.
Insuchsystems,abusmaycarryboth3.
3V-and5V-compatibleI/Ovoltagelevels(astandard3.
3VI/Oisdesignedtoreceiveamaximumvoltageof3.
3V±10%duringnormaloperationwithoutcausingdamage).
This5V-tolerantcapabilitythereforeoffersthepowersavingsof3.
3VI/Olevelscombinedwiththeabilitytoreceive5Vlevelswithoutdamage.
AbsolutemaximumratingsinTable10-1arestressratingsonly,andfunctionaloperationatthemaximumisnotguaranteed.
Stressbeyondtheseratingsmayaffectdevicereliabilityorcausepermanentdamagetothedevice.
Note:AllspecificationsmeetbothAutomotiveandIndustrialrequirementsunlessindividualspecificationsarelisted.
Note:The56F8135deviceisguaranteedto40MHzandspecifiedtomeetIndustrialrequirementsonly.
Note:The56F8135deviceisspecifiedtomeetIndustrialrequirementsonly;CANisNOTavailableonthe56F8135device.
CAUTIONThisdevicecontainsprotectivecircuitrytoguardagainstdamageduetohighstaticvoltageorelectricalfields.
However,normalprecautionsareadvisedtoavoidapplicationofanyvoltageshigherthanmaximum-ratedvoltagestothishigh-impedancecircuit.
Reliabilityofoperationisenhancedifunusedinputsaretiedtoanappropriatevoltagelevel.
Table10-1AbsoluteMaximumRatings(VSS=VSSA_ADC=0)CharacteristicSymbolNotesMinMaxUnitSupplyvoltageVDD_IO-0.
34.
0VADCSupplyVoltageVDDA_ADC,VREFHVREFHmustbelessthanorequaltoVDDA_ADC-0.
34.
0VOscillator/PLLSupplyVoltageVDDA_OSC_PLL-0.
34.
0VInternalLogicCoreSupplyVoltageVDD_COREOCR_DISisHigh-0.
33.
0VInputVoltage(digital)VINPinGroups1,2,5,6,9,10-0.
36.
0VGeneralCharacteristics56F8335TechnicalData,Rev.
5FreescaleSemiconductor127PreliminaryNote:PinsinitalicsareNOTavailableinthe56F8135device.
PinGroup1:TXD0-1,RXD0-1,SS0,MISO0,MOSI0PinGroup2:PHASEA0,PHASEA1,PHASEB0,PHASEB1,INDEX0,INDEX1,HOME0,HOME1,ISB0-2,ISA0-2,TD2-3,TC0-1,TDO,SCLK0PinGroup3:RSTO,TDOPinGroup4:CAN_TXPinGroup5:D0-15,GPIOD0-5PinGroup6:A8-15,GPIOB0-4,TD0-1PinGroup7:CLKOPinGroup8:PWMA0-5,PWMB0-5PinGroup9:IRQA,IRQB,RESET,EXTBOOT,TRST,TMS,TDI,CAN_RX,EMI_MODE,FAULTA0-3,FAULTB0-3PinGroup10:TCKPinGroup11:XTAL,EXTALPinGroup12:ANA0-7,ANB0-7PinGroup13:OCR_DIS,CLKMODEInputVoltage(analog)VINAPinGroups11,12,13-0.
34.
0VOutputVoltageVOUTPinGroups1,2,3,4,5,6,7,8-0.
34.
06.
01VOutputVoltage(opendrain)VODPinGroup4-0.
36.
0VAmbientTemperature(Automotive)TA-40125°CAmbientTemperature(Industrial)TA-40105°CJunctionTemperature(Automotive)TJ-40150°CJunctionTemperature(Industrial)TJ-40125°CStorageTemperature(Automotive)TSTG-55150°CStorageTemperature(Industrial)TSTG-55150°C1.
IfcorrespondingGPIOpinisconfiguredasopendrain.
Table10-1AbsoluteMaximumRatings(Continued)(VSS=VSSA_ADC=0)CharacteristicSymbolNotesMinMaxUnit56F8335TechnicalData,Rev.
5128FreescaleSemiconductorPreliminary1.
Theta-JAdeterminedon2s2ptestboardsisfrequentlylowerthanwouldbeobservedinanapplication.
Determinedon2s2pther-maltestboard.
2.
Junctiontoambientthermalresistance,Theta-JA(RθJA)wassimulatedtobeequivalenttotheJEDECspecificationJESD51-2inahorizontalconfigurationinnaturalconvection.
Theta-JAwasalsosimulatedonathermaltestboardwithtwointernalplanes(2s2p,where"s"isthenumberofsignallayersand"p"isthenumberofplanes)perJESD51-6andJESD51-7.
ThecorrectnameforTheta-JAforforcedconvectionorwiththenon-singlelayerboardsisTheta-JMA.
3.
Junctiontocasethermalresistance,Theta-JC(RθJC),wassimulatedtobeequivalenttothemeasuredvaluesusingthecoldplatetechniquewiththecoldplatetemperatureusedasthe"case"temperature.
ThebasiccoldplatemeasurementtechniqueisdescribedbyMIL-STD883D,Method1012.
1.
Thisisthecorrectthermalmetrictousetocalculatethermalperformancewhenthepackageisbeingusedwithaheatsink.
4.
ThermalCharacterizationParameter,Psi-JT(ΨJT),isthe"resistance"fromjunctiontoreferencepointthermocoupleontopcen-terofcaseasdefinedinJESD51-2.
ΨJTisausefulvaluetousetoestimatejunctiontemperatureinsteady-statecustomeren-vironments.
5.
Junctiontemperatureisafunctionofon-chippowerdissipation,packagethermalresistance,mountingsite(board)temperature,ambienttemperature,airflow,powerdissipationofothercomponentsontheboard,andboardthermalresistance.
6.
SeePart12.
1formoredetailsonthermaldesignconsiderations.
Table10-2ElectroStaticDischarge(ESD)ProtectionCharacteristicMinTypMaxUnitESDforHumanBodyModel(HBM)2000——VESDforMachineModel(MM)200——VESDforChargeDeviceModel(CDM)500——VTable10-3ThermalCharacteristics6CharacteristicCommentsSymbolValueUnitNotes128-pinLQFPJunctiontoambientNaturalconvectionRθJA50.
8°C/W2Junctiontoambient(@1m/sec)RθJMA46.
5°C/W2JunctiontoambientNaturalconvectionFourlayerboard(2s2p)RθJMA(2s2p)43.
9°C/W1,2Junctiontoambient(@1m/sec)Fourlayerboard(2s2p)RθJMA41.
7°C/W1,2JunctiontocaseRθJC13.
9°C/W3JunctiontocenterofcaseΨJT1.
2°C/W4,5I/OpinpowerdissipationPI/OUser-determinedWPowerdissipationPDPD=(IDDxVDD+PI/O)WMaximumallowedPDPDMAX(TJ-TA)/RθJA7WGeneralCharacteristics56F8335TechnicalData,Rev.
5FreescaleSemiconductor129Preliminary7.
TJ=JunctionTemperatureTA=AmbientTemperatureNote:The56F8135deviceisguaranteedto40MHzandspecifiedtomeetIndustrialrequirementsonly;CANisNOTavailableonthe56F8135device.
Note:Totalchipsourceorsinkcurrentcannotexceed200mASeePinGroupslistedinTable10-1Table10-4OperatingConditions(VREFLO=0V,VSS=VSSA_ADC=0V,VDDA=VDDA_ADC=VDDA_OSC_PLL)CharacteristicSymbolNotesMinTypMaxUnitSupplyvoltageVDD_IO33.
33.
6VADCSupplyVoltageVDDA_ADC,VREFHVREFHmustbelessthanorequaltoVDDA_ADC33.
33.
6VOscillator/PLLSupplyVoltageVDDA_OSC_PLL33.
33.
6VInternalLogicCoreSupplyVoltageVDD_COREOCR_DISisHigh2.
252.
52.
75VDeviceClockFrequencyFSYSCLK0—60MHzInputHighVoltage(digital)VINPinGroups1,2,5,6,9,102—5.
5VInputHighVoltage(analog)VIHAPinGroup132—VDDA+0.
3VInputHighVoltage(XTAL/EXTAL,XTALisnotdrivenbyanexternalclock)VIHCPinGroup11VDDA-0.
8—VDDA+0.
3VInputhighvoltage(XTAL/EXTAL,XTALisdrivenbyanexternalclock)VIHCPinGroup112—VDDA+0.
3VInputLowVoltageVILPinGroups1,2,5,6,9,10,11,13-0.
3—.
8VOutputHighSourceCurrentVOH=2.
4V(VOHmin.
)IOHPinGroups1,2,3——-4mAPinGroups5,6,7——-8PinGroups8——-12OutputLowSinkCurrentVOL=0.
4V(VOLmax)IOLPinGroups1,2,3,4——4mAPinGroups5,6,7——8PinGroup8——12AmbientOperatingTemperature(Automotive)TA-40—125°CAmbientOperatingTemperature(Industrial)TA-40—105°CFlashEndurance(Automotive)(ProgramEraseCycles)NFTA=-40°Cto125°C10,000——CyclesFlashEndurance(Industrial)(ProgramEraseCycles)NFTA=-40°Cto105°C10,000——CyclesFlashDataRetention(Automotive)TRTJ<=85°Cavg15——Years56F8335TechnicalData,Rev.
5130FreescaleSemiconductorPreliminary10.
2DCElectricalCharacteristicsNote:The56F8135deviceisspecifiedtomeetIndustrialrequirementsonly;CANisNOTavailableonthe56F8135device.
SeePinGroupslistedinTable10-1Table10-5DCElectricalCharacteristicsAtRecommendedOperatingConditions;seeTable10-4CharacteristicSymbolNotesMinTypMaxUnitTestConditionsOutputHighVoltageVOH2.
4——VIOH=IOHmaxOutputLowVoltageVOL——0.
4VIOL=IOLmaxDigitalInputCurrentHighpull-upenabledordisabledIIHPinGroups1,2,5,6,9—0+/-2.
5μAVIN=3.
0Vto5.
5VDigitalInputCurrentHighwithpull-downIIHPinGroup104080160μAVIN=3.
0Vto5.
5VAnalogInputCurrentHighIIHAPinGroup13—0+/-2.
5μAVIN=VDDAADCInputCurrentHighIIHADCPinGroup12—0+/-3.
5μAVIN=VDDADigitalInputCurrentLowpull-upenabledIILPinGroups1,2,5,6,9-200-100-50μAVIN=0VDigitalInputCurrentLowpull-updisabledIILPinGroups1,2,5,6,9—0+/-2.
5μAVIN=0VDigitalInputCurrentLowwithpull-downIILPinGroup10—0+/-2.
5μAVIN=0VAnalogInputCurrentLowIILAPinGroup13—0+/-2.
5μAVIN=0VADCInputCurrentLowIILADCPinGroup12—0+/-3.
5μAVIN=0VEXTALInputCurrentLowclockinputIEXTAL—0+/-2.
5μAVIN=VDDor0VXTALInputCurrentLowclockinputIXTALCLKMODE=High—0+/-2.
5μAVIN=VDDAor0VCLKMODE=Low——200μAVIN=VDDAor0VOutputCurrentHighImpedanceStateIOZPinGroups1,2,3,4,5,6,7,8—0+/-2.
5μAVOUT=3.
0Vto5.
5Vor0VSchmittTriggerInputHysteresisVHYSPinGroups2,6,9,10—0.
3—V—InputCapacitance(EXTAL/XTAL)CINC—4.
5—pF—OutputCapacitance(EXTAL/XTAL)COUTC—5.
5—pF—InputCapacitanceCIN—6—pF—OutputCapacitanceCOUT—6—pF—DCElectricalCharacteristics56F8335TechnicalData,Rev.
5FreescaleSemiconductor131PreliminaryTable10-6Power-OnResetLowVoltageParametersCharacteristicSymbolMinTypMaxUnitsPORTripPointPOR1.
751.
81.
9VLVI,2.
5voltSupply,trippoint11.
WhenVDD_COREdropsbelowVEI2.
5,aninterruptisgenerated.
VEI2.
5—2.
14—VLVI,3.
3voltsupply,trippoint22.
WhenVDD_COREdropsbelowVEI3.
3,aninterruptisgenerated.
VEI3.
3—2.
7—VBiasCurrentIbias—110130μATable10-7CurrentConsumptionperPowerSupplyPin(Typical)On-ChipRegulatorEnabled(OCR_DIS=Low)ModeIDD_IO11.
NoOutputSwitching2.
IncludesProcessorCorecurrentsuppliedbyinternalvoltageregulatorIDD_ADCIDD_OSC_PLLTestConditionsRUN1_MAC155mA50mA2.
5mA60MHzDeviceClockAllperipheralclocksareenabledAllperipheralsrunningContinuousMACinstructionswithfetchesfromDataRAMADCpoweredonandclockedWait391mA65μA2.
5mA60MHzDeviceClockAllperipheralclocksareenabledADCpoweredoffStop15.
8mA0μA155μA8MHzDeviceClockAllperipheralclocksareoffADCpoweredoffPLLpoweredoffStop25.
1mA0μA145μAExternalClockisoffAllperipheralclocksareoffADCpoweredoffPLLpoweredoffRES=(VREFH-VREFLO)X1212m56F8335TechnicalData,Rev.
5132FreescaleSemiconductorPreliminaryTable10-8CurrentConsumptionperPowerSupplyPin(Typical)On-ChipRegulatorDisabled(OCR_DIS=High)ModeIDD_CoreIDD_IO11.
NoOutputSwitchingIDD_ADCIDD_OSC_PLLTestConditionsRUN1_MAC150mA13μA50mA2.
5mA60MHzDeviceClockAllperipheralclocksareenabledAllperipheralsrunningContinuousMACinstructionswithfetchesfromDataRAMADCpoweredonandclockedWait386mA13μA65μA2.
5mA60MHzDeviceClockAllperipheralclocksareenabledAllperipheralsrunningADCpoweredoffStop1800μA13μA0μA155μA8MHzDeviceClockAllperipheralclocksareoffADCpoweredoffPLLpoweredoffStop2100μA13μA0μA145μAExternalClockisoffAllperipheralclocksareoffADCpoweredoffPLLpoweredoffTable10-9.
RegulatorParametersCharacteristicSymbolMinTypicalMaxUnitUnloadedOutputVoltage(0mALoad)VRNL2.
25—2.
75VLoadedOutputVoltage(200mAload)VRL2.
25—2.
75VLineRegulation@250mAload(VDD33rangesfrom3.
0Vto3.
6V)VR2.
25—2.
75VShortCircuitCurrent(outputshortedtoground)Iss——700mABiasCurrentIbias—5.
87mAPower-downCurrentIpd—02μAShort-CircuitTolerance(outputshortedtoground)TRSC——30minutesDCElectricalCharacteristics56F8335TechnicalData,Rev.
5FreescaleSemiconductor133Preliminary10.
2.
1TemperatureSenseNote:TemperatureSensorisNOTavailableinthe56F8135device.
Table10-10.
PLLParametersCharacteristicsSymbolMinTypicalMaxUnitPLLStart-uptimeTPS0.
30.
510msResonatorStart-uptimeTRS0.
10.
181msMin-MaxPeriodVariationTPV120—200psPeak-to-PeakJitterTPJ——175psBiasCurrentIBIAS—1.
52mAQuiescentCurrent,power-downmodeIPD—100150μATable10-11TemperatureSenseParametricsCharacteristicsSymbolMinTypicalMaxUnitSlope(Gain)1m—7.
762—mV/°CRoomTrimTemp.
1,21.
IncludestheADCconversionoftheanalogTemperatureSensevoltage.
2.
TheADCisnotcalibratedfortheconversionoftheTemperatureSensortrimvaluestoredintheFlashMemoryatFMOPT0andFMOPT1.
TRT242628°CHotTrimTemp.
(Industrial)1,2THT122125128°CHotTrimTemp.
(Automotive)1,2THT147150153°COutputVoltage@VDDA_ADC=3.
3V,TJ=0°C1VTS0—1.
370—VSupplyVoltageVDDA_ADC3.
03.
33.
6VSupplyCurrent-OFFIDD-OFF——10μASupplyCurrent-ONIDD-ON——250μAAccuracy3,1from-40°Cto150°CUsingVTS=mT+VTS03.
SeeApplicationNote,AN1980,formethodstoincreaseaccuracy.
TACC-6.
706.
7°CResolution4,5,14.
Assuminga12-bitrangefrom0Vto3.
3V.
5.
Typicalresolutioncalculatedusingequation,RES—0.
104—°C/bit56F8335TechnicalData,Rev.
5134FreescaleSemiconductorPreliminary10.
3ACElectricalCharacteristicsTestsareconductedusingtheinputlevelsspecifiedinTable10-5.
Unlessotherwisespecified,propagationdelaysaremeasuredfromthe50%tothe50%point,andriseandfalltimesaremeasuredbetweenthe10%and90%points,asshowninFigure10-1.
Figure10-1InputSignalMeasurementReferencesFigure10-2showsthedefinitionsofthefollowingsignalstates:Activestate,whenabusorsignalisdriven,andentersalowimpedancestateTri-stated,whenabusorsignalisplacedinahighimpedancestateDataValidstate,whenasignallevelhasreachedVOLorVOHDataInvalidstate,whenasignallevelisintransitionbetweenVOLandVOHFigure10-2SignalStates10.
4FlashMemoryCharacteristicsTable10-12FlashTimingParametersCharacteristicSymbolMinTypMaxUnitProgramtime11.
Thereisadditionaloverheadwhichispartoftheprogrammingsequence.
Seethe56F8300PeripheralUserManualfordetails.
Programtimeisper16-bitwordinFlashmemory.
TwowordsatatimecanbeprogrammedwithinthePro-gramFlashmodule,asitcontainstwointerleavedmemories.
Tprog20——μsErasetime22.
Specifiespageerasetime.
Thereare512bytesperpageintheDataandBootFlashmemories.
TheProgramFlashmoduleusestwointerleavedFlashmemories,increasingtheeffectivepagesizeto1024bytes.
Terase20——msMasserasetimeTme100——msVIHVILFallTimeInputSignalNote:ThemidpointisVIL+(VIH–VIL)/2.
Midpoint1LowHigh90%50%10%RiseTimeDataInvalidStateData1Data2ValidDataTri-statedData3ValidData2Data3Data1ValidDataActiveDataActiveExternalClockOperationTiming56F8335TechnicalData,Rev.
5FreescaleSemiconductor135Preliminary10.
5ExternalClockOperationTimingFigure10-3ExternalClockTiming10.
6PhaseLockedLoopTimingTable10-13ExternalClockOperationTimingRequirements11.
Parameterslistedareguaranteedbydesign.
CharacteristicSymbolMinTypMaxUnitFrequencyofoperation(externalclockdriver)22.
SeeFigure10-3fordetailsonusingtherecommendedconnectionofanexternalclockdriver.
fosc0—120MHzClockPulseWidth33.
Thehighorlowpulsewidthmustbenosmallerthan8.
0nsorthechipwillnotfunction.
tPW3.
0——nsExternalclockinputrisetime44.
Externalclockinputrisetimeismeasuredfrom10%to90%.
trise——10nsExternalclockinputfalltime55.
Externalclockinputfalltimeismeasuredfrom90%to10%.
tfall——10nsTable10-14PLLTimingCharacteristicSymbolMinTypMaxUnitExternalreferencecrystalfrequencyforthePLL11.
AnexternallysuppliedreferenceclockshouldbeasfreeaspossiblefromanyphasejitterforthePLLtoworkcorrectly.
ThePLLisoptimizedfor8MHzinputcrystal.
fosc488.
4MHzPLLoutputfrequency2(fOUT)2.
ZCLKmaynotexceed60MHz.
ForadditionalinformationonZCLKand(fOUT/2),pleaserefertotheOCCSchapterinthe56F8300PeripheralUserManual.
fop160—260MHzPLLstabilizationtime3-40°to+125°C3.
ThisistheminimumtimerequiredafterthePLLsetupischangedtoensurereliableoperation.
tplls—110msExternalClockVIHVILNote:ThemidpointisVIL+(VIH–VIL)/2.
90%50%10%90%50%10%tPWtPWtfalltrise56F8335TechnicalData,Rev.
5136FreescaleSemiconductorPreliminary10.
7CrystalOscillatorTiming10.
8Reset,Stop,Wait,ModeSelect,andInterruptTimingTable10-15CrystalOscillatorParametersCharacteristicSymbolMinTypMaxUnitCrystalStart-uptimeTCS4510msResonatorStart-uptimeTRS0.
10.
181msCrystalESRRESR——120ohmsCrystalPeak-to-PeakJitterTD70—250psCrystalMin-MaxPeriodVariationTPV0.
12—1.
5nsResonatorPeak-to-PeakJitterTRJ——300psResonatorMin-MaxPeriodVariationTRP——300psBiasCurrent,high-drivemodeIBIASH—250290μABiasCurrent,low-drivemodeIBIASL—80110μAQuiescentCurrent,power-downmodeIPD—01μATable10-16Reset,Stop,Wait,ModeSelect,andInterruptTiming1,21.
Intheformulas,T=clockcycle.
Foranoperatingfrequencyof60MHz,T=16.
67ns.
At8MHz(usedduringResetandStopmodes),T=125ns.
2.
Parameterslistedareguaranteedbydesign.
CharacteristicSymbolTypicalMinTypicalMaxUnitSeeFigureMinimumRESETAssertionDurationtRA16T—ns10-4Edge-sensitiveInterruptRequestWidthtIRW1.
5T—ns10-5IRQA,IRQBAssertiontoGeneralPurposeOutputValid,causedbyfirstinstructionexecutionintheinterruptserviceroutinetIG18T—ns10-6tIG-FAST14T—IRQAWidthAssertiontoRecoverfromStopState33.
TheinterruptinstructionfetchisvisibleonthepinsonlyinMode3.
tIW1.
5T—ns10-8Reset,Stop,Wait,ModeSelect,andInterruptTiming56F8335TechnicalData,Rev.
5FreescaleSemiconductor137PreliminaryFigure10-4AsynchronousResetTimingFigure10-5ExternalInterruptTiming(NegativeEdge-Sensitive)Figure10-6ExternalLevel-SensitiveInterruptTimingFigure10-7InterruptfromWaitStateTimingFirstFetchtRAtRAZtRDAA0–A15,D0–D15RESETIRQA,IRQBtIRWtIDMA0–A15IRQA,IRQBFirstInterruptInstructionExecutiona)FirstInterruptInstructionExecutiontIGGeneralPurposeI/OPinIRQA,IRQBb)GeneralPurposeI/OInstructionFetchtIRIIRQA,IRQBFirstInterruptVectorA0–A1556F8335TechnicalData,Rev.
5138FreescaleSemiconductorPreliminaryFigure10-8RecoveryfromStopStateUsingAsynchronousInterruptTiming10.
9SerialPeripheralInterface(SPI)TimingTable10-17SPITiming1CharacteristicSymbolMinMaxUnitSeeFigureCycletimeMasterSlavetC5050——nsns10-9,10-10,10-11,10-12EnableleadtimeMasterSlavetELD—25——nsns10-12EnablelagtimeMasterSlavetELG—100——nsns10-12Clock(SCK)hightimeMasterSlavetCH17.
625——nsns10-9,10-10,10-11,10-12Clock(SCK)lowtimeMasterSlavetCL24.
125——nsns10-12DatasetuptimerequiredforinputsMasterSlavetDS200——nsns10-9,10-10,10-11,10-12DataholdtimerequiredforinputsMasterSlavetDH02——nsns10-9,10-10,10-11,10-12Accesstime(timetodataactivefromhigh-impedancestate)SlavetA4.
815ns10-12Disabletime(holdtimetohigh-impedancestate)SlavetD3.
715.
2ns10-12DataValidforoutputsMasterSlave(afterenableedge)tDV——4.
520.
4nsns10-9,10-10,10-11,10-12NotIRQAInterruptVectortIWIRQAtIFA0–A15FirstInstructionFetchSerialPeripheralInterface(SPI)Timing56F8335TechnicalData,Rev.
5FreescaleSemiconductor139PreliminaryFigure10-9SPIMasterTiming(CPHA=0)DatainvalidMasterSlavetDI00——nsns10-9,10-10,10-11RisetimeMasterSlavetR——11.
510.
0nsns10-9,10-10,10-11,10-12FalltimeMasterSlavetF——9.
79.
0nsns10-9,10-10,10-11,10-121.
Parameterslistedareguaranteedbydesign.
Table10-17SPITiming1(Continued)CharacteristicSymbolMinMaxUnitSeeFigureSCLK(CPOL=0)(Output)SCLK(CPOL=1)(Output)MISO(Input)MOSI(Output)MSBinBits14–1LSBintFtCtCLtCLtRtRtFtDStDHtCHtDItDVtDI(ref)tRMasterMSBoutBits14–1MasterLSBoutSS(Input)tCHSSisheldHighonmastertF56F8335TechnicalData,Rev.
5140FreescaleSemiconductorPreliminaryFigure10-10SPIMasterTiming(CPHA=1)SCLK(CPOL=0)(Output)SCLK(CPOL=1)(Output)MISO(Input)MOSI(Output)MSBinBits14–1LSBintRtCtCLtCLtFtCHtDV(ref)tDVtDI(ref)tRtFMasterMSBoutBits14–1MasterLSBoutSS(Input)tCHSSisheldHighonmastertDStDHtDItRtFSerialPeripheralInterface(SPI)Timing56F8335TechnicalData,Rev.
5FreescaleSemiconductor141PreliminaryFigure10-11SPISlaveTiming(CPHA=0)Figure10-12SPISlaveTiming(CPHA=1)SCLK(CPOL=0)(Input)SCLK(CPOL=1)(Input)MISO(Output)MOSI(Input)SlaveMSBoutBits14–1tCtCLtCLtFtCHtDIMSBinBits14–1LSBinSS(Input)tCHtDHtRtELGtELDtFSlaveLSBouttDtAtDStDVtDItRSCLK(CPOL=0)(Input)SCLK(CPOL=1)(Input)MISO(Output)MOSI(Input)SlaveMSBoutBits14–1tCtCLtCLtCHtDIMSBinBits14–1LSBinSS(Input)tCHtDHtFtRSlaveLSBouttDtAtELDtDVtFtRtELGtDVtDS56F8335TechnicalData,Rev.
5142FreescaleSemiconductorPreliminary10.
10QuadTimerTimingFigure10-13TimerTiming10.
11QuadratureDecoderTimingTable10-18TimerTiming1,21.
Intheformulaslisted,T=theclockcycle.
For60MHzoperation,T=16.
67ns.
2.
Parameterslistedareguaranteedbydesign.
CharacteristicSymbolMinMaxUnitSeeFigureTimerinputperiodPIN2T+6—ns10-13Timerinputhigh/lowperiodPINHL1T+3—ns10-13TimeroutputperiodPOUT1T-3—ns10-13Timeroutputhigh/lowperiodPOUTHL0.
5T-3—ns10-13Table10-19QuadratureDecoderTiming1,21.
Intheformulaslisted,T=theclockcycle.
For60MHzoperation,T=16.
67ns.
2.
Parameterslistedareguaranteedbydesign.
CharacteristicSymbolMinMaxUnitSeeFigureQuadratureinputperiodPIN4T+12—ns10-14Quadratureinputhigh/lowperiodPHL2T+6—ns10-14QuadraturephaseperiodPPH1T+3—ns10-14POUTPOUTHLPOUTHLPINPINHLPINHLTimerInputsTimerOutputsSerialCommunicationInterface(SCI)Timing56F8335TechnicalData,Rev.
5FreescaleSemiconductor143PreliminaryFigure10-14QuadratureDecoderTiming10.
12SerialCommunicationInterface(SCI)TimingFigure10-15RXDPulseWidthFigure10-16TXDPulseWidthTable10-20SCITiming11.
Parameterslistedareguaranteedbydesign.
CharacteristicSymbolMinMaxUnitSeeFigureBaudRate22.
fMAXisthefrequencyofoperationofthesystemclock,ZCLK,inMHz,whichis60MHzforthe56F8335deviceand40MHzforthe56F8135device.
BR—(fMAX/16)Mbps—RXD3PulseWidth3.
TheRXDpininSCI0isnamedRXD0andtheRXDpininSCI1isnamedRXD1.
RXDPW0.
965/BR1.
04/BRns10-15TXD4PulseWidth4.
TheTXDpininSCI0isnamedTXD0andtheTXDpininSCI1isnamedTXD1.
TXDPW0.
965/BR1.
04/BRns10-16PhaseB(Input)PINPHLPHLPhaseA(Input)PINPHLPHLPPHPPHPPHPPHRXDPWRXDSCIreceivedatapin(Input)TXDPWTXDSCIreceivedatapin(Input)56F8335TechnicalData,Rev.
5144FreescaleSemiconductorPreliminary10.
13ControllerAreaNetwork(CAN)TimingNote:CANisNOTavailableinthe56F8135device.
Figure10-17BusWakeUpDetection10.
14JTAGTimingTable10-21CANTiming11.
ParameterslistedareguaranteedbydesignCharacteristicSymbolMinMaxUnitSeeFigureBaudRateBRCAN—1Mbps—BusWakeUpdetectionTWAKEUP5—μs10-17Table10-22JTAGTimingCharacteristicSymbolMinMaxUnitSeeFigureTCKfrequencyofoperationusingEOnCE11.
TCKfrequencyofoperationmustbelessthan1/8theprocessorrate.
fOPDCSYS_CLK/8MHz10-18TCKfrequencyofoperationnotusingEOnCE1fOPDCSYS_CLK/4MHz10-18TCKclockpulsewidthtPW50—ns10-18TMS,TDIdataset-uptimetDS5—ns10-19TMS,TDIdataholdtimetDH5—ns10-19TCKlowtoTDOdatavalidtDV—30ns10-19TCKlowtoTDOtri-statetTS—30ns10-19TRSTassertiontimetTRST2T22.
T=processorclockperiod(nominally1/60MHz)—ns10-20TWAKEUPCAN_RXCANreceivedatapin(Input)JTAGTiming56F8335TechnicalData,Rev.
5FreescaleSemiconductor145PreliminaryFigure10-18TestClockInputTimingDiagramFigure10-19TestAccessPortTimingDiagramFigure10-20TRSTTimingDiagramTCK(Input)VMVILVM=VIL+(VIH–VIL)/2tPW1/fOPtPWVMVIHInputDataValidOutputDataValidOutputDataValidtDStDHtDVtTStDVTCK(Input)TDI(Input)TDO(Output)TDO(Output)TDO(Output)TMSTRST(Input)tTRST56F8335TechnicalData,Rev.
5146FreescaleSemiconductorPreliminary10.
15Analog-to-DigitalConverter(ADC)ParametersTable10-23ADCParametersCharacteristicSymbolMinTypMaxUnitInputvoltagesVADINVREFL—VREFHVResolutionRES12—12BitsIntegralNon-Linearity1INL—+/-2.
4+/-3.
2LSB2DifferentialNon-LinearityDNL—+/-0.
7<+1LSB2MonotonicityGUARANTEEDADCinternalclockfADIC0.
5—5MHzConversionrangeRADVREFL—VREFHVADCchannelpower-uptimetADPU5616tAICcycles3ADCreferencecircuitpower-uptime4tVREF——25msConversiontimetADC—6—tAICcycles3SampletimetADS—1—tAICcycles3InputcapacitanceCADI—5—pFInputinjectioncurrent5,perpinIADI——3mAInputinjectioncurrent,totalIADIT——20mAVREFHcurrentIVREFH—1.
23mAADCAcurrentIADCA—25—mAADCBcurrentIADCB—25—mAQuiescentcurrentIADCQ—010μAUncalibratedGainError(ideal=1)EGAIN—+/-.
004+/-.
01—UncalibratedOffsetVoltageVOFFSET—+/-18+/-46mVCalibratedAbsoluteError6AECAL—SeeFigure10-21—LSBsCalibrationFactor17CF1—-0.
003141——CalibrationFactor27CF2—-17.
6——Crosstalkbetweenchannels——-60—dBCommonModeVoltageVcommon—(VREFH-VREFLO)/2—VSignal-to-noiseratioSNR—64.
6—dbAnalog-to-DigitalConverter(ADC)Parameters56F8335TechnicalData,Rev.
5FreescaleSemiconductor147PreliminarySignal-to-noiseplusdistortionratioSINAD—59.
1—dbTotalHarmonicDistortionTHD—60.
6—dbSpuriousFreeDynamicRangeSFDR—61.
1—dbEffectiveNumberOfBits8ENOB—9.
6—Bits1.
INLmeasuredfromVin=.
1VREFHtoVin=.
9VREFH10%to90%InputSignalRange2.
LSB=LeastSignificantBit3.
ADCclockcycles4.
Assumeseachvoltagereferencepinisbypassedwith0.
1μFceramiccapacitorstoground5.
ThecurrentthatcanbeinjectedorsourcedfromanunselectedADCsignalinputwithoutimpactingtheperformanceoftheADC.
ThisallowstheADCtooperateinnoisyindustrialenvironmentswhereinductiveflybackispossible.
6.
Absoluteerrorincludestheeffectsofbothgainerrorandoffseterror.
7.
Pleaseseethe56F8300PeripheralUser'sManualforadditionalinformationonADCcalibration.
8.
ENOB=(SINAD-1.
76)/6.
02Table10-23ADCParameters(Continued)CharacteristicSymbolMinTypMaxUnit56F8335TechnicalData,Rev.
5148FreescaleSemiconductorPreliminaryFigure10-21ADCAbsoluteErrorOverProcessingandTemperatureExtremesBeforeandAfterCalibrationforVDCin=0.
60Vand2.
70VNote:Theabsoluteerrordatashowninthegraphsabovereflectstheeffectsofbothgainerrorandoffseterror.
Thedatawastakenon15parts:threeeachfromfourprocessingcornerlotsaswellasthreefromonenominallyprocessedlot,eachatthreetemperatures:-40°C,27°C,and150°C(givingthe45datapointsshownabove),fortwoinputDCvoltages:0.
60Vand2.
70V.
Thedataindicatesthatforthegivenpopulationofparts,calibrationsignificantlyreduced(byasmuchas39%)thecollectivevariation(spread)oftheabsoluteerrorofthepopulation.
Italsosignificantlyreduced(byasmuchas80%)themean(average)oftheabsoluteerrorandtherebybroughtitsignificantlyclosertotheidealvalueofzero.
Althoughnotguaranteed,itisbelievedthatcalibrationwillproduceresultssimilartothoseshownaboveforanypopulationofpartsincludingthosewhichrepresentprocessingandtemperatureextremes.
10.
16EquivalentCircuitforADCInputsFigure10-22illustratestheADCinputcircuitduringsampleandhold.
S1andS2arealwaysopen/closedPowerConsumption56F8335TechnicalData,Rev.
5FreescaleSemiconductor149PreliminaryatthesametimethatS3isclosed/open.
WhenS1/S2areclosed&S3isopen,oneinputofthesampleandholdcircuitmovestoVREFH-VREFH/2,whiletheotherchargestotheanaloginputvoltage.
Whentheswitchesareflipped,thechargeonC1andC2areaveragedviaS3,withtheresultthatasingle-endedanaloginputisswitchedtoadifferentialvoltagecenteredaboutVREFH-VREFH/2.
TheswitchesswitchoneverycycleoftheADCclock(openone-halfADCclock,closedone-halfADCclock).
Notethatthereareadditionalcapacitancesassociatedwiththeanaloginputpad,routing,etc.
,butthesedonotfilterintotheS/Houtputvoltage,asS1providesisolationduringthecharge-sharingphase.
Oneaspectofthiscircuitisthatthereisanon-goinginputcurrent,whichisafunctionoftheanaloginputvoltage,VREFandtheADCclockfrequency.
1.
Parasiticcapacitanceduetopackage,pin-to-pinandpin-to-packagebasecoupling;1.
8pf2.
Parasiticcapacitanceduetothechipbondpad,ESDprotectiondevicesandsignalrouting;2.
04pf3.
EquivalentresistancefortheESDisolationresistorandthechannelselectmux;500ohms4.
Samplingcapacitoratthesampleandholdcircuit.
CapacitorC1isnormallydisconnectedfromtheinputandisonlyconnectedtoitatsamplingtime;1pfFigure10-22EquivalentCircuitforA/DLoading10.
17PowerConsumptionThissectionprovidesadditionaldetailwhichcanbeusedtooptimizepowerconsumptionforagivenapplication.
Powerconsumptionisgivenbythefollowingequation:A,theinternal[staticcomponent],iscomprisedoftheDCbiascurrentsfortheoscillator,leakagecurrent,PLL,andvoltagereferences.
Thesesourcesoperateindependentlyofprocessorstateoroperatingfrequency.
B,theinternal[state-dependentcomponent],reflectsthesupplycurrentrequiredbycertainon-chipresourcesonlywhenthoseresourcesareinuse.
TheseincludeRAM,FlashmemoryandtheADCs.
Totalpower=A:internal[staticcomponent]+B:internal[state-dependentcomponent]+C:internal[dynamiccomponent]+D:external[dynamiccomponent]+E:external[static]123AnalogInput4S1S2S3C1C2S/HC1=C2=1pF(VREFH-VREFLO)/256F8335TechnicalData,Rev.
5150FreescaleSemiconductorPreliminaryC,theinternal[dynamiccomponent],isclassicC*V2*FCMOSpowerdissipationcorrespondingtothe56800Ecoreandstandardcelllogic.
D,theexternal[dynamiccomponent],reflectspowerdissipatedon-chipasaresultofcapacitiveloadingontheexternalpinsofthechip.
ThisisalsocommonlydescribedasC*V2*F,althoughsimulationsontwooftheIOcelltypesusedonthedevicerevealthatthepower-versus-loadcurvedoeshaveanon-zeroY-intercept.
Table10-24IOLoadingCoefficientsat10MHzInterceptSlopePDU08DGZ_ME1.
30.
11mW/pFPDU04DGZ_ME1.
15mW0.
11mW/pFPowerConsumption56F8335TechnicalData,Rev.
5FreescaleSemiconductor151PreliminaryPowerduetocapacitiveloadingonoutputpinsis(firstorder)afunctionofthecapacitiveloadandfrequencyatwhichtheoutputschange.
Table10-24providescoefficientsforcalculatingpowerdissipatedintheIOcellsasafunctionofcapacitiveload.
Inthesecases:TotalPower=Σ((Intercept+Slope*Cload)*frequency/10MHz)where:SummationisperformedoveralloutputpinswithcapacitiveloadsTotalPowerisexpressedinmWCloadisexpressedinpFBecauseofthelowdutycycleonmostdevicepins,powerdissipationduetocapacitiveloadswasfoundtobefairlylowwhenaveragedoveraperiodoftime.
E,theexternal[staticcomponent],reflectstheeffectsofplacingresistiveloadsontheoutputsofthedevice.
SumthetotalofallV2/RorIVtoarriveattheresistiveloadcontributiontopower.
AssumeV=0.
5forthepurposesoftheseroughcalculations.
Forinstance,ifthereisatotalofeightPWMoutputsdriving10mAintoLEDs,thenP=8*.
5*.
01=40mW.
Inpreviousdiscussions,powerconsumptionduetoparasiticsassociatedwithpureinputpinsisignored,asitisassumedtobenegligible.
56F8335TechnicalData,Rev.
5152FreescaleSemiconductorPreliminaryPart11Packaging11.
156F8335PackageandPin-OutInformationThissectioncontainspackageandpin-outinformationforthe56F8335.
Thisdevicecomesina128-pinLow-profileQuadFlatPack(LQFP).
Figure11-1.
showsthepackageoutlineforthe128-pinLQFP,Figure11-3showsthemechanicalparametersforthispackage,andTable11-1liststhepin-outforthe128-pinLQFP.
56F8335PackageandPin-OutInformation56F8335TechnicalData,Rev.
5FreescaleSemiconductor153PreliminaryFigure11-1TopView,56F8335128-pinLQFPPackageTable11-156F8335128-PinLQFPPackageIdentificationbyPinNumberPinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalName1INDEX033PWMB165VSS97ANB12HOME034PWMB266PWMA598ANB2103PIN13965INDEX0HOME0VSSVDD_IOCLKOVPP2HOME1PHASEB1PHASEA1RXD0TXD0INDEX1GPIOA0GPIOA1GPIOA2GPIOA3GPIOA4GPIOA5VDD_IOVCAP4VSSGPIOF0GPIOF1GPIOF2GPIOF3GPIOB0VDD_IOGPIOB1GPIOB2GPIOB3GPIOB4PWMB0TXD1RXD1PWMB1PWMB2VSSVDD_IOPWMB3PWMB4PWMB5GPIOD0ISB0VCAP1IRQAFAULTB0GPIOD1GPIOD2GPIOD3GPIOD4GPIOD5ISB1ISB2IRQBFAULTB1FAULTB2FAULTB3PWMA0PWMA1PWMA2PWMA3PWMA4VSSVDD_IOPWMA5VSSFAULTA0FAULTA1FAULTA2FAULTA3OCR_DISVDDA_OSC_PLLXTALEXTALVCAP3RSTOCLKMODEANA0VDD_IORESETANA7ANA3ANA2ANA6ANA4ANA1ANA5TEMP_SENSEVREFHVREFPVREFMIDVREFNVREFLOVDDA_ADCVSSA_ADCISA0ANB6ANB5ANB4ANB3ANB2ANB1ANB0ANB7ISA2ISA1TD0TD3TD2TD1TC1TC0VDD_IOTDITMSTCKTRSTPHASEB0VCAP2CAN_RXVPP1TDOCAN_TXPHASEA0MOSI0MISO0SCLK0SS0MarkOrientation56F8335TechnicalData,Rev.
5154FreescaleSemiconductorPreliminary3VSS35VSS67FAULTA099ANB34VDD_IO36VDD_IO68FAULTA1100ANB45VPP237PWMB369FAULTA2101ANB56CLKO38PWMB470FAULTA3102ANB67TXD039PWMB571OCR_DIS103ANB78RXD040TXD172VDDA_OSC_PLL104ISA09PHASEA141RXD173XTAL105ISA110PHASEB142GPIOD074EXTAL106ISA211INDEX143GPIOD175VCAP3107TD012HOME144GPIOD276VDD_IO108TD113VCAP445GPIOD377RSTO109TD214VDD_IO46GPIOD478RESET110TD315GPIOA0147GPIOD579CLKMODE111TC016GPIOA1148ISB080ANA0112VDD_IO17GPIOA2149VCAP181ANA1113TC118GPIOA3150ISB182ANA2114TRST19GPIOA4151ISB283ANA3115TCK20GPIOA5152IRQA84ANA4116TMS21VSS53IRQB85ANA5117TDI20GPIOF0154FAULTB086ANA6118TDO23GPIOF1155FAULTB187ANA7119VPP124GPIOF2156FAULTB288TEMP_SENSE120CAN_TX25VDD_IO57FAULTB389VREFLO121CAN_RX1.
Primaryfunctionisnotavailableinthispackageconfiguration;GPIOfunctionmustbeusedinstead26GPIOF3158PWMA090VREFN122VCAP227GPIOB059VSS91VREFMID123SS028GPIOB160PWMA192VREFP124SCLK029GPIOB261PWMA293VREFH125MISO030GPIOB362VDD_IO94VDDA_ADC126MOSI0Table11-156F8335128-PinLQFPPackageIdentificationbyPinNumber(Continued)PinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalName56F8135PackageandPin-OutInformation56F8335TechnicalData,Rev.
5FreescaleSemiconductor155Preliminary11.
256F8135PackageandPin-OutInformationThissectioncontainspackageandpin-outinformationforthe56F8135.
Thisdevicecomesina128-pinLow-profileQuadFlatPack(LQFP).
Figure11-1.
showsthepackageoutlineforthe128-pinLQFP,Figure11-3showsthemechanicalparametersforthispackage,andTable11-1liststhepin-outforthe128-pinLQFP.
31GPIOB463PWMA395VSSA_ADC127PHASEA032PWMB064PWMA496ANB0128PHASEB0Table11-156F8335128-PinLQFPPackageIdentificationbyPinNumber(Continued)PinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalName56F8335TechnicalData,Rev.
5156FreescaleSemiconductorPreliminaryFigure11-2TopView,56F8135128-pinLQFPPackageTable11-256F8135128-PinLQFPPackageIdentificationbyPinNumberPinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalName1INDEX033PWMB165VSS97ANB12HOME034PWMB266NC98ANB2103PIN13965INDEX0HOME0VSSVDD_IOCLKOVPP2SS1MOSI1SCLK1RXD0TXD0MISO1GPIOA0GPIOA1GPIOA2GPIOA3GPIOA4GPIOA5VDD_IOVCAP4VSSGPIOF0GPIOF1GPIOF2GPIOF3GPIOB0VDD_IOGPIOB1GPIOB2GPIOB3GPIOB4PWMB0TXD1RXD1PWMB1PWMB2VSSVDD_IOPWMB3PWMB4PWMB5GPIOD0ISB0VCAP1IRQAFAULTB0GPIOD1GPIOD2GPIOD3GPIOD4GPIOD5ISB1ISB2IRQBFAULTB1FAULTB2FAULTB3NCNCNCNCNCVSSVDD_IONCVSSNCNCNCNCOCR_DISVDDA_OSC_PLLXTALEXTALVCAP3RSTOCLKMODEANA0VDD_IORESETANA7ANA3ANA2ANA6ANA4ANA1ANA5NCVREFHVREFPVREFMIDVREFNVREFLOVDDA_ADCVSSA_ADCGPIOC8ANB6ANB5ANB4ANB3ANB2ANB1ANB0ANB7GPIOC10GPIOC9GPIOE10GPIOE13GPIOE12GPIOE11TC1TC0VDD_IOTDITMSTCKTRSTPHASEB0VCAP2NCVPP1TDONCPHASEA0MOSI0MISO0SCLK0SS0MarkOrientation56F8135PackageandPin-OutInformation56F8335TechnicalData,Rev.
5FreescaleSemiconductor157Preliminary3VSS35VSS67NC99ANB34VDD_IO36VDD_IO68NC100ANB45VPP237PWMB369NC101ANB56CLKO38PWMB470NC102ANB67TXD039PWMB571OCR_DIS103ANB78RXD040TXD172VDDA_OSC_PLL104GPIOC89SCLK141RXD173XTAL105GPIOC910MOSI142GPIOD074EXTAL106GPIOC1011MISO143GPIOD175VCAP3107GPIOE1012SS144GPIOD276VDD_IO108GPIOE1113VCAP445GPIOD377RSTO109GPIOE1214VDD_IO46GPIOD478RESET110GPIOE1315GPIOA0147GPIOD579CLKMODE111TC016GPIOA1148ISB080ANA0112VDD_IO17GPIOA2149VCAP181ANA1113TC118GPIOA3150ISB182ANA2114TRST19GPIOA4151ISB283ANA3115TCK20GPIOA5152IRQA84ANA4116TMS21VSS53IRQB85ANA5117TDI22GPIOF0154FAULTB086ANA6118TDO23GPIOF1155FAULTB187ANA7119VPP124GPIOF2156FAULTB288NC120NC25VDD_IO57FAULTB389VREFLO121NC1.
Primaryfunctionisnotavailableinthispackageconfiguration;GPIOfunctionmustbeusedinstead26GPIOF3158NC90VREFN122VCAP227GPIOB059VSS91VREFMID123SS0Table11-256F8135128-PinLQFPPackageIdentificationbyPinNumber(Continued)PinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalName56F8335TechnicalData,Rev.
5158FreescaleSemiconductorPreliminary28GPIOB160NC92VREFP124SCLK029GPIOB261NC93VREFH125MISO030GPIOB362VDD_IO94VDDA_ADC126MOSI031GPIOB463NC95VSSA_ADC127PHASEA032PWMB064NC96ANB0128PHASEB0Table11-256F8135128-PinLQFPPackageIdentificationbyPinNumber(Continued)PinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalNamePinNo.
SignalName56F8135PackageandPin-OutInformation56F8335TechnicalData,Rev.
5FreescaleSemiconductor159PreliminaryFigure11-3128-pinLQFPMechanicalInformationNOTES:1.
DIMENSIONINGANDTOLERANCINGPERASMEY14.
5M,1994.
2.
CONTROLLINGDIMENSION:MILLIMETER.
3.
DATUMPLANEHISLOCATEDATBOTTOMOFLEADANDISCOINCIDENTWITHTHELEADWHERETHELEADEXITSTHEPLASTICBODYATTHEBOTTOMOFTHEPARTINGLINE.
4.
DATUMSA,B,ANDDTOBEDETERMINEDATDATUMPLANEH.
5.
DIMENSIONSDANDETOBEDETERMINEDATSEATINGPLANEC.
6.
DIMENSIONSD1ANDE1DONOTINCLUDEMOLDPROTRUSION.
ALLOWABLEPROTRUSIONIS0.
25PERSIDE.
DIMENSIONSD1ANDE1DOINCLUDEMOLDMISMATCHANDAREDETERMINEDATDATUMPLANEH.
7.
DIMENSIONbDOESNOTINCLUDEDAMBARPROTRUSION.
DAMBARPROTRUSIONSHALLNOTCAUSETHEbDIMENSIONTOEXCEED0.
35.
DIMMILLIMETERSMINMAXA---1.
60A10.
050.
15A21.
351.
45b0.
170.
27b10.
170.
23c0.
090.
20c10.
090.
16D22.
00BSCD120.
00BSCe0.
50BSCE16.
00BSCE114.
00BSCL0.
450.
75L11.
00REFL20.
50REFS0.
20---R10.
08---R20.
080.
2000o7o010o---0211o13o56F8335TechnicalData,Rev.
5160FreescaleSemiconductorPreliminaryPleaseseewww.
freescale.
comforthemostcurrentcaseoutline.
Part12DesignConsiderations12.
1ThermalDesignConsiderationsAnestimationofthechipjunctiontemperature,TJ,canbeobtainedfromtheequation:TJ=TA+(RθJΑxPD)where:Thejunction-to-ambientthermalresistanceisanindustry-standardvaluethatprovidesaquickandeasyestimationofthermalperformance.
Unfortunately,therearetwovaluesincommonusage:thevaluedeterminedonasingle-layerboardandthevalueobtainedonaboardwithtwoplanes.
ForpackagessuchasthePBGA,thesevaluescanbedifferentbyafactoroftwo.
Whichvalueisclosertotheapplicationdependsonthepowerdissipatedbyothercomponentsontheboard.
Thevalueobtainedonasingle-layerboardisappropriateforthetightlypackedprintedcircuitboard.
Thevalueobtainedontheboardwiththeinternalplanesisusuallyappropriateiftheboardhaslow-powerdissipationandthecomponentsarewellseparated.
Whenaheatsinkisused,thethermalresistanceisexpressedasthesumofajunction-to-casethermalresistanceandacase-to-ambientthermalresistance:RθJA=RθJC+RθCAwhere:RθJCisdevice-relatedandcannotbeinfluencedbytheuser.
Theusercontrolsthethermalenvironmenttochangethecase-to-ambientthermalresistance,RθCA.
Forinstance,theusercanchangethesizeoftheheatsink,theairflowaroundthedevice,theinterfacematerial,themountingarrangementonprintedcircuitboard,orchangethethermaldissipationontheprintedcircuitboardsurroundingthedevice.
Todeterminethejunctiontemperatureofthedeviceintheapplicationwhenheatsinksarenotused,theThermalCharacterizationParameter(ΨJT)canbeusedtodeterminethejunctiontemperaturewithameasurementofthetemperatureatthetopcenterofthepackagecaseusingthefollowingequation:TJ=TT+(ΨJTxPD)where:TA=Ambienttemperatureforthepackage(oC)RθJΑ=Junction-to-ambientthermalresistance(oC/W)PD=Powerdissipationinthepackage(W)RθJA=Packagejunction-to-ambientthermalresistance°C/WRθJC=Packagejunction-to-casethermalresistance°C/WRθCA=Packagecase-to-ambientthermalresistance°C/WTT=Thermocoupletemperatureontopofpackage(oC)ElectricalDesignConsiderations56F8335TechnicalData,Rev.
5FreescaleSemiconductor161PreliminaryThethermalcharacterizationparameterismeasuredperJESD51-2specificationusinga40-gaugetypeTthermocoupleepoxiedtothetopcenterofthepackagecase.
Thethermocoupleshouldbepositionedsothatthethermocouplejunctionrestsonthepackage.
Asmallamountofepoxyisplacedoverthethermocouplejunctionandoverabout1mmofwireextendingfromthejunction.
Thethermocouplewireisplacedflatagainstthepackagecasetoavoidmeasurementerrorscausedbycoolingeffectsofthethermocouplewire.
Whenheatsinkisused,thejunctiontemperatureisdeterminedfromathermocoupleinsertedattheinterfacebetweenthecaseofthepackageandtheinterfacematerial.
Aclearanceslotorholeisnormallyrequiredintheheatsink.
Minimizingthesizeoftheclearanceisimportanttominimizethechangeinthermalperformancecausedbyremovingpartofthethermalinterfacetotheheatsink.
Becauseoftheexperimentaldifficultieswiththistechnique,manyengineersmeasuretheheatsinktemperatureandthenback-calculatethecasetemperatureusingaseparatemeasurementofthethermalresistanceoftheinterface.
Fromthiscasetemperature,thejunctiontemperatureisdeterminedfromthejunction-to-casethermalresistance.
12.
2ElectricalDesignConsiderationsUsethefollowinglistofconsiderationstoassurecorrectoperationofthe56F8335/56F8135:Providealow-impedancepathfromtheboardpowersupplytoeachVDDpinonthedevice,andfromtheboardgroundtoeachVSS(GND)pinTheminimumbypassrequirementistoplacesix0.
01–0.
1μFcapacitorspositionedascloseaspossibletothepackagesupplypins.
TherecommendedbypassconfigurationistoplaceonebypasscapacitoroneachoftheVDD/VSSpairs,includingVDDA/VSSA.
Ceramicandtantalumcapacitorstendtoprovidebetterperformancetolerances.
EnsurethatcapacitorleadsandassociatedprintedcircuittracesthatconnecttothechipVDDandVSS(GND)pinsarelessthan0.
5inchpercapacitorleadΨJT=Thermalcharacterizationparameter(oC)/WPD=Powerdissipationinpackage(W)CAUTIONThisdevicecontainsprotectivecircuitrytoguardagainstdamageduetohighstaticvoltageorelectricalfields.
However,normalprecautionsareadvisedtoavoidapplicationofanyvoltageshigherthanmaximum-ratedvoltagestothishigh-impedancecircuit.
Reliabilityofoperationisenhancedifunusedinputsaretiedtoanappropriatevoltagelevel.
56F8335TechnicalData,Rev.
5162FreescaleSemiconductorPreliminaryUseatleastafour-layerPrintedCircuitBoard(PCB)withtwoinnerlayersforVDDandVSSBypasstheVDDandVSSlayersofthePCBwithapproximately100μF,preferablywithahigh-gradecapacitorsuchasatantalumcapacitorBecausethedevice'soutputsignalshavefastriseandfalltimes,PCBtracelengthsshouldbeminimalConsideralldeviceloadsaswellasparasiticcapacitanceduetoPCBtraceswhencalculatingcapacitance.
ThisisespeciallycriticalinsystemswithhighercapacitiveloadsthatcouldcreatehighertransientcurrentsintheVDDandVSScircuits.
TakespecialcaretominimizenoiselevelsontheVREF,VDDAandVSSApinsDesignsthatutilizetheTRSTpinforJTAGportorOnCEmodulefunctionality(suchasdevelopmentordebuggingsystems)shouldallowameanstoassertTRSTwheneverRESETisasserted,aswellasameanstoassertTRSTindependentlyofRESET.
Designsthatdonotrequiredebuggingfunctionality,suchasconsumerproducts,shouldtiethesepinstogether.
BecausetheFlashmemoryisprogrammedthroughtheJTAG/OnCEport,thedesignershouldprovideaninterfacetothisporttoallowin-circuitFlashprogramming12.
3PowerDistributionandI/ORingImplementationFigure12-1illustratesthegeneralpowercontrolincorporatedinthe56F8335/56F8135.
Thischipcontainstwointernalpowerregulators.
OneofthemispoweredfromtheVDDA_OSC_PLLpinandcannotbeturnedoff.
Thisregulatorcontrolspowertotheinternalclockgenerationcircuitry.
TheotherregulatorispoweredfromtheVDD_IOpinsandprovidespowertoalloftheinternaldigitallogicofthecore,allperipheralsandtheinternalmemories.
Thisregulatorcanbeturnedoff,ifanexternalVDD_COREvoltageisexternallyappliedtotheVCAPpins.
Insummary,theentirechipcanbesuppliedfromasingle3.
3voltsupplyifthelargecoreregulatorisenabled.
Iftheregulatorisnotenabled,adualsupply3.
3V/2.
5Vconfigurationcanalsobeused.
Notes:Flash,RAMandinternallogicarepoweredfromthecoreregulatoroutputVPP1andVPP2arenotconnectedinthecustomersystemAllcircuitry,analoganddigital,sharesacommonVSSbusFigure12-1PowerManagementREGCOREVCAPI/OADCVDDVSSREGVDDA_OSC_PLLOSCVSSA_ADCVDDA_ADCVREFHVREFPVREFMIDVREFNVREFLOPowerDistributionandI/ORingImplementation56F8335TechnicalData,Rev.
5FreescaleSemiconductor163PreliminaryPart13OrderingInformationTable13-1liststhepertinentinformationneededtoplaceanorder.
ConsultaFreescaleSemiconductorsalesofficeorauthorizeddistributortodetermineavailabilityandtoorderparts.
*ThispackageisRoHScompliant.
Table13-1OrderingInformationPartSupplyVoltagePackageTypePinCountFrequency(MHz)AmbientTemperatureRangeOrderNumberMC56F83353.
0–3.
6VLow-ProfileQuadFlatPack(LQFP)12860-40°to+105°CMC56F8335VFGE*MC56F83353.
0–3.
6VLow-ProfileQuadFlatPack(LQFP)12860-40°to+125°CMC56F8335MFGE*MC56F81353.
0–3.
6VLow-ProfileQuadFlatPack(LQFP)12840-40°to+105°CMC56F8135VFGE*HowtoReachUs:HomePage:www.
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Allrightsreserved.
MC56F8335Rev.
501/2007InformationinthisdocumentisprovidedsolelytoenablesystemandsoftwareimplementerstouseFreescaleSemiconductorproducts.
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