IOH0x00000006

24GHzVCOandPGAwith2-ChannelPAOutputDataSheetADF5901Rev.
BDocumentFeedbackInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
However,noresponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthatmayresultfromitsuse.
Specificationssubjecttochangewithoutnotice.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofAnalogDevices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
OneTechnologyWay,P.
O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781.
329.
47002015–2017AnalogDevices,Inc.
Allrightsreserved.
TechnicalSupportwww.
analog.
comFEATURES24GHzto24.
25GHzvoltagecontrolledoscillator(VCO)2-channel24GHzpoweramplifier(PA)with8dBmoutputSingle-endedoutputs2-channelmuxedoutputswithmutefunctionProgrammableoutputpowerNdivideroutput(frequencydiscriminator)24GHzlocaloscillator(LO)outputbuffer250MHzsignalbandwidthPowercontroldetectorAuxiliary8-bitADC±5°Ctemperaturesensor4-wireserialperipheralinterface(SPI)Electrostaticdischarge(ESD)performanceHumanbodymodel(HBM):2000VChargeddevicemodel(CDM):250VQualifiedforautomotiveapplicationsAPPLICATIONSAutomotiveradarsIndustrialradarsMicrowaveradarsensorsIndustrialsensorsPrecisioninstrumentationTanklevelsensorsSmartsensorsDooropeningEnergysavingCommercialsensors:objectdetectionandtrackingCars,boats,aircraft,andUAVs(drones):collisionavoidanceIntelligenttransportationsystems:intelligenttrafficmonitoringandcontrolSurveillanceandsecurityGENERALDESCRIPTIONTheADF5901isa24GHzTxmonolithicmicrowaveintegratedcircuit(MMIC)withanon-chip,24GHzVCOwithPGAanddualTxchannelsforradarsystems.
Theon-chip,24GHzVCOgeneratesthe24GHzsignalforthetwoTxchannelsandtheLOoutput.
EachTxchannelcontainsapowercontrolcircuit.
Thereisalsoanon-chiptemperaturesensor.
Controlofalltheon-chipregistersisthroughasimple4-wireinterface.
TheADF5901comesinacompact32-lead,5mm*5mmLFCSPpackage.
FUNCTIONALBLOCKDIAGRAMFigure1.
TXOUT1TXOUT2LOOUTVTUNERSETGNDTX_AHIATESTRF_AHIAHIDVDDVREGC1C2MUXOUTAUXAUXVCO_AHIREFINN-DIVIDERVCOCALR-DIVIDERTEMPERATURESENSORADC32-BITDATAREGISTERDOUTLEDATACLKCE÷2÷2REFERENCEREGULATORADCADCADF590113336-001ADF5901*PRODUCTPAGEQUICKLINKSLastContentUpdate:08/15/2017COMPARABLEPARTSViewaparametricsearchofcomparableparts.
EVALUATIONKITSADF5901EvaluationBoardEvaluationBoardfortheADF5901,ADF5904,andADF4159Chipsetfora24GHzFMCWRadarRadarDemonstrationPlatform.
EvaluatesRadarchipsetincludingtheADF5901,ADF5904andADF4159.
DOCUMENTATIONDataSheetADF5901:24GHzVCOandPGAwith2-ChannelPAOutputDataSheetProductHighlightDEMORADAnalogDevices24GHzRadarSensorPlatformUserGuidesUG-864:EvaluatingtheADF590124GHzVoltageControlledOscillator(VCO)andProgrammableGainAmplifier(PGA)witha2-ChannelPowerAmplifier(PA)OutputUG-866:EvaluationBoardfortheADF5901,ADF5904,andADF4159Chipsetfora24GHzFMCWRadarSOFTWAREANDSYSTEMSREQUIREMENTSADF5901andADF4159EvaluationBoardSoftwareEV-RADAR-MMICEvaluationSoftwareTOOLSANDSIMULATIONSADF5901S-ParametersREFERENCEMATERIALSTechnicalArticlesHighPerformanceIntegrated24GHzFMCWRadarTransceiverChipsetforAutoandIndustrialSensorApplicationsDESIGNRESOURCESADF5901MaterialDeclarationPCN-PDNInformationQualityAndReliabilitySymbolsandFootprintsDISCUSSIONSViewallADF5901EngineerZoneDiscussions.
SAMPLEANDBUYVisittheproductpagetoseepricingoptions.
TECHNICALSUPPORTSubmitatechnicalquestionorfindyourregionalsupportnumber.
DOCUMENTFEEDBACKSubmitfeedbackforthisdatasheet.
ThispageisdynamicallygeneratedbyAnalogDevices,Inc.
,andinsertedintothisdatasheet.
Adynamicchangetothecontentonthispagewillnottriggerachangetoeithertherevisionnumberorthecontentoftheproductdatasheet.
Thisdynamicpagemaybefrequentlymodified.
ADF5901DataSheetRev.
B|Page2of26TABLEOFCONTENTSFeatures1Applications.
1GeneralDescription.
1FunctionalBlockDiagram1RevisionHistory2Specifications.
3TimingSpecifications4AbsoluteMaximumRatings.
6ESDCaution.
6PinConfigurationandFunctionDescriptions.
7TypicalPerformanceCharacteristics9TheoryofOperation11ReferenceInputSection.
11RFINTDivider.
11INT,FRAC,andRRelationship11RCounter11InputShiftRegister.
11ProgramModes11RegisterMaps.
13Register015Register116Register2.
17Register3.
18Register4.
19Register5.
20Register6.
20Register7.
21Register8.
22Register9.
22Register10.
23Register11.
23InitializationSequence23RecalibrationSequence23TemperatureSensor24RFSynthesis:aWorkedExample.
24ApplicationsInformation.
25ApplicationoftheADF5901inFMCWRadar25OutlineDimensions.
26OrderingGuide26AutomotiveProducts.
26REVISIONHISTORY8/2017—Rev.
AtoRev.
BChangestoFigure17.
13ChangestoFigure20.
17UpdatedOutlineDimensions.
27ChangestoOrderingGuide277/2016—Rev.
0toRev.
AChangestoApplicationsSection.
1ChangestoInitializationSequenceSectionandRecalibrationSequenceSection.
2312/2015—Revision0:InitialVersionDataSheetADF5901Rev.
B|Page3of26SPECIFICATIONSAHI=TX_AHI=RF_AHI=VCO_AHI=DVDD=3.
3V±5%,AGND=0V,dBmreferredto50,TA=TMAXtoTMIN,unlessotherwisenoted.
Operatingtemperaturerangeis40°Cto+105°C.
Table1.
ParameterMinTypMaxUnitTestConditions/CommentsOPERATINGCONDITIONSRFFrequencyRange2424.
25GHzVCOCHARACTERISITICSVTUNE12.
8VVTUNEImpedance100kVCOPhaseNoisePerformanceAt100kHzOffset88dBc/HzAt1MHzOffset108dBc/HzAt10MHzOffset128dBc/HzAmplitudeNoise150dBc/HzAt1MHzoffsetStaticPullingfVCOChangevs.
Load±2MHzOpen-loopinto2:1voltagestandingwaveratio(VSWR)loadDynamicPullingTxOn/OffSwitchChange±10MHzOpen-loopDynamicPullingTxtoTxSwitchChange±5MHzOpen-loopPushingfVCOChangevs.
AHIChange±5MHz/VOpen-loopSpuriousLevelHarmonics30dBcSpuriousLevelNonharmonics25V/sREFINInputCapacitance1.
2pFREFINInputCurrent±100ALOGICINPUTSInputVoltageHigh(VIH)1.
4VLow(VIL)0.
6VInputCurrent(IINH,IINL)±1AInputCapacitance(CIN)10pFLOGICOUTPUTSOutputVoltageHigh(VOH)2VDD0.
4VLow(VOL)0.
4VOutputCurrentHigh(IOH)500ALow(IOL)500A1TA=25°C;AHI=3.
3V;fREFIN=100MHz;RF=24.
125GHzfollowinginitializationsequenceintheInitializationSequencesection.
2VDDselectedfromIOlevelbit(DB11inRegister3).
TIMINGSPECIFICATIONSAHI=TX_AHI=RF_AHI=VCO_AHI=DVDD=3.
3V±5%,AGND=0V,dBmreferredto50,TA=TMINtoTMAX,unlessotherwisenoted.
Operatingtemperaturerangeis40°Cto+105°C.
Table2.
WriteTimingParameterLimitatTMINtoTMAXUnitDescriptiont120nsminLEsetuptimet210nsminDATAtoCLKsetuptimet310nsminDATAtoCLKholdtimet425nsminCLKhighdurationt525nsminCLKlowdurationt610nsminCLKtoLEsetuptimet720nsminLEpulsewidtht810nsmaxLEsetuptimetoDOUTt915nsmaxCLKsetuptimetoDOUTDataSheetADF5901Rev.
B|Page5of26WriteTimingDiagramFigure2.
WriteTimingDiagramFigure3.
LoadCircuitforDOUT/MUXOUTTiming,CL=10pFCLKDATALEDB30DB1(CONTROLBITC2)DB2(CONTROLBITC3)DB0(LSB)(CONTROLBITC1)t1t2t3t4t5t7t6DB31(MSB)DB0DB1t8t9DB31(MSB)DB30DOUT13336-002500AIOL500AIOHVDD/2TODOUTANDMUXOUTPINSCL10pF13336-003ADF5901DataSheetRev.
B|Page6of26ABSOLUTEMAXIMUMRATINGSTable3.
ParameterRatingAHItoGND0.
3Vto+3.
9VAHItoTX_AHI0.
3Vto+0.
3VAHItoRF_AHI0.
3Vto+0.
3VAHItoVCO_AHI0.
3Vto+0.
3VAHItoDVDD0.
3Vto+0.
3VVTUNEtoGND0.
3Vto+3.
6VDigitalInput/OutputVoltagetoGND0.
3VtoDVDD+0.
3VOperatingTemperatureRange40°Cto+105°CStorageTemperatureRange65°Cto+150°CMaximumJunctionTemperature150°CθJAThermalImpedance1(PaddleSoldered)40.
83°C/WReflowSolderingPeakTemperature260°CTimeatPeakTemperature40secTransistorCountCMOS177,381Bipolar2315ESDChargedDeviceModel250VHumanBodyModel2000V1Twosignalplanes(thatis,ontopandbottomsurfacesoftheboard),twoburiedplanes,andninevias.
StressesatorabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetotheproduct.
Thisisastressratingonly;functionaloperationoftheproductattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Operationbeyondthemaximumoperatingconditionsforextendedperiodsmayaffectproductreliability.
ESDCAUTIONDataSheetADF5901Rev.
B|Page7of26PINCONFIGURATIONANDFUNCTIONDESCRIPTIONSFigure4.
PinConfigurationTable4.
PinFunctionDescriptionsPinNo.
MnemonicDescription1,3,6,8,10,12,13,19GNDRFGround.
Tieallgroundpinstogether.
2TXOUT124GHzTxOutput1.
4,5TX_AHIVoltageSupplyfortheTxSection.
Connectdecouplingcapacitors(0.
1μF,1nF,and10pF)tothegroundplaneascloseaspossibletothispin.
TX_AHImustbethesamevalueasAHI.
7TXOUT224GHzTxOutput2.
9ATESTAnalogTestPin.
11LOOUTLOOutput.
14RF_AHIVoltageSupplyfortheRFSection.
Connectdecouplingcapacitors(0.
1μF,1nF,and10pF)tothegroundplaneascloseaspossibletothispin.
RF_AHImustbethesamevalueasAHI.
15REFINReferenceInput.
ThispinisaCMOSinputwithanominalthresholdofDVDD/2andadcequivalentinputresistanceof100k.
SeeFigure14.
ThisinputcanbedrivenfromaTTLorCMOScrystaloscillator,oritcanbeac-coupled.
16AHIVoltageSupplyfortheAnalogSection.
Connectdecouplingcapacitors(0.
1μF,1nF,and10pF)tothegroundplaneascloseaspossibletothispin.
17DVDDDigitalPowerSupply.
Thissupplymayrangefrom3.
135Vto3.
465V.
Placedecouplingcapacitors(0.
1μF,1nF,and10pF)tothegroundplaneascloseaspossibletothispin.
DVDDmustbethesamevalueasAHI.
18VREGInternal1.
8VRegulatorOutput.
Connecta220nFcapacitortogroundascloseaspossibletothispin.
20CEChipEnable.
Alogiclowonthispinpowersdownthedevice.
Takingthepinhighpowersupthedevice,dependingonthestatusofthepower-downbit,PD1.
21CLKSerialClockInput.
Thisserialclockinputclocksintheserialdatatotheregisters.
Thedataislatchedintothe32-bitshiftregisterontheCLKrisingedge.
ThisinputisahighimpedanceCMOSinput.
22DATASerialDataInput.
TheserialdataisloadedMSBfirstwiththefourLSBsasthecontrolbits.
ThisinputisahighimpedanceCMOSinput.
23LELoadEnable,CMOSInput.
WhenLEgoeshigh,thedatastoredintheshiftregistersisloadedintooneofthe16latcheswiththelatchselectedviathecontrolbits.
24DOUTSerialDataOutput.
25MUXOUTMultiplexerOutput.
ThismultiplexeroutputallowseitherthescaledRForthescaledreferencefrequencytobeaccessedexternally.
26RSETResistorSettingPin.
Connectinga5.
1kresistorbetweenthispinandGNDsetsaninternalcurrent.
ThenominalvoltagepotentialattheRSETpinis0.
62V.
27AUXAuxiliaryOutput.
TheVCO/2outputorVCO/4isavailable.
28AUXComplementaryAuxiliaryOutput.
TheVCO/2outputorVCO/4isavailable.
GNDNOTES1.
THELFCSPHASANEXPOSEDPADTHATMUSTBECONNECTEDTOGND.
TXOUT1GNDTX_AHITX_AHIGNDTXOUT2GNDDOUTLEDATACLKCEGNDVREGDVDDATESTGNDLOOUTGNDGNDRF_AHIREFINAHIC2C1VCO_AHIVTUNEAUXAUXRSETMUXOUT2423222120191817123456789101112131415163231302928272625ADF5901TOPVIEW(NottoScale)13336-004ADF5901DataSheetRev.
B|Page8of26PinNo.
MnemonicDescription29VTUNEControlInputtotheVCO.
Thisvoltagedeterminestheoutput.
30VCO_AHIVoltageSupplyfortheVCOSection.
Connectdecouplingcapacitors(0.
1μF,1nF,and10pF)tothegroundplaneascloseaspossibletothispin.
VCO_AHImustbethesamevalueasAHI.
31C1DecouplingCapacitor1.
Placea47nFcapacitortogroundascloseaspossibletothispin.
32C2DecouplingCapacitor2.
Placea220nFcapacitortogroundascloseaspossibletothispin.
EPExposedPad.
TheLFCSPhasanexposedpadthatmustbeconnectedtoGND.
DataSheetADF5901Rev.
B|Page9of26TYPICALPERFORMANCECHARACTERISTICSFigure5.
TxOutputPowervs.
OutputFrequencyFigure6.
Transmitter1(Tx1)OutputPowerVariationwithTemperatureandSupplyvs.
OutputFrequencyFigure7.
TxOutputPowervs.
TxAmplitudeCalibrationReferenceCodeFigure8.
LOOutputPowervs.
OutputFrequencyFigure9.
AUX/AUXOutputPowervs.
OutputFrequencywithDivideby2SelectedFigure10.
AUX/AUXOutputPowervs.
OutputFrequencywithDivideby4Selected02468101223.
9524.
0024.
0524.
1024.
1524.
2024.
2524.
30OUTPUTPOWER(dBm)OUTPUTFREQUENCY(GHz)–40°C+25°C+105°CTx1Tx213336-005OUTSIDEOFSPECIFIEDRANGE02468101223.
9524.
0024.
0524.
1024.
1524.
2024.
2524.
30OUTPUTPOWER(dBm)OUTPUTFREQUENCY(GHz)–40°C+25°C+105°C3.
300V3.
465V3.
135V13336-006OUTSIDEOFSPECIFIEDRANGE–20–15–10–50510150102030405060708090100OUTPUTPOWER(dBm)TxAMPLITUDECALIBRATIONREFERENCECODE–40°C+25°C+105°C13336-007–8–6–4–2042623.
9524.
0024.
0524.
1024.
1524.
2024.
2524.
30OUTPUTPOWER(dBm)OUTPUTFREQUENCY(GHz)–40°C+25°C+105°COUTSIDEOFSPECIFIEDRANGE13336-008–10–9–8–7–6–5–4–3–2–1011.
9912.
0112.
0312.
0512.
0712.
0912.
1112.
13OUTPUTPOWER(dBm)OUTPUTFREQUENCY(GHz)–40°C+25°C+105°CAUXAUXOUTSIDEOFSPECIFIEDRANGE13336-009–5–4–3–2–10123455.
996.
006.
016.
026.
036.
046.
056.
066.
07OUTPUTPOWER(dBm)–40°C+25°C+105°CAUXAUXOUTSIDEOFSPECIFIEDRANGEOUTPUTFREQUENCY(GHz)13336-010ADF5901DataSheetRev.
B|Page10of26Figure11.
VTUNEFrequencyRangeFigure12.
Open-LoopPhaseNoiseonTx1Outputat24.
125GHzFigure13.
ATESTVoltageandADCCodevs.
Temperature00.
51.
01.
52.
02.
53.
03.
523.
7523.
8824.
1024.
1324.
2524.
3824.
50VTUNE(V)OUTPUTFREQUENCY(GHz)13336-011–40°C+25°C+105°COUTSIDEOFSPECIFIEDRANGE–150–140–130–120–110–100–90–80–70–60–50–40–30–20–1001k10k100k1M10MPHASENOISE(dBc/Hz)FREQUENCYOFFSET(Hz)13336-01205010015020025000.
20.
40.
60.
81.
01.
21.
41.
61.
8–40–30–20–100102030405060708090100110120ADCCODE(Count)ATEST(V)TEMPERATURE(C)13336-013DataSheetADF5901Rev.
B|Page11of26THEORYOFOPERATIONREFERENCEINPUTSECTIONThereferenceinputstageisshowninFigure14.
SW1andSW2arenormallyclosedswitches.
SW3isnormallyopen.
Whenpower-downisinitiated,SW3isclosedandSW1andSW2areopened.
ThisconfigurationensuresthatthereisnoloadingoftheREFINpinonpower-down.
Figure14.
ReferenceInputStageRFINTDIVIDERTheRFINTcounterallowsadivisionratiointheRFfeedbackcounter.
Divisionratiosfrom75to4095areallowed.
INT,FRAC,ANDRRELATIONSHIPGeneratetheRFVCOfrequency(RFOUT)usingtheINTandFRACvaluesinconjunctionwiththeRcounter,asfollows:RFOUT=fREF*(INT+(FRAC/225))*2(1)where:RFOUTistheoutputfrequencyofinternalVCO.
fREFistheinternalreferencefrequency.
INTisthepresetdivideratioofthebinary12-bitcounter(75to4095).
FRACisthenumeratorofthefractionaldivision(0to2251).
fREF=REFIN*((1+D)/(R*(1+T)))(2)where:REFINisthereferenceinputfrequency.
DistheREFINdoublerbit(0or1).
Risthepresetdivideratioofthebinary,5-bit,programmablereferencecounter(1to32).
TistheREFINdivideby2bit(0or1).
Figure15.
RFNDividerFigure16.
ReferenceDividerRCOUNTERThe5-bitRcounterallowstheinputreferencefrequency(REFIN)tobedivideddowntosupplythereferenceclocktotheVCOcalibrationblock.
Divisionratiosfrom1to32areallowed.
INPUTSHIFTREGISTERTheADF5901digitalsectionincludesa5-bitRFRcounter,a12-bitRFNcounter,anda25-bitFRACcounter.
Dataisclockedintothe32-bitinputshiftregisteroneachrisingedgeofCLK.
ThedataisclockedinMSBfirst.
Dataistransferredfromtheinputshiftregistertooneof12latchesontherisingedgeofLE.
Thedestinationlatchisdeterminedbythestateofthefivecontrolbits(C5,C4,C3,C2,andC1)intheinputshiftregister.
ThesearethefiveLSBs(DB4,DB3,DB2,DB1,andDB0,respectively),asshowninFigure2.
Table5showsthetruthtableforthesebits.
Figure17andFigure18showasummaryofhowthelatchesareprogrammed.
PROGRAMMODESTable5andFigure19throughFigure30showhowtosetuptheprogrammodesintheADF5901.
SeveralsettingsintheADF5901aredoublebuffered.
TheseincludetheLSBfractionalvalue,Rcountervalue(Rdivider),referencedoubler,clockdivider,RDIV2,andMUXOUT.
Thismeansthattwoeventsmustoccurbeforethedeviceusesanewvalueforanyofthedouble-bufferedsettings.
First,thenewvalueislatchedintothedevicebywritingtotheappropriateregister.
Second,anewwritemustbeperformedonRegisterR5.
Forexample,updatingthefractionalvaluecaninvolveawritetothe13LSBbitsinRegisterR6andthe12MSBbitsinRegisterR5.
WritetoRegisterR6first,followedbythewritetoRegisterR5.
ThefrequencychangebeginsafterthewritetoRegisterR0.
DoublebufferingensuresthatthebitswrittentoinRegisterR6donottakeeffectuntilafterthewritetoRegisterR5.
BUFFERTORCOUNTERREFIN100kNCSW2SW3NONCSW1POWER-DOWNCONTROL13336-014THIRD-ORDERFRACTIONALINTERPOLATORFRACVALUEINTREGRFNDIVIDERN=INT+FRAC/225FROMRFINPUTSTAGETOCALBLOCKNCOUNTER13336-015*2DOUBLER5-BITRCOUNTER÷2DIVIDERTOCALBLOCKREFINRDIVIDER13336-016ADF5901DataSheetRev.
B|Page12of26Table5.
C5,C4,C3,C2,andC1TruthTableControlBitsC5(DB4)C4(DB3)C3(DB2)C2(DB1)C1(DB0)Register00000R000001R100010R200011R300100R400101R500110R600111R701000R801001R901010R1001011R11DataSheetADF5901Rev.
B|Page13of26REGISTERMAPSFigure17.
RegisterSummary(Register0toRegister6)1DBR=DOUBLEBUFFEREDREGISTER—BUFFEREDBYTHEWRITETOREGISTER5.
REGISTER0(R0)REGISTER1(R1)REGISTER3(R3)REGISTER4(R4)REGISTER2(R2)REGISTER5(R5)REGISTER6(R6)DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB010000000CONTROLBITSAG2AG1AG0AD1111PRCPNC1Tx2CTx1CPVCOVCALPADCPTx2PTx1PLOC4(0)C3(0)C2(0)C1(0)C5(0)PUPLOPUPTx1PUPTx2PUPADCVCOCALPUPVCOTx1AMPCALTx2AMPCALPUPNCNTRPUPRCNTRAUXDIVRESERVEDAUXBUFFERGAINRESERVEDRESERVEDDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB011111111CONTROLBITS11110111111C4(0)C3(0)C2(0)C1(1)TxAMPCALREFCODEC5(0)TAR7TAR6TAR5TAR4TAR3TAR2TAR1TAR0DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000000000CONTROLBITS0000010ASAA0AA0AC7AC6AC5AC4AC3AC2AC1AC0C4(0)C3(0)C2(1)C1(0)RESERVEDADCCLOCKDIVIDERADCAVERAGEADCSTARTC5(0)DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB00000000110001001M3M2M1M0IOLRC5RC4RC3RC2RC1RC0C4(0)C3(0)C2(1)C1(1)CONTROLBITSMUXOUTRESERVEDC5(0)READBACKCONTROLIOLEVELDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB000000000AB9AB8AB7AB6AB5AB4AB3AB2AB1AB0C4(0)C3(1)C2(0)C1(0)CONTROLBITSRESERVEDRESERVEDTESTBUSTOPIN00NDM0000TBATBPANALOGTESTBUSC5(0)TESTBUSTOADCDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000N11N10N9N8N7N6N5N4N3N2N1N0F24F23F22F21F20F19F18F17F16F15F14F13C4(0)C3(1)C2(0)C1(1)CONTROLBITSRESERVEDFRACMSBWORDINTEGERWORDC5(0)DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB000000000000000F12F11F10F9F8F7F6F5F4F3F2F1F0C4(0)C3(1)C2(1)C1(0)CONTROLBITSFRACLSBWORDC5(0)DBR1RESERVEDRESERVEDDBR113336-017NDIVTOMUXOUTENADF5901DataSheetRev.
B|Page14of26Figure18.
RegisterSummary(Register7toRegister11)1DBR=DOUBLEBUFFEREDREGISTER—BUFFEREDBYTHEWRITETOREGISTER5.
REGISTER7(R7)REGISTER8(R8)REGISTER10(R10)REGISTER9(R9)DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000000MR1CONTROLBITSRD2RDR4R3R2R1R0C4(0)C3(1)C2(1)C1(1)C5(0)REFDOUBLERRDIV2RESERVEDMASTERRESETRDIVIDERDBR1DBR1DBR1DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB001000000CONTROLBITS000000000FC9FC8FC7FC6FC5FC4FC3FC2FC1FC0C4(1)C3(0)C2(0)C1(0)FREQENCYCALDIVIDERC5(0)RESERVEDDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0001010100CONTROLBITS010000010111001001C4(1)C3(0)C2(0)C1(1)C5(0)RESERVEDDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000111010011001010100110010C4(1)C3(0)C2(1)C1(0)CONTROLBITSRESERVEDC5(0)CLOCKDIVIDERC1D11C1D10C1D9C1D8C1D7C1D6C1D5C1D4C1D3C1D2C1D1C1D0DBR1RESERVEDDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB000000000000000000000000000CRC4(1)C3(0)C2(1)C1(1)CONTROLBITSRESERVEDC5(0)REGISTER11(R11)CNTRRESET13336-018DataSheetADF5901Rev.
B|Page15of26Figure19.
Register0(R0)REGISTER0ControlBitsWithBits[C5:C1]setto00000,RegisterR0isprogrammed.
Figure19showstheinputdataformatforprogrammingthisregister.
AuxiliaryBufferGainBits[DB23:DB21]settheauxiliaryoutputbuffergain(seeFigure19).
AuxiliaryDivideby2BitDB20selectstheauxiliaryoutputdivider.
Settingthisbitto0selectsdivideby2(6GHzoutput).
Settingthebitto1selectsdivideby1(12GHzoutput).
Power-UpRCounterBitDB15providesthepower-upbitfortheRcounterblock.
Settingthisbitto0performsapower-downofthecounterblock.
Settingthisbitto1returnsthecounterblocktonormaloperation.
Power-UpNCounterBitDB14providesthepower-upbitfortheNcounterblock.
Settingthisbitto0performsapower-downofthecounterblock.
Settingthisbitto1returnsthecounterblocktonormaloperation.
Tx2AmplitudeCalibrationBitDB12providesthecontrolbitforamplitudecalibrationoftheTransmitter2(Tx2)output.
Setthisbitto0fornormaloperation.
Settingthisbitto1performsanamplitudecalibrationoftheTx2output.
Tx1AmplitudeCalibrationBitDB11providesthecontrolbitforamplitudecalibrationoftheTx1output.
Setthisbitto0fornormaloperation.
Settingthisbitto1performsanamplitudecalibrationoftheTx1output.
Power-UpVCOBitDB10providesthepower-upbitfortheVCO.
Settingthisbitto0performsapower-downoftheVCO.
Settingthisbitto1performsapower-upoftheVCO.
DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB010000000CONTROLBITSAG2AG1AG0AD1111PRCPNC1Tx2CTx1CPVCOVCALPADCPTx2PTx1PLOC4(0)C3(0)C2(0)C1(0)C5(0)PUPLOPUPTx1PUPTx2PUPADCVCOCALPUPVCOTx1AMPCALTx2AMPCALPUPNCNTRPUPRCNTRAUXDIVRESERVEDAUXBUFFERGAINPLO01PUPLOPOWERUPLOPOWERDOWNLOPTx101PUPTx1POWERUPTx1POWERDOWNTx1PTx201PUPTx2POWERUPTx2POWERDOWNTx2PADC01PUPADCPOWERUPADCPOWERDOWNADCVCAL01VCOCALVCOFULLCALNORMALOPERATIONPVCO01PUPVCOPOWERUPVCOPOWERDOWNVCOTx1C01Tx1AMPCALTx1AMPCALNORMALOPERATIONTx2C01Tx2AMPCALTx2AMPCALNORMALOPERATIONAD01AUXDIVDIV1DIV2PNC01PUPNCNTRPOWERUPNCNTRPOWERDOWNNCNTRPNC01PUPRCNTRPOWERUPRCNTRPOWERDOWNRCNTRAG2AG1AG0AUXBUFFERGAIN000BUFFERDISABLED001GAINSETTING1010GAINSETTING2011GAINSETTING3100GAINSETTING4101GAINSETTING5110GAINSETTING6111GAINSETTING7RESERVEDRESERVED13336-019ADF5901DataSheetRev.
B|Page16of26VCOCalibrationBitDB9providesthecontrolbitforfrequencycalibrationoftheVCO.
Setthisbitto0fornormaloperation.
Settingthisbitto1performsaVCOfrequencyandamplitudecalibration.
Power-UpADCBitDB8providesthepower-upbitfortheADC.
Settingthisbitto0performsapower-downoftheADC.
Settingthisbitto1performsapower-upoftheADC.
Power-UpTx2OutputBitDB7providesthepower-upbitfortheTx2output.
Settingthisbitto0performsapower-downoftheTx2output.
Settingthisbitto1performsapower-upoftheTx2output.
OnlyoneTxoutputcanbepoweredupatanytime,eitherTx1(DB6)orTx2(DB7).
Power-UpTx1OutputBitDB6providesthepower-upbitfortheTx1output.
Settingthisbitto0performsapower-downoftheTx1output.
Settingthisbitto1performsapower-upoftheTx1output.
OnlyoneTxoutputcanbepoweredupatanytime,eitherTx1(DB6)orTx2(DB7).
Power-UpLOOutputBitDB5providesthepower-upbitfortheLOoutput.
Settingthisbitto0performsapower-downoftheLOoutput.
Settingthisbitto1performsapower-upoftheLOoutput.
REGISTER1ControlBitsWithBits[C5:C1]setto00001,RegisterR1isprogrammed.
Figure20showstheinputdataformatforprogrammingthisregister.
TxAmplitudeCalibrationReferenceCodeBits[DB12:DB5]settheTxamplitudecalibrationreferencecode(seeFigure20)forthetwoTxoutputsduringcalibration.
CalibratetheoutputpowerontheTxoutputsfrom20dBmto8dBmbysettingtheTxamplitudecalibrationreferencecode(seeFigure7).
Figure20.
Register1(R1)DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB011111111CONTROLBITS11110111111C4(0)C3(0)C2(0)C1(1)TxAMPCALREFCODEC5(0)TAR7TAR6TAR5TAR4TAR3TAR2TAR1TAR0TAR7TAR6TAR1TAR0000000001100102001131100252110125311102541111255TxAMPCALREFCODERESERVED13336-020DataSheetADF5901Rev.
B|Page17of26Figure21.
Register2(R2)REGISTER2ControlBitsWithBits[C5:C1]setto00010,RegisterR2isprogrammed.
Figure21showstheinputdataformatforprogrammingthisregister.
ADCStartBitDB15startstheADCconversion.
Settingthisbitto1startsanADCconversion.
ADCAverageBits[DB14:DB13]programtheADCaverage,whichisthenumberofaveragesoftheADCoutput(seeFigure21).
ADCClockDividerBits[DB12:DB5]programtheclockdivider,whichisusedasthesamplingclockfortheADC(seeFigure21).
TheoutputoftheRdividerblockclockstheADCclockdivider.
ProgramadividervaluetoensuretheADCsamplingclockis1MHz.
DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000000000CONTROLBITS0000010ASAA0AA0AC7AC6AC5AC4AC3AC2AC1AC0C4(0)C3(0)C2(1)C1(0)RESERVEDADCCLOCKDIVIDERADCAVERAGEADCSTARTC5(0)AC7AC6AC1AC0ADCCLOCKDIVIDER00011001021100124110112511101261111127.
.
.
.
.
.
.
.
.
.
AS01ADCSTARTSTARTADCCONVERSIONNORMALOPERATIONAA1AA0ADCAVERAGE00101210311413336-021ADF5901DataSheetRev.
B|Page18of26Figure22.
Register3(R3)REGISTER3ControlBitsWithBits[C5:C1]setto00011,RegisterR3isprogrammed.
Figure22showstheinputdataformatforprogrammingthisregister.
MUXOUTControlBits[DB15:DB12]controltheon-chipmultiplexeroftheADF5901.
SeeFigure22forthetruthtable.
Input/Output(IO)LevelBitDB11controlstheDOUTlogiclevels.
Settingthisbitto0setstheDOUTlogiclevelto1.
8V.
Settingthisbitto1setstheDOUTlogiclevelto3.
3V.
ReadbackControlBits[DB10:DB5]controlthereadbackdatatoDOUTontheADF5901.
SeeFigure22forthetruthtable.
DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB00000000110001001M3M2M1M0IOLRC5RC4RC3RC2RC1RC0C4(0)C3(0)C2(1)C1(1)CONTROLBITSRESERVEDC5(0)READBACKCONTROLIOLEVELRC3RC2RC1RC0READBACKCONTROL0000NONE0001REGISTER00010REGISTER10011REGISTER20100REGISTER30101REGISTER40110REGSITER50111REGISTER61000REGISTER71001REGISTER81010REGISTER91011REGISTER101100REGISTER11.
.
.
.
RESERVED0101RESERVED0110ADCREADBACKRC40000000000000.
110111RESERVED.
.
.
.
RESERVED.
.
.
.
RESERVED1111RESERVED1.
.
1M3M2M1M0MUXOUT0000TRISTATEOUTPUT0001LOGICHIGH0010LOGICLOW0011R-DIVIDEROUTPUT0100N-DIVIDEROUTPUT0101RESERVED0110RESERVED0111CALBUSY1000RESERVED1001RESERVED1010RESERVED1011R-DIVIDER/21100N-DIVIDER/21101RESERVED1110RESERVED1111RESERVEDRC50000000000000.
000.
.
1IOL01IOLEVEL3.
3VLOGICOUTPUTS1.
8VLOGICOUTPUTS1DBR=DOUBLE-BUFFEREDREGISTER.
MUXOUTDBR110849-022DataSheetADF5901Rev.
B|Page19of26Figure23.
Register4(R4)Figure24.
Register5(R5)REGISTER4ControlBitsWithBits[C5:C1]setto00100,RegisterR4isprogrammed.
Figure23showstheinputdataformatforprogrammingthisregister.
NDividertoMUXOUTEnableBitDB21controlstheinternalNdividersignalforMUXOUT.
Settingthisbitto0enablestheinternalNdividersignaltoMUXOUT.
Settingthisbitto1returnsthedevicetonormaloperation.
TestBustoADCBitDB16controlstheATESTpin.
Setthisbitto0fornormaloperation.
Settingthisbitto1connectstheanalogtestbustotheADCinput.
TestBustoPinBitDB15controlstheATESTpin.
Settingthisbitto0setstheATESTpintohighimpedance.
Settingthisbitto1connectstheanalogtestbustotheATESTpin.
AnalogTestBusBits[DB14:DB5]controltheanalogtestbus.
Thisanalogtestbusallowsaccesstointernaltestsignalsforthetemperaturesensor.
SeeFigure23forthetruthtable.
DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB000000000AB9AB8AB7AB6AB5AB4AB3AB2AB1AB0C4(0)C3(1)C2(0)C1(0)CONTROLBITSRESERVEDRESERVEDTESTBUSTOPIN00NDM0000TBATBPANALOGTESTBUSC5(0)TESTBUSTOADCTBP01TESTBUSTOPINTESTBUSTOPINNORMALOPERATIONNDM01NDIVTOMUXOUTENNORMALOPERATIONENABLENDIVTOMUXOUTTBA01TESTBUSTOADCTESTBUSTOADCNORMALOPERATIONAB3AB2AB1AB000000011ANALOGTESTBUSAB7AB6AB5AB400000000AB9AB800010259NONETEMPERATURESENSOR13336-023NDIVTOMUXOUTENDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000N11N10N9N8N7N6N5N4N3N2N1N0F24F23F22F21F20F19F18F17F16F15F14F13C4(0)C3(1)C2(0)C1(1)CONTROLBITSRESERVEDFRACMSBWORDINTEGERWORDC5(0)N11N10.
.
.
N4N3N2N1N000.
.
.
00000NOTALLOWED00.
.
.
00001NOTALLOWED00.
.
.
00010NOTALLOWED00.
.
.
01010NOTALLOWED00.
.
.
010117500.
.
.
011007611.
.
.
11101409311.
.
.
11110409411.
.
.
111114095F24F23F14F13(FRAC)*0000000011001020011311004092110140931110409411114095*THEFRACVALUEISMADEUPOFTHE12-BITMSBSTOREDINREGISTERR5,ANDTHE13-BITLSBREGISTERSTOREDINREGISTERR6.
FRACVALUE=13-BITLSB+12-BITMSB*213.
INTEGERWORDFRACMSBWORD13336-024ADF5901DataSheetRev.
B|Page20of26REGISTER5ControlBitsWithBits[C5:C1]setto00101,RegisterR5isprogrammed.
Figure24showstheinputdataformatforprogrammingthisregister.
12-BitIntegerValue(INT)These12bits(Bits[DB28:DB17])settheINTvalue,whichdeterminestheintegerpartoftheRFdivisionfactor.
ThisINTvalueisusedinEquation5.
SeetheRFSynthesis:aWorkedExamplesectionformoreinformation.
Allintegervaluesfrom75to4095areallowed.
12-BitMSBFractionalValue(FRAC)These12bits(Bits[DB16:DB5]),togetherwithBits[DB17:DB5](FRACLSBword)inRegisterR6,controlwhatisloadedastheFRACvalueintothefractionalinterpolator.
ThisFRACvaluepartiallydeterminestheoverallRFdivisionfactor.
ItisalsousedinEquation1.
These12bitsarethemostsignificantbits(MSB)ofthe25-bitFRACvalue,andBits[DB17:DB5](FRACLSBword)inRegisterR6aretheleastsignificantbits(LSB).
SeetheRFSynthesis:aWorkedExamplesectionformoreinformation.
REGISTER6ControlBitsWithBits[C5:C1]setto00110,RegisterR6isprogrammed.
Figure25showstheinputdataformatforprogrammingthisregister.
13-BitLSBFRACValueThese13bits(Bits[DB17:DB5]),togetherwithBits[DB16:DB5](FRACMSBword)inRegisterR5,controlwhatisloadedastheFRACvalueintothefractionalinterpolator.
ThisFRACvaluepartiallydeterminestheoverallRFdivisionfactor.
ItisalsousedinEquation1.
These13bitsaretheleastsignificantbits(LSB)ofthe25-bitFRACvalue,andBits[DB14:DB3](FRACMSBword)inRegisterR5arethemostsignificantbits(MSB).
SeetheRFSynthesis:aWorkedExamplesectionformoreinformation.
Figure25.
Register6(R6)DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB000000000000000F12F11F10F9F8F7F6F5F4F3F2F1F0C4(0)C3(1)C2(1)C1(0)CONTROLBITSFRACLSBWORDC5(0)F12F11F1F0(FRAC)*00000000110010200113110081881101818911108190111181911DBR=DOUBLE-BUFFEREDREGISTER.
*THEFRACVALUEISMADEUPOFTHE12-BITMSBSTOREDINREGISTERR5,ANDTHE13-BITLSBREGISTERSTOREDINREGISTERR6.
FRACVALUE=13-BITLSB+12-BITMSB*213.
FRACLSBWORDDBR1RESERVED13336-025DataSheetADF5901Rev.
B|Page21of26Figure26.
Register7(R7)REGISTER7ControlBitsWithBits[C5:C1]setto00111,RegisterR7isprogrammed.
Figure26showstheinputdataformatforprogrammingthisregister.
MasterResetBitDB25providesamasterresetbitforthedevice.
Settingthisbitto1performsaresetofthedeviceandallregistermaps.
Settingthisbitto0returnsthedevicetonormaloperation.
ClockDividerBits[DB23:DB12]setadividerfortheVCOfrequencycalibration.
Loadthedividersuchthatthetimebaseis10s(seeFigure26).
Divideby2(RDIV2)SettingtheDB11bitto1insertsadivideby2toggleflipflopbetweentheRcounterandVCOcalibrationblock.
ReferenceDoublerSettingDB10to0feedstheREFINsignaldirectlytothe5-bitRcounter,disablingthedoubler.
Settingthisbitto1multipliestheREFINfrequencybyafactorof2beforetheREFINsignalisfedintothe5-bitRcounter.
ThemaximumallowableREFINfrequencywhenthedoublerisenabledis50MHz.
5-BitRDividerThe5-bitRcounterallowstheinputreferencefrequency(REFIN)tobedivideddowntoproducethereferenceclocktotheVCOcalibrationblock.
Divisionratiosfrom1to31areallowed.
DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000000MR1CONTROLBITSRD2RDR4R3R2R1R0C4(0)C3(1)C2(1)C1(1)C5(0)REFDOUBLERRDIV2RESERVEDMASTERRESETRDIVIDERR4R3R1R0RDIVIDER(R)0001100102110028110129111030111131RDDOUBLER0DISABLED1ENABLEDRD20DISABLED1ENABLEDR200.
.
.
1111REFRDIV2MR01MASTERRESETENABLEDDISABLEDDBR1DBR1DBR1CLOCKDIVIDERC1D11C1D10C1D2C1D00000000011001020011311004092110140931110409411114095C1D11C1D10C1D9C1D8C1D7C1D6C1D5C1D4C1D3C1D2C1D1C1D0DBR1CLOCKDIVIDERRESERVED13336-0261DBR=DOUBLE-BUFFEREDREGISTER.
ADF5901DataSheetRev.
B|Page22of26Figure27.
Register8(R8)Figure28.
Register9(R9)REGISTER8ControlBitsWithBits[C5:C1]setto01000,RegisterR8isprogrammed.
Figure27showstheinputdataformatforprogrammingthisregister.
FrequencyCalibrationClockBits[DB14:DB5]setadividerfortheVCOfrequencycalibrationclock.
Loadthedividersuchthatthetimebaseis10s(seeFigure27).
REGISTER9ControlBitsWithBits[C5:C1]setto01001,RegisterR9isprogrammed.
Figure28showstheinputdataformatforprogrammingthisregister.
DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB001000000CONTROLBITS000000000FC9FC8FC7FC6FC5FC4FC3FC2FC1FC0C4(1)C3(0)C2(0)C1(0)FREQENCYCALDIVIDERC5(0)RESERVEDFC9FC8.
.
.
FC4FC3FC2FC1FC000.
.
.
0000000.
.
.
0000100.
.
.
0001012.
.
.
11.
.
.
11101102111.
.
.
11110102311.
.
.
111111024FREQUENCYCALDIVIDER.
.
.
013336-027DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0001010100CONTROLBITS010000010111001001C4(1)C3(0)C2(0)C1(1)C5(0)RESERVED13336-028DataSheetADF5901Rev.
B|Page23of26Figure29.
Register10(R10)Figure30.
Register11(R11)REGISTER10ControlBitsWithBits[C5:C1]setto01010,RegisterR10isprogrammed.
Figure29showstheinputdataformatforprogrammingthisregister.
REGISTER11ControlBitsWithBits[C5:C1]setto01011,RegisterR11isprogrammed.
Figure30showstheinputdataformatforprogrammingthisregister.
CounterResetBitDB5providesacounterresetbitforthecounters.
Settingthisbitto1performsacounterresetofthedevicecounters.
Settingthisbitto0returnsthedevicetonormaloperation.
INITIALIZATIONSEQUENCEAfterpoweringupthedevice,administerthefollowingprogrammingsequence.
ThefollowingsequencelockstheVCOto24.
125GHzwitha100MHzreferenceanda50MHzreferencedividerfrequency:1.
Write0x02000007toRegisterR7toperformamasterreset.
2.
Write0x0000002BtoRegisterR11toresetthecounters.
3.
Write0x0000000BtoRegisterR11toenablethecounters.
4.
Write0x1D32A64AtoRegisterR10.
5.
Write0x2A20B929toRegisterR9.
6.
Write0x40003E88toRegisterR8tosetthefrequencycalibrationdividerclockto100kHz.
7.
Write0x809FE520toRegisterR0topowerupthedeviceandLO(10s).
8.
Write0x011F4827toRegisterR7tosettheRcounterclockto50MHzandthecalibrationclockto100kHz.
9.
Write0x00000006toRegisterR6tosettheLSBFRAC=0.
10.
Write0x01E28005toRegisterR5tosetINT=241andMSBFRAC=1024.
Therefore,N=240.
25.
11.
Write0x00200004toRegisterR4tosettheATESTpintohighimpedance.
12.
Write0x01890803toRegisterR3tosettheIOleveltoVDD=3.
3V.
13.
Write0x00020642toRegisterR2tosettheADCclockto1MHz.
14.
Write0xFFF7FFE1toRegisterR1tosettheTxamplitudelevel.
15.
Write0x809FE720toRegisterR0tosettheVCOfrequencycalibration(800s).
16.
Write0x809FE560toRegisterR0topowerTx1on,Tx2off,andLOon.
17.
Write0x809FED60toRegisterR0tosettheTx1amplitudecalibration(400s).
18.
Write0x809FE5A0toRegisterR0toturnTx1off,Tx2on,andLOon.
19.
Write0x809FF5A0toRegisterR0tosettheTx2amplitudecalibration(400s).
20.
Write0x2800B929toRegisterR9.
21.
Write0x809F25A0toRegisterR0todisabletheRandNcounters.
RECALIBRATIONSEQUENCETheADF5901canberecalibratedaftertheinitializationsequenceiscompleteandthedeviceispoweredup.
Therecalibrationsequencemustberunforevery10°Ctemperaturechange;thetemperaturecanbemonitoredusingthetemperaturesensor(seetheTemperatureSensorsection).
1.
Write0x809FE520toRegisterR0toenablethecounters.
Tx1andTx2areoff,andLOison.
2.
Write0x2A20B929toRegisterR9.
DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0000111010011001010100110010C4(1)C3(0)C2(1)C1(0)CONTROLBITSRESERVEDC5(0)13336-029DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB000000000000000000000000000CRC4(1)C3(0)C2(1)C1(1)CONTROLBITSRESERVEDC5(0)CNTRRESET13336-030CR0DISABLED1ENABLEDCNTRRESETADF5901DataSheetRev.
B|Page24of263.
Write0xFFF7FFE1toRegisterR1tosettheTxamplitudelevel.
4.
Write0x809FE720toRegisterR0tosettheVCOfrequencycalibration(800s).
5.
Write0x809FE560toRegisterR0topowerTx1on,Tx2off,andLOon.
6.
Write0x809FED60toRegisterR0tosettheTx1amplitudecalibration(400s).
7.
Write0x89FE5A0toRegisterR0topowerTx1off,Tx2on,andLOon.
8.
Write0x809FF5A0toRegisterR0tosettheTx2amplitudecalibration(400s).
9.
Write0x2800B929toRegisterR9.
10.
Write0x809F25A0toRegisterR0todisabletheRandNcounters.
TEMPERATURESENSORTheADF5901hasanon-chiptemperaturesensorthatcanbeaccessedontheATESTpinorasadigitalwordonDOUTfollowinganADCconversion.
Thetemperaturesensoroperatesoverthefulloperatingtemperaturerangeof40°Cto+105°C.
Theaccuracycanbeimprovedbyperformingaone-pointcalibrationatroomtemperatureandstoringtheresultinmemory.
WiththetemperaturesensorontheanalogtestbusandtestbusconnectedtotheATESTpin(Register4setto0x0000A064)theATESTvoltagecanbeconvertedtotemperaturewiththefollowingequation:()GAINOFFATESTVVVeTemperatur=C)((3)where:VATESTisthevoltageontheATESTpin.
VOFF=0.
699V,theoffsetvoltage.
VGAIN=6.
4*103,thevoltagegain.
ThetemperaturesensorresultcanbeconvertedtoadigitalwordwiththeADCandreadbackonDOUTwiththefollowingsequence:1.
Write0x809FA5A0toRegisterR0toenablethecounters.
2.
Write0x00012064toRegisterR4toconnecttheanalogtestbustotheADCandVTEMPtotheanalogtestbus.
3.
Write0x00028C82toRegisterR2tostarttheADCconversion.
4.
Write0x018902C3toRegisterR3tosettheoutputADCdatatoDOUT.
5.
ReadbackDOUT.
6.
Write0x809F25A0toRegisterR0todisableRandNcounters.
ConverttheDOUTwordtotemperaturewiththefollowingequation:()()GAINOFFLSBVVVADCeTemperatur*=C)((4)where:ADCistheADCcodereadbackonDOUT.
VLSB=7.
33mV,theADCLSBvoltage.
VOFF=0.
699V,theoffsetvoltage.
VGAIN=6.
4*103,thevoltagegain.
RFSYNTHESIS:AWORKEDEXAMPLEThefollowingequationgovernshowtoprogramtheADF5901:RFOUT=(INT+(FRAC/225))*(fREF)*2(5)where:RFOUTistheRFfrequencyoutput.
INTistheintegerdivisionfactor.
FRACisthefractionality.
fREF=REFIN*((1+D)/(R*(1+T)))(6)where:REFINisthereferencefrequencyinput.
Disthereferencedoublerbit,DB10inRegisterR7(0or1).
Risthereferencedivisionfactor.
Tisthereferencedivideby2bit,DB11inRegisterR7(0or1).
Forexample,inasystemwherea24.
125GHzRFfrequencyoutput(RFOUT)isrequiredanda100MHzreferencefrequencyinput(REFIN)isavailable,fREFissetto50MHz.
FromEquation6,fREF=(100MHz*(1+0)/(1*(1+1))=50MHzFromEquation5,24.
125GHz=50MHz*(N+FRAC/225)*2CalculatingtheNandFRACvalues,N=int(RFOUT/(fREF*2))=241FRAC=FMSB*213+FLSBFMSB=int(((RFOUT/(fREF*2))N)*212)=1024FLSB=int(((((RFOUT/(fREF*2))N)*212)FMSB)*213)=0where:FMSBisthe12-bitMSBFRACvalueinRegisterR5.
FLSBisthe13-bitLSBFRACvalueinRegisterR6.
int()makesanintegeroftheargumentinparentheses.
DataSheetADF5901Rev.
B|Page25of26APPLICATIONSINFORMATIONAPPLICATIONOFTHEADF5901INFMCWRADARFigure31showstheapplicationoftheADF5901inafrequencymodulatedcontinuouswave(FMCW)radarsystem.
IntheFMCWradarsystem,theADF4159generatesthesawtoothortrianglerampsnecessaryforthistypeofradartooperate.
TheADF4159controlstheVTUNEpinontheADF5901(Tx)MMICandthusthefrequencyoftheVCOandtheTxoutputsignalonTXOUT1orTXOUT2.
TheLOsignalfromtheADF5901isfedtotheLOinputontheADF5904.
TheADF5904downconvertsthesignalfromthefourreceiverantennastobasebandwiththeLOsignalfromtheTxMMIC.
ThedownconvertedbasebandsignalsfromthefourreceiverchannelsontheADF5904arefedtotheADAR72514-channel,continuoustime,Σ-Δanalog-to-digitalconverter(ADC).
Adigitalsignalprocessor(DSP)followstheADCtohandlethetargetinformationprocessing.
Figure31.
FMCWRadarwithADF5901ADF5901ADF5904ADF4159TXOUT1TXOUT2RX3_RFRX2_RFRX1_RFRX4_RFLO_INLOOUTRFINARFINBAUXAUXADAR7251DSPRXBASEBANDVTUNECPLOOPFILTER13336-031ADF5901DataSheetRev.
B|Page26of26OUTLINEDIMENSIONSFigure32.
32-LeadLeadFrameChipScalePackage[LFCSP]5mm*5mmBodyand0.
75mmPackageHeight(CP-32-12)ORDERINGGUIDEModel1TemperatureRangePackageDescriptionPackageOptionADF5901ACPZ40°Cto+105°C32-LeadLeadFrameChipScalePackage[LFCSP]CP-32-12ADF5901ACPZ-RL740°Cto+105°C32-LeadLeadFrameChipScalePackage[LFCSP]CP-32-12ADF5901WCCPZ40°Cto+105°C32-LeadLeadFrameChipScalePackage[LFCSP]CP-32-12ADF5901WCCPZ-RL740°Cto+105°C32-LeadLeadFrameChipScalePackage[LFCSP]CP-32-12EV-ADF5901SD2ZEvaluationBoard1Z=RoHSCompliantPart.
AUTOMOTIVEPRODUCTSTheADF5901Wmodelsareavailablewithcontrolledmanufacturingtosupportthequalityandreliabilityrequirementsofautomotiveapplications.
Notethattheseautomotivemodelsmayhavespecificationsthatdifferfromthecommercialmodels;therefore,designersshouldreviewtheSpecificationssectionofthisdatasheetcarefully.
Onlytheautomotivegradeproductsshownareavailableforuseinautomotiveapplications.
ContactyourlocalAnalogDevicesaccountrepresentativeforspecificproductorderinginformationandtoobtainthespecificAutomotiveReliabilityreportsforthesemodels.
0.
500.
400.
3001-26-2016-B10.
50BSCBOTTOMVIEWTOPVIEWPIN1INDICATOR329161724258EXPOSEDPADPIN1INDICATORSEATINGPLANE0.
05MAX0.
02NOM0.
20REFCOPLANARITY0.
080.
300.
250.
185.
105.
00SQ4.
900.
800.
750.
70FORPROPERCONNECTIONOFTHEEXPOSEDPAD,REFERTOTHEPINCONFIGURATIONANDFUNCTIONDESCRIPTIONSSECTIONOFTHISDATASHEET.
0.
25MIN3.
753.
60SQ3.
55COMPLIANTTOJEDECSTANDARDSMO-220-WHHD-5.
PKG-0045702015–2017AnalogDevices,Inc.
Allrightsreserved.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
D13336-0-8/17(B)