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GenericSerialFlashInterfaceIntelFPGAIPUserGuideUpdatedforIntelQuartusPrimeDesignSuite:20.
3IPVersion:20.
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0SubscribeSendFeedbackUG-20161|2020.
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28Latestdocumentontheweb:PDF|HTMLContents1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuide.
31.
1.
ReleaseInformation.
41.
2.
DeviceFamilySupport.
41.
3.
Signals.
51.
4.
Parameters.
71.
5.
RegisterMap.
71.
6.
UsingGenericSerialFlashInterfaceIntelFPGAIP.
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1.
ControlStatusRegisterByteEnable.
111.
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2.
MemoryOperations.
121.
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3.
ByteEnabling.
131.
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4.
ConstrainingtheI/OPins.
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GenericSerialFlashInterfaceIntelFPGAIPReferenceDesign.
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HardwareandSoftwareRequirements.
161.
7.
2.
FunctionalDescription.
171.
7.
3.
CreatingNiosIIHardwareSystem.
191.
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4.
IntegratingModulesintoIntelQuartusPrimeProject.
211.
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5.
Programmingthe.
sofFile.
211.
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BuildingApplicationSoftwareSystemusingNiosIISoftwareBuildTools.
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FlashAccessUsingtheGenericSerialFlashInterfaceIntelFPGAIP.
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FlashOperationsthatRequireOperationCode.
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FlashOperationstoReadFlashRegisters.
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FlashOperationstoWriteFlashRegisters.
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FlashOperationsthatRequireAnAddress.
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ReadMemoryfromtheFlash.
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ProgramFlash.
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GenericSerialFlashInterfaceIntelFPGAIPUserGuideArchives.
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DocumentRevisionHistoryfortheGenericSerialFlashInterfaceIntelFPGAIPUserGuide.
32ContentsGenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback21.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideTheGenericSerialFlashInterfaceIntelFPGAIPprovidesaccesstoSerialPeripheralInterface(SPI)flashdevices.
TheGenericSerialFlashInterfaceIPisamoreefficientalternativecomparedtotheASMIParallelIntelFPGAIPandASMIParallelIIIntelFPGAIP.
TheGenericSerialFlashInterfaceIntelFPGAIPsupportsIntelconfigurationdevicesaswellasflashfromdifferentvendors.
IntelrecommendsyoutousetheGenericSerialFlashInterfaceIntelFPGAIPfornewdesigns.
YoucanusetheGenericSerialFlashInterfaceIntelFPGAIPtowritethefollowingdatatotheflashdevice:Configurationmemory(1)—configurationdataforActiveSerial(AS)configurationscheme.
Generalpurposememory—application-specificdata.
TheGenericSerialFlashInterfaceIPsupportsthefollowingfeatures:Single,dualorquadI/Omode.
DirectflashaccessviatheAvalonmemory-mappedslaveinterfacewhichallowsaprocessorsuchasNiosIItodirectlyexecutecodesfromtheflash.
Upto3flashdevicesupport(IntelArria10devices,IntelCyclone10GXdevices,andotherFPGAdeviceswithflashesthatareconnectedtotheFPGAGPIOpins).
IPcontrolregisterforaccessingflashcontrolandstatusregisters.
Programmableclockgeneratorwithrun-timebaudratechangeforflashdeviceclock.
Programmablechipselectdelay.
Readdatacapturinglogicwhenrunningwithhighfrequency.
FPGAactiveserialmemoryinterface(ASMI)blockatomconnectiontotheactiveserial(AS)pinsorexporttoFPGAI/Opins.
RelatedInformationGenericSerialFlashInterfaceIntelFPGAIPReferenceDesignonpage16GenericSerialFlashInterfaceIntelFPGAIPCoreReferenceDesignFilesHowdoIenableMicron'sMT25QdevicesupportinreplacementtoEndOfLife(EOL)EPCQ(>=256Mb)andEPCQ-LdevicesConfigurationDevicesProvidesmoreinformationonthethird-partyflashsupport.
(1)Thesupportedflashdevicesforconfigurationmemoryare,EPCQ,EPCQ-A,EPCQ-L,andMicron*MT25Q(256Mbto2Gb)devices.
UG-20161|2020.
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28SendFeedbackIntelCorporation.
Allrightsreserved.
Agilex,Altera,Arria,Cyclone,Enpirion,Intel,theIntellogo,MAX,Nios,QuartusandStratixwordsandlogosaretrademarksofIntelCorporationoritssubsidiariesintheU.
S.
and/orothercountries.
IntelwarrantsperformanceofitsFPGAandsemiconductorproductstocurrentspecificationsinaccordancewithIntel'sstandardwarranty,butreservestherighttomakechangestoanyproductsandservicesatanytimewithoutnotice.
Intelassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,product,orservicedescribedhereinexceptasexpresslyagreedtoinwritingbyIntel.
Intelcustomersareadvisedtoobtainthelatestversionofdevicespecificationsbeforerelyingonanypublishedinformationandbeforeplacingordersforproductsorservices.
*Othernamesandbrandsmaybeclaimedasthepropertyofothers.
ISO9001:2015RegisteredUsingtheGenericSerialFlashInterface(ODEVGSFI)TrainingCourse1.
1.
ReleaseInformationIPversionsarethesameastheIntelQuartusPrimeDesignSuitesoftwareversionsuptov19.
1.
FromIntelQuartusPrimeDesignSuitesoftwareversion19.
2orlater,IPcoreshaveanewIPversioningscheme.
TheIPversion(X.
Y.
Z)numbermaychangefromoneIntelQuartusPrimesoftwareversiontoanother.
Achangein:XindicatesamajorrevisionoftheIP.
IfyouupdateyourIntelQuartusPrimesoftware,youmustregeneratetheIP.
YindicatestheIPincludesnewfeatures.
RegenerateyourIPtoincludethesenewfeatures.
ZindicatestheIPincludesminorchanges.
RegenerateyourIPtoincludethesechanges.
Table1.
GenericSerialFlashInterfaceIntelFPGAIPReleaseInformationItemDescriptionIPVersion20.
0.
0IntelQuartusPrimeProEditionVersion20.
3ReleaseDate2020.
09.
28ItemDescriptionIntelQuartusPrimeStandardEditionVersion20.
1ReleaseDate2020.
04.
13Note:ThenewIPversioningschemeisonlyavailablefortheGenericSerialFlashInterfaceIntelFPGAIPintheIntelQuartusPrimeProEditionsoftware.
1.
2.
DeviceFamilySupportTheGenericSerialFlashInterfaceIPissupportedinthefollowingdevices:IntelAgilexIntelStratix10IntelArria10IntelCyclone10GXIntelCyclone10LPIntelMAX10(Forgeneralpurposememoryonly)StratixVArriaVCycloneV1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback4StratixIVCycloneIVArriaIINote:ForIntelAgilex,IntelStratix10,andIntelMAX10devices,exporttheflashpinbyenablingEnableSPIpinsinterfaceparameterofthisIP.
ForIntelAgilexandIntelStratix10devices,theIPcanonlyaccessflashthatisconnectedtoFPGAGPIOpins.
TheIPcannotbeusedtoaccessflashthatisconnectedtoSDMforconfigurationpurpose.
RelatedInformationConfigurationDevicesProvidesmoreinformationaboutthethird-partyflashsupport.
1.
3.
SignalsFigure1.
SignalBlockDiagramTheinclusionandwidthofsomesignalsdependonthefeaturesselected.
GenericSerialFlashInterfaceIntelFPGAIPresetclkavl_csr_readflash_ncsavl_csr_wrdataavl_mem_writeavl_mem_burstcountavl_mem_waitrequestavl_mem_readdataavl_mem_rddata_validavl_mem_readavl_mem_addravl_mem_wrdataavl_mem_byteenbleflash_dclkflash_dataavl_csr_writeavl_csr_addravl_csr_rddataavl_csr_rddata_validavl_csr_waitrequestavl_csr_byteenableTable2.
PortsDescriptionSignalWidthDirectionDescriptionAvalonMemory-MappedSlaveInterfaceforCSR(avl_csr)avl_csr_addr6InputAvalonmemory-mappedaddressbus.
Theaddressbusisinwordaddressing.
continued.
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GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide5SignalWidthDirectionDescriptionavl_csr_read1InputAvalonmemory-mappedreadcontroltotheCSR.
avl_csr_rddata32OutputAvalonmemory-mappedreaddatabusfromtheCSR.
avl_csr_write1InputAvalonmemory-mappedwritecontroltotheCSR.
avl_csr_wrdata32InputAvalonmemory-mappedwritedatabustoCSR.
avl_csr_waitrequest1OutputAvalonmemory-mappedwaitrequestcontrolfromtheCSR.
avl_csr_rddata_valid1OutputAvalonmemory-mappedreaddatavalidthatindicatestheCSRreaddataisavailable.
avl_csr_byteenable4InputAvalonmemory-mappedbyteenablecontroltotheCSR.
AvailablewhenyouenabletheUsebyteenableforCSRparameter.
AvalonMemory-MappedSlaveInterfaceforMemoryAccess(avl_mem)avl_mem_write1InputAvalonmemory-mappedwritecontroltothememoryavl_mem_burstcount7InputAvalonmemory-mappedburstcountforthememory.
Thevaluerangefrom1to64(Maxpagesize).
avl_mem_waitrequest1OutputAvalonmemory-mappedwaitrequestcontrolfromthememory.
avl_mem_read1InputAvalonmemory-mappedreadcontroltothememoryavl_mem_addrNInputAvalonmemory-mappedaddressbus.
Theaddressbusisinwordaddressing.
Thewidthoftheaddressdependsontheflashmemorydensity.
IfyouareusingIntelArria10,andIntelCyclone10GXoranysupporteddeviceswithgeneralpurposeI/Owithmultiplesflashes,writetheCSRtoselectthechipselect.
TheIPtargetstheselectedflashwhenbeingaccessedviathisaddress.
avl_mem_wrdata32InputAvalonmemory-mappedwritedatabustothememoryavl_mem_readddata32OutputAvalonmemory-mappedreaddatabusfromthememory.
avl_mem_rddata_valid1OutputAvalonmemory-mappedreaddatavalidthatindicatesthememoryreaddataisavailable.
avl_mem_byteenble4InputAvalonmemory-mappedwritedataenablebustomemory.
Duringburstingmode,byteenablebuswillbelogichigh,4'b1111.
ClockandResetclk1InputInputclocktoclocktheIP.
reset1InputAsynchronousresettoresettheIP.
InterruptIrq1OutputInterruptsignalthatindicateifthereisanillegalwriteorillegalerase.
ConduitInterface(2)flash_data4BidirectionalInputoroutputporttofeeddatafromtheflashdevice.
flash_dclk1OutputProvidesclocksignaltotheflashdevice.
flash_ncs1/3OutputProvidesthencssignaltotheflashdevice.
(2)AvailablewhenyouenabletheEnableSPIpinsinterfaceparameter.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback61.
4.
ParametersTable3.
ParameterSettingsParameterLegalValuesDescriptionsDeviceDensity1,2,4,8,16,32,64,128,256,512,1024,2048DensityoftheflashdeviceusedinMb.
DisablededicatedActiveSerialinterface—Routesthesignalstothetoplevelofyourdesign.
EnablethiswhenyouwanttoincludetheSerialFlashLoaderIntelFPGAIPinyourdesign.
EnableSPIpinsinterface—TranslatesthesignalstotheSPIpininterface.
NumberofChipSelectused123Selectsthenumberofchipselectconnectedtotheflash.
Enableflashsimulationmodel—UsesthedefaultEPCQ1024simulationmodelforsimulation.
Whendisabled,refertoAN-720:SimulatingtheASMIBlockinYourDesignforcreatingawrappertousewithotherflashsimulationmodel.
UsebyteenableforCSR—TurnsonbyteenableforCSRwritedatainterface.
RelatedInformationAN-720:SimulatingtheASMIBlockinYourDesign1.
5.
RegisterMapTable4.
RegisterMapEachaddressoffsetinthefollowingtablerepresents1wordofmemoryaddressspace.
IP_CLKistheclockthatdrivestheIP.
SCLKistheclockthatdrivestheflashdevice.
Offset(Hex)RegisterNameR/WFieldNameBitDefaultValue(Hex)Description0ControlRegisterReserved31:8ReservedR/WAddressingmode80x0Addressingmodeforreadandwriteoperation:0x0:3-bytesaddressing.
0x1:4-bytesaddressing.
For4-byteaddressingmode,youmustenable4-byteaddressbysendingcommandtotheflash.
ThisbitaffectsdirectaccesstomemoryviatheAvalonmemory-mappedinterfaceforbothwriteandreadoperation.
R/WChipselect7:40x0Selectstheflashdevice.
0x0:Toselectfirstdevice.
0x1:Toselectseconddevice.
0x2:Toselectthirddevice.
Reserved3:1Reservedcontinued.
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GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide7Offset(Hex)RegisterNameR/WFieldNameBitDefaultValue(Hex)DescriptionR/WEnable00x1Setthisbitto0todisabletheoutputoftheIPandputalloutputsignaltohighimpedancestate.
Thiscanbeusedtosharebuswithotherdevices.
1SPIClockBaud-rateRegisterReserved31:5ReservedR/WBaudratedivisor4:00x10TheIPhasaninternalclockdividertogeneratetheclockthatconnectstotheflashdevice.
Thepossibledivisorvalueisfrom2to32withtheincrementof2.
So,themaximumclockthattheflashrunishalfoftheclockoftheIP.
ExiftheIPisrunwith100Mhzclock,thentheclockoftheflashisat50Mhz.
Bydefault,theclockissettothelowestclock(/32)toensurethattheIPworksinmostcases.
Divisorvalues:0x1:/20x2:/40x3:/6.
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0xF:/300x10:/322CSDelaySettingRegisterReserved31:12ReservedR/WtSHSL11:8ThisregistersettingcontrolsthetSHSL.
0:tSHSLis3IP_CLK.
n:tSHSLis3+nIP_CLK.
R/WCSde-assert7:40x0Setsthechipselectde-assertiondelay.
0:Chipselectisde-assertedatthelastfallingedgeofSCLK.
n:Chipselectisde-assertednnumberofclocksafterthelastfallingedgeofSCLK.
R/WCSassert3:00x0Setsthechipselectassertiondelay.
0:ChipselectisassertedhalfflashclockperiodbeforethefirstrisingedgeofSCLK.
n:ChipselectisassertedhalfflashclockperiodplusnnumberofIP_CLK.
(3)3ReadCapturingRegisterReserved31:4ReservedR/WReaddelay3:00x0Theclocktooutputtimingoftheflashplustheboardtrace,I/OpintimingcancontributetohighvalueofdelaytothedataarrivingattheIPlogic.
ThedelaycaptureprovidesawayfortheIPtodelayitsreadinglogictocompensateforthosedelays.
continued.
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(3)Intelrecommendsthatyousetthechipselectassertiondelayto5ifyouarerunningtheIPclockat100MHz.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback8Offset(Hex)RegisterNameR/WFieldNameBitDefaultValue(Hex)DescriptionDelaythereaddatalogicbyavalueoftheIP_CLKcycles.
4OperatingProtocolsSettingRegisterReserved31:18ReservedR/WReaddataouttransfermode17:160x0Transfermodeforreaddataoutput.
Reserved15:14ReservedR/WReadaddresstransfermode13:120x0TransfermodeforreadaddressinputDescriptionasbit1:0.
Reserved11:10ReservedR/WWriteDataintransfermode9:80x0TransfermodeforwritedatainputDescriptionasbit1:0.
Reserved7:6ReservedR/WWriteaddresstransfermode5:40x0TransfermodeforwriteaddressinputDescriptionasbit1:0.
Reserved3:2ReservedR/WInstructiontransfermode1:00x0Transfermodeforopcode:0x0:StandardSPImode–commandinputissentonDQ0.
0x1:DualI/Omode–commandinputissentonDQ[1:0].
0x2:QuadI/Omode–commandinputissentonDQ[3:0].
Thissettingaffectstheflashcommandregister.
Forexample,ifthisfieldissetto0x1,flashcommonoperations(suchasreadid,readstatus,writestatusregister)uses0x1aswell.
5ReadInstructionRegisterReserved31:14ReservedR/WDummycycles12:80xANumberofdefaultdummycyclesusedforreadoperation.
Refertotherespectiveflashdevicedatasheet.
R/WReadopcode7:00x03Theopcodeforreadoperation.
Refertotherespectiveflashdevicedatasheettoselectthecorrectopcodeaccordingtothetransfermodesetting.
6WriteInstructionRegisterReserved31:16ReservedR/WPollingopcode15:80x05Theopcodetocheckifthewriteoperationhasbeencompleted.
Afterwriteoperationiscompleted,theIPreleasesthewaitrequestoftheAvalonmemory-mappedinterface.
Inapplicabledevices,youcansetasthestatusregisterorflagstatusregister.
R/WWriteopcode7:00x02Theopcodeforwriteoperation.
Refertotherespectiveflashdevicedatasheettoselectthecorrectopcodeaccordingtothetransfermodesetting.
7FlashCommandReserved31:21Reservedcontinued.
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GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide9Offset(Hex)RegisterNameR/WFieldNameBitDefaultValue(Hex)DescriptionSettingRegister(4)R/WNumberofdummycycles20:160x0Thenumberofdummycycles.
Setto0whentheoperationdoesnotrequireanydummycycles.
Refertotherespectiveflashdevicedatasheetfordummyclockrequirements.
R/WNumberofdatabytes15:120x08Thenumberofwriteorreaddata.
Thisworkstogetherwithbit11.
IfthevalueisSetto0iftheoperationhasnowriteorreaddata,forexample,writeenable.
R/WDatatype110x01Indicatesthetypeofdata(bit[15:12]).
0:Numberofbytedeclaredin[15:12]iswritedatatoflashdevice1:Numberofbytedeclaredin[15:12]isreaddatafromflashdeviceR/WNumberofaddressbytes10:80x0Numberofaddressbytestosendtotheflashdevice.
Either3or4bytesIfthisissettozerothentheoperationdoesnotcarryanyaddressbyte.
R/WOpcode7:00x05Theopcodeoftheoperation.
8FlashCommandControlRegisterReserved31:1ReservedWStart00x0Write1tothisbittostarttheoperation.
9FlashCommandAddressRegisterR/WStatingaddress31:031:0Addressofflashcommand.
AFlashCommandWriteData0RegisterR/WLower4byteswritedata31:00x0Thefirst4-byteofwritedatatoflashdevice.
BFlashCommandWriteData1RegisterR/WUpper4byteswritedata31:00x0Thelast4-byteofwritedatatotheflashdevice.
CFlashCommandReadData0RegisterRLower4bytesreaddata31:00x0Thefirst4-byteofreaddatafromflashdevice.
DFlashCommandReadData1RegisterRUpper4bytesreaddata31:00x0Thelast4-byteofreaddatafromtheflashdevice.
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UsingGenericSerialFlashInterfaceIntelFPGAIPTheGenericSerialFlashInterfaceIntelFPGAIPcoreinterfacesareAvalonmemory-mappedcompliant.
Formoredetails,refertotheAvalonspecification.
(4)Defaultsettingisforreadstatuscommand.
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GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback10Note:Foroperationsthatrequirewritevaluetoflash,youmustperformwriteenableoperationfirst.
Youmustreadtheflagstatusregistereverytimeyouissueawriteorerasecommand.
Incaseofsupportmultiplesflashdevices,youmustwritechipselectregistertoselectthecorrectflashdevicebeforeperforminganyoperationtothespecificflashdevice.
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6.
1.
ControlStatusRegisterByteEnableThebyteenablefortheControlStatusRegister(CSR)interfacefeatureallowsyoutowritetoallCSRs,from0x0to0xD,intheGenericSerialFlashInterfaceIntelFPGAIPwhileselectingonlycertainbytestowrite.
Theavl_csr_byteenableportprovidessupportforthisfeature.
FornormalCSRs(allCSRsexceptwritedataregisters,0xAand0xB),theCSRsretaintheirvaluesifaparticularbyteenableisnotenabled,andonlywritethenewvalueforenabledbytes.
ThewritedataCSRs(0xAand0xB)storethewritedatatotargetflash.
TheIPonlywritesenabledbyteswiththecorrespondingdataanddoesnotretaintheoldvaluesfordisabledbytes.
—TheIPwritesthewritedataforallvalidenabledbytesintotheflashataspecifiedstartingaddressasthefirstdata.
—Setthecorrectnumberofdatabytesregisterinbit[15:12]intheflashcommandsettingregister(0x7).
Ifyouintendtowritebothwritedata0andwritedata1intotheflash,youmustwritethenumberofdatabytesto8,regardlessofhowmanyCSRbyteenablebitsareset.
TheIPwritestheenabledbyteasthefirstdataintothestartingaddressforwritedata0,andthenfillstherestofthebytesforwritedata0asFF.
TheIPdoesthesameforwritedata1.
Ifyouintendtowriteonewritedata0orwritedata1intoflash,youmustsetthenumberofdatabytestothesameasavl_csr_byteeanablebytes.
Inotherwords,ifyouenable2bytesinavl_csr_byteenable(4'b0110),thenumberofdatabytestobesentisalso2bytes.
TheIPwritesonlytheenableddatadirectlyintotheaddressthatyouspecifiedintheflashcommandaddressregister(0x9).
YouhavetheoptiontoturnonUsebyteenableforCSRtoenablethebyteenablefortheCSRinterfacefeatureintheparametereditoroftheGenericSerialFlashInterfaceIntelFPGAIP.
ThefollowingstepsaretheprogrammingflowusingtheCSRtowritedatatoflash(Macronix*flash):1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide111.
Writetheaddressthatyouintendtowritedatainto.
Writetheaddressintheflashcommandaddressregister(0x9).
Forexample,write0x2001.
2.
Writethewritedataintheflashcommandwritedata0register(0xA)orflashcommandwritedata1register(0xB)usingavl_csr_byteenabletoselectthedesiredbytesonly.
Forexample,theCSRbyteenableof4'b0110)forwritedata0is44332211andwritedata1is88776655.
3.
StartthesetupofthewriteoperationopcodeintheIPbywritingtoflashcommandsettingregister(0x7)with'writeenable'opcode(h06)andthensetthecontrolbitto1inflashcontrolregister(0x8).
4.
Next,writethewritestatusregisteropcode(h01)inthesameregister(0x7).
Setthedatatypeas'write'andwritethenumberofdatabytesas8.
Forexample,bothwritedata0andwritedata1have2bytesenabled.
Youmustwriteallthebytes(thatis,8bytes)eveniftheintendedtotalbytestobewrittenis4.
Theresultingwriteoperationwillwrite77663322(4bytes)intotheflashaddress0x2001.
Table5.
VisualizationofCSRbyteenableforWriteDataintoFlashMemoryCSREnabledBytesinWriteDataCSRbyteenableforwritedata1and00110Writedata04433(5)22(5)11Writedata18877(5)66(5)55WriteintoFlashMemoryFlashaddress0x20070x20060x20050x2004Writedata1FF77(5)66(5)FFFlashaddress0x20030x20020x20010x2000Writedata0FF33(5)22(5)FF1.
6.
2.
MemoryOperationsDuringflashmemoryaccess,theIPperformsthefollowingstepstoallowyoutoperformanydirectreadorwriteoperation:WriteenableforwriteoperationCheckflagstatusregistertomakesuretheoperationhasbeencompletedattheflashReleasewaitrequestsignalwhenoperationcompletedMemoryoperationsareAvalonmemory-mappedoperations.
Youmustsetthecorrectaddressontheaddressbus,writedataifitiswritetransaction,driveburstcountbus1ifsingletransactionordesiredburstcountvalueandtriggerthewriteorreadsignal.
Note:Formultipleflashdevicesetup,theaddressbusisextendedtoincludethechipselectvalue.
(5)Newdatawrittenintotheflash.
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GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback12Figure2.
8-WordWriteBurstWaveformExampleFigure3.
8-WordReadingBurstWaveformExampleFigure4.
1-ByteWritebyteenable=4'b0001WaveformExampleNote:TherearetwointernalunconstrainedclocksintheGenericFlashSerialInterfaceIntelFPGAIPcorewhenyoucompileyourdesignintheIntelQuartusPrimeProEditionsoftware.
Intelrecommendsthatyouconstraintthepathbyusingthefollowingcommand:create_generated_clock-name-source[get_ports]-divide_by2[get_registers]1.
6.
3.
ByteEnabling1.
6.
3.
1.
ByteEnablingSupportedPatternsTable6.
ByteEnablingSupportedPatternsByteEnablePatternSupport4'b0000Supported(whenburstismorethan1)4'b0001Supported4'b0010Supported4'b0100Supported4'b1000Supported4'b0011Supported4'b0110Supported4'b1100Supportedcontinued.
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GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide13ByteEnablePatternSupport4'b0111Supported4'b1110Supported4'b1111SupportedAllwriteburstsgreaterthan1issettobyteenableof4'b1111,inwhichallbyteenablesareassertedthroughallthewordsoftheburst.
Whenamasterwiderthan32bitsisusedtoconnecttotheIP,theinterconnectfabricofthePlatformDesignerproducesmulti-wordburststoadaptthewidemasterintothenarrow32-bitslave(theIP).
ChoosetousethebyteenablingpatternsintheByteEnablingSupportedPatternstableifthewidemasterintendstowriteonlycertainbytesintheentiretransaction.
Youmustensurethatthebyteenablingpatterniscontiguousforburstwrites.
Note:Forburstwrites,theIPwritesallbytes(4'b1111)intotheflashevenwithyourselectedbyteenablepattern.
Ifyouhavenotenabledthedata,theIPwrites0xFF.
TheperformanceoftheIPisstillthesameaswriting8bytesfora64-bitwidemaster,evenifyouhaveenabledonly1byteusingbyteenable.
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4.
ConstrainingtheI/OPinsTheIntelQuartusPrimesoftwaredoesnotautomaticallygeneratetheI/OtimingconstraintsfortheGenericSerialFlashInterfaceIntelFPGAIPfile.
ToenabletheSPIpininterfaceusingthegeneralpurposeI/Opins,youmustmanuallyenterthetimingconstraints.
FollowthetimingguidelinesandexamplestoensurethattheTimingAnalyzeranalyzestheI/Otimingcorrectly.
ConstraintheinputclockoftheGenericSerialFlashInterfaceIntelFPGAIP.
Example:#CreateClock#constrainthebaseclockusingcreate_clock,thisistypicallyaclockcomingintothedeviceonaninputclockpin#here,clk_clkisa10nsclockwitha50percentdutycycle,wherethefirstrisingedgeoccursat0nsappliedtoportclk_clkcreate_clock-name{clk_clk}-period10.
000-waveform{0.
0005.
00}[get_ports{clk_clk}]Createatimingconstrainttodclk,whichistheSPIoutputclockfromGenericSerialFlashInterfaceIntelFPGAIP.
ThemaximumSPIclockishalfoftheinputclock.
Example:#CreateGeneratedClock#constrainthegeneratedclockdclk.
TheinputclockofGSFIIPisusedandcreatedacounterlogictogenerateaslowerDCLKthatisusedasSPIclock#here,wesetthemaximumdclk,whichishalfoftheinputclk_clk#refertotheGSFIUG,andyoufindthatthemaximumSPIclockbaud-ratedivisoris2.
create_generated_clock-name{dclk_int}-source[get_ports{clk_clk}]-divide_by2[get_pins{u0|intel_generic_serial_flash_interface_top_0|intel_generic_serial_flash_interface_top_0|qspi_inf_inst|flash_clk_reg|q}]create_generated_clock-name{dclk}-source[get_pins{u0|1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback14intel_generic_serial_flash_interface_top_0|intel_generic_serial_flash_interface_top_0|qspi_inf_inst|flash_clk_reg|q}][get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_dclk}]SetamulticyclepathtochangethesetupandholdclockrelationshipbetweentheinputclockandtheSPIclock.
Example:#SetMulticyclePath#Foradivideby2DCLK#SPIlactcheddataonrisingedgedclkandFPGAdrivendataoutputonrisingedgeclk_clkset_multicycle_path-setup-start-from[get_clocks{clk_clk}]-to[get_clocks{dclk}]2set_multicycle_path-hold-start-from[get_clocks{clk_clk}]-to[get_clocks{dclk}]1#SPIdrivendataonfallingedgeofdclkandFPGAlatcheddataonsecondrisingedgeofclk_clkset_multicycle_path-setup-end-from[get_clocks{dclk}]-to[get_clocks{clk_clk}]2set_multicycle_path-hold-end-from[get_clocks{dclk}]-to[get_clocks{clk_clk}]1Settheinputandoutputdelaysforthequadserialperipheralinterface(QSPI)IOpin.
Example:#SetInputDelay#$input_delayisdeterminedbyTcovaluesandboardparameters(outsideofFPGA)#$input_delaymax=data_trace_max-clk_trace_min+ext_tco_max#$input_delaymin=data_trace_min-clk_trace_max+ext_tco_minset_input_delay-clock{dclk}-max-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[0]}]set_input_delay-clock{dclk}-min-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[0]}]set_input_delay-clock{dclk}-max-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[1]}]set_input_delay-clock{dclk}-min-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[1]}]set_input_delay-clock{dclk}-max-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[2]}]set_input_delay-clock{dclk}-min-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[2]}]set_input_delay-clock{dclk}-max-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[3]}]set_input_delay-clock{dclk}-min-clock_fall-add_delay$input_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[3]}]#SetOutputDelay#$output_delayisdeterminedbyThandTsuvaluesandboardparameters(outsideofFPGA)#$output_delaymax=data_trace_max+Tsu-clk_trace_min#$output_delaymin=data_trace_min-Th-clk_trace_maxset_output_delay-clock{dclk}-max-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[0]}]set_output_delay-clock{dclk}-min-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[0]}]set_output_delay-clock{dclk}-max-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[1]}]set_output_delay-clock{dclk}-min-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[1]}]set_output_delay-clock{dclk}-max-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[2]}]1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide15set_output_delay-clock{dclk}-min-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[2]}]set_output_delay-clock{dclk}-max-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[3]}]set_output_delay-clock{dclk}-min-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_data[3]}]set_output_delay-clock{dclk}-max-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_ncs}]set_output_delay-clock{dclk}-min-add_delay$output_delay[get_ports{intel_generic_serial_flash_interface_top_0_qspi_pins_ncs}]1.
7.
GenericSerialFlashInterfaceIntelFPGAIPReferenceDesignThereferencedesignimplementstheGenericSerialFlashInterfaceIntelFPGAIPtoperformthefollowinggeneral-purposememoryoperations:ReaddeviceIDEnablesectorprotectPerformsectoreraseReadandwritedatafromandtoflashdevicesRelatedInformationGenericSerialFlashInterfaceIntelFPGAIPUserGuideonpage3GenericSerialFlashInterfaceIntelFPGAIPCoreReferenceDesignFiles1.
7.
1.
HardwareandSoftwareRequirementsThefollowingarethehardwareandsoftwarerequirementsforthedesignexample:CycloneVEFPGADevelopmentKitIntelQuartusPrimeStandardEditionsoftwareversion18.
0withNiosIISoftwareBuildToolsforEclipseIntelFPGADownloadCableIITestedflashdevices:—Cypress*S70FL01G—MicronMT25Q01G—MicronMT25Q512—EPCQ2561.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback161.
7.
2.
FunctionalDescription1.
7.
2.
1.
ReferenceDesignComponentsFigure5.
ReferenceDesignBlockDiagramNiosIIProcessorJTAGDebugModuleHostPCFlashDeviceJTAGUARTAvalonMemory-MappedDataMasterPortAvalonMemory-MappedInstructionMasterPortOn-ChipMemoryIPGenericSerialFlashInterfaceIPAvalonMemory-MappedSlavePort(CSR)AvalonMemory-MappedSlavePortAvalonMemory-MappedSlavePort(MEM)IntelFPGATable7.
ReferenceDesignComponentsDescriptionsComponentDescriptionJTAGUARTIntelFPGAIPEnablescommunicationbetweentheNiosIIprocessorandthehostcomputer.
NiosIIProcessorRunsapplicationprogrambyexecutingdataandinstruction.
On-ChipMemoryIntelFPGAIPStorescodeanddata.
ConnectstheNiosIIinstructionmastertotheon-chipmemoryblock.
GenericSerialFlashInterfaceIntelFPGAIPControlsvendor-independentflashdevicetoperformflashinteraction.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide171.
7.
2.
2.
ReferenceDesignApplicationProgramFigure6.
ReferenceDesignApplicationProgramFlowDiagramReadDeviceIDSectorProtectedNoNoYesYesProtectSectorEraseSectorEraseSectorUnprotectSectorEraseErrorEraseErrorReadDataEndAddress0ContainsDataWriteDataandReadBackEraseAddress0ProtectSectorStartFlowdiagramsequencedescription:1.
TheapplicationprogramstartswithidentifyingtheflashdeviceattachedtotheFPGA.
Note:Theflashdevicesserveassamplestodemonstratethisreferencedesignonly.
2.
Theapplicationprogramperformssectorprotectionanderasestheprotectedsector:a.
Toperformsectorprotect,theapplicationprogram:i.
Performswriteenablecommand.
ii.
Performswritestatusregistercommandtosetblockprotect(BP)bitandTop/Bottom(TB)bit.
iii.
Pollswriteinprogress(WIP)bit(bit0ofstatusregister)untilitreturnsa0(ready).
iv.
Performsreadstatusregistercommandtocheckifsectorprotectoperationsucceededorfailed.
b.
Toperformsectorerase,theapplicationprogram:1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback18i.
Performswriteenablecommand.
ii.
Performssectorerasecommand.
iii.
Pollswriteinprogress(WIP)bit(bit0ofstatusregister)untilitreturna0(ready).
iv.
Performsreadstatusregistertocheckwhethereraseoperationsucceededorfailed.
3.
Eraseerroroccurredbecausethesectorisprotected.
Theapplicationprogramclearstheerrorbitthrough:Clearflagstatusregistercommand(EPCQ-LorMicron).
Clearstatusregistercommand(Cypress).
4.
Theapplicationprogramdisablesthesectorprotect:a.
Performswriteenablecommand.
b.
PerformswritestatusregistercommandtoclearBPbitandTBbit.
c.
PollsWIPbit(bit0ofstatusregister)untilitreturnsa0(ready).
d.
PerformsreadstatusregistercommandtocheckwhetherBPbitandTBbithassucceededclear.
5.
Theapplicationprogramperformsflashdeviceprogrammingafterthesectorisnotprotected.
Theapplicationprogram:a.
Performswritememoryintotheaddresswithemptymemory.
b.
PollsWIPbit(bit0ofstatusregister)untilitreturnsa0(ready)c.
Performsreadbackmemoryoftheaddresstoconfirmtheaddresshasprogrammed.
6.
RepeatStep2andreadbackmemoryoftheaddress.
Memoryisnoterasedbecausethesectorisprotected.
1.
7.
3.
CreatingNiosIIHardwareSystem1.
IntheIntelQuartusPrimesoftware,gotoFileNewProjectWizard.
2.
CreateanewIntelQuartusPrimePrimeprojectnamedgeneric_flash_accessinanewdirectoryandselecttheCycloneVE5CEFA7F3117device.
3.
SelectToolsPlatformDesigner,andsavethefileasgeneric_flash_access.
qsys.
4.
Double-clickontheclocksourceclk_0andchangetheClockfrequencyto100000000Hz(100MHz).
5.
Rightclickonclk_0andrenameitassys_clk.
6.
AddaNiosIIprocessor:a.
GotoProcessorandPeripheralsEmbeddedProcessorsNiosIIProcessor,andclickAdd.
b.
ClickFinishtoaddtheNiosIIprocessortothedesignandrenameitasnios2.
Note:Ignoreanymessagesaboutparametersthathavenotbeenspecifiedyet.
7.
AddaGenericSerialFlashInterfaceIP:1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide19a.
SelectBasicFunctionsConfigurationandProgrammingGenericSerialFlashInterfaceIntelFPGAIP,andclickAdd.
Renamethiscomponentasintel_generic_serial_flash_interface_top0.
b.
Setthedevicedensity.
Note:Thisreferencedesignuses1024MBflashdevicedensity.
c.
Connectdata_masterofprocessortoavl_memandavl_csr,andinstruction_masterofprocessortoonlyavl_memofthiscomponent.
8.
AddanOn-chipMemoryIP:a.
SelectBasicFunctionsOnChipMemoryOn-ChipMemory(RAMorROM)IntelFPGAIP.
b.
SettheTotalMemorySizeto40960bytes(40KBytes).
c.
ClickFinishandrenameasmain_memory.
d.
Connectitsslavetodata_masterandinstruction_masterofprocessor.
9.
AddaJTAGUARTIP:a.
GotoInterfaceProtocolsSerialJTAGUARTIntelFPGAIP,andclickAdd.
b.
ClickFinishandrenameitasjtag_uart.
c.
Connectitsavalon_jtag_slaveporttothedata_masterportoftheprocessor.
d.
IntheIRQcolumn,connecttheinterruptsenderportfromtheAvalon_jtag_slaveporttotheinterruptreceiverportoftheprocessorandtype0.
10.
Connectclockinputofsys_clktoclockinputofallothercomponents.
11.
ResolveallNiosIIprocessorerrormessagesbeforegeneratingthePlatformDesignersystem:a.
DoubleclicktheNiosIIprocessornios2.
b.
ClickVectors,changeboththeResetvectormemoryandExceptionvectormemorytomain_memory.
s1.
c.
ClickSystemtabandclickonthedrop-downmenuSystemandclickAssignBaseAddresstoautoassignbaseaddressesforallthecomponents.
d.
Underthesamemenu,clickCreateGlobalResetNetworktoconnecttheresetsignalstoformaglobalresetnetwork.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback20Figure7.
CompletedPlatformDesignerConnection12.
Generatethesystem:a.
ClickGenerateHDLonthebottomofthewindow.
b.
Whencompleted,thePlatformDesignerdisplaysGenerate:Completedsuccessfully.
1.
7.
4.
IntegratingModulesintoIntelQuartusPrimeProject1.
IntheIntelQuartusPrimesoftware,selectAssignmentSettings.
2.
IntheSettingswindow,addgeneric_flash_access.
qysfilelocatedinthesynthesisfolderandclickApply.
3.
Thegeneric_flash_access.
qysfileisshownunderFilesdirectory.
RightclickthefileandchooseSetasTop-LevelEntity.
4.
GotoProcessingStartStartAnalysisandElaborationtoallowthehardwaresystemtodetermineinputandoutputpins.
5.
StartpinassignmentbygoingtoAssignmentsPinPlanner,andassignPIN_L14asclk_clkandPIN_AA26asreset_reset_n.
6.
GotoAssignmentsDeviceDeviceandPinOptionsConfiguration,andchangetheConfigurationschemetoActiveSerialx1.
7.
ProcessingStartStartAnalysisandSynthesistoperformfullhardwaresystemcompilation.
1.
7.
5.
Programmingthe.
sofFile1.
IntheIntelQuartusPrimeProgrammer,clickonHardwaresetupandchoosethecorrectUSBchainconnectingyourFPGA.
2.
ClickonAutoDetectand5CEFA7F31appears,andchangethefiletotop.
sof.
3.
EnableProgram/Configure,andclickStart.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide211.
7.
6.
BuildingApplicationSoftwareSystemusingNiosIISoftwareBuildTools1.
IntheIntelQuartusPrime,gotoToolsNiosIISoftwareBuildToolsforEclipse.
2.
Browsetoyourworkspacedirectory.
3.
IntheNiosIISoftwareBuildToolsforEclipse,gotoFileNewNiosIIApplicationandBSPfromTemplate.
4.
IntheSOPCInformationFilenamefield,selectgeneric_flash_access.
sopcinfofromyourprojectdirectoryandclickOpen.
5.
ForProjectName,settogeneric_flash_access,chooseHelloWorldSmallprojecttemplateandclickFinish.
6.
Inthegeneric_flash_accessprojectdirectoryandreplacethehello_world_small.
cfilewithmain.
candoperation.
cfilesattachedinthereferencedesign.
7.
Selectthemain.
cfileandgotoProjectBuildProjecttocreatethegeneric_flash_access.
elffile.
8.
Selectthegeneric_flash_access.
elffileandgotoRunRunAsNiosIIHardware.
9.
TheNiosIIConsoleprintsthefollowingresults.
1.
7.
6.
1.
ReferenceDesignResultsCypressS70FL01G:FlashDevice:CypressflashS70FL01GDeviceID:4d210201AllsectorsinthisflashdeviceisnotprotectedNowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
ERASEERRORassectorisprotected!
Nowperformsectorunprotect.
.
.
Sectorunprotectsuccessfully!
:)Readingdataataddress0.
.
.
Memorycontentataddress0:abcd1234Tryingtoerasesector0.
.
.
Sectorerasesuccessfully.
Sector0isnowempty.
Writingdatatoaddress0.
.
.
Readbackdatafromaddress0.
.
.
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawritten.
Writememorysuccessful.
Nowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
ERASEERRORassectorisprotected!
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawrittenpreviously.
Sectorerasedoesnotperformduringsectorisprotected.
MicronMT25Q01G:FlashDevice:MicronflashMT25Q01GDeviceID:1021ba20AllsectorsinthisflashdeviceisnotprotectedNowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback22EraseErroraseraseisnotallowduringsectorisprotected!
Nowperformsectorunprotect.
.
.
Sectorunprotectsuccessfully!
:)Readingdataataddress0.
.
.
Memorycontentataddress0:abcd1234Address0containingdata,itisnotempty.
Tryingtoerasesector0.
.
.
Sectorerasesuccessfully.
Sector0isnowempty.
Memorynotcontainingdata.
.
.
Writingdatatoaddress0.
.
.
Readbackdatafromaddress0.
.
.
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawritten.
Writememorysuccessful.
Nowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
ERASEERRORassectorisprotected!
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawrittenpreviously.
Sectorerasedoesnotperformduringsectorisprotected.
MicronMT25Q512:FlashDevice:MicronflashMT25Q512DeviceID:1020ba20AllsectorsinthisflashdeviceisnotprotectedNowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
EraseErroraseraseisnotallowduringsectorisprotected!
Nowperformsectorunprotect.
.
.
Sectorunprotectsuccessfully!
:)Readingdataataddress0.
.
.
Memorycontentataddress0:abcd1234Address0containingdata,itisnotempty.
Tryingtoerasesector0.
.
.
Sectorerasesuccessfully.
Sector0isnowempty.
Memorynotcontainingdata.
.
.
Writingdatatoaddress0.
.
.
Readbackdatafromaddress0.
.
.
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawritten.
Writememorysuccessful.
Nowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
ERASEERRORassectorisprotected!
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawrittenpreviously.
Sectorerasedoesnotperformduringsectorisprotected.
EPCQ256:FlashDevice:EPCQ256DeviceID:1019ba20AllsectorsinthisflashdeviceisnotprotectedNowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
EraseErroraseraseisnotallowduringsectorisprotected!
Nowperformsectorunprotect.
.
.
Sectorunprotectsuccessfully!
:)Readingdataataddress0.
.
.
Memorycontentataddress0:abcd1234Address0containingdata,itisnotempty.
Tryingtoerasesector0.
.
.
Sectorerasesuccessfully.
Sector0isnowempty.
Memorynotcontainingdata.
.
.
Writingdatatoaddress0.
.
.
Readbackdatafromaddress0.
.
.
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawritten.
Writememorysuccessful.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide23Nowperformingsectorprotection.
.
.
AllsectorsinthisflashdeviceisnowsuccessfullyprotectedTryingtoerasesector0.
.
.
ERASEERRORassectorisprotected!
Currentmemoryinaddress0:abcd1234Readdatamatchwithdatawrittenpreviously.
Sectorerasedoesnotperformduringsectorisprotected.
1.
8.
FlashAccessUsingtheGenericSerialFlashInterfaceIntelFPGAIPThissectionprovidesinformationonhowtousetheregistersofthisIPtoperformflashaccess.
Tobegin,buildthePlatformDesignersystemwithafewcomponents(clock,jtagmaster,pll,andthisIP)asshownbelow.
Then,usetheflashoperationsinthenextexample.
Figure8.
ExampleofCreatingFlashAccessUsingtheGenericSerialFlashInterfaceIntelFPGAIPNote:YoumustsettheMSELpinsoftheFPGAdevicestotheASconfigurationmode.
ForIntelMAX10devices,youmustenabletheEnableSPIPinsInterfaceparameterofthisIP.
Flashoperationsaredividedintoseveralcategories.
Exampleofoperations,registerstouse,andsample.
tclscriptsforeachcategoryareprovided.
1.
8.
1.
FlashOperationsthatRequireOperationCodeThefollowingflashoperationsrequireanoperationcode:WriteenableEnter4-byteaddressingmodeExit4-byteaddressingmodeClearflagstatusregisterClearstatusregisterThefollowingregistersareusedforoperationsthatrequireanoperationcode:FlashcommandsettingregisterFlashcommandcontrolregister1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback24Example1.
PerformtheWriteEnableOperationfortheFlashprocwrite_enable{}{globalmpflash_cmd_settingflash_cmd_ctrlflash_cmd_write_data_0master_write_32$mp$flash_cmd_setting0x00000006master_write_32$mp$flash_cmd_ctrl0x1}Toperformthewriteenableoperationfortheflash,followthesesteps:1.
Definetheglobalvariables.
2.
Customizethewriteenableoperationbywritingtotheflashcommandsettingregister.
a.
Setbit[7:0]ofthisregisterto06as06histheoperationcodeofthewriteenableoperation.
3.
Write1tobit0oftheflashcommandcontrolregistertostartthewriteenableoperation.
1.
8.
2.
FlashOperationstoReadFlashRegistersThefollowingflashoperationsareusedtoreadflashregisters:ReaddeviceIDReadstatusregisterReadflagstatusregisterReadconfigurationregisterReadbankregisterReadenhancedvolatileconfigurationregisterThefollowingregistersareusedtoreadthestatusofaregister:FlashcommandsettingregisterFlashcommandcontrolregisterFlashcommandreaddata0registerExample2.
PerformtheReadDeviceIDOperationprocread_device_id{}{globalmpflash_cmd_settingflash_cmd_ctrlflash_cmd_read_data_0master_write_32$mp$flash_cmd_setting0x0000489Fmaster_write_32$mp$flash_cmd_ctrl0x1setdevice_id[master_read_32$mp$flash_cmd_read_data_01]puts$device_id}1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide25ToperformthereaddeviceIDoperation,followthesesteps:1.
Definetheglobalvariables.
2.
CustomizethereaddeviceIDoperationbywritingtotheflashcommandsettingregister.
a.
Setbit[7:0]ofthisregisterto9Fas9FhistheoperationcodeofthereaddeviceIDoperation.
b.
Setbit[10:8]to0asthisoperationdoesnotcarryanyaddressbyte.
c.
Setbit11to1asthenumberofbytedeclaredinbit[15:12]isthereaddatafromtheflashdevice.
d.
Setbit[15:12]to4asyouwillbereading4bytesdeviceIDdatafromtheflash.
3.
Write1tobit0oftheflashcommandcontrolregistertostartthereaddeviceIDoperation.
4.
ReadthedeviceIDfromtheflashcommandreaddata0register.
1.
8.
3.
FlashOperationstoWriteFlashRegistersThefollowingflashoperationsareusedtowriteflashregisters:WriteenhancedvolatileconfigurationregisterWritebankregisterWritestatusregisterWriteconfigurationregisterNote:Youmustexecutethewriteenableoperationbeforeyoustarttheseoperations.
Thefollowingregistersareusedtowritethestatusofaregister:FlashcommandsettingregisterFlashcommandcontrolregisterFlashcommandwritedata0registerExample3.
PerformtheWriteStatusRegisterOperationtoProtectSectorofFlashprocwrite_status_register{}{globalmpflash_cmd_settingflash_cmd_write_data_0flash_cmd_ctrlmaster_write_32$mp$flash_cmd_setting0x00001001master_write_32$mp$flash_cmd_write_data_00x0000007cmaster_write_32$mp$flash_cmd_ctrl0x1}Toperformthewritestatusregisteroperation,followthesesteps:1.
Definetheglobalvariables.
2.
Customizethewritestatusregisteroperationbywritingtotheflashcommandsettingregister.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback26a.
Setbit[7:0]ofthisregisterto01as01histheoperationcodeofthewritestatusregisteroperation.
b.
Setbit[10:8]to0asthisoperationdoesnotcarryanyaddressbyte.
c.
Setbit11to0asthenumberofbytedeclaredinbit[15:12]isthewritedatatotheflashdevice.
d.
Setbit[15:12]to1asyouwillbewriting1byte(8bits)ofdataintothestatusregister.
3.
Writethedatatosetthesectorprotectionintotheflashcommandwritedata0register.
a.
Bit6andbit[4:2]ofthestatusregisteraretheblockprotectbitsandbit5istheTop/Bottombit.
Inthisexample,protectionisrequiredforallsectorsfromthebottomofthememoryarray.
Formoreinformation,refertotherespectiveflashdatasheet.
4.
Write1tobit0oftheflashcommandcontrolregistertostartthewritestatusregisterforthesectorprotectoperation.
1.
8.
4.
FlashOperationsthatRequireAnAddressThefollowingflashoperationsrequireanaddress:SectoreraseBulkeraseDieeraseNote:Youmustexecutethewriteenableoperationbeforeyoustarttheseoperations.
Thefollowingregistersareusedforoperationsthatrequireanaddress:FlashcommandsettingregisterFlashcommandcontrolregisterFlashcommandaddressregisterExample4.
PerformtheFlashSectorEraseOperationprocerase_sector{}{globalmpflash_cmd_settingflash_cmd_ctrlflash_cmd_addr_registermaster_write_32$mp$flash_cmd_setting0x000004D8master_write_32$mp$flash_cmd_addr_register0x00001000master_write_32$mp$flash_cmd_ctrl0x1}Toperformtheflashsectoreraseoperation,followthesesteps:1.
Definetheglobalvariables.
2.
Customizethesectoreraseoperationbywritingtotheflashcommandsettingregister.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28SendFeedbackGenericSerialFlashInterfaceIntelFPGAIPUserGuide27a.
Setbit[7:0]ofthisregistertoD8asD8histheoperationcodeofthesectoreraseoperation.
b.
Setbit[10:8]to4as4bytesofaddresswillbesenttotheflashdevice.
c.
Setbit11to0asthenumberofbytedeclaredinbit[15:12]isthewritedatatotheflashdevice.
3.
Specifyanyaddresswithinthesectorthatyouwanttoeraseandwriteittotheflashcommandaddressregister.
a.
Inthisexample,weareperformingtheerasesectoroperationforaddress00001000.
4.
Write1tobit0oftheflashcommandcontrolregistertostartthesectoreraseoperation.
ThisIPcoresupportsflashintheextended,dual,andquadI/Oprotocols.
Currently,theprotocolssupportedbythisIPcoreisasingle-transferrate(STR)only.
ThisIPcoresupportsboththe3-byteand4-byteaddressingmodes.
Differentprotocolsandaddressingmodestoreadmemoryandprogramoperationsareexplainedinthefollowingsections.
1.
8.
5.
ReadMemoryfromtheFlashThefollowingregistersareusedtoperformthereadmemory:OperatingprotocolssettingregisterControlregisterReadinstructionregisterExample5.
PerformtheReadMemory(ExtendedMode)procread{}{globalmpoperating_protocols_settingcontrol_registerread_instrmaster_write_32$mp$operating_protocols_setting0x00000000master_write_32$mp$control_register0x00000001master_write_32$mp$read_instr0x00000003master_read_32$mp0x01000000x1}Toperformthereadmemoryfortheextendedmode,followthesesteps:1.
Definetheglobalvariables.
2.
Writetotheoperatingprotocolssettingregistertosetthetransfermodeofthereadmemoryoperation.
Inthisexample,thetransfermodeforreadis(1-1-1).
a.
Settheinstructiontransfermode[1:0]to0,readaddresstransfermode[13:12]to0,andreaddataouttransfermode[17:16]to0.
3.
Writetothecontrolregistertochoosethebyteaddressingmodeofthereadmemoryoperation.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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28GenericSerialFlashInterfaceIntelFPGAIPUserGuideSendFeedback28a.
Thisexampleisusingthe3-byteaddressingmode.
Setbit8to0.
4.
Writetothereadinstructionregistertocustomizethereadmemoryoperation.
a.
Setthereadoperationcode[7:0]to03as03histheoperationcodeforread.
b.
Setthedummycycles[12:8]to0asthereadoperationdoesnotcontainanydummycycles.
5.
Aftersettingtheregisters,youcanperformreadmemorycontentintheaddress.
a.
Inthisexample,1wordofdataisreadfromaddress0x01000000.
Example6.
PerformtheDual-OutputFastRead(Dual-SPIMode)procdual_output_fast_read{}{globalmpoperating_protocols_settingcontrol_registerread_instrmaster_write_32$mp$operating_protocols_setting0x00011001master_write_32$mp$control_register0x00000101master_write_32$mp$read_instr0x00000A3Bmaster_read_32$mp0x000001000x1}Toperformthedual-outputfastreadmode,followthesesteps:1.
Definetheglobalvariables.
2.
Writetotheoperatingprotocolssettingregistertosetthetransfermodeofthereadmemoryoperation.
Inthisexample,thetransfermodeforreadis(2-2-2).
a.
Settheinstructiontransfermode[1:0]to1,readaddresstransfermode[13:12]to1,andreaddataouttransfermode[17:16]to1.
3.
Writetothecontrolregistertochoosethebyteaddressingmodeofthereadmemoryoperation.
a.
Thisexampleisusingthe4-byteaddressingmode.
Setbit8to1.
4.
Writetothereadinstructionregistertocustomizethereadmemoryoperation.
a.
Setthereadoperationcode[7:0]to3Bas3Bhistheoperationcodeforthedual-outputfastread.
b.
Setthedummycycles[12:8]toAasthedual-outputfastreadoperationcontains10dummycycles.
5.
Aftersettingtheregisters,youcanperformdual-outputfastreadmemorycontentintheaddress.
a.
Inthisexample,thememorycontentisreadfromaddress0x00000100.
1.
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8.
6.
ProgramFlashThefollowingregistersareusedtoperformprogramflash:OperatingprotocolssettingControlregisterWriteinstructionExample7.
PerformPageProgram(ExtendedMode)procpage_program{}{globalmpoperating_protocols_settingcontrol_registerwrite_instrmaster_write_32$mp$operating_protocols_setting0x00000000master_write_32$mp$control_register0x00000001master_write_32$mp$write_instr0x00007002master_write_32$mp0x000010000x1234abcd}Toperformthepageprogramfortheextendedmode,followthesesteps:1.
Definetheglobalvariables.
2.
Writetotheoperatingprotocolssettingregistertosetthetransfermodeoftheprogramoperation.
Inthisexample,thetransfermodeforreadis(1-1-1).
a.
Settheinstructiontransfermode[1:0]to1,writeaddresstransfermode[5:4]to1,andwritedataintransfermode[9:8]to1.
3.
Writetothecontrolregistertochoosethebyteaddressingmodeofthewriteoperation.
a.
Thisexampleisusingthe3-byteaddressingmode.
Setbit8to0.
4.
Writetothewriteinstructionregistertocustomizetheprogramoperation.
a.
Setthewriteoperationcode[7:0]to02as02histheoperationcodeforpageprogram.
b.
Setthepollingoperationcode[15:8]to70as70histheoperationcodeforthereadflagstatusregister.
Aftercompletingthewriteoperation,theIPcorereleasesthewaitrequestoftheAvalonmemory-mappedinterface.
Fortheflashtohavethereadflagstatusregister,youcanusethereadstatusregister(05h).
5.
Aftersettingtheregisters,youcanstarttoprogramthememoryintotheaddress.
a.
Inthisexample,1234abcdhiswrittentothememoryaddress0x00001000.
1.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideUG-20161|2020.
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Perform4-byteQuadInputFastProgram(QuadSPIMode)procfourbyte_quad_input_fast_program{}{globalmpoperating_protocols_settingcontrol_registerwrite_instrmaster_write_32$mp$operating_protocols_setting0x00000222master_write_32$mp$control_register0x00000101master_write_32$mp$write_instr0x00007034master_write_32$mp0x000020000xabcd1234}Toperformthe4-bytequadinputfastprogram,followthesesteps:1.
Definetheglobalvariables.
2.
Writetotheoperatingprotocolssettingregistertosetthetransfermodeoftheprogramoperation.
Inthisexample,thetransfermodefor4-bytequadinputfastprogramis(4-4-4).
a.
Settheinstructiontransfermode[1:0]to2,writeaddresstransfermode[5:4]to2,andwritedataintransfermode[9:8]to2.
3.
Writetothecontrolregistertochoosethebyteaddressingmodeofthewriteoperation.
a.
Thisexampleisusingthe4-byteaddressingmode.
Setbit8to1.
4.
Writetothewriteinstructionregistertocustomizetheprogramoperation.
a.
Setthewriteoperationcode[7:0]to34as34histheoperationcodeforthe4-bytequadinputfastprogram.
b.
Setthepollingoperationcode[15:8]to70as70histheoperationcodeforthereadflagstatusregister.
Aftercompletingthewriteoperation,theIPcorereleasesthewaitrequestoftheAvalonmemory-mappedinterface.
Fortheflashtohavethereadflagstatusregister,youcanusethereadstatusregister(05h).
5.
Aftersettingtheregisters,youcanstarttoprogramthememoryintotheaddress.
a.
Inthisexample,1234abcdhiswrittentothememoryaddress0x00002000.
1.
9.
GenericSerialFlashInterfaceIntelFPGAIPUserGuideArchivesIPversionsarethesameastheIntelQuartusPrimeDesignSuitesoftwareversionsuptov19.
1.
FromIntelQuartusPrimeDesignSuitesoftwareversion19.
2orlater,IPcoreshaveanewIPversioningscheme.
IfanIPcoreversionisnotlisted,theuserguideforthepreviousIPcoreversionapplies.
IntelQuartusPrimeVersionIPCoreVersionUserGuide20.
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DocumentRevisionHistoryfortheGenericSerialFlashInterfaceIntelFPGAIPUserGuideDocumentVersionIntelQuartusPrimeVersionIPVersionChanges2020.
09.
2820.
320.
0.
0Addedanewregistersetting—tSHSL.
Addedanewsection—ConstrainingtheI/OPins.
UpdatedthedescriptionforEnableflashsimulationmodelinTable:ParameterSettings.
RemovedControlStatusRegisterOperations.
Updatedthefollowingtopics:—GenericSerialFlashInterfaceIntelFPGAIPUserGuide—ReleaseInformation—MemoryOperationsUpdatedtheHardwareandSoftwareRequirementsoftheGenericSerialFlashInterfaceIntelFPGAIPReferenceDesignsection.
UpdatedthedescriptionofOn-ChipMemoryIntelFPGAIPinTable:ReferenceDesignComponentsDescriptions.
UpdatedCreatingNiosIIHardwareSystem:—Updatedthedescriptioninstep7c.
—UpdatedFigure:CompletedPlatformDesignerConnection.
Mademinoreditorialupdatesthroughoutthedocument.
2020.
05.
0820.
119.
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1Addednewsections—ReleaseInformationandControlStatusRegisterByteEnable.
UpdatedTable:ParameterSettingstoincludeanewparameter—UsebyteenableforCSR.
Addedanewsignal—avl_csr_byteenable.
UpdatedFigure:SignalBlockDiagram.
UpdatedthenotetotheDeviceFamilySupporttopic.
2020.
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1RenameddocumenttitleasGenericSerialFlashInterfaceIntelFPGAIPUserGuideAddedtheByteEnablingsection.
AddedanotetotheDeviceFamilySupporttopic.
UpdatedtheMemoryOperationstopic.
Updatedforlatestbrandingstandards.
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1AddedanotetotheMemoryOperationstopic.
2019.
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1AddedsupportforIntelAgilexdevices.
UpdatedtheDeviceFamilySupporttopic.
Mademinoreditorialupdatestothedocument.
continued.
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1AddedtheFlashAccessUsingtheGenericSerialFlashInterfaceIntelFPGAIPCoresection.
AddedtheGenericSerialFlashInterfaceIntelFPGAIPCoreUserGuideArchivessection.
UpdatedtheGenericSerialFlashInterfaceIntelFPGAIPCoreUserGuidesectiontoprovidemoreinformationontheGenericSerialFlashInterfaceIntelFPGAIPcore.
UpdatedthesignalnamesoftheSignalBlockDiagramfigure.
UpdatedtheConduitInterfacesignalnamesinthePortsDescriptiontable.
UpdatedthedescriptionofthewriteopcodefieldnameofthewriteinstructionregisterintheRegisterMaptable.
2018.
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0UpdatedtheGenericSerialFlashInterfaceIntelFPGAIPCoreReferenceDesignFileslink.
AddedFlashCommandAddressRegisterintheRegisterMap.
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