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2005byCatalystSemiconductor,Inc.
Characteristicssubjecttochangewithoutnotice1CAT25C11/03/05/09/171K/2K/4K/8K/16KSPISerialCMOSEEPROMDoc.
No.
1017,Rev.
LFEATURESs10MHzSPIcompatibles1.
8to6.
0voltoperationsHardwareandsoftwareprotectionsLowpowerCMOStechnologysSPImodes(0,0&1,1)*sCommercial,industrial,automotiveandextendedtemperaturerangess1,000,000program/erasecycless100yeardataretentionsSelf-timedwritecycles8-pinDIP/SOIC,8-pinTSSOPand8-pinMSOPs16/32-bytepagewritebuffersWriteprotection–Protectfirstpage,lastpage,any1/4arrayorlower1/2arrayPINCONFIGURATIONDIPPackage(P,L,GL)PINFUNCTIONSPinNameFunctionSOSerialDataOutputSCKSerialClockWPWriteProtectVCC+1.
8Vto+6.
0VPowerSupplyVSSGroundCSChipSelectSISerialDataInputHOLDSuspendsSerialInputNCNoConnectBLOCKDIAGRAMDESCRIPTIONTheCAT25C11/03/05/09/17isa1K/2K/4K/8K/16K-BitSPISerialCMOSEEPROMinternallyorganizedas128x8/256x8/512x8/1024x8/2048x8bits.
Catalyst'sadvancedCMOSTechnologysubstantiallyreducesdevicepowerrequirements.
TheCAT25C11/03/05featuresa16-bytepagewritebuffer.
The25C09/17featuresa32-bytepagewritebuffer.
ThedeviceoperatesviatheSPIbusserialinterfaceandisenabledthoughaChipSelect(CS).
InadditiontotheChipSelect,theclockinput(SCK),datain(SI)anddataout(SO)arerequiredtoaccessthedevice.
TheHOLDpinmaybeusedtosuspendanyserialcommunicationwithoutresettingtheserialsequence.
TheCAT25C11/03/05/09/17isdesignedwithsoftwareandhardwarewriteprotectionfeaturesincludingBlockWriteprotection.
Thedeviceisavailablein8-pinDIP,8-pinSOIC,8/14-pinTSSOPand8-pinMSOPpackages.
SOICPackage(S,V,GV)VSSSOWPVCCHOLDSCKSI12348765CSSOWPCSVCCSCKSI12348765VSSHOLDTSSOPPackage(U,Y,GY)8765VCCWPSCKCSVSS1234SOHOLDSISOWPCSVCCSCKSI12348765VSSHOLDMSOPPackage(R,Z,GZ)**CAT25C11/03onlySENSEAMPSSHIFTREGISTERSSPICONTROLLOGICWORDADDRESSBUFFERSI/OCONTROLEEPROMARRAYCOLUMNDECODERSXDECHIGHVOLTAGE/TIMINGCONTROLSOSTATUSREGISTERBLOCKPROTECTLOGICCONTROLLOGICDATAINSTORAGESICSWPHOLDSCK*OtherSPImodesavailableonrequest.
2CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeD.
C.
OPERATINGCHARACTERISTICSVCC=+1.
8Vto+6.
0V,unlessotherwisespecified.
LimitsSymbolParameterMin.
Typ.
Max.
UnitsTestConditionsICC1PowerSupplyCurrent5mAVCC=5V@5MHz(OperatingWrite)SO=open;CS=VssICC2PowerSupplyCurrent3mAVCC=5.
5V(OperatingRead)FCLK=5MHzISB(6)PowerSupplyCurrent1ACS=VCC(Standby)VIN=VSSorVCCILIInputLeakageCurrent2AILOOutputLeakageCurrent3AVOUT=0VtoVCC,CS=0VVIL(5)InputLowVoltage-1VCCx0.
3VVIH(5)InputHighVoltageVCCx0.
7VCC+0.
5VVOL1OutputLowVoltage0.
4VVOH1OutputHighVoltageVCC-0.
8VVOL2OutputLowVoltage0.
2V1.
8V≤VCC<2.
7VVOH2OutputHighVoltageVCC-0.
2VIOL=150AIOH=-100AABSOLUTEMAXIMUMRATINGS*TemperatureUnderBias55°Cto+125°CStorageTemperature.
65°Cto+150°CVoltageonanyPinwithRespecttoVSS(1)2.
0Vto+VCC+2.
0VVCCwithRespecttoVSS2.
0Vto+7.
0VPackagePowerDissipationCapability(Ta=25°C)1.
0WLeadSolderingTemperature(10secs)300°COutputShortCircuitCurrent(2)100mA*COMMENTStressesabovethoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsoutsideofthoselistedintheoperationalsectionsofthisspecifica-tionisnotimplied.
Exposuretoanyabsolutemaximumratingforextendedperiodsmayaffectdeviceperfor-manceandreliability.
Note:(1)TheminimumDCinputvoltageis–0.
5V.
Duringtransitions,inputsmayundershootto–2.
0Vforperiodsoflessthan20ns.
MaximumDCvoltageonoutputpinsisVCC+0.
5V,whichmayovershoottoVCC+2.
0Vforperiodsoflessthan20ns.
(2)Outputshortedfornomorethanonesecond.
Nomorethanoneoutputshortedatatime.
(3)TheseparameteraretestedinitiallyandafteradesignorprocesschangethataffectstheparameteraccordingtoappropriateAEC-Q100andJEDECtestmethods.
(4)Latch-upprotectionisprovidedforstressesupto100mAonaddressanddatapinsfrom–1VtoVCC+1V.
(5)VILMINandVIHMAXarereferencevaluesonlyandarenottested.
(6)Maximumstandbycurrent(ISB)=10AfortheAutomotiveandExtendedAutomotivetemperaturerange.
2.
7V≤VCC<5.
5VIOL=3.
0mAIOH=-1.
6mARELIABILITYCHARACTERISTICSSymbolParameterMin.
Typ.
Max.
UnitsNEND(3)Endurance1,000,000Cycles/ByteTDR(3)DataRetention100YearsVZAP(3)ESDSusceptibility2000VoltsILTH(3)(4)Latch-up100mA3CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeLimits1.
8V-6.
0V2.
5V-6.
0V4.
5V-5.
5VTestSYMBOLPARAMETERMin.
Max.
Min.
Max.
Min.
Max.
UNITSConditionstSUDataSetupTime502020nsVIH=2.
4VtHDataHoldTime502020nsCL=100pFtWHSCKHighTime2507540nsVOL=0.
8VtWLSCKLowTime2507540nsVOH=2.
0vfSCKClockFrequencyDC1DC5DC10MHztLZHOLDtoOutputLowZ505050nstRI(1)InputRiseTime222stFI(1)InputFallTime222stHDHOLDSetupTime1004040nstCDHOLDHoldTime1004040nsCL=100pFtWC(3)WriteCycleTime1055mstVOutputValidfromClockLow2507540nstHOOutputHoldTime000nstDISOutputDisableTime2507575nstHZHOLDtoOutputHighZ1505050nstCSCSHighTime500100100nstCSSCSSetupTime500100100nstCSHCSHoldTime500100100nstWPSWPSetupTime1505050nstCSHCSHoldTime1505050ns(1)Thisparameteristestedinitiallyandafteradesignorprocesschangethataffectstheparameter.
(2)ACTestConditions:InputPulseVoltages:0.
3VCCto0.
7VCCInputriseandfalltimes:≤10nsInputandoutputreferencevoltages:0.
5VCCOutputload:currentsourceIOLmax/IOHmax;CL=50pF(3)tWCisthetimefromtherisingedgeofCSafteravalidwritesequencetotheendoftheinternalwritecycle.
A.
C.
CHARACTERISTICSCL=50pF(note2)PINCAPACITANCE(1)ApplicableoverrecommendedoperatingrangefromTA=25C,f=1.
0MHz,VCC=+5.
0V(unlessotherwisenoted).
SymbolTestConditionsMax.
UnitsConditionsCOUTOutputCapacitance(SO)8pFVOUT=0VCINInputCapacitance(CS,SCK,SI,WP,HOLD)6pFVIN=0V4CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeFUNCTIONALDESCRIPTIONTheCAT25C11/03/05/09/17supportstheSPIbusdatatransmissionprotocol.
ThesynchronousSerialPeriph-eralInterface(SPI)helpstheCAT25C11/03/05/09/17tointerfacedirectlywithmanyoftoday'spopularmicrocontrollers.
TheCAT25C11/03/05/09/17containsan8-bitinstructionregister.
(Theinstructionsetandtheoperationcodesaredetailedintheinstructionsettable)AfterthedeviceisselectedwithCSgoinglow,thefirstbytewillbereceived.
ThepartisaccessedviatheSIpin,withdatabeingclockedinontherisingedgeofSCK.
Thefirstbytecontainsoneofthesixop-codesthatdefineInstructionOpcodeOperationWREN00000110EnableWriteOperationsWRDI00000100DisableWriteOperationsRDSR00000101ReadStatusRegisterWRSR00000001WriteStatusRegisterREAD0000X011(1)ReadDatafromMemoryWRITE0000X010(1)WriteDatatoMemoryINSTRUCTIONSETtheoperationtobeperformed.
PINDESCRIPTIONSI:SerialInputSIistheserialdatainputpin.
Thispinisusedtoinputallopcodes,byteaddresses,anddatatobewrittentothe25C11/03/05/09/17.
InputdataislatchedontherisingedgeoftheserialclockforSPImodes(0,0&1,1).
SO:SerialOutputSOistheserialdataoutputpin.
Thispinisusedtotransferdataoutofthe25C11/03/05/09/17.
Duringareadcycle,dataisshiftedoutonthefallingedgeoftheserialclockforFigure1.
SychronousDataTimingCSNC123414131211NCNCNC5671098NCSCKVSSSINCWPVCCHOLDSO1516NCNCNote:DashedLine=mode(1,1)Note:(1)X=0for25C11,25C03,25C09,25C17.
X=A8for25C05(2)Thisparameteristestedinitiallyandafteradesignorprocesschangethataffectstheparameter.
(3)tPURandtPUWarethedelaysrequiredfromthetimeVCCisstableuntilthespecifiedoperationcanbeinitiated.
Power-UpTiming(2)(3)SymbolParameterMax.
UnitstPURPower-uptoReadOperation1mstPUWPower-uptoWriteOperation1ms5CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeSPImodes(0,0&1,1).
SCK:SerialClockSCKistheserialclockpin.
Thispinisusedtosynchronizethecommunicationbetweenthemicrocontrollerandthe25C11/03/05/09/17.
Opcodes,byteaddresses,ordatapresentontheSIpinarelatchedontherisingedgeoftheSCK.
DataontheSOpinisupdatedonthefallingedgeoftheSCKforSPImodes(0,0&1,1).
CSCSCSCSCS:ChipSelectCSistheChipselectpin.
CSlowenablestheCAT25C11/03/05/09/17andCShighdisablestheCAT25C11/03/05/09/17.
CShightakestheSOoutputpintohighimpedance76543210WPEN11BP2BP1BP0WELRDYSTATUSREGISTERBP2BP1BP0000Non-Protection001Q1Protected010Q2Protected011Q3Protected100Q4Protected101H1Protected110P0Protected111PnProtectedMEMORYPROTECTION25C1125C0325C0525C0925C17Q100-1F00-3F000-07F000-0FF000-1FFQ220-3F40-7F080-0FF100-1FF200-3FFQ340-5F80-BF100-17F200-2FF400-5FFQ460-7FC0-FF180-1FF300-3FF600-7FFH100-3F00-7F000-0FF000-1FF000-3FFP000-0F00-0F000-00F000-01F000-01FPn70-7FF0-FF1F0-1FF3E0-3FF7E0-7FFProtectedUnprotectedStatusWPENWPWPWPWPWPWELBlocksBlocksRegister0X0ProtectedProtectedProtected0X1ProtectedWritableWritable1Low0ProtectedProtectedProtected1Low1ProtectedWritableProtectedXHigh0ProtectedProtectedProtectedXHigh1ProtectedWritableWritableWRITEPROTECTENABLEOPERATIONandforcesthedevicesintoaStandbyMode(unlessaninternalwriteoperationisunderway)TheCAT25C11/03/05/09/17drawsZEROcurrentintheStandbymode.
AhightolowtransitiononCSisrequiredpriortoanysequencebeinginitiated.
AlowtohightransitiononCSafteravalidwritesequenceiswhatinitiatesaninternalwritecycle.
WPWPWPWPWP:WriteProtectWPistheWriteProtectpin.
TheWriteProtectpinwillallownormalread/writeoperationswhenheldhigh.
WhenWPistiedlowandtheWPENbitinthestatusregisterissetto"1",allwriteoperationstothestatusregisterareinhibited.
WPgoinglowwhileCSisstilllowwillinterruptawritetothestatusregister.
Iftheinternalwritecycleasalreadybeeninitiated,WPgoinglowwillhavenoeffectonanywriteBYTEADDRESSDeviceAddressSignificantBitsAddressDon'tCareBits#AddressClockPulseCAT25C11A6-A0A78CAT25C03A7-A0—8CAT25C05A7-A0(A8=XbitfromOpcode)—8CAT25C09A9-A0A15-A1016CAT25C17A10-A0A15-A11166CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeFigure2.
WRENInstructionTimingFigure3.
WRDIInstructionTimingoperationtothestatusregister.
TheWPpinfunctionisblockedwhentheWPENbitissetto0.
Figure10illustratestheWPtimingsequenceduringawriteoperation.
HOLDHOLDHOLDHOLDHOLD:HoldHOLDistheHOLDpin.
TheHOLDpinisusedtopausetransmissiontotheCAT25C11/03/05/09/17whileinthemiddleofaserialsequencewithouthavingtore-transmitentiresequenceatalatertime.
Topause,HOLDmustbebroughtlowwhileSCKislow.
TheSOpinisinahighimpedancestateduringthetimethepartispaused,andtransitionsontheSIpinswillbeignored.
Toresumecommunication,HOLDisbroughthigh,whileSCKislow.
HOLDshouldbeheldhighanytimethisfunctionisnotbeingused.
HOLDmaybetiedhighdirectlytoVCCortiedtoVCCthrougharesistor.
Figure9illustratesholdtimingsequence.
STATUSREGISTERTheStatusRegisterindicatesthestatusofthedevice.
TheRDY(Ready)bitindicateswhethertheCAT25C11/SKSICSSO00000110HIGHIMPEDANCESKSICSSO00000100HIGHIMPEDANCENote:DashedLine=mode(1,1)Note:DashedLine=mode(1,1)03/05/09/17isbusywithawriteoperation.
Whensetto1awritecycleisinprogressandwhensetto0thedeviceindicatesitisready.
ThisbitisreadonlytheWEL(WriteEnable)bitindicatesthestatusofthewriteenablelatch.
Whensetto1,thedeviceisinaWriteEnablestateandwhensetto0thedeviceisinaWriteDisablestate.
TheWELbitcanonlybesetbytheWRENinstructionandcanberesetbytheWRDIinstruction.
TheBP0,BP1andBP2bitsindicatewhichpartofthememoryarrayiscurrentlyprotected.
ThesebitsaresetbytheuserissuingtheWRSRinstruction.
Theuserisallowedtoprotectfromonepagetoasmuchashalftheentirearray.
Oncethethreeprotectionbitsaresettheassociatedmemorycanbereadbutnotwrittenuntiltheprotectionbitsarereset.
Thesebitsarenonvolatile.
TheWPEN(WriteProtectEnable)isanenablebitfortheWPpin.
TheWPpinandWPENbitinthestatusregistercontroltheprogrammablehardwarewriteprotectfea-ture.
HardwarewriteprotectionisenabledwhenWPislowandWPENbitissettohigh.
Theusercannotwritetothestatusregister,(includingtheblockprotectbits7CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeFigure4.
ReadInstructionTimingAfterthecorrectreadinstructionandaddressaresent,thedatastoredinthememoryattheselectedaddressisshiftedoutontheSOpin.
Thedatastoredinthememoryatthenextaddresscanbereadsequentiallybycontinuingtoprovideclockpulses.
Theinternaladdresspointerisautomaticallyincrementedtothenexthigheraddressaftereachbyteofdataisshiftedout.
Whenthehighestaddressisreached,theaddresscounterrollsoverto0000hallowingthereadcycletobecontinuedindefinitely.
ThereadoperationisterminatedbypullingtheCShigh.
ReadsequeceisillustratedinFigure4.
ReadingstatusregisterisillustratedinFigure5.
Toreadthestatusregister,RDSRinstructionshouldbesent.
ThecontentsofthestatusregisterareshiftedoutontheSOline.
Ifanon-volatilewriteisinprogress,theRDSRinstructionreturnsahighonSO.
Whenthenon-volatilewritecycleiscompleted,thestatusregisterdataisreadout.
WRITESequenceTheCAT25C11/03/05/09/17powersupinaWriteDis-ablestate.
Priortoanywriteinstructions,theWRENinstructionmustbesenttoCAT25C11/03/05/09/17.
ThedevicegoesintoWriteenablestatebypullingtheCSlowandthenclockingtheWRENinstructionintoCAT25C11/03/05/09/17.
TheCSmustbebroughthighSKSISO0000X*011BYTEADDRESS*012345678910202122232425262728293076543210*PleasechecktheByteAddressTable.
CSOPCODEDATAOUTMSBHIGHIMPEDANCE**ANA0*X=0forCAT25C11,CAT25C03,CAT25C09andCAT25C17;X=A8forCAT25C05.
Note:DashedLine=mode(1,1)andtheWPENbit)andtheblockprotectedsectionsinthememoryarraywhenthechipishardwarewriteprotected.
Onlythesectionsofthememoryarraythatarenotblockprotectedcanbewritten.
HardwarewriteprotectionisdisabledwheneitherWPpinishighortheWPENbitiszero.
DEVICEOPERATIONWriteEnableandDisableTheCAT25C11/03/05/09/17containsawriteenablelatch.
Thislatchmustbesetbeforeanywriteoperation.
ThedevicepowersupinawritedisablestatewhenVccisapplied.
WRENinstructionwillenablewrites(setthelatch)tothedevice.
WRDIinstructionwilldisablewrites(resetthelatch)tothedevice.
Disablingwriteswillprotectthedeviceagainstinadvertentwrites.
READSequenceThepartisselectedbypullingCSlow.
The8-bitreadinstructionistransmittedtotheCAT25C11/03/05/09/17,followedbythe16-bitaddressfor25C09/17(only10-bitaddressesareusedfor25C09,11-bitaddressesareusedfor25C17.
Therestofthebitsaredon'tcarebits)and8-bitaddressfor25C11/03/05(forthe25C05,bit3ofthereaddatainstructioncontainsaddressA8).
8CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeFigure6.
WriteInstructionTimingSKSISO0000X*010D7D6D5D4D3D2D1D00123456782122232425262728293031CSOPCODEDATAINHIGHIMPEDANCEBYTEADDRESS***ANA0*PleasechecktheByteAddressTableX=0forCAT25C11,CAT25C03,CAT25C09andCAT25C17;X=A8forCAT25C05Note:DashedLine=mode(1,1)device.
IfthewriteoperationisinitiatedimmediatelyaftertheWRENinstructionwithoutCSbeingbroughthigh,thedatawillnotbewrittentothearraybecausethewriteupto16bytesofdatatotheCAT25C11/03/05and32bytesofdatafor25C09/17.
Aftereachbyteofdatareceived,lowerorderaddressbitsareinternallyincrementedbyone;thehighorderbitsofaddresswillremainconstant.
TheonlyrestrictionisthattheX(X=16for25C11/03/05andX=32for25C09/17)bytesmustresideonthesamepage.
Iftheaddresscounterreachestheendofthepageandclockcontinues,thecounterwill"rollover"tothefirstaddressofthepageandoverwriteanydatathatmayhavebeenwritten.
TheCAT25C11/03/05/09/17isautomaticallyreturnedtothewritedisablestateatthecompletionofthewritecycle.
Figure8illustratesthepagewritesequence.
Towritetothestatusregister,theWRSRinstructionshouldbesent.
OnlyBit2,Bit3,Bit4andBit7ofthestatusregistercanbewrittenusingthewritestatusregisterinstruction.
Figure7illustratesthesequenceofwritingtostatusregister.
enablelatchwillnothavebeenproperlyset.
Also,forasuccessfulwriteoperationtheaddressofthememorylocation(s)tobeprogrammedmustbeoutsidethepro-tectedaddressfield.
ByteWriteOncethedeviceisinaWriteEnablestate,theusermayproceedwithawritesequencebysettingtheCSlow,issuingawriteinstructionviatheSIline,followedbythe16-bitaddressfor25C09/17.
(only10-bitaddressesareusedfor25C09,11-bitaddressesareusedfor25C17.
Therestofthebitsaredon'tcarebits)and8-bitaddressfor25C11/03/05(forthe25C05,bit3ofthereaddatainstructioncontainsaddressA8).
ProgrammingwillstartaftertheCSisbroughthigh.
Figure6illustratesbytewritesequence.
PageWriteTheCAT25C11/03/05/09/17featurespagewritecapa-bility.
Aftertheinitialbyte,thehostmaycontinuetowriteaftertheWRENinstructiontoenablewritestotheeFigure5.
RDSRInstructionTiming01234567810911121314SCKSIDATAOUTMSBHIGHIMPEDANCEOPCODESO76543210CS00000101Note:DashedLine=mode(1,1)9CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeFigure7.
WRSRInstructionTimingDESIGNCONSIDERATIONSTheCAT25C11/03/05/09/17powersupinawritedis-ablestateandinalowpowerstandbymode.
AWRENinstructionmustbeissuedtoperformanywritestothedeviceafterpowerup.
Also,onpowerupCSshouldbebroughtlowtoenterareadystateandreceiveaninstruction.
Afterasuccessfulbyte/pagewriteorstatusregisterwritetheCAT25C11/03/05/09/17goesintoawritedisablemode.
CSmustbesethighafterthepropernumberofclockcyclestostartaninternalwritecycle.
Accesstothearrayduringaninternalwritecycleisignoredandprogrammingiscontinued.
Onpowerup,SOisinahighimpedance.
IfaninvalidopcodeisFigure8.
PageWriteInstructionTiming01234567810911121314SCKSIMSBHIGHIMPEDANCEDATAIN15SOCS7654321000000001OPCODENote:DashedLine=mode(1,1)Note:DashedLine=mode(1,1)received,nodatawillbeshiftedintotheCAT25C11/03/05/09/17,andtheserialoutputpin(SO)willremaininahighimpedancestateuntilthefallingedgeofCSisdetectedagain.
Whenpoweringdown,thesupplyshouldbetakendownto0V,sothattheCAT25C11/03/05/09/17willberesetwhenpowerisrampedbackup.
Ifthisisnotpossible,then,followingabrown-outepisode,theCAT25C11/03/05/09/17canberesetbyrefreshingthecontentsoftheStatusRegister(SeeApplicationNoteAN10).
SKSISO0000X*010DataByte101234567821222324-3132-39DataByte2DataByte3DataByteNCSOPCODE7.
.
1024+(N-1)x8-1.
.
24+(N-1)x824+Nx8-1DATAINHIGHIMPEDANCEBYTEADDRESS**PleasechecktheByteAddressTable.
ANA0*X=0forCAT25C11,CAT25C03,CAT25C09andCAT25C17;X=A8forCAT25C0510CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeFigure9.
HOLDHOLDHOLDHOLDHOLDTimingCSSCKHOLDSOtCDtHDtHDtCDtLZtHZHIGHIMPEDANCENote:DashedLine=mode(1,1)tCSHCSSCKWPWPtWPStWPHFigure10.
WPWPWPWPWPTiming11CAT25C11/03/05/09/17Doc.
No.
1017,Rev.
L2005byCatalystSemiconductor,Inc.
CharacteristicssubjecttochangewithoutnoticeNotes:(1)Thedeviceusedintheaboveexampleisa25C17SI-1.
8TE13(SOIC,IndustrialTemperature,1.
8Voltto6VoltOperatingVoltage,Tape&Reel)(2)CAT25C11andCAT25C03only.
ORDERINGINFORMATIONPrefixDevice#Suffix25C17SITE13ProductNumber25C17:16K25C09:8K25C05:4K25C03:2KTape&ReelOperatingVoltageBlank(Vcc=2.
5to6.
0V)1.
8(Vcc=1.
8to6.
0V)-1.
8CATTemperatureRangeBlank=Commercial(0°Cto+70°C)I=Industrial(-40°Cto+85°C)A=Automotive(-40°Cto+105°C)OptionalCompanyID25C11:1KE=Extended(-40°Cto+125°C)PackageP:PDIPR:MSOP2S:SOICU:TSSOPL:PDIP(Leadfree,Halogenfree)V:SOIC,JEDEC(Leadfree,Halogenfree)Y:TSSOP(Leadfree,Halogenfree)Z:MSOP2(Leadfree,Halogenfree)GL:PDIP(Lead-free,Halogen-free,NiPdAuleadplating)GV:SOIC,JEDEC(Lead-free,Halogen-free,NiPdAuleadplating)GY:TSSOP(Lead-free,Halogen-free,NiPdAuleadplating)GZ:MSOP2(Lead-free,Halogen-free,NiPdAuleadplating)CatalystSemiconductor,Inc.
CorporateHeadquarters1250BorregasAvenueSunnyvale,CA94089Phone:408.
542.
1000Fax:408.
542.
1200www.
caalyst-semiconductor.
comCopyrights,TrademarksandPatentsTrademarksandregisteredtrademarksofCatalystSemiconductorincludeeachofthefollowing:DPPAE2MiniPotCatalystSemiconductorhasbeenissuedU.
S.
andforeignpatentsandhaspatentapplicationspendingthatprotectitsproducts.
ForacompletelistofpatentsissuedtoCatalystSemiconductorcontacttheCompany'scorporateofficeat408.
542.
1000.
CATALYSTSEMICONDUCTORMAKESNOWARRANTY,REPRESENTATIONORGUARANTEE,EXPRESSORIMPLIED,REGARDINGTHESUITABILITYOFITSPRODUCTSFORANYPARTICULARPURPOSE,NORTHATTHEUSEOFITSPRODUCTSWILLNOTINFRINGEITSINTELLECTUALPROPERTYRIGHTSORTHERIGHTSOFTHIRDPARTIESWITHRESPECTTOANYPARTICULARUSEORAPPLICATIONANDSPECIFICALLYDISCLAIMSANYANDALLLIABILITYARISINGOUTOFANYSUCHUSEORAPPLICATION,INCLUDINGBUTNOTLIMITEDTO,CONSEQUENTIALORINCIDENTALDAMAGES.
CatalystSemiconductorproductsarenotdesigned,intended,orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody,orotherapplicationsintendedtosupportorsustainlife,orforanyotherapplicationinwhichthefailureoftheCatalystSemiconductorproductcouldcreateasituationwherepersonalinjuryordeathmayoccur.
CatalystSemiconductorreservestherighttomakechangestoordiscontinueanyproductorservicedescribedhereinwithoutnotice.
Productswithdatasheetslabeled"AdvanceInformation"or"Preliminary"andotherproductsdescribedhereinmaynotbeinproductionorofferedforsale.
CatalystSemiconductoradvisescustomerstoobtainthecurrentversionoftherelevantproductinformationbeforeplacingorders.
Circuitdiagramsillustratetypicalsemiconductorapplicationsandmaynotbecomplete.
Publication#:1017Revison:LIssuedate:09/22/05REVISIONHISTORYDateRev.
Reason08/03/2004JUpdatedFeaturesUpdatedDCOperatingCharacteristicstable¬es07/08/2005KUpdateFeaturesUpdatePinConfigurationUpdateReliabilityCharacteristicsUpdateOrderingInformation09/22/2005LUpdatePinConfiguration