VOLwww

DAC3482www.
ti.
comSLAS748E–MARCH2011–REVISEDJULY2013Dual-Channel,16-BIT,1.
25GSPSDigital-to-AnalogConverter(DAC)CheckforSamples:DAC34821FEATURESDESCRIPTIONTheDAC3482isaverylowpower,highdynamicVeryLowPower:900mWat1.
25GSPS,Fullrange,dual-channel,16-bitdigital-to-analogconverterOperatingConditions(DAC)withasamplerateashighas1.
25GSPS.
Multi-DACSynchronizationThedeviceincludesfeaturesthatsimplifythedesignSelectable2x,4x,8x,16xInterpolationFilterofcomplextransmitarchitectures:2xto16xdigital–Stop-BandAttenuation>90dBcinterpolationfilterswithover90dBofstop-bandattenuationsimplifythedatainterfaceandFlexibleOn-ChipComplexMixingreconstructionfilters.
Acomplexmixerallowsflexible–FineMixerwith32-bitNCOcarrierplacement.
Ahigh-performancelowjitterclock–PowerSavingCoarseMixer:±n*Fs/8multipliersimplifiesclockingofthedevicewithoutHighPerformance,LowJitterClocksignificantimpactonthedynamicrange.
ThedigitalQuadratureModulatorCorrection(QMC)enablesMultiplyingPLLcompleteIQcompensationforgain,offset,phase,DigitalIandQCorrectionandgroupdelaybetweenchannelsindirectup-–Gain,Phase,Offset,andGroupDelayconversionapplications.
CorrectionDigitaldataisinputtothedevicethroughaflexibleDigitalInverseSincFilterLVDSdatabuswithon-chiptermination.
DatacanbeFlexibleLVDSInputDataBusinputeitherword-wideorbyte-wide.
ThedeviceincludesaFIFO,datapatterncheckerandparitytest–Word-orByte-WideInterfacetoeasetheinputinterface.
Theinterfacealsoallows–8SampleInputFIFOfullsynchronizationofmultipledevices.
–DataPatternCheckerThedeviceischaracterizedforoperationoverthe–ParityCheckentireindustrialtemperaturerangeof–40°Cto85°CTemperatureSensorandisavailableinavery-small88-pin9x9mmWQFNpackage.
DifferentialScalableOutput:10mAto30mAMultiplePackageOptions:88-pin9x9mmTheDAC3482verylowpower,smallsize,superiorWQFNand196-ball12mmx12mmBGAcrosstalk,highdynamicrangeandfeaturesareanidealfitfortoday'scommunicationsystems.
(GREEN/Pb-Free)APPLICATIONSCellularBaseStationsDiversityTransmitWidebandCommunicationsThesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2011–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
ti.
comFUNCTIONALBLOCKDIAGRAM2SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013DEVICEINFORMATIONPINOUTPINFUNCTIONSPINI/ODESCRIPTIONNAMENO.
A36,A37,A38,A40,AVDDIAnalogsupplyvoltage.
(3.
3V)A41,A42,B31CMOSoutputforALARMcondition.
TheALARMoutputfunctionalityisdefinedthroughtheconfig7ALARMB29Oregister.
Defaultpolarityisactivehigh,butcanbechangedtoactivelowviaconfig0alarm_out_polcontrolbit.
Full-scaleoutputcurrentbias.
For30mAfull-scaleoutputcurrent,connect1.
28kΩtoground.
ChangeBIASJA33Othefull-scaleoutputcurrentthroughcoarse_dac(3:0)inconfig3,bitInternalclockbuffersupplyvoltage.
(1.
2V)CLKVDDA4IItisrecommendedtoisolatethissupplyfromDIGVDDandDACVDD.
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comPINFUNCTIONS(continued)PINI/ODESCRIPTIONNAMENO.
LVDSpositiveinputdatabits0through15.
Internal100terminationresistor.
DataformatrelativetoA7,A8,B9,DATACLKP/NclockisDoubleDataRate(DDR)andcanbetransferredineitherbyte-wideorword-B10,A12,widemode.
Inbyte-widemodetheunusedpinscanbeleftunconnected.
A13,A14,A15,B17,D15Pismostsignificantdatabit(MSB)inword-widemodeD[15.
.
0]PIB18,B19,D7Pismostsignificantdatabit(MSB)inbyte-widemodeB20,A23,D0Pisleastsignificantdatabit(LSB)A24,B23,B24Theorderofthebuscanbereversedviaconfig2revbusbit.
B7,B8,A10,A11,B11,B12,B13,B14,A19,D[15.
.
0]NILVDSnegativeinputdatabits0through15.
(SeeD[15:0]Pdescriptionabove)A20,A21,A22,B21,B22,A26,A27DACCLKPA3IPositiveexternalLVPECLclockinputforDACcorewithaself-bias.
DACCLKNB3IComplementaryexternalLVPECLclockinputforDACcore.
(seetheDACCLKPdescription)A35,A39,DACcoresupplyvoltage.
(1.
2V).
ItisrecommendedtoisolatethissupplyfromCLKVDDandDACVDDIA43DIGVDD.
LVDSpositiveinputdataclock.
Internal100terminationresistor.
InputdataD[15:0]P/NislatchedDATACLKPA16IonbothedgesofDATACLKP/N(DoubleDataRate).
DATACLKNB15ILVDSnegativeinputdataclock.
(SeeDATACLKPdescription)A6,A9,A25,DIGVDDIDigitalsupplyvoltage.
(1.
2V).
ItisrecommendedtoisolatethissupplyfromCLKVDDandDACVDD.
A28Usedasexternalreferenceinputwheninternalreferenceisdisabledthroughconfig27extref_ena=EXTIOA34I/O'1'.
Usedasinternalreferenceoutputwhenconfig27extref_ena='0'(default).
Requiresa0.
1μFdecouplingcapacitortoAGNDwhenusedasreferenceoutput.
LVDSframeindicatorpositiveinput.
Internal100terminationresistor.
ThemainfunctionsofthisinputaretoresettheFIFOortobeusedasasyncingsource.
ThesetwofunctionsarecapturedwithFRAMEPB16ItherisingedgeofDATACLKP/N.
ThesignalcapturedbythefallingedgeofDATACLKP/Ncanbeusedasablockparitybit.
TheFRAMEP/Nsignalshouldbeedge-alignedwithD[15:0]P/N.
FRAMENA18ILVDSframeindicatornegativeinput.
(SeetheFRAMEPdescription)C1,C2,C3,C4,B32,GNDB33,B38,IThesepinsaregroundforallsupplies.
B39,ThermalPadIOUTIPB36OI-ChannelDACcurrentoutput.
Connectdirectlytogroundifunused.
IOUTINB37OI-ChannelDACcomplementarycurrentoutput.
Connectdirectlytogroundifunused.
IOUTQPB35OQ-ChannelDACcurrentoutput.
Connectdirectlytogroundifunused.
IOUTQNB34OQ-ChannelDACcomplementarycurrentoutput.
Connectdirectlytogroundifunused.
IOVDDB6,A17,B25ISupplyvoltageforalldigitalI/O.
(3.
3V)LPFA1I/OPLLloopfilterconnection.
IfnotusingtheclockmultiplyingPLL,theLPFpincanbeleftunconnected.
LVPECLoutputstrobepositiveinput.
Thispositive/negativepairiscapturedwiththerisingedgeofOSTRPA2IDACCLKP/N.
Itisusedtosyncthedivided-downclocksandFIFOoutputpointerinDualSyncSourcesMode.
Ifunuseditcanbeleftunconnected.
OSTRNB2ILVPECLoutputstrobenegativeinput.
(SeetheOSTRPdescription)OptionalLVDSpositiveinputparitybit.
ThePARITYP/NLVDSpairhasaninternal100terminationPARITYPB26Iresistor.
Ifunuseditcanbeleftunconnected.
PARITYNA29IOptionalLVDSnegativeinputparitybit.
PLLAVDDB1IPLLanalogsupplyvoltage.
(3.
3V)SCLKA31ISerialinterfaceclock.
Internalpull-down.
SDENBB28IActivelowserialdataenable,alwaysaninputtotheDAC3482.
Internalpull-up.
Serialinterfacedata.
Bi-directionalin3-pinmode(default)anduni-directionalin4-pinmode.
InternalSDIOA30I/Opull-down.
4SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013PINFUNCTIONS(continued)PINI/ODESCRIPTIONNAMENO.
Uni-directionalserialinterfacedatain4-pinmode.
TheSDOpinistri-statedin3-pininterfacemodeSDOB27O(default).
SLEEPB40IActivehighasynchronoushardwarepower-downinput.
Internalpull-down.
OptionalLVDSSYNCpositiveinput.
TheSYNCP/NLVDSpairhasaninternal100ΩterminationSYNCPA5Iresistor.
Ifunuseditcanbeleftunconnected.
SYNCNB5IOptionalLVDSSYNCnegativeinput.
ActivelowinputforchipRESET,whichresetsalltheprogrammingregisterstotheirdefaultstate.
RESETBB30IInternalpull-up.
Transmitenableactivehighinput.
Internalpull-down.
Toenableanalogoutputdatatransmission,setsif_txenableinregisterconfig3to"1"orpullCMOSTXENABLEA32ITXENABLEpintohigh.
Todisableanalogoutput,setsif_txenableto"0"andpullCMOSTXENABLEpintolow.
Thedigitallogicsectionisforcedtoall0,andanyinputdataisignored.
TESTMODEA44IThispinisusedforfactorytesting.
Internalpull-down.
Leaveunconnectedfornormaloperation.
Digitalsupplyvoltage.
Thissupplypinisalsousedforfactoryfuseprogramming.
ConnecttoVFUSEB4IDACVDDfornormaloperation.
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com6SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013PINFUNCTIONSPINI/ODESCRIPTIONNAMENO.
D10,E11,F11,AVDDG11,H11,J11,IAnalogsupplyvoltage.
(3.
3V)K11,L10CMOSoutputforALARMcondition.
TheALARMoutputfunctionalityisdefinedthroughtheconfig7ALARMN12Oregister.
Defaultpolarityisactivelow,butcanbechangedtoactivehighviaconfig0alarm_out_polcontrolbit.
Full-scaleoutputcurrentbias.
For30mAfull-scaleoutputcurrent,connect1.
28kΩtoground.
BIASJH12OChangethefull-scaleoutputcurrentthroughcoarse_dac(3:0)inconfig3,bitInternalclockbuffersupplyvoltage.
(1.
2V)CLKVDDC12IItisrecommendedtoisolatethissupplyfromDIGVDDandDACVDD.
LVDSpositiveinputdatabits0through15.
Internal100terminationresistor.
DataformatrelativeN4,N3,N2,toDATACLKP/NclockisDoubleDataRate(DDR).
N1,M2,L2,D15Pismostsignificantdatabit(MSB)D[15.
.
0]PK2,J2,F2,E2,ID2,C2,A1,D0Pisleastsignificantdatabit(LSB)A2,A3,A4Theorderofthebuscanbereversedviaconfig2revbusbit.
P4,P3,P2,P1,M1,L1,D[15.
.
0]NK1,J1,F1,E1,ILVDSnegativeinputdatabits0through15.
(SeeD[15:0]Pdescriptionabove)D1,C1,B1,B2,B3,B4DACCLKPA12IPositiveexternalLVPECLclockinputforDACcorewithaself-bias.
DACCLKNA11IComplementaryexternalLVPECLclockinputforDACcore.
(seetheDACCLKPdescription)D9,E9,E10,F10,G10,DACcoresupplyvoltage.
(1.
2V).
ItisrecommendedtoisolatethissupplyfromCLKVDDandDACVDDIH10,J10,K9,DIGVDD.
K10,L9LVDSpositiveinputdataclock.
Internal100terminationresistor.
InputdataD[15:0]P/NislatchedDATACLKPG2IonbothedgesofDATACLKP/N(DoubleDataRate).
DATACLKNG1ILVDSnegativeinputdataclock.
(SeeDATACLKPdescription)E5,E6,E7,Digitalsupplyvoltage.
(1.
2V).
ItisrecommendedtoisolatethissupplyfromCLKVDDandDIGVDDF5,J5,K5,K6,IDACVDD.
K7Usedasexternalreferenceinputwheninternalreferenceisdisabledthroughconfig27extref_ena=EXTIOG12I/O'1'.
Usedasinternalreferenceoutputwhenconfig27extref_ena='0'(default).
Requiresa0.
1μFdecouplingcapacitortoAGNDwhenusedasreferenceoutput.
LVDSframeindicatorpositiveinput.
Internal100terminationresistor.
ThemainfunctionsofthisinputaretoresettheFIFOpointerortobeusedasasyncingsource.
ThesetwofunctionsarecapturedwiththerisingedgeofDATACLKP/N.
ThesignalcapturedbytheFRAMEPH2IfallingedgeofDATACLKP/Ncanbeusedasablockparitybit.
TheFRAMEP/Nsignalshouldbeedge-alignedwithD[15:0]P/N.
Additionallyitisusedtoindicatethebeginningoftheframe.
FRAMENH1ILVDSframeindicatornegativeinput.
(SeetheFRAMEPdescription)Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comPINFUNCTIONS(continued)PINI/ODESCRIPTIONNAMENO.
A10,A13,A14,B10,B11,B12,B13,B14,C5,C6,C7,C8,C9,C10,C13,C14,D8,D13,D14,E8,E12,E13,F6,F7,F8,F9,F12,F13,G6,G7,G8,G9,G13,GNDG14,H6,H7,IThesepinsaregroundforallsupplies.
H8,H9,H13,H14,J6,J7,J8,J9,J12,J13,K8,K13,L8,L13,L14,M5,M6,M7,M8,M9,M10,M11,M12,M13,M14,N13,N14,P13,P14IOUTIPF14OI-ChannelDACcurrentoutput.
IOUTINE14OI-ChannelDACcomplementarycurrentoutput.
IOUTQPJ14OQ-ChannelDACcurrentoutput.
IOUTQNK14OQ-ChannelDACcomplementarycurrentoutput.
D5,D6,G5,IOVDDISupplyvoltageforalldigitalI/O.
(3.
3V)H5,L5,L6PLLloopfilterconnection.
IfnotusingtheclockmultiplyingPLL,theLPFpincanbeleftLPFD12Iunconnected.
LVPECLoutputstrobepositiveinput.
Thispositive/negativepairiscapturedwiththerisingedgeofOSTRPA9IDACCLKP/N.
ItisusedformultipleDACsynchronization.
Ifunuseditcanbeleftunconnected.
OSTRNB9ILVPECLoutputstrobenegativeinput.
(SeetheOSTRPdescription)OptionalLVDSpositiveinputparitybit.
ThePARITYP/NLVDSpairhasaninternal100PARITYPN5Iterminationresistor.
Ifunuseditcanbeleftunconnected.
PARITYNP5IOptionalLVDSnegativeinputparitybit.
PLLAVDDC11,D11IPLLanalogsupplyvoltage.
(3.
3V)SCLKP9ISerialinterfaceclock.
Internalpull-down.
SDENBP10IActivelowserialdataenable,alwaysaninputtotheDAC3484.
Internalpull-up.
SDIOP11I/OSerialinterfacedata.
Bi-directionalin3-pinmode(default)and4-pinmode.
Internalpull-down.
Uni-directionalserialinterfacedatain4-pinmode.
TheSDOpinisthree-statedin3-pininterfaceSDOP12Omode(default).
SLEEPB8IActivehighasynchronoushardwarepower-downinput.
Internalpull-down.
OptionalLVDSSYNCpositiveinput.
TheSYNCP/NLVDSpairhasaninternal100ΩterminationSYNCPA5Iresistor.
Ifunuseditcanbeleftunconnected.
SYNCNB5ILVDSSYNCnegativeinput.
ActivelowinputforchipRESET,whichresetsalltheprogrammingregisterstotheirdefaultstate.
RESETBN10IInternalpull-up.
Transmitenableactivehighinput.
Internalpull-down.
Toenableanalogoutputdatatransmission,setsif_txenableinregisterconfig3to"1"orpullCMOSTXENABLEN9ITXENABLEpintohigh.
Todisableanalogoutput,setsif_txenableto"0"andpullCMOSTXENABLEpintolow.
TheDACoutputisforcedtomidscale.
TESTMODEA8OThispinisusedforfactorytesting.
Internalpull-down.
Leaveunconnectedfornormaloperation.
Digitalsupplyvoltage.
Thissupplypinisalsousedforfactoryfuseprogramming.
ConnecttoVFUSED7IDACVDDfornormaloperation.
8SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013ORDERINGINFORMATION(1)TAORDERCODEPACKAGEDRAWING/TYPE(2)(3)TRANSPORTMEDIAQUANTITYDAC3482IRKDT250RKD,88WQFNQuadFlatpackNo-LeadDAC3482IRKDR2000–40°Cto85°CTapeandReelDAC3482IZAY160ZAY,196NFBGADAC3482IZAYR1000(1)Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthedeviceproductfolderatwww.
ti.
com.
(2)ThermalPadSize:6.
4mmx6.
4mm(3)MSLPeakTemperature:Level-3-260C-168HRABSOLUTEMAXIMUMRATINGSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(1)VALUEUNITMINMAXDACVDD,DIGVDD,CLKVDD–0.
51.
5VVFUSE–0.
51.
5VSupplyvoltagerange(2)IOVDD–0.
54VAVDD,PLLAVDD–0.
54VD[15.
.
0]P/N,DATACLKP/N,FRAMEP/N,PARITYP/N,SYNCP/N–0.
5IOVDD+0.
5VDACCLKP/N,OSTRP/N–0.
5CLKVDD+0.
5VALARM,SDO,SDIO,SCLK,SDENB,SLEEP,RESETB,TESTMODE,–0.
5IOVDD+0.
5VTXENABLEPinvoltagerange(2)IOUTIP/N,IOUTQP/N–1.
0AVDD+0.
5VEXTIO,BIASJ–0.
5AVDD+0.
5VLPF0.
5PLLAVDD+0.
5VVPeakinputcurrent(anyinput)20mAPeaktotalinputcurrent(allinputs)–30mAOperatingfree-airtemperaturerange,TA:DAC3482–4085°CAbsolutemaximumjunctiontemperature,TJ150°CStoragetemperaturerange–65150°C(1)Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonlyandfunctionaloperationoftheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperatingconditions"isnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)MeasuredwithrespecttoGND.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTHERMALINFORMATIONDAC3482THERMALMETRIC(1)RKDPACKAGEZAYPACKAGEUNITS(88)PINS(196)BALLθJAJunction-to-ambientthermalresistance(2)22.
137.
6θJCtopJunction-to-case(top)thermalresistance(3)7.
16.
8θJCbotJunction-to-case(bottom)thermalresistance(4)0.
6N/A°C/WθJBJunction-to-boardthermalresistance(5)4.
716.
8ψJTJunction-to-topcharacterizationparameter(6)0.
10.
2ψJBJunction-to-boardcharacterizationparameter(7)4.
616.
4(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
(2)Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,high-Kboard,asspecifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a.
(3)Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.
NospecificJEDEC-standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
(4)Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.
NospecificJEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
Spacer(5)Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCBtemperature,asdescribedinJESD51-8.
(6)Thejunction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofadeviceinarealsystemandisextractedfromthesimulationdataforobtainingθJA,usingaproceduredescribedinJESD51-2a(sections6and7).
(7)Thejunction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofadeviceinarealsystemandisextractedfromthesimulationdataforobtainingθJA,usingaproceduredescribedinJESD51-2a(sections6and7).
spacerRECOMMENDEDOPERATINGCONDITIONSMINNOMMAXUNITRecommendedoperatingjunctiontemperature105TJ°CMaximumratedoperatingjunctiontemperature(1)125TARecommendedfree-airtemperature–402585°C(1)Prolongeduseatthisjunctiontemperaturemayincreasethedevicefailure-in-time(FIT)rate.
10SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013ELECTRICALCHARACTERISTICS–DCSPECIFICATIONS(1)overrecommendedoperatingfree-airtemperaturerange,nominalsupplies,IOUTFS=20mA(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITResolution16BitsDCACCURACYDNLDifferentialnonlinearity±2LSB1LSB=IOUTFS/216INLIntegralnonlinearity±4LSBANALOGOUTPUTCoarsegainlinearity±0.
04LSBOffseterrorMidcodeoffset±0.
001%FSRGainerrorWithexternalreference±2%FSRWithinternalreference±2%FSRGainmismatchWithinternalreference±2%FSRFullscaleoutputcurrent102030mAOutputcompliancerange–0.
50.
6VOutputresistance300kΩOutputcapacitance5pFREFERENCEOUTPUTVREFReferenceoutputvoltage1.
2VReferenceoutputcurrent(2)100nAREFERENCEINPUTVEXTIOInputvoltagerange0.
61.
21.
25VExternalReferenceModeInputresistance1MΩSmallsignalbandwidth472kHzInputcapacitance100pFTEMPERATURECOEFFICIENTSOffsetdrift±1ppm/°CWithexternalreference±15ppm/°CGaindriftWithinternalreference±30ppm/°CReferencevoltagedrift±8ppm/°C(1)MeasureddifferentiallyacrossIOUTP/Nwith25eachtoGND.
(2)Useanexternalbufferamplifierwithhighimpedanceinputtodriveanyexternalload.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comELECTRICALCHARACTERISTICS–DCSPECIFICATIONS(1)(continued)overrecommendedoperatingfree-airtemperaturerange,nominalsupplies,IOUTFS=20mA(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITPOWERSUPPLY(3)AVDD,IOVDD,PLLAVDDAllconditions3.
143.
33.
46VDIGVDDAllconditions1.
141.
21.
32FDACSampleRate≤1.
25GSPS,PLLOFF1.
141.
21.
32CLKVDD,DACVDD(4)FDACSampleRate≤1GSPS,PLLON1.
141.
21.
32VFDACSampleRate≥1GSPS,PLLON1.
251.
291.
32PSRRPowersupplyrejectionratioDCtested±0.
2%FSR/VPOWERCONSUMPTIONI(AVDD)Analogsupplycurrent(5)8085mAMODE1I(DIGVDD)Digitalsupplycurrent390450mAfDAC=1.
25GSPS,2xinterpolation,Mixeron,I(DACVDD)DACsupplycurrent3050mAQMCon,invsincon,I(CLKVDD)Clocksupplycurrent95110mAPLLenabled,20mAFSoutput,IF=200MHzPPowerdissipation882980mWI(AVDD)Analogsupplycurrent(5)65mAMODE2I(DIGVDD)Digitalsupplycurrent385mAfDAC=1.
25GSPS,2xinterpolation,Mixeron,I(DACVDD)DACsupplycurrent30mAQMCon,invsincon,I(CLKVDD)Clocksupplycurrent70mAPLLdisabled,20mAFSoutput,IF=200MHzPPowerdissipation800mWI(AVDD)Analogsupplycurrent(5)65mAMODE3I(DIGVDD)Digitalsupplycurrent190mAfDAC=625MSPS,2xinterpolation,Mixeron,I(DACVDD)DACsupplycurrent15mAQMCon,invsincoff,I(CLKVDD)Clocksupplycurrent45mAPLLdisabled,20mAFSoutput,IF=200MHzPPowerdissipation515mWI(AVDD)Analogsupplycurrent(5)35mAMODE4I(DIGVDD)Digitalsupplycurrent395mAfDAC=1.
25GSPS,2xinterpolation,Mixeron,I(DACVDD)DACsupplycurrent30mAQMCon,invsincon,I(CLKVDD)Clocksupplycurrent95mAPLLenabled,I/Qoutputsleep,IF=200MHz,PPowerdissipation740mWI(AVDD)Analogsupplycurrent(5)20mAMode5I(DIGVDD)Digitalsupplycurrent10mAPower-Downmode:Noclock,I(DACVDD)DACsupplycurrent4mADAConsleepmode(clockreceiversleep),I(CLKVDD)Clocksupplycurrent10mAI/Qoutputsleep,staticdatapatternPPowerdissipation95mWI(AVDD)Analogsupplycurrent(4)80mAMode6I(DIGVDD)Digitalsupplycurrent200mAfDAC=1GSPS,2xinterpolation,Mixeroff,I(DACVDD)DACsupplycurrent25mAQMCoff,invsincoff,PLLenabled,20mAFSI(CLKVDD)Clocksupplycurrent85mAoutput,IF=200MHzPPowerdissipation636mW(3)Toensurepowersupplyaccuracyandtoaccountforpowersupplyfilternetworklossatoperatingconditions,theuseoftheATESTfunctioninregisterconfig27tochecktheinternalpowersupplynodesisrecommended.
(4)RefertoClarificationsforDAC3482PowerSupplyandPhase-LockedLoopSpecificationSectionfordetails.
(5)IncludesAVDD,PLLAVDD,andIOVDD.
12SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013ELECTRICALCHARACTERISTICS–DIGITALSPECIFICATIONSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITLVDSINPUTS:D[15:0]P/N,DATACLKP/N,FRAMEP/N,SYNCP/N,PARITYP/N(1)LogichighdifferentialVA,B+200mVinputvoltagethresholdLogiclowdifferentialVA,B––200mVinputvoltagethresholdVCOMInputcommonmode1.
01.
21.
6VZTInternaltermination85110135ΩCLLVDSInputcapacitance2pFInterleavedLVDSdatafINTERL1250MSPStransferrateWord-wideinterfacemode625fDATAInputdatarateMSPSByte-wideinterfacemode312.
5CLOCKINPUT(DACCLKP/N)Dutycycle40%60%Differentialvoltage(2)|DACCLKP-DACCLKN|0.
40.
8VInternallybiased0.
2Vcommon-modevoltageSingle-endedswinglevel–0.
4VDACCLKP/Ninput1250MHzfrequencyOUTPUTSTROBE(OSTRP/N)fOSTR=fDACCLK/(nx8xInterp)wherenisanypositiveinteger,fDACCLK/fOSTRFrequencyMHzfDACCLKisDACCLKfrequencyinMHz(8xinterp)Dutycycle50%Differentialvoltage|OSTRP–OSTRN|0.
40.
8VInternallybiased0.
2Vcommon-modevoltageSingle-endedswinglevel–0.
4VCMOSINTERFACE:ALARM,SDO,SDIO,SCLK,SDENB,SLEEP,RESETB,TXENABLEVIHHigh-levelinputvoltage2VVILLow-levelinputvoltage0.
8VIIHHigh-levelinputcurrent-4040AIILLow-levelinputcurrent-4040ACICMOSinputcapacitance2pFIload=–100μAIOVDD–0.
2VVOHALARM,SDO,SDIOIload=–2mA0.
8xIOVDDVIload=100μA0.
2VVOLALARM,SDO,SDIOIload=2mA0.
5V(1)SeeLVDSINPUTSsectionforterminology.
(2)StandardhighswingLVPECLclocksignalshouldbeappliedforbestperformance.
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comELECTRICALCHARACTERISTICS–DIGITALSPECIFICATIONS(continued)overoperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITDIGITALINPUTTIMINGSPECIFICATIONSTimingLVDSinputs:D[15:0]P/N,FRAMEP/N,SYNCP/N,PARITYP/N,doubleedgelatchingConfig36Settingdatadlyclkdly0015001100025003004-50Setuptime,D[15:0]P/N,FRAMEP/Nresetandframeindicatorlatched05-100FRAMEP/N,SYNCP/NonrisingedgeofDATACLKP/N.
ts(DATA)andPARITYP/N,validto06-150psFRAMEP/Nparitybitlatchedonfallingedgeeitheredgeof07-200ofDATACLKP/N.
DATACLKP/N10200202503030040350504006045070500Config36Settingdatadlyclkdly0035001400024500350004550Holdtime,D[15:0]P/N,FRAMEP/Nresetandframeindicatorlatched05600FRAMEP/N,SYNCP/NonrisingedgeofDATACLKP/N.
th(DATA)andPARITYP/N,valid06650psFRAMEP/Nparitybitlatchedonfallingedgeaftereitheredgeof07700ofDATACLKP/N.
DATACLKP/N10300202503020040150501006050700FRAMEP/Nandt(FRAME_SYNC)fDATACLKisDATACLKfrequencyinMHz1/2fDATACLKnsSYNCP/Npulsewidth14SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013ELECTRICALCHARACTERISTICS–DIGITALSPECIFICATIONS(continued)overoperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITTIMINGOUTPUTSTROBEINPUT:DACCLKP/NrisingedgeLATCHING(3)Setuptime,OSTRP/Nts(OSTR)validtorisingedgeof0psDACCLKP/NHoldtime,OSTRP/Nth(OSTR)validafterrisingedgeof300psDACCLKP/NTIMINGSYNCINPUT:DACCLKP/NrisingedgeLATCHING(4)Setuptime,SYNCP/Nts(SYNC_PLL)validtorisingedgeof200psDACCLKP/NHoldtime,SYNCP/Nth(SYNC_PLL)validafterrisingedgeof300psDACCLKP/NTIMINGSERIALPORTSetuptime,SDENBtots(SDENB)20nsrisingedgeofSCLKSetuptime,SDIOvalidtots(SDIO)10nsrisingedgeofSCLKHoldtime,SDIOvalidtoth(SDIO)5nsrisingedgeofSCLKRegisterconfig6read(temperaturesensorread)1st(SCLK)PeriodofSCLKAllotherregisters100nsDataoutputdelayaftertd(Data)10nsfallingedgeofSCLKMinimumRESETBpulsetRESET25nswidth(3)OSTRisrequiredinDualSyncSourcesmode.
InordertominimizetheskewitisrecommendedtousethesameclockdistributiondevicesuchasTexasInstrumentsCDCE62005toprovidetheDACCLKandOSTRsignalstoalltheDAC3482devicesinthesystem.
SwapthepolarityoftheDACCLKoutputswithrespecttotheOSTRonestoestablishproperphaserelationship.
(4)SYNCisrequiredtosynchronizethePLLcircuitinmultipledevices.
TheSYNCsignalmustmeetthetimingrelationshipwithrespecttothereferenceclock(DACCLKP/N)oftheon-chipPLLcircuit.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comELECTRICALCHARACTERISTICS–ACSPECIFICATIONSoverrecommendedoperatingfree-airtemperaturerange,nominalsupplies,IOUTFS=20mA(unlessotherwisenoted)PARAMETERTESTCONDITIONS/COMMENTSMINTYPMAXUNITANALOGOUTPUT(1)PLLOFF1250fDACMaximumDACrate(2)PLLON-deviceswithoutenhancedtestcoverage1000MSPSPLLON-deviceswithenhancedtestcoverage1250ts(DAC)Outputsettlingtimeto0.
1%Transition:Code0x0000to0xFFFF10nsDACoutputsareupdatedonthefallingedgeofDACclock.
DoesnotincludetpdOutputpropagationdelay2nsDigitalLatency(seebelow).
tr(IOUT)Outputrisetime10%to90%220pstf(IOUT)Outputfalltime90%to10%220psNointerpolation,FIFOenabled,Mixeroff,QMCoff,Inversesincoff2502xInterpolation2128-bit4xInterpolation372interface8xInterpolation72316xInterpolation1440Nointerpolation,FIFOenabled,Mixeroff,QMCoff,Inversesincoff140DACDigitallatency2xInterpolation228clockcycles16-bit4xInterpolation417interface8xInterpolation81716xInterpolation1630Finemixer24QMC32Inversesinc36Power-DACwake-uptimeIOUTcurrentsettlingto1%ofIOUTFSfromoutputsleep2upμsDACsleeptimeIOUTcurrentsettlingtolessthan1%ofIOUTFSinoutputsleep2TimeACPERFORMANCE(3)fDAC=1.
25GSPS,fOUT=20MHz82SpuriousfreedynamicrangeSFDRfDAC=1.
25GSPS,fOUT=50MHz77dBc(0tofDAC/2)toneat0dBFSfDAC=1.
25GSPS,fOUT=70MHz72fDAC=1.
25MSPS,fOUT=30±0.
5MHz81Third-ordertwo-toneintermodulationdistortionIMD3fDAC=1.
25GSPS,fOUT=50±0.
5MHz79dBcEachtoneat–12dBFSfDAC=1.
25GSPS,fOUT=100±0.
5MHz77.
5fDAC=1.
25GSPS,fOUT=10MHz160NoisespectraldensityNSDdBc/HzToneat0dBFSfDAC=1.
25GSPS,fOUT=80MHz155fDAC=1.
2288GSPS,fOUT=30.
72MHz77Adjacentchannelleakageratio,singlecarrierfDAC=1.
2288GSPS,fOUT=153.
6MHz74ACLR(4)dBcfDAC=1.
2288GSPS,fOUT=30.
72MHz82Alternatechannelleakageratio,singlecarrierfDAC=1.
2288GSPS,fOUT=153.
6MHz80ChannelisolationfDAC=1.
25GSPS,fOUT=10MHz84dBc(1)Measuredsingleendedinto50Ωload.
(2)RefertoClarificationsforDAC3482PowerSupplyandPhase-LockedLoopSpecificationSectionfordetails.
(3)4:1transformeroutputtermination,50doublyterminatedload.
(4)Singlecarrier,W-CDMAwith3.
84MHzBW,5-MHzspacing,centeredatIF,PAR=12dB.
TESTMODEL1,10ms16SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013ELECTRICALCHARACTERISTICS-PHASE-LOCKEDLOOPSPECIFICATIONSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)pll_vco(5:0)inCONFIG26ON-CHIPVCORANGEBINARYVALUE/DECIMALVALUEMINMAXUNITb111111/6339004000MHzb111010/5838503950MHzb110110/5438003900MHzb110010/5037703840MHzb101110/4637303790MHzb101010/4236903750MHzb100110/3836503700MHzb100010/3436003650MHzb011110/3035803600MHzb010111/23Testedat3500MHzClarificationsforDAC3482PowerSupplyandPhase-LockedLoopSpecificationIn2013,TIhasenhancedproductiontestcoveragefortheon-chipphase-lockedloop.
ThepurposeoftheproductiontestcoverageenhancementistoincreasetheDACoperatingspeedandallowthephase-lockedlooptostaylockedthroughouttherecommendedrangeovertheoperatingfree-airtemperaturespecificationusingonlyonepll_vco(5:0)settinginsteadofpossibleadjustmentsovertemperature.
Thisnewspecificationreducesalarmcheckingandpll_vco(5:0)adjustmentoverheadifthephase-lockedloopisusedintheendapplication.
Thetesteddeviceswillhaveupdateddatecode.
FortheRKDpackageoption,thetesteddeviceswillhavedatecodethatstart36orlater.
FortheZAYpackageoption,thetesteddeviceswillhavedatecodethatstart3Borlater.
RefertoFigure1forthelocationofthedatecodefortherespectivepackages.
Figure1.
DateCodeLocationforRKDPackageOptionandZAYPackageOptionCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTYPICALCHARACTERISTICSAllplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure2.
IntegralNonlinearityFigure3.
DifferentialNonlinearityFigure4.
SFDRvsOutputFrequencyOverInputScaleFigure5.
SecondHarmonicDistortionvsOutputFrequencyOverInputScaleFigure6.
ThirdHarmonicDistortionvsFigure7.
SFDRvsOutputFrequencyOverInterpolationOutputFrequencyOverInputScale18SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013TYPICALCHARACTERISTICS(continued)Allplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure8.
SFDRvsOutputFrequencyOverfDACFigure9.
SFDRvsOutputFrequencyOverIOUTFSFigure10.
SingleToneSpectralPlotFigure11.
SingleToneSpectralPlotFigure12.
SingleToneSpectralPlotFigure13.
SingleToneSpectralPlotCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTYPICALCHARACTERISTICS(continued)Allplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure14.
SingleToneSpectralPlotFigure15.
IMD3vsOutputFrequencyOverInputScaleFigure16.
IMD3vsOutputFrequencyOverInterpolationFigure17.
IMD3vsOutputFrequencyOverfDACFigure18.
IMD3vsOutputFrequencyOverIOUTFSFigure19.
TwoToneSpectralPlot20SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013TYPICALCHARACTERISTICS(continued)Allplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure20.
TwoToneSpectralPlotFigure21.
NSDvsOutputFrequencyOverInputScaleFigure22.
NSDvsOutputFrequencyOverInterpolationFigure23.
NSDvsOutputFrequencyOverfDACFigure24.
NSDvsOutputFrequencyOverIOUTFSFigure25.
NSDvsOutputFrequencyOverClockingOptionsCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTYPICALCHARACTERISTICS(continued)Allplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure26.
SingleCarrierWCDMAACLR(Adjacent)vsFigure27.
SingleCarrierWCDMAACLR(Alternate)vsOutputFrequencyOverClockingOptionsOutputFrequencyOverClockingOptionsFigure28.
SingleCarrierW-CDMATestModel1Figure29.
SingleCarrierW-CDMATestModel1Figure30.
SingleCarrierW-CDMATestModel1Figure31.
FourCarrierW-CDMATestModel122SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013TYPICALCHARACTERISTICS(continued)Allplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure32.
FourCarrierW-CDMATestModel1Figure33.
FourCarrierW-CDMATestModel1Figure34.
10MHzSingleCarrierLTETestModel3.
1Figure35.
10MHzSingleCarrierLTETestModel3.
1Figure36.
20MHzSingleCarrierLTETestModel3.
1Figure37.
20MHzSingleCarrierLTETestModel3.
1Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTYPICALCHARACTERISTICS(continued)Allplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure38.
PowerConsumptionvsfDACOverInterpolationFigure39.
PowerConsumptionvsfDACOverInterpolationFigure40.
PowerConsumptionvsfDACOverDigitalFigure41.
DIGVDDCurrentvsfDACOverInterpolationProcessingFunctionsFigure42.
DIGVDDCurrentvsfDACOverInterpolationFigure43.
DIGVDDCurrentvsfDACOverDigitalProcessingFunctions24SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013TYPICALCHARACTERISTICS(continued)Allplotsareat25°C,nominalsupplyvoltage,fDAC=1250MSPS,4xinterpolation,NCOenabled,MixerGaindisabled,QMCenabledwithgainsetat1446forbothI/Qchannels,0dBFSdigitalinput,20mAfull-scaleoutputcurrentwith4:1transformer(unlessotherwisenoted)Figure44.
DACVDDCurrentvsfDACFigure45.
CLKVDDCurrentvsfDACFigure46.
AVDDCurrentvsfDACFigure47.
IsolationLevelvsOutputFrequencyFigure48.
SFDRvsOutputFrequencyFigure49.
IMD3vsOutputFrequencyCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comDEFINITIONOFSPECIFICATIONSAdjacentCarrierLeakageRatio(ACLR):Definedfora3.
84Mcps3GPPW-CDMAinputsignalmeasuredina3.
84MHzbandwidthata5MHzoffsetfromthecarrierwitha12dBpeak-to-averageratio.
AnalogandDigitalPowerSupplyRejectionRatio(APSSR,DPSSR):DefinedasthepercentageerrorintheratioofthedeltaIOUTanddeltasupplyvoltagenormalizedwithrespecttotheidealIOUTcurrent.
DifferentialNonlinearity(DNL):Definedasthevariationinanalogoutputassociatedwithanideal1LSBchangeinthedigitalinputcode.
GainDrift:Definedasthemaximumchangeingain,intermsofppmoffull-scalerange(FSR)per°C,fromthevalueatambient(25°C)tovaluesoverthefulloperatingtemperaturerange.
GainError:Definedasthepercentageerror(inFSR%)fortheratiobetweenthemeasuredfull-scaleoutputcurrentandtheidealfull-scaleoutputcurrent.
IntegralNonlinearity(INL):Definedasthemaximumdeviationoftheactualanalogoutputfromtheidealoutput,determinedbyastraightlinedrawnfromzeroscaletofullscale.
IntermodulationDistortion(IMD3):Thetwo-toneIMD3isdefinedastheratio(indBc)ofthe3rd-orderintermodulationdistortionproducttoeitherfundamentaloutputtone.
OffsetDrift:DefinedasthemaximumchangeinDCoffset,intermsofppmoffull-scalerange(FSR)per°C,fromthevalueatambient(25°C)tovaluesoverthefulloperatingtemperaturerange.
OffsetError:Definedasthepercentageerror(inFSR%)fortheratiobetweenthemeasuredmid-scaleoutputcurrentandtheidealmid-scaleoutputcurrent.
OutputComplianceRange:Definedastheminimumandmaximumallowablevoltageattheoutputofthecurrent-outputDAC.
Exceedingthislimitmayresultreducedreliabilityofthedeviceoradverselyaffectingdistortionperformance.
ReferenceVoltageDrift:DefinedasthemaximumchangeofthereferencevoltageinppmperdegreeCelsiusfromvalueatambient(25°C)tovaluesoverthefulloperatingtemperaturerange.
SpuriousFreeDynamicRange(SFDR):Definedasthedifference(indBc)betweenthepeakamplitudeoftheoutputsignalandthepeakspurioussignalwithinthefirstNyquistzone.
NoiseSpectralDensity(NSD):Definedasthedifferenceofpower(indBc)betweentheoutputtonesignalpowerandthenoisefloorof1HzbandwidthwithinthefirstNyquistzone.
SERIALINTERFACETheserialportoftheDAC3482isaflexibleserialinterfacewhichcommunicateswithindustrystandardmicroprocessorsandmicrocontrollers.
Theinterfaceprovidesread/writeaccesstoallregistersusedtodefinetheoperatingmodesofDAC3482.
Itiscompatiblewithmostsynchronoustransferformatsandcanbeconfiguredasa3or4pininterfacebysif4_enainregisterconfig2.
Inbothconfigurations,SCLKistheserialinterfaceinputclockandSDENBisserialinterfaceenable.
For3pinconfiguration,SDIOisabidirectionalpinforbothdatainanddataout.
For4pinconfiguration,SDIOisdatainonlyandSDOisdataoutonly.
DataisinputintothedevicewiththerisingedgeofSCLK.
DataisoutputfromthedeviceonthefallingedgeofSCLK.
Eachread/writeoperationisframedbysignalSDENB(SerialDataEnableBar)assertedlow.
Thefirstframebyteistheinstructioncyclewhichidentifiesthefollowingdatatransfercycleasreadorwriteaswellasthe7-bitaddresstobeaccessed.
Table1belowindicatesthefunctionofeachbitintheinstructioncycleandisfollowedbyadetaileddescriptionofeachbit.
Thedatatransfercycleconsistsoftwobytes.
Table1.
InstructionByteoftheSerialInterfaceMSBLSBBit76543210DescriptionR/WA6A5A4A3A2A1A026SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013R/WIdentifiesthefollowingdatatransfercycleasareadorwriteoperation.
AhighindicatesareadoperationfromDAC3482andalowindicatesawriteoperationtoDAC3482.
[A6:A0]Identifiestheaddressoftheregistertobeaccessedduringthereadorwriteoperation.
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comFigure50showstheserialinterfacetimingdiagramforaDAC3482writeoperation.
SCLKistheserialinterfaceclockinputtoDAC3482.
SerialdataenableSDENBisanactivelowinputtoDAC3482.
SDIOisserialdatain.
InputdatatoDAC3482isclockedontherisingedgesofSCLK.
Figure50.
SerialInterfaceWriteTimingDiagram28SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Figure51showstheserialinterfacetimingdiagramforaDAC3482readoperation.
SCLKistheserialinterfaceclockinputtoDAC3482.
SerialdataenableSDENBisanactivelowinputtoDAC3482.
SDIOisserialdatainduringtheinstructioncycle.
In3pinconfiguration,SDIOisdataoutfromtheDAC3482duringthedatatransfercycle,whileSDOisinahigh-impedancestate.
In4pinconfiguration,SDOisdataoutfromtheDAC3482duringthedatatransfercycle.
Attheendofthedatatransfer,SDIOandSDOwilloutputlowonthefinalfallingedgeofSCLKuntiltherisingedgeofSDENBwhentheywill3-state.
Figure51.
SerialInterfaceReadTimingDiagramCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTable2.
RegisterMap(1)(MSB)(LSB)NameAddressDefaultBit14Bit13Bit12Bit11Bit10Bit9Bit8Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit15Bit0qmc_offset_qmc_corr_alarm_outalarm_outclkdiv_sync_config00x000x049Creservedreservedinterp(3:0)fifo_enareservedreservedinvsinc_enareservedenaena_enapolenaword_frame_alarm_alarm_alarm_64cnt_oddeven_dacI_dacQ_config10x010x050Eiotest_enareservedreservedparity_parity_ereservedreservedreserved2away_1away_collision_reservedparitycomplementcomplementenaenanaenaenaenadacclkdataclkcollision_config20x020x700016bit_inresrevedreservedreservedreservedsif4_enamixer_enamixer_gainnco_enarevbusreservedtwosreservedgone_enagone_enagone_enaconfig30x030xF000coarse_dac(3:0)reservedreservedsif_txenableconfig40x04NAiotest_results(15:0)alarm_alarm_alarm_alarm_alarm_alarm_alarm_alarm_alarm_dacclk_dataclk_output_config50x05NAfrom_reservedalarms_from_fifo(2:0)from_reservedreservedreservedfrom_pllrparityframe_parityfparitygonegonegonezerochkiotestconfig60x06NAtempdata(7:0)reservedreservedreservedconfig70x070xFFFFalarms_mask(15:0)config80x080x0000reservedreservedreservedqmc_offsetI(12:0)config90x090x8000fifo_offset(2:0)qmc_offsetQ(12:0)config100x0A0x0000reservedreservedreservedreservedconfig110x0B0x0000reservedreservedreservedreservedconfig120x0C0x0400reservedreservedreservedreservedreservedqmc_gainI(10:0)config130x0D0x0400cmix(3:0)reservedqmc_gainQ(10:0)config140x0E0x0400reservedreservedreservedreservedreservedreservedconfig150x0F0x0400output_delay(1:0)reservedreservedreservedconfig160x100x0000reservedreservedreservedreservedqmc_phase(11:0)config170x110x0000reservedreservedreservedreservedreservedconfig180x120x0000phase_offset(15:0)config190x130x0000reservedconfig200x140x0000phase_add(15:0)config210x150x0000phase_add(31:16)config220x160x0000reservedconfig230x170x0000reservedpll_config240x18NAreservedpll_resetndivsync_pll_enareservedpll_cp(1:0)pll_p(2:0)pll_lfvolt(2:0)enaconfig250x190x0440pll_m(7:0)pll_n(3:0)pll_vcoitune(2:0)reservedbias_tsense_clkrecv_config260x1A0x0020pll_vco(5:0)reservedreservedpll_sleepreservedreservedreservedreservedsleepsleepsleepfuse_config270x1B0x0000extref_enareservedreservedreservedreservedreservedreservedreservedreservedreservedsleepconfig280x1C0x0000reservedreservedconfig290x1D0x0000reservedreservedconfig300x1E0x1111syncsel_qmoffset(3:0)reservedsyncsel_qmcorr(3:0)reserved(1)Unlessotherwisenoted,allreservedregistersshouldbeprogrammedtodefaultvalues.
30SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Table2.
RegisterMap(1)(continued)(MSB)(LSB)NameAddressDefaultBit14Bit13Bit12Bit11Bit10Bit9Bit8Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit15Bit0config310x1F0x1140syncsel_mixer(3:0)reservedsyncsel_nco(3:0)syncsel_dataformattersif_syncreservedclkdiv_config320x200x2400syncsel_fifoin(3:0)syncsel_fifoout(3:0)reservedsync_selconfig330x210x0000reservedconfig340x220x1B1Breservedreservedreservedreservedreservedreservedreservedreservedconfig350x230xFFFFsleep_cntl(15:0)config360x240x0000datadly(2:0)clkdly(2:0)reservedconfig370x250x7A7Aiotest_pattern0config380x260xB6B6iotest_pattern1config390x270xEAEAiotest_pattern2config400x280x4545iotest_pattern3config410x290x1A1Aiotest_pattern4config420x2A0x1616iotest_pattern5config430x2B0xAAAAiotest_pattern6config440x2C0xC6C6iotest_pattern7ostrtodig_config450x2D0x0004reservedramp_enareservedsifdac_enaselconfig460x2E0x0000reservedgrp_delayI(7:0)config470x2F0x0000grp_delayQ(7:0)reservedconfig480x300x0000sifdac(15:0)version0x7F0x540Creservedreservedreservedreserveddeviceid(1:0)versionid(2:0)Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback31ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comREGISTERDESCRIPTIONSRegistername:config0–Address:0x00,Default:0x049CRegisterDefaultAddressBitNameFunctionNameValueconfig00x0015qmc_offset_enaWhenset,thedigitalQuadratureModulatorCorrection(QMC)offset0correctionisenabled.
14ReservedReservedforfactoryuse.
013qmc_corr_enaWhenset,theQMCphaseandgaincorrectioncircuitryisenabled.
012ReservedReservedforfactoryuse.
011:8interp(3:0)Thesebitsdefinetheinterpolationfactor0100interpInterpolationFactor00001x00012x00104x01008x100016x7fifo_enaWhenset,theFIFOisenabled.
WhentheFIFOisdisabled1DACCCLKP/NandDATACLKP/Nmustbealigned(notrecommended).
6ReservedReservedforfactoryuse.
05ReservedReservedforfactoryuse.
04alarm_out_enaWhenset,theALARMpinbecomesanoutput.
Whencleared,the1ALARMpinis3-stated.
3alarm_out_polThisbitchangesthepolarityoftheALARMsignal.
1MM0:NegativelogicMM1:Positivelogic2clkdiv_sync_enaWhenset,enablesthesyncingoftheclockdividerusingthesync1sourceselectedbyregisterconfig32.
Theinternaldivided-downclockswillbephasealignedaftersyncing.
SeethePower-UpSequencesectionformoredetail.
1invsinc_enaWhenset,theinversesincfilterisenabled.
00ReservedReservedforfactoryuse.
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comSLAS748E–MARCH2011–REVISEDJULY2013Registername:config1–Address:0x01,Default:0x050ERegisterDefaultAddressBitNameFunctionNameValueconfig10x0115iotest_enaWhenset,enablesthedatapatterncheckertest.
Theoutputsare0deactivatedregardlessofthestateofTXENABLEandsif_txenable.
14ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
01264cnt_enaWhenset,enablesresettingofthealarmsafter64goodsamples0withthegoalofremovingunnecessaryerrors.
Forinstance,whencheckingsetup/holdthroughthepatterncheckertest,theremayinitiallybeerrors.
SettingthisbitremovestheneedforaSIFwritetoclearthealarmregister.
11oddeven_paritySelectsbetweenoddandevenparitycheck0MM0:EvenparityMM1:Oddparity10word_parity_enaWhenset,enablesparitycheckingofeachinputwordusingthe1PARITYP/Nparityinput.
Itshouldmatchtheoddeven_parityregistersetting.
9frame_parity_enaWhenset,enablesparitycheckingusingtheFRAMEsignalto0sourcetheparitybit.
8ReservedReservedforfactoryuse.
1Note:Defaultvalueis'1'.
Mustbesetto'0'forproperoperation7ReservedReservedforfactoryuse.
06dacI_complementWhenset,theDACIoutputiscomplemented.
Thisallowsto0effectivelychangethe+and–designationsoftheLVDSdatalines.
5dacQ_complementWhenset,theDACQoutputiscomplemented.
Thisallowsto0effectivelychangethe+and–designationsoftheLVDSdatalines.
4ReservedReservedforfactoryuse.
03alarm_2away_enaWhenset,thealarmfromtheFIFOindicatingthewriteandread1pointersbeing2awayisenabled.
2alarm_1away_enaWhenset,thealarmfromtheFIFOindicatingthewriteandread1pointersbeing1awayisenabled.
1alarm_collision_enaWhenset,thealarmfromtheFIFOindicatingacollisionbetweenthe1writeandreadpointersisenabled.
0ReservedReservedforfactoryuse.
0Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback33ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comRegistername:config2–Address:0x02,Default:0x7000RegisterDefaultAddressBitNameFunctionNameValueconfig20x021516bit_inWhenset,theinputinterfaceissettoword-widemode.
0Whencleared,theinputinterfaceissettobyte-widemode.
14dacclkgone_enaWhenset,theDACCLK-gonesignalfromtheclockmonitorcircuitcan1beusedtoshutofftheDACoutputs.
Thecorrespondingalarms,alarm_dacclk_goneandalarm_output_gone,mustnotbemasked(i.
e.
Config7,bitandbitmustsetto"0").
13dataclkgone_enaWhenset,theDATACLK-gonesignalfromtheclockmonitorcircuit1canbeusedtoshutofftheDACoutputs.
Thecorrespondingalarms,alarm_dataclk_goneandalarm_output_gone,mustnotbemasked(i.
e.
Config7,bitandbitmustsetto"0").
12collisiongone_enaWhenset,theFIFOcollisionalarmscanbeusedtoshutofftheDAC1outputs.
Thecorrespondingalarms,alarm_fifo_collisionandalarm_output_gone,mustnotbemasked(i.
e.
Config7,bitandbitmustsetto"0").
11ReservedReservedforfactoryuse.
010ReservedReservedforfactoryuse.
09ReservedReservedforfactoryuse.
08ReservedReservedforfactoryuse.
07sif4_enaWhenset,theserialinterface(SIF)isa4bitinterface,otherwiseitis0a3bitinterface.
6mixer_enaWhenset,themixerblockisenabled.
05mixer_gainWhenset,a6dBgainisaddedtothemixeroutput.
04nco_enaWhenset,theNCOisenabled.
Thisisnotrequiredforcoarsemixing.
03revbusWhenset,theinputbitsforthedatabusarereversed.
MSBbecomes0LSB.
2ReservedReservedforfactoryuse.
01twosWhenset,theinputdataformatisexpectedtobe2'scomplement.
0Whencleared,theinputisexpectedtobeoffset-binary.
0ReservedReservedforfactoryuse.
0Registername:config3–Address:0x03,Default:0xF000RegisterDefaultAddressBitNameFunctionNameValueconfig30x0315:12coarse_dac(3:0)Scalestheoutputcurrentin16equalsteps.
111111:8ReservedReservedforfactoryuse.
00007:1ReservedReservedforfactoryuse.
00000000sif_txenableWhenset,theinternalvalueofTXENABLEissetto"1".
0Toenableanalogoutputdatatransmission,setsif_txenableto"1"orpullCMOSTXENABLEpin(A32)tohigh.
Todisableanalogoutput,setsif_txenableto"0"andpullCMOSTXENABLEpin(A32)tolow.
34SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Registername:config4–Address:0x04,Default:NoRESETValue(WRITETOCLEAR)RegisterDefaultAddressBitNameFunctionNameValueconfig40x0415:0iotest_results(15:0)Thisregisterisusedwithpatterncheckertestenabled(iotest_enainconfig1,NoRESETbitsetto"1").
ItdoesnothaveadefaultRESETvalue.
ValueThevaluesofthesebitstellwhichbitinthewordfailedduringthepatterncheckertest.
iotest_results(15:8)correspondtothedatabitsonD[15:8]andiotest_results(7:0)correspondtothedatabitsonD[7:0].
Registername:config5–Address:0x05,Default:SetupandPower-UpConditionsDependent(WRITETOCLEAR)RegisterAddressDefaultBitNameFunctionNameValueconfig50x0515alarm_from_zerochkThisalarmindicatesthe8-bitFIFOwritepointeraddresshasanallNAzerospatterns.
Duetopointeraddressbeingashiftregister,thisisnotavalidaddressandwillcausethewritepointertobestuckuntilthenextsync.
Thiserroristypicallycausedbytimingerrororimproperpowerstart-upsequence.
Ifthisalarmisasserted,resynchronizationofFIFOisnecessary.
RefertothePower-UpSequencesectionformoredetail.
14ReservedReservedforfactoryuse.
NA13:11alarms_from_fifo(2:0)AlarmindicatingFIFOpointercollisionsandnearness:NAMM000:AllfineMM001:Pointersare2awayMM01x:Pointersare1awayMM1xx:FIFOpointercollisionIftheFIFOpointercollisionalarmissetwhencollisiongone_enaisenabled,theFIFOmustbere-synchronizedandthebitsmustbeclearedtoresumenormaloperation.
10alarm_dacclk_goneAlarmindicatingtheDACCLKhasbeenstopped.
IfthebitissetNAwhendacclkgone_enaisenabled,theDACCLKmustresumeandthebitmustbeclearedtoresumenormaloperation.
9alarm_dataclk_goneAlarmindicatingtheDATACLKhasbeenstopped.
NAIfthebitissetwhendataclkgone_enaisenabled,theDATACLKmustresumeandthebitmustbeclearedtoresumenormaloperation.
8alarm_output_goneAlarmindicatingeitheralarm_dacclk_gone,alarm_dataclk_gone,orNAalarm_fifo_collisionareasserted.
Itcontrolstheoutput.
Whenhighitwilloutput"0x8000"foreachoutputconnectedtotheDAC.
Ifthebitissetwhendacclkgone_ena,dataclkgone_ena,orcollisiongone_enaareenabled,thenthecorrespondingerrorsmustbefixedandthebitsmustbeclearedtoresumenormaloperation.
7alarm_from_iotestAlarmindicatingtheinputdatapatterndoesnotmatchthepatterninNAtheiotest_patternregisters.
Whendatapatterncheckermodeisenabled,thisalarminregisterconfig5,bit7istheonlyvalidalarm.
Otheralarmsinregisterconfig5arenotvalidandcanbedisregarded.
6ReservedReservedforfactoryuse.
NA5alarm_from_pllAlarmindicatingthePLLhaslostlock.
ForversionID"100"orNAearlier,alarm_from_PLLmaynotindicatethecorrectstatusofthePLL.
Refertopll_lfvolt(2:0)inregisterconfig24forproperPLLlockindication.
4alarm_rparityAlarmindicatingaparityerrorondatacapturedontherisingedgeNAofDATACLKP/N.
3alarm_fparityAlarmindicatingaparityerrorondatacapturedonthefallingedgeNAofDATACLKP/N.
2alarm_frame_parityAlarmindicatingaparityerrorwhenusingtheFRAMEasparitybit.
NA1ReservedReservedforfactoryuse.
NA0ReservedReservedforfactoryuse.
NACopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback35ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comRegistername:config6–Address:0x06,Default:NoRESETValue(READONLY)RegisterDefaultAddressBitNameFunctionNameValueconfig60x0615:8tempdata(7:0)Thisistheoutputfromthechiptemperaturesensor.
ThevalueofthisregisterinNotwo'scomplementformatrepresentsthetemperatureindegreesCelsius.
ThisRESETregistermustbereadwithaminimumSCLKperiodof1μs.
Value7:2ReservedReservedforfactoryuse.
0000001ReservedReservedforfactoryuse.
00ReservedReservedforfactoryuse.
0Registername:config7–Address:0x07,Default:0xFFFFRegisterDefaultAddressBitNameFunctionNameValueconfig70x0715:0alarms_mask(15:0)Thesebitscontrolthemaskingofthealarms.
(0=notmasked,1=masked)0xFFFFalarm_maskAlarmthatisMasked15alarm_from_zerochk14notused13alarm_fifo_collision12alarm_fifo_1away11alarm_fifo_2away10alarm_dacclk_gone9alarm_dataclk_gone8alarm_output_gone7alarm_from_iotest6notused5alarm_from_pll4alarm_rparity3alarm_lparity2alarm_frame_parity1notused0notusedRegistername:config8–Address:0x08,Default:0x0000(CAUSESAUTO-SYNC)RegisterDefaultAddressBitNameFunctionValueNameconfig80x0815ReservedReservedforfactoryuse.
014ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
012:0qmc_offsetI(12:0)DACIoffsetcorrection.
TheoffsetismeasuredinDACLSBs.
Ifenabledinconfig30Allzeroswritingtothisregistercausesanauto-synctobegenerated.
ThisloadsthevaluesoftheQMCoffsetregisters(config8-config9)intotheoffsetblockatthesametime.
Whenupdatingtheoffsetvaluesconfig8shouldbewrittenlast.
Programmingconfig9willnotaffecttheoffsetsetting.
Registername:config9–Address:0x09,Default:0x8000RegisterDefaultAddressBitNameFunctionValueNameconfig90x0915:13fifo_offset(2:0)WhenthesynctotheFIFOoccurs,thisisthevalueloadedintotheFIFOreadpointer.
With100thisvaluetheinitialdifferencebetweenwriteandreadpointerscanbecontrolled.
Thismaybehelpfulinsyncingmultiplechipsorcontrollingthedelaythroughthedevice.
12:0qmc_offsetQ(12:0)DACQoffsetcorrection.
TheoffsetismeasuredinDACLSBs.
Allzeros36SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Registername:config10–Address:0x0A,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig100x0A15ReservedReservedforfactoryuse.
014ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
012:0ReservedReservedforfactoryuse.
AllzerosRegistername:config11–Address:0x0B,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig100x0A15ReservedReservedforfactoryuse.
014ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
012:0ReservedReservedforfactoryuse.
AllzerosRegistername:config12–Address:0x0C,Default:0x0400RegisterDefaultAddressBitNameFunctionValueNameconfig120x0C15ReservedReservedforfactoryuse.
014ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
012ReservedReservedforfactoryuse.
011ReservedReservedforfactoryuse.
010:0qmc_gainI(10:0)QMCgainforDACI.
Thefull11-bitqmc_gainI(10:0)wordisformattedasUNSIGNED10000000witharangeof0to1.
9990.
Theimplieddecimalpointforthemultiplicationisbetweenbit0009andbit10.
Registername:config13–Address:0x0D,Default:0x0400RegisterDefaultAddressBitNameFunctionValueNameconfig130x0D15cmix_mode(3:0)Setsthemixingfunctionofthecoarsemixer.
0000MMBit15:Fs/8mixerMMBit14:Fs/4mixerMMBit13:Fs/2mixerMMBit12:-Fs/4mixerThevariousmixerscanbecombinedtogethertoobtaina±n*Fs/8totalmixingfactor.
11ReservedReservedforfactoryuse.
010:0qmc_gainQ(10:0)QMCgainforDACQ.
Thefull11-bitqmc_gainb(10:0)wordisformattedasUNSIGNED10000000witharangeof0to1.
9990.
Theimplieddecimalpointforthemultiplicationisbetween000bit9andbit10.
Registername:config14–Address:0x0E,Default:0x0400RegisterDefaultAddressBitNameFunctionValueNameconfig140x0E15ReservedReservedforfactoryuse.
014ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
012ReservedReservedforfactoryuse.
011ReservedReservedforfactoryuse.
010:0ReservedReservedforfactoryuse.
10000000000Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback37ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comRegistername:config15–Address:0x0F,Default:0x0400RegisterDefaultAddressBitNameFunctionValueNameconfig150x0F15:14output_delay(1:0)DelaystheDACoutputsfrom0to3DACclockcycles.
0013:12ReservedReservedforfactoryuse.
0011ReservedReservedforfactoryuse.
010:0ReservedReservedforfactoryuse.
10000000000Registername:config16–Address:0x10,Default:0x0000(CAUSESAUTO-SYNC)RegisterDefaultAddressBitNameFunctionValueNameconfig160x1015ReservedReservedforfactoryuse.
014ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
Note:Defaultvalueis'0'.
Mustbesetto'1'forproper0operation12ReservedReservedforfactoryuse.
Note:Defaultvalueis'0'.
Mustbesetto'1'forproper0operation11:0qmc_phase(11:0)QMCcorrectionphase.
The12-bitqmc_phase(11:0)wordisformattedastwo'sAllzeroscomplementandscaledtooccupyarangeof-0.
5to0.
49975andadefaultphasecorrectionof0.
00.
ToaccomplishQMCphasecorrection,thisvalueismultipliedbythecurrentBsample,thensummedintotheAsample.
Ifenabledinconfig30writingtothisregistercausesanauto-synctobegenerated.
ThisloadsthevaluesoftheQMCoffsetregisters(config12,config13,andconfig16)intotheQMCblockatthesametime.
WhenupdatingtheQMCvaluesconfig16shouldbewrittenlast.
Programmingconfig12andconfig13willnotaffecttheQMCsettings.
Registername:config17–Address:0x11,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig170x1115ReservedReservedforfactoryuse.
014ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
012ReservedReservedforfactoryuse.
011:0ReservedReservedforfactoryuse.
AllzerosRegistername:config18–Address:0x12,Default:0x0000(CAUSESAUTO-SYNC)RegisterDefaultAddressBitNameFunctionValueNameconfig180x1215:0phase_offset(15:0)PhaseoffsetaddedtotheNCOaccumulatorbeforethegenerationoftheSINand0x0000COSvalues.
Thephaseoffsetisaddedtotheupper16bitsoftheNCOaccumulatorresultsandthese16bitsareusedinthesin/coslookuptables.
Ifenabledinconfig31writingtothisregistercausesanauto-synctobegenerated.
ThisloadsthevaluesoftheQfinemixerblockregisters(config18,config20,andconfig21)atthesametime.
Whenupdatingthemixervaluestheconfig18shouldbewrittenlast.
Programmingconfig20andconfig21willnotaffectthemixersettings.
Registername:config19–Address:0x13,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig190x1315:0ReservedReservedforfactoryuse.
0x000038SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Registername:config20–Address:0x14,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig200x1415:0phase_add(15:0)Thephase_add(15:0)valueisusedtodeterminetheNCOfrequency.
Thetwo's0x0000complementformattedvaluecanbepositiveornegative.
EachLSBrepresentsFs/(2^32)frequencystep.
Registername:config21–Address:0x15,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig210x1515:0phase_add(31:16)Seeconfig20above.
0x0000Registername:config22–Address:0x16,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig220x1615:0ReservedReservedforfactoryuse.
0x0000Registername:config23–Address:0x17,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig230x1715:0ReservedReservedforfactoryuse.
0x0000Registername:config24–Address:0x18,Default:NARegisterDefaultAddressBitNameFunctionValueNameconfig240x1815:13ReservedReservedforfactoryuse.
00112pll_resetWhenset,thePLLloopfilter(LPF)ispulleddownto0V.
Togglefrom'1'to'0'to0restartthePLLifanover-speedlock-upoccurs.
Over-speedcanhappenwhentheprocessisfast,thesuppliesarehigherthannominal,etc.
resultinginthefeedbackdividersmissingaclock.
11pll_ndivsync_enaWhenset,theLVDSSYNCinputisusedtosyncthePLLNdividers.
110pll_enaWhenset,thePLLisenabled.
Whencleared,thePLLisbypassed.
09:8ReservedReservedforfactoryuse.
007:6pll_cp(1:0)PLLpumpchargeselect00MM00:NochargepumpMM01:SinglepumpchargeMM10:NotusedMM11:Dualpumpcharge5:3pll_p(2:0)PLLpre-scalerdividingmodulecontrol.
001MM010:2MM011:3MM100:4MM101:5MM110:6MM111:7MM000:82:0pll_lfvolt(2:0)PLLloopfiltervoltage.
Thisthreebitread-onlyindicatorhasstepsizeof0.
4125V.
NATheentirerangecoversfrom0Vto3.
3V.
TheoptimallockrangeofthePLLwillbefrom010to101(i.
e.
0.
825Vto2.
063V).
Adjustpll_vco(5:0)foroptimallockrange.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback39ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comRegistername:config25–Address:0x19,Default:0x0440RegisterDefaultAddressBitNameFunctionValueNameconfig250x1915:8pll_m(7:0)MportionoftheM/NdividerofthePLL.
00000100Ifpll_m=0,theMdividervaluehastherangeofpll_m,spanningfrom4to127.
(i.
e.
0,1,2,and3arenotvalid.
)Ifpll_m=1,theMdividervaluehastherangeof2*pll_m,spanningfrom8to254.
(i.
e.
0,2,4,and6arenotvalid.
Mdividerhasevenvaluesonly.
)7:4pll_n(3:0)NportionoftheM/NdividerofthePLL.
0100MM0000:1MM0001:2MM0010:3MM0011:4MM0100:5MM0101:6MM0110:7MM0111:8MM1000:9MM1001:10MM1010:11MM1011:12MM1100:13MM1101:14MM1110:15MM1111:163:2pll_vcoitune(1:0)PLLVCObiastuningbits.
Setto"01"fornormalPLLoperation.
001:0ReservedReservedforfactoryuse.
00Registername:config26–Address:0x1A,Default:0x0020RegisterDefaultAddressBitNameFunctionValueNameconfig260x1A15:10pll_vco(5:0)VCOfrequencycoarsetuningbits.
0000009ReservedReservedforfactoryuse.
08ReservedReservedforfactoryuse.
07bias_sleepWhenset,thebiasamplifierisputintosleepmode.
06tsense_sleepTurnsoffthetemperaturesensorwhenasserted.
05pll_sleepWhenset,thePLLisputintosleepmode.
14clkrecv_sleepWhenassertedtheclockinputreceivergetsputintosleepmode.
Thisaffectsthe0OSTRreceiveraswell.
3ReservedReservedforfactoryuse.
02ReservedReservedforfactoryuse.
01ReservedReservedforfactoryuse.
00ReservedReservedforfactoryuse.
040SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Registername:config27–Address:0x1B,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig270x1B15extref_enaAllowsthedevicetouseanexternalreferenceortheinternalreference.
0MM0:InternalreferenceMM1:Externalreference14ReservedReservedforfactoryuse.
013ReservedReservedforfactoryuse.
012ReservedReservedforfactoryuse.
011fuse_sleepPutsthefusestosleepwhensethigh.
0Note:Defaultvalueis'0'.
Mustbesetto'1'forproperoperation10ReservedReservedforfactoryuse.
09ReservedReservedforfactoryuse.
08ReservedReservedforfactoryuse.
07ReservedReservedforfactoryuse.
06ReservedReservedforfactoryuse.
05:0atestATESTmodeallowstheusertocheckfortheinternaldievoltagestoensurethe000000supplyvoltagesarewithintherange.
WhenATESTmodeisprogrammed,theinternaldievoltagescanbemeasuredattheTXENABLEpin.
TheTXENABLEpin(A32forDAC3482IRKDandN9forDAC3482IZAY)mustbefloatingwithoutanypull-uporpull-downresistors.
InATESTmode,theTXENABLEandsif_txenablelogicsarebypassed,andoutputwillbeactiveatalltime.
ExpectedNominalConfig27,bitDescriptionVoltage001110DACAAVSS0V001111DACADVDD1.
2V010000DACAAVDD3.
3V010110DACBAVSS0V010111DACBDVDD1.
2V011000DACBAVDD3.
3V011110DACCAVSS0V011111DACCDVDD1.
2V100000DACCAVDD3.
3V100110DACDAVSS0V100111DACDDVDD1.
2V101000DACDAVDD3.
3V1100001.
2VDIG1.
2V0001011.
2VCLK1.
2VRegistername:config28–Address:0x1C,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig280x1C15:8ReservedReservedforfactoryuse.
0x007:0ReservedReservedforfactoryuse.
0x00Registername:config29–Address:0x1D,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig290x1D15:8ReservedReservedforfactoryuse.
0x007:0ReservedReservedforfactoryuse.
0x00Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback41ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comRegistername:config30–Address:0x1E,Default:0x1111RegisterDefaultAddressBitNameFunctionValueNameconfig300x1E15:12syncsel_qmoffset(3:0)Selectsthesyncingsource(s)ofthedoublebufferedQMCoffsetregisters.
A'1'in0001thebitenablesthesignalasasyncsource.
Morethanonesyncsourceispermitted.
MMBit15:sif_sync(viaconfig31)MMBit14:SYNCMMBit13:OSTRMMBit12:Auto-syncfromregisterwrite11:8ReservedReservedforfactoryuse.
00017:4syncsel_qmcorr(3:0)Selectsthesyncingsource(s)ofthedoublebufferedQMCcorrectionregisters.
A'1'0001inthebitenablesthesignalasasyncsource.
Morethanonesyncsourceispermitted.
MMBit7:sif_sync(viaconfig31)MMBit6:SYNCMMBit5:OSTRMMBit4:Auto-syncfromregisterwrite3:0ReservedReservedforfactoryuse.
0001Registername:config31–Address:0x1F,Default:0x1140RegisterDefaultAddressBitNameFunctionValueNameconfig310x1F15:12syncsel_mixer(3:0)Selectsthesyncingsource(s)ofthedoublebufferedmixerregisters.
A'1'inthe0001bitenablesthesignalasasyncsource.
Morethanonesyncsourceispermitted.
MMBit15:sif_sync(viaconfig31)MMBit14:SYNCMMBit13:OSTRMMBit12:Auto-syncfromregisterwrite11:8ReservedReservedforfactoryuse.
00017:4syncsel_nco(3:0)Selectsthesyncingsource(s)ofthetwoNCOaccumulators.
A'1'inthebit0100enablesthesignalasasyncsource.
Morethanonesyncsourceispermitted.
MMBit7:sif_sync(viaconfig31)MMBit6:SYNCMMBit5:OSTRMMBit4:FRAME3:2syncsel_dataformatterSelectsthesyncingsourceofthedataformatter.
Unliketheothersyncsonly00onesyncsourceisallowed.
MM00:FRAMEMM01:SYNCMM10:NosyncMM11:Nosync1sif_syncSIFcreatedsyncsignal.
Setto'1'tocauseasyncandthenclearto'0'to0removeit.
0ReservedReservedforfactoryuse.
042SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Registername:config32–Address:0x20,Default:0x2400RegisterDefaultAddressBitNameFunctionValueNameconfig320x2015:12syncsel_fifoin(3:0)Selectsthesyncingsource(s)oftheFIFOinputside.
A'1'inthebitenablesthe0010signalasasyncsource.
Morethanonesyncsourceispermitted.
MMBit15:sif_sync(viaconfig31)MMBit14:AlwayszeroMMBit13:FRAMEMMBit12:SYNC11:8syncsel_fifoout(3:0)Selectsthesyncingsource(s)oftheFIFOoutputside.
A'1'inthebitenablesthe0100signalasasyncsource.
Morethanonesyncsourceispermitted.
MMBit11:sif_sync(viaconfig31)MMBit10:OSTR–DualSyncSourcesModeMMBit9:FRAME–SingleSyncSourcemodeMMBit8:SYNC–SingleSyncSourcemode7:1ReservedReservedforfactoryuse.
00000clkdiv_sync_selSelectsthesignalsourceforclockdividersynchronization.
0clkdiv_sync_selSyncSource0OSTR1FRAME,SYNC,orSIFSYNCbasedonsyncsel_fifoinsourceselection(config32,bit)Registername:config33–Address:0x21,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig330x2115:0ReservedReservedforfactoryuse.
0x0000Registername:config34–Address:0x22,Default:0x1B1BRegisterDefaultAddressBitNameFunctionValueNameconfig340x2215:14ReservedReservedforfactoryuse.
0013:12ReservedReservedforfactoryuse.
0111:10ReservedReservedforfactoryuse.
109:8ReservedReservedforfactoryuse.
117:6ReservedReservedforfactoryuse.
005:4ReservedReservedforfactoryuse.
013:2ReservedReservedforfactoryuse.
101:0ReservedReservedforfactoryuse.
11Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback43ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comRegistername:config35–Address:0x23,Default:0xFFFFRegisterDefaultAddressBitNameFunctionValueNameconfig350x2315:0sleep_cntl(15:0)ControlstheroutingoftheCMOSSLEEPsignal(pinB40)todifferentblocks.
Whena0xFFFF0xFFFFbitinthisregisterisset,theSLEEPsignalwillbesenttothecorrespondingblock.
TheblockwillonlybedisabledwhentheSLEEPislogicHIGHandthecorrespondbitissetto"1".
ThesebitsdonotoverrideSIFbitsinregisterconfig26thatcontrolthesamesleepfunction.
sleep_cntl(bit)Function15reserved14DACIsleep13DACQsleep12reserved11Clockreceiversleep10PLLsleep9LVDSdatasleep8LVDScontrolsleep7Tempsensorsleep6reserved5BiasamplifiersleepAllothersnotusedRegistername:config36–Address:0x24,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig360x2415:13datadly(2:0)ControlsthedelayofthedatainputsthroughtheLVDSreceivers.
EachLSBadds000approximately50psMM0:Minimum12:10clkdly(2:0)ControlsthedelayofthedataclockthroughtheLVDSreceivers.
EachLSBadds000approximately50psMM0:Minimum9:0ReservedReservedforfactoryuse.
0x000Registername:config37–Address:0x25,Default:0x7A7ARegisterDefaultAddressBitNameFunctionValueNameconfig370x2515:0iotest_pattern0Dataword0intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinputdata.
0x7A7AAtthestartoftheIOtestpattern,thiswordshouldbealignedwithrisingedgeofFRAMEorSYNCsignaltoindicatesample0.
Registername:config38–Address:0x26,Default:0xB6B6RegisterDefaultAddressBitNameFunctionValueNameconfig380x2615:0iotest_pattern1Dataword1intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinputdata.
0xB6B6Registername:config39–Address:0x27,Default:0xEAEARegisterDefaultAddressBitNameFunctionValueNameconfig390x2715:0iotest_pattern2Dataword2intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinput0xEAEAdata.
Registername:config40–Address:0x28,Default:0x4545RegisterDefaultAddressBitNameFunctionValueNameconfig400x2815:0iotest_pattern3Dataword3intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinputdata.
0x454544SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Registername:config41–Address:0x29,Default:0x1A1ARegisterDefaultAddressBitNameFunctionValueNameconfig410x2915:0iotest_pattern4Dataword4intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinputdata.
0x1A1ARegistername:config42–Address:0x2A,Default:0x1616RegisterDefaultAddressBitNameFunctionValueNameconfig420x2A15:0iotest_pattern5Dataword5intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinput0x1616data.
Registername:config43–Address:0x2B,Default:0xAAAARegisterDefaultAddressBitNameFunctionValueNameconfig430x2B15:0iotest_pattern6Dataword6intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinput0xAAAAdata.
Registername:config44–Address:0x2C,Default:0xC6C6RegisterDefaultAddressBitNameFunctionValueNameconfig440x2C15:0iotest_pattern7Dataword7intheIOtestpattern.
Itisusedwiththesevenotherwordstotesttheinput0xC6C6data.
Registername:config45–Address:0x2D,Default:0x0004RegisterDefaultAddressBitNameFunctionValueNameconfig450x2D15ReservedReservedforfactoryuse.
014ostrtodig_selWhenset,theOSTRsignalispasseddirectlytothedigitalblock.
Thisisthesignalthat0isusedtoclockthedividers.
13ramp_enaWhenset,arampsignalisinsertedintheinputdataattheFIFOinput.
012:1ReservedReservedforfactoryuse.
0000000000100sifdac_enaWhenset,theDACoutputissettothevalueinsifdac(15:0)inregisterconfig48.
Inthis0mode,sif_txenainconfig3andTXENABLEinputsareignored.
Registername:config46–Address:0x2E,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig460x2E15:8ReservedReservedforfactoryuse.
0x007:0grp_delayI(7:0)SetsthegroupdelayfunctionforDACI.
Themaximumdelayrangesfrom30psto0x00100psandisdependentonDACsampleclock.
ContactTIforspecificapplicationinformation.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback45ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comRegistername:config47–Address:0x2F,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig470x2F15:8grp_delayQ(7:0)SetsthegroupdelayfunctionforDACQ.
Themaximumdelayrangesfrom30psto0x00100psandisdependentonDACsampleclock.
ContactTIforspecificapplicationinformation.
7:0ReservedReservedforfactoryuse.
0x00Registername:config48–Address:0x30,Default:0x0000RegisterDefaultAddressBitNameFunctionValueNameconfig480x3015:0sifdac(15:0)ValuesenttotheDACswhensifdac_enaisasserted.
DATACLKmustberunningto0x0000latchthisvalueintotheDACs.
Theformatwouldbebasedontwosinregisterconfig2.
Registername:version–Address:0x7F,Default:0x540C(READONLY)RegisterDefaultAddressBitNameFunctionValueNameversion0x7F15:10ReservedReservedforfactoryuse.
0101019ReservedReservedforfactoryuse.
08:7ReservedReservedforfactoryuse.
006:5ReservedReservedforfactoryuse.
004:3deviceid(1:0)Returns'01'forDAC3482.
012:0versionid(2:0)Ahardwiredregisterthatcontainstheversionofthechip.
10046SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013DATAINTERFACETheDAC3482hasa16-bitLVDSbusthataccepts16-bitIandQdataineitherword-wideorbyte-wideformats.
Inword-widemodedataissentthrougha16-bitbuswhileinbyte-widemodean8-bitbusisused.
Theselectionbetweenthetwomodesisdonethrough16bit_inintheconfig2register.
TheLVDSbusinputsineachmodeareshowninTable3.
Table3.
LVDSBusInputAssignmentInputModePinsWord-wideD[15.
.
0]Byte-wide(1)D[7.
.
0](1)Theunusedpinscanbeleftfloating.
Forword-by-wordparityandIOpatterncheckerfunctionality,thepinsneedtohaveknownlogicvaluesforvalidfunctionality.
DataissampledbytheLVDSdoubledatarate(DDR)clockDATACLK.
Setupandholdrequirementsmustbemetforpropersampling.
Forbothinputbusmodes,asyncsignal,eitherFRAMEorSYNC,cansynctheFIFOreadand/orwritepointers.
Inbyte-widemodethesyncsourceisneededtoestablishthecorrectsampleboundaries.
Thesyncsignal,eitherFRAMEorSYNC,canbeeitherapulseoraperiodicsignalwherethesyncperiodcorrespondstomultiplesof8samples.
FRAMEorSYNCissampledbyarisingedgeinDATACLK.
Thepulse-width(t(FRAME_SYNC))needstobeatleastequaltooftheDATACLKperiod.
Forbothinputbusmode,thevalueinFRAMEsampledbythenextfallingedgeinDATACLKcanbeusedasablockparityvalue.
Thisfeatureisenabledbysettingframe_parity_enainregisterconfig1to"1".
Referto"ParityCheckTest"sectionformoredetailWORD-WIDEFORMATTheword-wideformatisselectedbysetting16bit_into"1"intheconfig2register.
Inthismodethe16-bitdataforchannelsIandQisword-wideinterleavedintheformI0,Q0,I1,Q1…intotheD[15:0]16-bitbus.
DataintotheDAC3482isformattedaccordingtothediagramshowninFigure52whereindex0isthedataLSBandindex15isthedataMSB.
Figure52.
Word-WideDataTransmissionFormatForword-wideformatonly.
TheFIFOreadandwritepointerscanalsobesyncedbySIFSYNCasthethirdoptionifmulti-devicesynchronizationisnotneeded.
Inthissyncmode,syncsel_data_formatter(1:0)inregisterconfig32canbesetto"10"or"11".
Thesyncsel_fifoin(3:0)andsyncsel_fifoout(3:0)inregisterconfig32needtobebothsetto"1000"fortheSIFSYNCoption.
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comBYTE-WIDEFORMATThebyte-wideformatisselectedbysetting16bit_into"0"intheconfig2register.
Inthismodethe16-bitdataforchannelsIandQisbyte-wideinterleavedintheformI0[15:8],I0[7:0],Q0[15:8],Q0[7:0],I1[15:8]…intotheD[7:0]8-bitbus.
DataintotheDAC3482isformattedaccordingtothediagramshowninFigure53whereindex0isthedataLSBandindex15isthedataMSB.
Arisingedgetransitionofthesyncsignal,eitherFRAMEorSYNC,isusedtoestablishthecorrectsampleboundaries.
Figure53.
Byte-WideDataTransmissionFormatINPUTFIFOTheDAC3482includesa2-channel,16-bitswideand8-samplesdeepinputFIFOwhichactsasanelasticbuffer.
ThepurposeoftheFIFOistoabsorbanytimingvariationsbetweentheinputdataandtheinternalDACdatarateclocksuchastheonesresultingfromclock-to-datavariationsfromthedatasource.
Figure54showsasimplifiedblockdiagramoftheFIFO.
48SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Figure54.
DAC3482FIFOBlockDiagramDataiswrittentothedeviceontherisingandfallingedgesofDATACLK.
Each32-bitwidesample(16-bitI-dataand16-bitQ-data)iswrittenintotheFIFOattheaddressindicatedbythewritepointer.
Similarly,datafromtheFIFOisreadbytheFIFOOutClock32-bitsatatimefromtheaddressindicatedbythereadpointer.
TheFIFOOutClockisgeneratedinternallyfromtheDACCLKsignal.
ItsrateisequaltoDACCLK/2/Interpolationforword-widedatatransmission,orDACCLK/Interpolationforbyte-widedatatransmission.
EachtimeaFIFOwriteorFIFOreadisdonethecorrespondingpointermovestothenextaddress.
TheresetpositionfortheFIFOreadandwritepointersissetbydefaulttoaddresses0and4asshowninFigure54.
ThisoffsetgivesoptimalmarginwithintheFIFO.
Thedefaultreadpointerlocationcanbesettoanothervalueusingfifo_offset(2:0)inregisterconfig9(address4bydefault).
Undernormalconditionsdataiswritten-toandread-fromtheFIFOatthesamerateandconsequentlythewriteandreadpointergapremainsconstant.
IftheFIFOwriteandreadratesaredifferent,thecorrespondingpointerswillbecyclingatdifferentspeedswhichcouldresultinpointercollision.
UnderthisconditiontheFIFOattemptstoreadandwritedatafromthesameaddressatthesametimewhichwillresultinerrorsandthusmustbeavoided.
Thewritepointersyncsourceisselectedbysyncsel_fifoin(3:0)inregisterconfig32.
InmostapplicationseitherFRAMEorSYNCisusedtoresetthewritepointer.
UnlikeDATA,thesyncsignalislatchedonlyontherisingedgesofDATACLK.
Arisingedgeonthesyncsignalsourcecausesthepointertoreturntoitsoriginalposition.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback49ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comSimilarly,thereadpointersyncsourceisselectedbysyncsel_fifoout(3:0).
Thewritepointersyncsourcecanbesettoresetthereadpointeraswell.
Inthiscase,theFIFOOutclockwillrecapturethewritepointersyncsignaltoresetthereadpointer.
Thisclockdomaintransfer(DATACLKtoFIFOOutClock)resultsinphaseambiguityoftheresetsignal,andwillcreatelatencyvariationbasedonthecaptureedgeoftheFIFOOutClock.
SincetheresetsignalalsosynchronizestheclockdividercircuitfortheFIFOOutclockgeneration,thelatencyvariationalsoincludesthecaptureedgeoftheDACCLKcycleintheclockdividerstage.
Ultimately,thevariationincaptureedgeofboththeFIFOOutclockandtheDACCLKlimitstheprecisecontroloftheoutputtiminglatency.
ThefulllatencycontroloftheDACwillbedifficultandisnotrecommendedinthissetup.
NOTEForfulllatencycontroloftheDAC,refertotheDualSyncSourceModesectionofthedatasheet.
Toalleviatethis,thedeviceoffersthealternativeofresettingtheFIFOreadpointerindependentlyofthewritepointerbyusingtheOSTRsignal.
TheOSTRsignalissampledbyDACCLKandmustsatisfythetimingrequirementsinthespecificationstable.
InordertominimizetheskewitisrecommendedtousethesameclockdistributiondevicesuchasTexasInstrumentsCDCE62005toprovidetheDACCLKandOSTRsignalstoalltheDAC3482devicesinthesystem.
SwappingthepolarityoftheDACCLKoutputswithrespecttotheOSTRonesestablishesproperphaserelationship.
TheFIFOpointersresetprocedurecanbedoneperiodicallyoronlyonceduringinitializationasthepointersautomaticallyreturntotheinitialpositionwhentheFIFOhasbeenfilled.
ToresettheFIFOperiodically,thesignalstosynctheFIFOreadandwritepointercanrepeatatmultiplesof8FIFOsampleswhenthedatainterfaceisbyte-wideformat.
Whenthedatainterfaceisword-wideformat,thesignaltosynctheFIFOreadandwritepointercanrepeatatmultiplesof16FIFOsamples.
ThefrequencylimitationforFRAMEandSYNCsignalsarethefollowing:fsync=fDATACLK/(nx16)wheren=1,2,…canrepeatmultiplesof8FIFOsamplesforByte-WideModefsync=fDATACLK/(nx16)wheren=1,2,…canrepeatmultiplesof16FIFOsamplesforWord-WideModeThefrequencylimitationfortheOSTRsignalisthefollowing:fOSTR=fDAC/(nxinterpolationx8)wheren=1,2,…canrepeatmultiplesof8FIFOsamplesforByte-WideModefOSTR=fDAC/(nxinterpolationx16)wheren=1,2,…canrepeatmultiplesof16FIFOsamplesforWorld-WideModeThefrequenciesaboveareatmaximumwhenn=1.
ThisiswhentheFRAME,SYNC,orOSTRhavearisingedgetransitionevery8or16FIFOsamples.
Theoccurrencecanbemadelessfrequentbysettingn>1,forexample,everyn*8orn*16FIFOsamples.
50SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Figure55.
FIFOWriteandReadDescriptions(ExampleshownwithWord-WideMode)Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback51ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comFIFOMODESOFOPERATIONTheDAC3482inputFIFOcanbecompletelybypassedthroughregistersconfig0andconfig32.
TheregisterconfigurationforeachmodeisdescribedinTable4.
RegisterControlBitsconfig0fifo_enaconfig32syncsel_fifoout(3:0)Table4.
FIFOOperationModesconfig0andconfig32FIFOBitsFIFOModesyncsel_fifooutfifo_enaBit3:sif_syncBit2:OSTRBit1:FRAMEBit0:SYNCDualSyncSources10100SingleSync1or0Dependsonthesync1or0Dependsonthe100SourcesourcesyncsourceBypass0XXXXDUALSYNCSOURCESMODEThisistherecommendedmodeofoperationforthoseapplicationsthatrequireprecisecontroloftheoutputtiming.
InDualSyncSourcesmode,theFIFOwriteandreadpointersareresetindependently.
TheFIFOwritepointerisresetusingtheLVDSFRAMEorSYNCsignal,andtheFIFOreadpointerisresetusingtheLVPECLOSTRsignal.
ThisallowsLVPECLOSTRsignaltocontrolthephaseoftheoutputforeitherasinglechipormultiplechips.
Multipledevicescanbefullysynchronizedinthismode.
SINGLESYNCSOURCEMODEInSingleSyncSourcemode,theFIFOwriteandreadpointersareresetfromthesamesource,eitherLVDSFRAMEorLVDSSYNCsignal.
Asdescribedinthe"InputFIFO"section,thismodehaslatencyvariationsinboththeFIFOOutclockandDACclockbetweenthemultipleDACdevices.
ApplicationsrequiringexactoutputlatencycontrolwillneedDualSyncSourcesmodeinsteadofSingleSyncSourcemode.
AsinglerisingedgeforFIFOandclockdividerisrecommendedinthismode.
Periodicsyncsignalisnotrecommendedduetonon-deterministiclatencyofthesyncsignalthroughtheclockdomaintransfer.
Inthismode,thereisachanceforFIFOpointers2awayalarm(orpossibly1awayalarm)tooccuratinitialsetup/syncing.
ThisistheresultofSingleSyncSourcemodehaving0to3addresslocationslip,whichiscausedbytheasynchronoushandoffofthesyncsignaloccurringbetweentheDATACLKzoneandDACCLKzone.
Theasynchronousrelationshipbetweentheclockdomainsmeanstherecouldbeaslip(fromnominal)intheREADandWritepointersatinitialsyncing.
Forexample,withthedefaultprogrammingofFIFOOffsetof4,theactualFIFOOffsetmaybe3,2,orinsomeinstances,1.
Pleasenotethatinthismode,thenominaladdresslocationslipis0withthepossibilitygettinglessforeachincreaseinslipamount.
Also,theslipdoesnotcontinuetooccurasthedevicefunctions,buttheREAD/WRITEpointersmaynotbeatoptimalsettings.
Insituationofalarmoccurrence:.
1.
AdjusttheFIFOoffsetaccordinglyandresynchronizetheFIFO,dataformatter,etcsuchthattherearenoalarmreportedoratleastonly2awayalarmisreported2.
TheFIFOcollisionalarmisawarningofthesystemsincethereadandwriteprocessesoccuratthesamepointer.
However,theFIFO1awayor2awayalarmsareinformationalforthesystemdesigner.
Theimportantthingforthesetwoalarmsisthatthealarmshouldnotgetclosertocollisionduringnormaloperation.
If1awayalarmandalarmcollisionstartstooccur,itisawarningtocheckforsystemerrors.
Thesystemshouldhaveaninterruptoralgorithmtofixtheerrorandresynchronizethealarmappropriately.
52SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013BYPASSMODEInFIFObypassmode,theFIFOblockisnotused.
AsaresulttheinputdataishandedofffromtheDATACLKtotheDACCLKdomainwithoutanycompensation.
InthismodetherelationshipbetweenDATACLKandDACCLKiscriticalandusedasasynchronizingmechanismfortheinternallogic.
Duetothisconstraintthismodeisnotrecommended.
TheeffectsofbypassingtheFIFOarethefollowing:1.
TheFIFOpointershavenoeffectonthedatapathorhandoff.
2.
TheFIFOwillnotbeabletopassthecontrolssignalsfromtheLVDSFRAMEandLVDSSYNCtodigitalcircuitsaftertheFIFO.
Thesedigitalcircuitsmainlyarequadraturemodulationcorrectioncircuits,complexmixercircuit,andnumericalcontrolledoscillatorcircuits.
CLOCKINGMODESTheDAC3482hasadualclocksetupinwhichaDACclocksignalisusedtoclocktheDACcoresandinternaldigitallogicandaseparateDATAclockisusedtoclocktheinputLVDSreceiversandFIFOinput.
TheDAC3482DACclocksignalcanbesourceddirectlyorgeneratedthroughanon-chiplow-jitterphase-lockedloop(PLL).
InthoseapplicationsrequiringextremelylownoiseitisrecommendedtobypassthePLLandsourcetheDACclockdirectlyfromahigh-qualityexternalclocktotheDACCLKinput.
Inmostapplicationssystemclockingcanbesimplifiedbyusingtheon-chipPLLtogeneratetheDACcoreclockwhilestillsatisfyingperformancerequirements.
InthiscasetheDACCLKpinsareusedasthereferencefrequencyinputtothePLL.
Figure56.
TopLevelClockDiagramPLLBYPASSMODEInPLLbypassmodeaveryhighqualityclockissourcedtotheDACCLKinputs.
ThisclockisusedtodirectlyclocktheDAC3482DACsamplerateclock.
Thismodegivesthedevicebestperformanceandisrecommendedforextremelydemandingapplications.
Thebypassmodeisselectedbysettingthefollowing:1.
pll_enabitinregisterconfig24to"0"tobypassthePLLcircuitry.
2.
pll_sleepbitinregisterconfig26to"1"toputthePLLandVCOintosleepmode.
PLLMODEInthismodetheclockattheDACCLKinputfunctionsasareferenceclocksourcetotheon-chipPLL.
Theon-chipPLLwillthenmultiplythisreferenceclocktosupplyahigherfrequencyDACsamplerateclock.
Figure57showstheblockdiagramofthePLLcircuit.
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comFigure57.
PLLBlockDiagramTheDAC3482PLLmodeisselectedbysettingthefollowing:1.
pll_enabitinregisterconfig24to"1"toroutetothePLLclockpath.
2.
pll_sleepbitinregisterconfig26to"0"toenablethePLLandVCO.
TheoutputfrequencyoftheVCOisdesignedtobetheintherangefrom3.
3GHzto4.
0GHz.
Theprescalervalue,pll_p(2:0)inregisterconfig24,shouldbechosensuchthattheproductoftheprescalervalueandDACsamplerateclockiswithintheVCOrange.
TomaintainoptimalPLLloop,thecoarsetunebits,pll_vco(5:0)inregisterconfig26,canadjustthecenterfrequencyoftheVCOtowardstheproductoftheprescalervalueandDACsamplerateclock.
Figure58showsatypicalrelationshipbetweencoarsetunebitsandVCOcenterfrequency.
Fortherecommendedpll_vco(5:0)settingoverfree-airtemperature,refertoElectricalCharacteristic–Phased-LockedLoopSpecificationtablefordetail.
Figure58.
TypicalPLL/VCOLockRangevsCoarseTuningBits54SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Ifthecorrespondingpll_vco(5:0)settingandtheVCOfrequencyofinterestarenotinthePhase-LockedLoopSpecificationtable,TIrecommendstheuseofthetypicalpll_vco(5:0)valuefoundinFigure58alongwithimplementationofPLLlockstatuscheckovertemperature.
ThePLLlockstatuscanbereadbackinpll_lfvolt(2:0)registerofconfig24.
IfthePLLisoutofrange,adjustpll_vco(5:0)inconfig26accordingly.
TheexamplePLLlockstatusandadjustmentalgorithmcanbefoundinFigure59.
Figure59.
ExamplePLLLockStatusandAdjustmentAlgorithmCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback55ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comCommonwirelessinfrastructurefrequencies(614.
4MHz,737.
28MHz,983.
04MHz,etc.
)aregeneratedfromthisVCOfrequencyinconjunctionwiththepre-scalersettingasshowninTable5.
Table5.
VCOOperationVCOFrequency(MHz)Pre-ScaleDividerDesiredDACCLK(MHz)pll_p(2:0)3932.
168491.
521113686.
46614.
41103686.
45737.
281013932.
164983.
04100TheMdividerisusedtodeterminethephase-frequency-detector(PFD)andcharge-pump(CP)frequency.
Table6.
PFDandCPOperationDACCLKFrequencyMDividerPDFUpdateRate(MHz)pll_m(7:0)(MHz)491.
524122.
8800000100491.
52861.
4400001000491.
521630.
7200010000491.
523215.
3600100000TheNdividerintheloopallowsthePFDtooperateatalowerfrequencythanthereferenceclock.
BothMandNdividerscankeepthePFDfrequencybelow155MHzforpeakoperation.
TheoveralldivideratioinsidetheloopistheproductofthePre-ScaleandMdividers(P*M)andthefollowingguidelinesshouldbefollowed:Theoveralldivideratiorangeisfrom24to480Whentheoveralldivideratioislessthan120,theinternalloopfiltercanguaranteeastableloopWhentheoveralldivideratioisgreaterthan120,anexternalloopfilterordoublechargepumpisrequiredtoensureloopstabilityThesingle-anddouble-charge-pumpcurrentoptionareselectedbysettingpll_cpinregisterconfig24to01and11,respectively.
Whenusingthedouble-charge-pumpsetting,anexteranlloopfilterisnotrequired.
Ifanexternalfilterisrequired,thefollowingfiltershouldbeconnectedtotheLPFpin(A1):Figure60.
RecommendedExternalLoopFilterThePLLwillgenerateaninternalOSTRsignalanddoesnotrequiretheexternalLVPECLOSTRsignal.
TheOSTRsignalisbufferedfromtheN-divideroutputinthePLLblock,andthefrequencyofthesignalisthesameasthePFDfrequency.
Therefore,usingPLLwithDualSyncSourcesmoderequiresthePFDfrequencytobethepre-definedOSTRfrequencylistedinInputFIFOsection.
ThiswillallowtheFIFOtobesyncedcorrectlybytheinternalOSTR.
MULTI-DEVICESYNCHRONIZATIONInvariousapplications,suchasmultiantennasystemswherethevarioustransmitchannelsinformationiscorrelated,itisrequiredthatmultipleDACdevicesarecompletelysynchronizedsuchthattheiroutputsarephasealigned.
TheDAC3482architecturesupportsthismodeofoperation.
56SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013MULTI-DEVICESYNCHRONIZATION:PLLBYPASSEDWITHDUALSYNCSOURCESMODEForsingleormulti-devicesynchronizationitisimportantthatdelaydifferencesinthedataareabsorbedbythedevicesothatlatencythroughthedeviceremainsthesame.
Furthermore,toguaranteethattheoutputsfromeachDACarephasealigneditisnecessarythatdataisreadfromtheFIFOofeachdevicesimultaneously.
IntheDAC3482thisisaccomplishedbyoperatingthemultipledevicesinDualSyncSourcesmode.
InthismodetheadditionalOSTRsignalisrequiredbyeachDAC3482tobesynchronized.
DataintothedeviceisinputasLVDSsignalsfromoneormultiplebasebandASICsorFPGAs.
DataintothemultipleDACdevicescanexperiencedifferentdelaysduetovariationsinthedigitalsourceoutputpathsorboardlevelwiring.
ThesedifferentdelayscanbeeffectivelyabsorbedbytheDAC3482FIFOsothatalloutputsarephasealignedcorrectly.
Figure61.
SynchronizationSysteminDualSyncSourcesModewithPLLBypassedForcorrectoperationbothOSTRandDACCLKmustbegeneratedfromthesameclockdomain.
TheOSTRsignalissampledbyDACCLKandmustsatisfythetimingrequirementsinthespecificationstable.
IftheclockgeneratordoesnothavetheabilitytodelaytheDACCLKtomeettheOSTRtimingrequirement,thepolarityoftheDACCLKoutputscanbeswappedwithrespecttotheOSTRonestocreate180degreephasedelayoftheDACCLK.
ThismayhelpestablishpropersetupandholdtimerequirementoftheOSTRsignal.
CarefulboardlayoutplanningmustbedonetoensurethattheDACCLKandOSTRsignalsaredistributedfromdevicetodevicewiththelowestskewpossibleasthiswillaffectthesynchronizationprocess.
InordertominimizetheskewacrossdevicesitisrecommendedtousethesameclockdistributiondevicetoprovidetheDACCLKandOSTRsignalstoalltheDACdevicesinthesystem.
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comFigure62.
TimingDiagramforLVPECLSynchronizationSignalsThefollowingstepsarerequiredtoensurethedevicesarefullysynchronized.
TheprocedureassumesalltheDAC3482deviceshaveaDACCLKandOSTRsignalandmustbecarriedoutoneachdevice.
1.
Start-upthedeviceasdescribedinthepower-upsequence.
SettheDAC3482inDualSyncSourcesmodeandselectOSTRastheclockdividersyncsource(clkdiv_sync_selinregisterconfig32).
2.
SynctheclockdividerandFIFOpointers.
3.
VerifytherearenoFIFOalarmseitherthroughregisterconfig5orthroughtheALARMpin.
4.
Disableclockdividersyncbysettingclkdiv_sync_enato"0"inregisterconfig0.
AfterthesestepsalltheDAC3482outputswillbesynchronized.
MULTI-DEVICESYNCHRONIZATION:PLLENABLEDWITHDUALSYNCSOURCESMODETheDAC3482allowsexactphasealignmentbetweenmultipledevicesevenwhenoperatingwiththeinternalPLLclockmultiplier.
InPLLclockmode,thePLLgeneratestheDACclockandaninternalOSTRsignalfromthereferenceclockappliedtotheDACCLKinputssothereisnoneedtosupplyanadditionalLVPECLOSTRsignal.
ForthismethodtooperateproperlytheSYNCsignalshouldbesettoresetthePLLNdividerstoaknownstatebysettingpll_ndivsync_enainregisterconfig24to"1".
TheSYNCsignalresetsthePLLNdividerswitharisingedge,andthetimingrelationshipts(SYNC_PLL)andth(SYNC_PLL)arerelativetothereferenceclockpresentedontheDACCLKpin.
BothSYNCandDACCLKcanbesetaslowfrequencysignalstogreatlysimplifyingtracerouting(SYNCcanbejustapulseasasinglerisingedgeisrequired,ifusingaperiodicsignalitisrecommendedtoclearthepll_ndivsync_enabitafterresettingthePLLdividers).
Besidesthet(SYNC_PLL)requirementbetweenSYNCandDACCLK,thereisnoadditionalrequiredtimingrelationshipbetweentheSYNCandFRAMEsignalsorbetweenDACCLKandDATACLK.
TheonlyrestrictionasinthePLLdisabledcaseisthattheDACCLKandSYNCsignalsaredistributedfromdevicetodevicewiththelowestskewpossible.
58SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Figure63.
SynchronizationSysteminDualSyncSourcesModewithPLLEnabledThefollowingstepsarerequiredtoensurethedevicesarefullysynchronized.
TheprocedureassumesalltheDAC3482deviceshaveaDACCLKandOSTRsignalandmustbecarriedoutoneachdevice.
1.
Start-upthedeviceasdescribedinthepower-upsequence.
SettheDAC3482inDualSyncSourcesmodeandenableSYNCtoresetthePLLdividers(setpll_ndivsync_enainregisterconfig24to"1").
2.
ResetthePLLdividerswitharisingedgeonSYNC.
3.
DisablePLLdividersresetting.
4.
SynctheclockdividerandFIFOpointers.
5.
VerifytherearenoFIFOalarmseitherthroughregisterconfig5orthroughtheALARMpin.
6.
Disableclockdividersyncbysettingclkdiv_sync_enato"0"inregisterconfig0.
AfterthesestepsalltheDAC3482outputswillbesynchronized.
MULTI-DEVICEOPERATION:SINGLESYNCSOURCEMODEInSingleSyncSourcemodetheFIFOreadpointerresetishandoffbetweenthetwoclockdomains(DATACLKandFIFOOutclock)bysimplyre-samplingthewritepointerreset.
Sincethetwoclocksareasynchronousthereisasmallbutdistinctpossibilityofameta-stablesituationduringthepointerhandoff.
Asdescribedinthe"InputFIFO"section,thismeta-stablesituationcanchangethelatencyofthemultipleDACdevicesbyboththeFIFOOutclockcyclesandDACclockcycles.
WhenthePLLisenabledwithSingleSyncSourcemode,theFIFOreadpointerisnotsynchronizedbytheOSTRsignal.
Therefore,thereisnorestrictiononthePLLPFDfrequencyasdescribedintheprevioussection.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback59ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comFigure64.
Multi-DeviceOperationinSingleSyncSourceModeFIRFILTERSFigure65throughFigure68showthemagnitudespectrumresponsefortheFIR0,FIR1,FIR2andFIR3interpolatingfilterswherefINistheinputdataratetotheFIRfilter.
Figure69toFigure72showthecompositefilterresponsefor2x,4x,8xand16xinterpolation.
Thetransitionbandforallinterpolationsettingsisfrom0.
4to0.
6xfDATA(theinputdataratetothedevice)with90dBstop-bandattenuation.
TheDAC3482alsohasa9-tapinversesincfilter(FIR4)thatrunsattheDACupdaterate(fDAC)thatcanbeusedtoflattenthefrequencyresponseofthesample-and-holdoutput.
TheDACsample-and-holdoutputsetstheoutputcurrentandholdsitconstantforoneDACclockcycleuntilthenextsample,resultinginthewell-knownsin(x)/xorsinc(x)frequencyresponse(Figure15,redline).
Theinversesincfilterresponse(Figure66,blueline)hastheoppositefrequencyresponsefrom0to0.
4xFdac,resultinginthecombinedresponse(Figure66,greenline).
Between0to0.
4xfDAC,theinversesincfiltercompensatesthesample-and-holdroll-offwithlessthan0.
03dBerror.
Theinversesincfilterhasagain>1atallfrequencies.
Therefore,thesignalinputtoFIR4mustbereducedfromfullscaletopreventsaturationinthefilter.
Theamountofback-offrequireddependsonthesignalfrequency,andissetsuchthatatthesignalfrequenciesthecombinationoftheinputsignalandfilterresponseislessthan1(0dB).
Forexample,ifthesignalinputtoFIR4isat0.
25xfDAC,theresponseofFIR4is0.
9dB,andthesignalmustbebackedofffromfullscaleby0.
9dBtoavoidsaturation.
ThegainfunctionintheQMCblockscanbeusedtoreducetheamplitudeoftheinputsignal.
TheadvantageofFIR4havingapositivegainatallfrequenciesisthattheuseristhenabletooptimizetheback-offofthesignalbasedonitsfrequency.
ThefiltertapsforalldigitalfiltersarelistedinTable4.
NotethatthelossofsignalamplitudemayresultinlowerSNRduetodecreaseinsignalamplitude.
SPACER60SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Figure65.
MagnitudeSpectrumforFIR0Figure66.
MagnitudeSpectrumforFIR1SPACERSPACERFigure67.
MagnitudeSpectrumforFIR2Figure68.
MagnitudeSpectrumforFIR3SPACERSPACERFigure69.
2xInterpolationCompositeResponseFigure70.
4xInterpolationCompositeResponseSPACERSPACERCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback61ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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8xInterpolationCompositeResponseFigure72.
16xInterpolationCompositeResponseSPACERSPACERFigure73.
MagnitudeSpectrumforInverseSincFilter62SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Table7.
FIRFilterCoefficientsNon-InterpolatingInterpolatingHalf-bandFiltersInverse-SINCFilterFIR0FIR1FIR2FIR3FIR459Taps23Taps11Taps11Taps9Taps66-12-122929331100000000-4-4-19-198484-214-214-25-25131300000000-50-504747-336-33612091209150150592(1)00002048(1)256(1)-100-100100610060000192192-2691-26910000-342-34210141101410016384(1)57257200-914-914001409140900-2119-2119003152315200-4729-4729007420742000-13334-1333400415274152765536(1)(1)CentertapsarehighlightedinBOLDCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback63ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
ti.
comCOMPLEXSIGNALMIXERTheDAC3482hastwopathsofcomplexsignalmixerblocksthatcontaintwofullcomplexmixer(FMIX)blocksandpowersavingcoarsemixer(CMIX)blocks.
ThesignalpathisshowninFigure74.
Figure74.
PathofComplexSignalMixerFULLCOMPLEXMIXERTheDAC3482hasafullcomplexmixer(FMIX)blockwithaNumericallyControlledOscillators(NCO)thatenablesflexiblefrequencyplacementwithoutimposingadditionallimitationsinthesignalbandwidth.
TheNCOhasa32-bitfrequencyregisters(phaseadd(31:0))anda16-bitphaseregister(phaseoffset(15:0))thatgeneratethesineandcosinetermsforthecomplexmixing.
TheNCOblockdiagramisshownbelowinFigure75.
Figure75.
NCOBlockDiagramSynchronizationoftheNCOsoccursbyresettingtheNCOaccumulatorstozero.
Thesynchronizationsourceisselectedbysyncsel_NCO(3:0)inconfig31.
Thefrequencywordinthephaseadd(31:0)registerisaddedtotheaccumulatorseveryclockcycle,fDAC.
TheoutputfrequencyoftheNCOis:(1)64SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Withthecomplexmixerenabled,thetwochannelsinthemixerpatharetreatedascomplexvectorsoftheformIIN(t)+jQIN(t).
Thecomplexsignalmultiplier(showninFigure76)willmultiplythecomplexchannelswiththesineandcosinetermsgeneratedbytheNCO.
Theresultingoutput,IOUT(t)+jQOUT(t),ofthecomplexsignalmultiplieris:IOUT(t)=(IIN(t)cos(2πfNCOt+δ)–QIN(t)sin(2πfNCOt+δ))*2(mixer_gain–1)QOUT(t)=(IIN(t)sin(2πfNCOt+δ)+QIN(t)cos(2πfNCOt+δ))*2(mixer_gain–1)Figure76.
ComplexSignalMultiplierwheretisthetimesincethelastresettingoftheNCOaccumulator,δisthephaseoffsetvalueandmixer_gainiseither0or1.
δisgivenby:δ=2π*phase_offset(15:0)/216Themixer_gainoptionallowstheoutputsignalsofthemultipliertoreducebyhalf(6dB).
SeeMixerGainSectionfordetail.
COARSECOMPLEXMIXERInadditiontothefullcomplexmixer,theDAC3482alsohasacoarsemixerblockcapableofshiftingtheinputsignalspectrumbythefixedmixingfrequencies±n*fS/8.
Usingthecoarsemixerinsteadofthefullmixerlowerspowerconsumption.
Theoutputofthefs/2,fs/4,and–fs/4mixerblockis:IOUT(t)=I(t)cos(2πfCMIXt)–Q(t)sin(2πfCMIXt)QOUT(t)=I(t)sin(2πfCMIXt)+Q(t)cos(2πfCMIXt)Sincethesineandthecosinetermsareafunctionoffs/2,fs/4,or–fs/4mixingfrequencies,thepossibleresultingvalueofthetermswillonlybe1,-1,or0.
Thesimplifiedmathematicsallowsthecomplexsignalmultipliertobebypassedinanyoneofthemodes,thusmixergainisnotavailable.
Thefs/2,fs/4,and–fs/4mixerblocksperformsmixingthroughnegatingandswappingofI/Qchanneloncertainsequenceofsamples.
Table8showsthealgorithmusedforthosemixerblocks.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback65ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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Fs/2,Fs/4,and–Fs/4MixingSequenceMODEMIXINGSEQUENCEIout={+I1,+I2,+I3,+I4…}Normal(mixerbypassed)Qout={+Q1,+Q2,+Q3,+Q4…}Iout={+I1,-I2,+I3,-I4…}fs/2Qout={+Q1,-Q2,+Q3,-Q4…}Iout={+I1,-Q2,-I3,+Q4…}fs/4Qout={+Q1,+I2,-Q3,-I4…}Iout={+I1,+Q2,-I3,-Q4…}-fs/4Qout={+Q1,-I2,-Q3,+I4…}Thefs/8mixercanbeenabledalongwithvariouscombinationsoffs/2,fs/4,and–fs/4mixer.
Sincethefs/8mixerusesthecomplexsignalmultiplierblockwithfixedfs/8sineandcosineterm,theoutputofthemultiplieris:IOUT(t)=(IIN(t)cos(2πfNCOt+δ)–QIN(t)sin(2πfNCOt+δ))*2(mixer_gain–1)QOUT(t)=(IIN(t)sin(2πfNCOt+δ)+QIN(t)cos(2πfNCOt+δ))*2(mixer_gain–1)wherefCMIXisthefixedmixingfrequencyselectedbycmix(3:0).
ThemixingcombinationsaredescribedinTable9.
Themixer_gainoptionallowstheoutputsignalsofthemultipliertoreducebyhalf(6dB).
SeeMixerGainsectionfordetail.
Table9.
CoarseMixerCombinationsFs/8MixerFs/4MixerFs/2Mixer–Fs/4Mixercmix(3:0)MixingModecmix(3)cmix(2)cmix(1)cmix(0)0000DisabledDisabledDisabledDisabledNomixing0001DisabledDisabledDisabledEnabled–Fs/40010DisabledDisabledEnabledDisabledFs/20100DisabledEnabledDisabledDisabled+Fs/41000EnabledDisabledDisabledDisabled+Fs/81010EnabledDisabledEnabledDisabled–3Fs/81100EnabledEnabledDisabledDisabled+3Fs/81110EnabledEnabledEnabledDisabled–Fs/8Allothers––––NotrecommendedMIXERGAINThemaximumoutputamplitudeoutofthecomplexsignalmultiplier(i.
e.
,FMIXmodeorCMIXmodewithfs/8mixerenabled)occursifIIN(t)andQIN(t)aresimultaneouslyfullscaleamplitudeandthesineandcosineargumentsareequalto2πxfMIXt+δ(2N-1)xπ/4,whereN=1,2,3,etc.
.
.
.
Figure77.
MaximumOutputoftheComplexSignalMultiplierWithmixer_gain=1andbothIIN(t)andQIN(t)aresimultaneouslyfullscaleamplitude,themaximumoutputpossibleoutofthecomplexsignalmultiplieris0.
707+0.
707=1.
414(or3dB).
Thisconfigurationcancauseclippingofthesignalandshouldthereforebeusedwithcaution.
66SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Withmixer_gain=0inconfig2,themaximumoutputpossibleoutofthecomplexsignalmultiplieris0.
5x(0.
707+0.
707)=0.
707(or-3dB).
Thislossinsignalpowerisinmostcasesundesirable,anditisrecommendedthatthegainfunctionoftheQMCblockbeusedtoincreasethesignalby3dBtocompensate.
REALCHANNELUPCONVERSIONThemixerintheDAC3482treatstheIandQinputsarecomplexinputdataandproducesacomplexoutputformostmixingfrequencies.
Therealinputdataforeachchannelcanbeisolatedonlywhenthemixingfrequencyissettonormalmodeorfs/2mode.
RefertoTable8fordetails.
QUADRATUREMODULATIONCORRECTION(QMC)GAINANDPHASECORRECTIONTheDAC3482includesaQuadratureModulatorCorrection(QMC)block.
TheQMCblocksprovideameanforchangingthegainandphaseofthecomplexsignalstocompensateforanyIandQimbalancespresentinananalogquadraturemodulator.
TheblockdiagramfortheQMCblockisshowninFigure78.
TheQMCblockcontains3programmableparameters.
Registerqmc_gain(10:0)controlstheIandQpathgainsandisan11-bitunsignedvaluewitharangeof0to1.
9990andthedefaultgainis1.
0000.
Theimplieddecimalpointforthemultiplicationisbetweenbit9andbit10.
Registerqmc_phase(11:0)controlthephaseimbalancebetweenIandQandisa12-bitvalueswitharangeof–0.
5toapproximately0.
49975.
TheQMCphasetermisnotadirectphaserotationbutaconstantthatismultipliedbyeach"Q"samplethensummedintothe"I"samplepath.
Thisisanapproximationofatruephaserotationinordertokeeptheimplementationsimple.
Thecorrespondingphaserotationcorrespondstoapproximately+26.
5to–26.
5degreesin4096steps.
LOfeed-throughcanbeminimizedbyadjustingtheDACoffsetfeaturedescribedbelow.
Figure78.
QMCBlockDiagramOFFSETCORRECTIONRegistersqmc_offsetI(12:0)andqmc_offsetQ(12:0)canbeusedtoindependentlyadjusttheDCoffsetsofeachchannel.
Theoffsetvaluesareinrepresentedin2s-complementformatwitharangefrom–4096to4095.
Theoffsetvalueaddsadigitaloffsettothedigitaldatabeforedigital-to-analogconversion.
Sincetheoffsetisaddeddirectlytothedataitmaybenecessarytobackoffthesignaltopreventsaturation.
BothdataandoffsetvaluesareLSBaligned.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback67ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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DigitalOffsetBlockDiagramGROUPDELAYCORRECTIONAcomplextransmittersystemtypicallyisconsistedofaDAC,reconstructionfilternetwork,andI/Qmodulator.
Besidesthegainandphasemismatchcontribution,therecouldalsobetimingmismatchcontributionfromeachcomponents.
Forinstance,thetimingmismatchcouldcomefromthePCBtracelengthvariationbetweentheIandQchannelsandthegroupdelayvariationfromthereconstructionfilter.
Thistimingmismatchinthecomplextransmittersystemcreatesphasemismatchthatvarieslinearlywithrespecttofrequency.
TocompensatefortheI/Qimbalancesduetothismismatch,theDAC3482hasgroupdelaycorrectionblockforeachDACchannel.
EachDACchannelcanadjustitsdelaythroughgrp_delayI(7:0)andgrp_delayq(7:0)inregisterconfig46andconfig47,respectively.
Themaximumdelayrangesfrom30psto100psandisdependentonDACsampleclock.
ContactTIforspecificapplicationinformation.
Thegroupdelaycorrection,alongwithgain/phasecorrection,canbeusefulforcorrectingimbalancesinwide-bandtransmittersystem.
TEMPERATURESENSORTheDAC3482incorporatesatemperaturesensorblockwhichmonitorsthetemperaturebymeasuringthevoltageacross2transistors.
Thevoltageisconvertedtoan8-bitdigitalwordusingasuccessive-approximation(SAR)analogtodigitalconversionprocess.
Theresultisscaled,limitedandformattedasatwoscomplementvaluerepresentingthetemperatureindegreesCelsius.
ThesamplingiscontrolledbytheserialinterfacesignalsSDENBandSCLK.
Ifthetemperaturesensorisenabled(tsense_sleep=0inregisterconfig26)aconversiontakesplaceeachtimetheserialportiswrittenorread.
Thedataisonlyreadandsentoutbythedigitalblockwhenthetemperaturesensorisreadintempdata(7:0)inconfig6.
Theconversionusesthefirsteightclocksoftheserialclockasthecaptureandconversionclock,thedataisvalidonthefallingeighthSCLK.
ThedataisthenclockedoutofthechipontherisingedgeoftheninthSCLK.
Nootherclockstothechiparenecessaryforthetemperaturesensoroperation.
Asaresultthetemperaturesensorisenabledevenwhenthedeviceisinsleepmode.
Inorderfortheprocessdescribedabovetooperateproperly,theserialportreadfromconfig6mustbedonewithanSCLKperiodofatleast1μs.
Ifthisisnotsatisfiedthetemperaturesensoraccuracyisgreatlyreduced.
DATAPATTERNCHECKERTheDAC3482incorporatesasimplepatterncheckertestinordertodetermineerrorsinthedatainterface.
Themaincauseoffailuresissetup/holdtimingissues.
Thetestmodeisenabledbyassertingiotest_enainregisterconfig1.
IntestmodetheanalogoutputsaredeactivatedregardlessofthestateofTXENABLEorsif_texnableinregisterconfig3.
Thedatapatternkeyusedforthetestis8wordslongandisspecifiedbythecontentsofiotest_pattern[0:7]inregistersconfig37throughconfig44.
Thedatapatternkeycanbemodifiedbychangingthecontentsoftheseregisters.
68SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013ThefirstwordinthetestframeisdeterminedbyarisingedgetransitioninFRAMEorSYNC,dependingonthesyncsel_fifoin(3:0)settinginconfig32.
Atthistransition,thepattern0wordshouldbeinputtothedatapins.
Patterns1through7shouldfollowsequentiallyoneachedgeofDATACLK(risingandfalling).
Thesequenceshouldberepeateduntilthepatterncheckertestisdisabledbysettingiotest_enabackto0.
ItisnotnecessarytohavearisingFRAMEorSYNCedgealignedwitheverypattern0word,justthefirstonetomarkthebeginningoftheseries.
Figure80.
IOPatternCheckerDataTransmissionFormatThetestmodedeterminesifthe16-bitLVDSdataD[15:0]P/Nofallthepatternswerereceivedcorrectlybycomparingthereceiveddataagainstthedatapatternkey.
Ifanyofthe16-bitdataD[15:0]P/Nwerereceivedincorrectly,thecorrespondingbitsiniotest_results(15:0)inregisterconfig4willbesetto"1"toindicatebiterrorlocation.
Furthermore,theerrorconditionwilltriggerthealarm_from_iotestbitinregisterconfig5toindicateageneralerrorinthedatainterface.
Whendatapatterncheckermodeisenabled,thisalarminregisterconfig5,bit7istheonlyvalidalarm.
Otheralarmsinregisterconfig5arenotvalidandcanbedisregarded.
Forinstance,pattern0isprogrammedtothedefaultof0x7A7A.
IfthereceivedPattern0is0x7A7B,thenbit0iniotest_results(15:0)willbesetto"1"toindicateanerrorinbit0location.
Thealarm_from_iotestwillalsobesetto"1"toreportthedatatransfererror.
Theusercanthennarrowdowntheerrorfromthealarm_from_iotestbitlocationinformationandimplementthefixaccordingly.
Thealarmscanbeclearedbywriting0x0000toiotest_results(15:0)and"0"toalarm_from_iotestthroughtheserialinterface.
Theserialinterfacewillreadback0siftherearenoerrorsoriftheerrorsarecleared.
Thecorrespondingalarmbitwillremaina"1"iftheerrorsremain.
Basedonthepatterntestresult,theusercanadjustthedatasourceoutputtiming,PCBtracesdelay,orDAC3482CONFIG36LVDSProgrammabledelaytohelpoptimizethesetupandholdtimeofthetransmittersystem.
Notethatunlesstheunuseddatapinsinbyte-wideinputformatareforcedtoaknownvaluethedatapatterncheckerisonlyavailablefortheword-wideinputdataformat.
Inbyte-wideinputformat,thefirst8-bitsoftheiotest_pattern[0:7]inregistersconfig37throughconfig44willeitherneedtobe0sor1sforvaliddatapatternchecking.
Itisrecommendedtoenablethepatterncheckerandthenrunthepatternsequencefor100ormorecompletecyclesbeforeclearingtheiotest_results(15:0)andalarm_from_iotest.
Thiswilleliminatethepossibilityoffalsealarmsgeneratedduringthesetupsequence.
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DAC3482PatternCheckBlockDiagram70SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013PARITYCHECKTESTTheDAC3482hasaparitychecktestthatenablescontinuousvaliditymonitoringofthedatareceivedbytheDAC.
Paritychecktestingincombinationwiththedatapatterncheckerofferanexcellentsolutionfordetectingboardassemblyissuesduetomissingpadconnections.
Fortheparitychecktest,anextraparitybitisaddedtothedatabitstoensurethatthetotalnumberofsetbits(bitswithlogicvalueof"1")isevenorodd.
Thissimpleschemeisusedtodetectdatatransfererrors.
ParitytestingisimplementedintheDAC3482intwoways:word-by-wordparityandblockparity.
WORD-BY-WORDPARITYWord-by-wordparityistheeasiestmodetoimplement.
Inthismodetheadditionalparitybitissourcedtotheparityinput(PARITYP/N)foreachdatawordtransferintotheD[15:0]P/Ninputs.
Thismodeisenabledbysettingtheword_parity_enabit.
Theinputparityvalueisdefinedtobethetotalnumberoflogic1sonthe17-bitdatabus,theD[15:0]P/NinputsandthePARITYP/Ninput.
Thisvalue,thetotalnumberoflogic1s,mustmatchtheparitytestselectedintheoddeven_paritybitinregisterconfig1.
Forexample,iftheoddeven_paritybitissetto"1"foroddparity,thenthenumberof1sonthe17-bitdatabusshouldbeodd.
TheDACwillcheckthedatatransferthroughtheparityinput.
Ifthedatareceivedhasoddnumberof1s,thentheparityiscorrect.
Ifthedatareceivedhasevennumberof1s,thentheparityisincorrect.
Thecorrespondingalarmforparityerrorwillbesetaccordingly.
Notethatunlesstheunuseddatapinsinbyte-wideinputformatareforcedtoaknownvaluetheword-by-wordparityisonlyavailablefortheword-wideinputdataformat.
Figure82showsthesimpleXORstructureusedtocheckwordparity.
ParityistestedindependentlyfordatacapturedonbothrisingandfallingedgesofDATACLK(alarm_rparityandalarm_fparity,respectively).
Testingonbothedgeshelpsindeterminingapossiblesetup/holdissue.
Bothalarmsarecapturedindividuallyinregisterconfig5.
Figure82.
DAC3482Word-by-WordParityCheckBLOCKPARITYTheblockparitymethodusestheFRAMEsignaltodeterminetheboundariesofthedatablocktocomputeparity.
Thismodeisenabledbysettingtheframe_parity_enabitinregisterconfig1.
Alow-to-hightransitionofFRAMEcapturedwiththeDATACLKrisingedgedeterminestheendpointoftheparityblockandthebeginningofthenextone.
InthismethodtheparitybitofthecompletedblockcorrespondstotheFRAMEvaluecapturedontheDATACLKfallingedgerightaftertheSTOP/STARTpoint.
Theinputparityvalueisdefinedtobethetotalnumberoflogic1sinthedatablock.
AlogicHIGHcapturedonthefallingedgeofDATACLKindicatesoddparityoroddnumberoflogic1s,whilealogicLOWindicatesevenparityorevennumberoflogic1s.
Iftheexpectedparitydoesnotmatchthenumberoflogic1sinthereceiveddata,thenalarm_frame_parityinregisterconfig5willbesetto"1".
ThemainadvantageoftheblockparitymodeisthatthereisnoneedforanadditionalparityLVDSinput.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback71ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comSincetheFRAMEsignalisusedforparitytestinginadditiontoFIFOsyncingandframeboundaryassignment,itismandatorytotakesomeextrastepstoavoiddevicemalfunction.
IfFRAMEisusedtoresettheFIFOpointerscontinuously,theblocksizemustbeamultipleof8samples(eachsamplecorrespondingto16-bitsIand16-bitsQ).
InadditionsinceFRAMEisusedinbyte-wideinputdatamodetoestablishtheframeboundary,theparityblockmustbealignedwiththedataframeboundaries.
Inaddition,theuseofblockparityinbyte-wideinputdatamoderequiresthefollowingsteps:1.
SinceFRAMEisusedtoestablishFRAMEboundary,theparityblockmustbealignedwiththedataframeboundaries.
2.
Unuseddatapinsneedtohaveknownlogicvalueforblockparitytofunctioncorrectly.
Notes:RisingedgeofFRAMEP/Nindicatesthebeginningofdatablock.
ParitybitforthecurrentdatablockislatchedonfallingedgeofDATACLKafterthestartpointfornextdatablock.
Figure83.
DAC3482BlockParityCheck(ExampleshownwithWord-WideMode)DAC3482ALARMMONITORINGTheDAC3482includesaflexiblesetofalarmmonitoringthatcanbeusedtoalertofapossiblemalfunctionscenario.
Allthealarmeventscanbeaccessedeitherthroughtheconfig5registerorthroughtheALARMpin.
Onceanalarmisset,thecorrespondingalarmbitinregisterconfig5mustberesetthroughtheserialinterfacetoallowfurthertesting.
ThesetofalarmsincludesthefollowingconditionsZerocheckalarmAlarm_from_zerochk.
OccurswhentheFIFOwritepointerhasanallzerospattern.
Sincethewritepointerisashiftregister,allzeroswillcausetheinputpointtobestuckuntilthenextsyncevent.
WhenthishappensasynctotheFIFOblockisrequired.
FIFOalarmsalarm_from_fifo.
OccurswhenthereisacollisionintheFIFOpointersoracollisioneventisclose.
–alarm_fifo_2away.
Pointersarewithintwoaddressesofeachother.
–alarm_fifo_1away.
Pointersarewithinoneaddressofeachother.
–alarm_fifo_collision.
Pointersareequaltoeachother.
Clockalarmsclock_gone.
OccurswheneithertheDACCLKorDATACLOCKhavebeenstopped.
–alarm_dacclk_gone.
OccurswhentheDACCLKhasbeenstopped.
–alarm_dataclk_gone.
OccurswhentheDATACLKhasbeenstopped.
Patterncheckeralarmalarm_from_iotest.
Occurswhentheinputdatapatterndoesnotmatchthepatternkey.
72SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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OccurswhenthePLLisoutoflock.
Parityalarmsalarm_rparity.
OccurswhenthereisaparityerrorinthedatacapturedbytherisingedgeofDATACLKP/N.
ThePARITYP/Ninputistheparitybit(word-by-wordparitytest).
alarm_fparity.
OccurswhenthereisaparityerrorinthedatacapturedbythefallingedgeofDATACLKP/N.
ThePARITYP/Ninputistheparitybit(word-by-wordparitytest).
alarm_frame_parity_err.
OccurswhenthereisaframeparityerrorwhenusingtheFRAMEastheparitybit(blockparitytest).
TopreventunexpectedDACoutputsfrompropagatingintothetransmitchannelchain,theclockandalarm_fifo_collisionalarmscanbesetinconfig2toshut-offtheDACoutputautomaticallyregardlessofthestateofTXENABLEorsif_txenable.
Alarmmonitoringisimplementedasfollows:Powerupthedeviceusingtherecommendedpower-upsequence.
Clearallthealarmsinconfig5bysettingthemto0.
UnmaskthosealarmsthatwillgenerateahardwareinterruptthroughtheALARMpininconfig7.
EnableautomaticDACshut-offinregisterconfig2ifrequired.
Inthecaseofanalarmevent,theALARMpinwilltrigger.
IfautomaticDACshut-offhasbeenenabledtheDACoutputswillbedisabled.
Readregistersconfig5todeterminewhichalarmtriggeredtheALARMpin.
Correcttheerrorconditionandre-synchronizetheFIFO.
Clearthealarmsinconfig5.
Re-readconfig5toensurethealarmeventhasbeencorrected.
Keepclearingandreadingconfig5untilnoerrorisreported.
POWER-UPSEQUENCEThefollowingstartupsequenceisrecommendedtopower-uptheDAC3482:1.
SetTXENABLElow2.
Supplyall1.
2Vvoltages(DACVDD,DIGVDD,CLKVDDandVFUSE)andall3.
3Vvoltages(AVDD,IOVDD,andPLLAVDD).
The1.
2Vand3.
3Vsuppliescanbepoweredupsimultaneouslyorinanyorder.
Therearenospecificrequirementsontheramprateforthesupplies.
3.
ProvideallLVPECLinputs:DACCLKP/NandtheoptionalOSTRP/N.
TheseinputscanalsobeprovidedaftertheSIFregisterprogramming.
4.
ToggletheRESETBpinforaminimum25nsactivelowpulsewidth.
5.
ProgramtheSIFregisters.
6.
Programconfig1,bit="0"andconfig16,bit="11".
7.
Programfuse_sleep(config27,Bit)toputinternalfusestosleep.
8.
FIFOconfigurationneededforsynchronization:(a)Programsyncsel_fifoin(3:0)(config32,bit)toselecttheFIFOinputpointersyncsource.
(b)Programsyncsel_fifoout(3:0)(config32,bit)toselecttheFIFOoutputpointersyncsource.
(c)Programsyncsel_dataformatter(1:0)(config31,bit)toselecttheFIFODataFormattersyncsource.
9.
Clockdividerconfigurationneededforsynchronization:(a)Programclkdiv_sync_sel(config32,bit)toselecttheclockdividersyncsource.
(b)Programclkdiv_sync_ena(config0,bit)to"1"toenableclockdividersync.
(c)Formulti-DACsynchronizationinPLLmode,programpll_ndivsync_ena(config24,bit)to"1"tosynchronizethePLLN-divider.
10.
ProvideallLVDSinputs(D[15:0]P/N,DATACLKP/N,FRAMEP/N,SYNCP/NandPARITYP/N)simultaneously.
SynchronizetheFIFOandclockdividerbyprovidingthepulseorperiodicsignalsneeded.
(a)ForSingleSyncSourceModewhereeitherFRAMEP/NorSYNCP/NisusedtosynctheFIFO,asinglerisingedgeforFIFO,FIFOdataformatter,andclockdividersyncisrecommended.
PeriodicsyncsignalCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback73ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comisnotrecommendedduetothenon-deterministiclatencyofthesyncsignalthroughtheclockdomaintransfer.
(b)ForDualSyncSourcesMode,bothsinglepulseorperiodicsyncsignalscanbeused.
(c)Formulti-DACsynchronizationinPLLmode,theLVDSSYNCP/NsignalisusedtosyncthePLLN-dividerandcanbesourcedfromeithertheFPGA/ASICpatterngeneratororclockdistributioncircuitaslongasthet(SYNC_PLL)setupandholdtimingrequirementismetwithrespecttothereferenceclocksourceatDACCLKP/Npins.
TheLVDSSYNCP/Nsignalcanbeprovidedatthispoint.
11.
FIFOandclockdividerconfigurationsafterallthesyncsignalshaveprovidedtheinitialsyncpulsesneededforsynchronization:(a)ForSingleSyncSourceModewheretheclockdividersyncsourceiseitherFRAMEP/NorSYNCP/N,clockdividersyncingmaybedisabledafterDAC3482initializationandbeforethedatatransmissionbysettingclkdiv_sync_ena(config0,bit2)to"0".
ThisistopreventaccidentalsyncingoftheclockdividerorwhensendingFRAMEP/NorSYNCP/Npulsetootherdigitalblocks.
(b)ForDualSyncSourcesMode,wheretheclockdividersyncsourceisfromtheOSTRsignal(eitherfromexternalOSTRP/NorinternalPLLNdivideroutput),theclockdividersyncingmaybeenabledatalltime.
(c)Optionally,topreventaccidentalsyncingoftheFIFOandFIFOdataformatterwhensendingtheFRAMEP/NorSYNCP/NpulsetootherdigitalblockssuchasNCO,QMC,etc,disableFIFOsyncingbysettingsyncsel_fifoin(3:0)andsyncsel_fifoout(3:0)to"0000"aftertheFIFOinputandoutputpointersareinitialized.
AlsoDisabletheFIFOdataformatterbysettingsyncsel_dataformatter(1:0)to"10"or"11".
IftheFIFOandFIFOdataformattersyncremainenabledafterinitialization,theFRAMEP/NorSYNCP/NpulsemustoccurinwaystonotdisturbtheFIFOoperation.
RefertotheINPUTFIFOsectionfordetail.
(d)DisablePLLN-dividersyncingbysettingpll_ndivsync_ena(config24,bit)to"0".
12.
EnabletransmitofdatabyassertingtheTXENABLEpinorsetsif_txenableto"1".
13.
Atanytime,ifanyoftheclocks(i.
eDATACLKorDACCLK)islostoraFIFOcollisionalarmisdetected,acompleteresynchronizationoftheDACisnecessary.
SetTXENABLElowandrepeatsteps8through12.
ProgramtheFIFOconfigurationandclockdividerconfigurationpersteps8and9appropriatelytoacceptthenewsyncpulseorpulsesforthesynchronization.
EXAMPLESTART-UPROUTINEDEVICECONFIGURATIONfDATA=491.
52MSPS,16-bitwordwideinterfaceInterpolation=2xInputdata=basebanddatafOUT=122.
88MHzPLL=EnabledFullMixer=EnabledDualSyncSourcesModePLLCONFIGURATIONfREFCLK=491.
52MHzattheDACCLKP/NLVPECLpinsfDACCLK=fDATAxInterpolation=983.
04MHzfVCO=4xfDACCLK=3932.
16MHz(keepfVCObetween3.
3GHzto4GHz)PFD=fOSTR=30.
72MHzN=16,M=32,P=3,singlechargepumppll_vco(5:0)="100100"(36)74SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013NCOCONFIGURATIONfNCO=122.
88MHzfNCO_CLK=983.
04MHzfreq=fNCOx2^32/983.
04=536870912=0x20000000phaseaddAB(31:0)orphaseaddCD(31:0)=0x20000000NCOSYNC=risingedgeofSYNCEXAMPLESTART-UPSEQUENCETable10.
ExampleStart-UpSequenceDescriptionSTEPREAD/WRITEADDRESSVALUEDESCRIPTION1N/AN/AN/ASetTXENABLELow2N/AN/AN/APower-upthedevice3N/AN/AN/AApplyLVPECLDACCLKP/NforPLLreferenceclock4N/AN/AN/AToggleRESETBpinQMCoffsetandcorrectionenabled,2xint,FIFOenabled,Alarmenabled,5Write0x000xA19Eclockdividersyncenabled,inversesincfilterenabled.
Singleparityenabled,FIFOalarmsenabled(2away,1away,andcollision).
6Write0x010x040ENote:bit8='0'Outputshut-offwhenDACCLKgone,DATACLKgone,andFIFOcollision.
7Write0x020xF052MixerblockwithNCOenabled,twoscomplement.
Wordwideinterface.
Outputcurrentsetto20mAFSwithinternalreferenceand1.
28kohmRBIAS8Write0x030xA000resistor.
Un-maskFIFOcollision,DACCLK-gone,andDATACLK-gonealarmstothe9Write0x070xD8FFAlarmoutput.
ProgramthedesiredchannelIQMCoffsetvalue.
(CausesAuto-Syncfor10Write0x08N/AQMCOffsetBlock)11Write0x09N/AProgramthedesiredFIFOoffsetvalueandchannelQQMCoffsetvalue.
12Write0x0CN/AProgramthedesiredchannelIQMCgainvalue.
Coarsemixermodenotused.
ProgramthedesiredchannelQQMCgain13Write0x0DN/Avalue.
ProgramthedesiredchannelIQQMCphasevalue.
(CausesAuto-Sync14Write0x10N/AQMCCorrectionBlock)Note:bit13andbit12='1'ProgramthedesiredchannelIQNCOphaseoffsetvalue.
(CausesAuto-15Write0x12N/ASyncforChannelIQNCOMixer)16Write0x140x2000ProgramthedesiredchannelIQNCOfrequencyvalue17Write0x150x0000ProgramthedesiredchannelIQNCOfrequencyvaluePLLenabled,PLLN-dividerssyncenabled,singlechargepump,prescaler=18Write0x180x2C674.
19Write0x190x20F4M=32,N=16,PLLVCObiastune="01"20Write0x1A0xEC00PLLVCOcoarsetune=5921Write0x1B0x0800InternalreferenceQMCoffsetIQandQMCcorrectionIQcanbesyncedbysif_syncorauto-22Write0x1E0x9191syncfromregisterwriteMixerIQvaluessyncedbySYNCP/N.
NCOaccumulatorsyncedby23Write0x1F0x4140SYNCP/N.
FIFOdataformattersyncedbyFRAMEP/N.
FIFOInputPointerSyncSource=FRAME24Write0x200x2400FIFOOutputPointerSyncSource=OSTR(fromPLLN-divideroutput)ClockDividerSyncSource=OSTRProvidealltheLVDSDATAandDATACLK25N/AN/AN/AProviderisingedgeFRAMEP/NandrisingedgeSYNCP/NtosynctheFIFOinputpointerandPLLN-dividers.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback75ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTable10.
ExampleStart-UpSequenceDescription(continued)STEPREAD/WRITEADDRESSVALUEDESCRIPTIONReadbackpll_lfvolt(2:0).
Ifthevalueisnotoptimal,adjustpll_vco(5:0)in26Read0x18N/A0x1A.
27Write0x050x0000Clearallalarmsin0x05.
Readbackallalarmsin0x05.
CheckforPLLlock,FIFOcollision,DACCLK-28Read0x05N/Agone,DATACLK-gone,etc.
Fixtheerrorappropriately.
Repeatstep26and27asnecessary.
SyncalltheQMCblocksusingsif_sync.
Theseblockscanalsobesynced29Write0x1F0x4142viaauto-syncthroughappropriateregisterwrites.
30Write0x000xA19ADisableclockdividersync.
DisableFIFOdataformattersync.
Setsif_syncto"0"forthenextsif_sync31Write0x1F0x4148event.
32Write0x200x0000DisableFIFOinputandoutputpointersync.
33Write0x180x2467DisablePLLN-dividerssync.
34N/AN/AN/ASetTXENABLEhigh.
Enabledatatransmission.
LVPECLINPUTSFigure84showsanequivalentcircuitfortheDACinputclock(DACCLKP/N)andtheoutputstrobeclock(OSTRP/N).
Figure84.
DACCLKP/NandOSTRP/NEquivalentInputCircuitFigure85showsthepreferredconfigurationfordrivingtheCLKIN/CLKINCinputclockwithadifferentialECL/PECLsource.
76SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013Figure85.
PreferredClockInputConfigurationwithaDifferentialECL/PECLClockSourceLVDSINPUTSTheD[15:0]P/N,DATACLKP/N,SYNCP/N,PARITYP/NandFRAMEP/NLVDSpairshavetheinputconfigurationshowninFigure86.
Figure87showsthetypicalinputlevelsandcommon-movevoltageusedtodrivetheseinputs.
Figure86.
D[15:0]P/N,DATACLKP/N,FRAMEP/N,SYNCP/NandPARITYP/NLVDSInputConfigurationFigure87.
LVDSDataInputLevelsCopyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback77ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comTable11.
ExampleLVDSDataInputLevelsResultingDifferentialResultingCommon-ModeAppliedVoltagesLogicalBitBinaryVoltageVoltageEquivalentVAVBVA,BVCOM1.
4V1.
0V400mV1.
2V11.
0V1.
4V-400mV01.
2V0.
8V400mV1.
0V10.
8V1.
2V-400mV0CMOSDIGITALINPUTSFigure88showsaschematicoftheequivalentCMOSdigitalinputsoftheDAC3482.
SDIO,SCLK,SLEEPandTXENABLEhavepull-downresistorswhileSDENBandRESETBhavepull-upresistorsinternaltotheDAC3482.
Seethespecificationtableforlogicthresholds.
Thepull-upandpull-downcircuitryisapproximatelyequivalentto100k.
Figure88.
CMOSDigitalEquivalentInputREFERENCEOPERATIONTheDAC3482usesabandgapreferenceandcontrolamplifierforbiasingthefull-scaleoutputcurrent.
Thefull-scaleoutputcurrentissetbyapplyinganexternalresistorRBIAStopinBIASJ.
ThebiascurrentIBIASthroughresistorRBIASisdefinedbytheon-chipbandgapreferencevoltageandcontrolamplifier.
Thedefaultfull-scaleoutputcurrentequals64timesthisbiascurrentandcanthusbeexpressedas:IOUTFS=64xIBIAS=64x(VEXTIO/RBIAS)/2TheDAC3482hasa4-bitcoarsegaincontrolcoarse_dac(3:0)intheconfig3register.
Usinggaincontrol,theIOUTFScanbeexpressedas:IOUTFS=(coarse_dac+1)/16xIBIASx64=(coarse_dac+1)/16x(VEXTIO/RBIAS)/2x64whereVEXTIOisthevoltageatterminalEXTIO.
Thebandgapreferencevoltagedeliversanaccuratevoltageof1.
2V.
Thisreferenceisactivewhenextref_ena='0'inconfig27.
AnexternaldecouplingcapacitorCEXTof0.
1FshouldbeconnectedexternallytoterminalEXTIOforcompensation.
Thebandgapreferencecanadditionallybeusedforexternalreferenceoperation.
Inthatcase,anexternalbufferwithhighimpedanceinputshouldbeappliedinordertolimitthebandgaploadcurrenttoamaximumof100nA.
Theinternalreferencecanbedisabledandoverriddenbyanexternalreferencebysettingtheextref_enacontrolbit.
CapacitorCEXTmayhencebeomitted.
TerminalEXTIOthusservesaseitherinputoroutputnode.
Thefull-scaleoutputcurrentcanbeadjustedfrom30mAdownto10mAbyvaryingresistorRBIAS,programmingcoarse_dac(3:0),orchangingtheexternallyappliedreferencevoltage.
78SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013NOTEWithinternalreference,theminimumRbiasresistorvalueis1.
28kΩ.
Resistorvaluebelow1.
28kΩisnotrecommendedsinceitwillprogramthefull-scalecurrenttogoabove30mAandpotentiallydamagesthedevice.
DACTRANSFERFUNCTIONTheCMOSDAC'sconsistofasegmentedarrayofPMOScurrentsources,capableofsourcingafull-scaleoutputcurrentupto30mA.
DifferentialcurrentswitchesdirectthecurrenttoeitheroneofthecomplementaryoutputnodesIOUTPorIOUTN.
Complementaryoutputcurrentsenabledifferentialoperation,thuscancelingoutcommonmodenoisesources(digitalfeed-through,on-chipandPCBnoise),dcoffsets,evenorderdistortioncomponents,andincreasingsignaloutputpowerbyafactoroftwo.
Thefull-scaleoutputcurrentissetusingexternalresistorRBIASincombinationwithanon-chipbandgapvoltagereferencesource(+1.
2V)andcontrolamplifier.
CurrentIBIASthroughresistorRBIASismirroredinternallytoprovideamaximumfull-scaleoutputcurrentequalto64timesIBIAS.
TherelationbetweenIOUTPandIOUTNcanbeexpressedas:IOUTFS=IOUTP+IOUTNWewilldenotecurrentflowingintoanodeas–currentandcurrentflowingoutofanodeas+current.
SincetheoutputstageisacurrentsourcethecurrentflowsfromtheIOUTPandIOUTNpins.
Theoutputcurrentflowineachpindrivingaresistiveloadcanbeexpressedas:IOUTP=IOUTFSxCODE/65536IOUTN=IOUTFSx(65535–CODE)/65536whereCODEisthedecimalrepresentationoftheDACdatainputwordForthecasewhereIOUTPandIOUTNdriveresistorloadsRLdirectly,thistranslatesintosingleendedvoltagesatIOUTPandIOUTN:VOUTP=IOUT1xRLVOUTN=IOUT2xRLAssumingthatthedataisfullscale(65535inoffsetbinarynotation)andtheRLis25Ω,thedifferentialvoltagebetweenpinsIOUTPandIOUTNcanbeexpressedas:VOUTP=20mAx25Ω=0.
5VVOUTN=0mAx25Ω=0VVDIFF=VOUTP–VOUTN=0.
5VNotethatcareshouldbetakennottoexceedthecompliancevoltagesatnodeIOUTPandIOUTN,whichwouldleadtoincreasedsignaldistortion.
ANALOGCURRENTOUTPUTSTheDAC3482canbeeasilyconfiguredtodriveadoublyterminated50ΩcableusingaproperlyselectedRFtransformer.
Figure89andFigure90showthe50Ωdoublyterminatedtransformerconfigurationwith1:1and4:1impedanceratio,respectively.
NotethatthecentertapoftheprimaryinputofthetransformerhastobegroundedtoenableaDCcurrentflow.
Applyinga20mAfull-scaleoutputcurrentwouldleadtoa0.
5Vppfora1:1transformeranda1Vppoutputfora4:1transformer.
Thelowdc-impedancebetweenIOUTPorIOUTNandthetransformercentertapsetsthecenteroftheac-signaltoGND,sothe1Vppoutputforthe4:1transformerresultsinanoutputbetween–0.
5Vand+0.
5V.
Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback79ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comFigure89.
DrivingaDoublyTerminated50ΩCableUsinga1:1ImpedanceRatioTransformerFigure90.
DrivingaDoublyTerminated50ΩCableUsinga4:1ImpedanceRatioTransformer80SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482DAC3482www.
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comSLAS748E–MARCH2011–REVISEDJULY2013REVISIONHISTORYChangesfromOriginal(March2011)toRevisionAPageChangedfromPRODUCTPREVIEWtoPRODUCTIONDATA1ChangesfromRevisionA(March2011)toRevisionBPageChangedALARMdescription3AddednotestoELECTRICALCHARACTERISTICS–DCSPECIFICATIONS11DeletedTYPandMAXvaluesfromVA,B+13ChangedVCOMMINvaluefrom1.
075Vto1.
0V13AddedMINandMAXvaluesforZT13AddedfDACPLLONMINof1000MSPSinELECTRICALCHARACTERISTICS–ACSPECIFICATIONS16Changedconfig5defaultvaluefrom0x0000toNAinRegisterMap30Changedregisterversiondefaultvaluefrom0x5409to0x540CinRegisterMap31AddedSIFSYNCtoregisterconfig32description43Changedregisterconfig35description44Changedregisterconfig36descriptionfrom40psto50ps44Changedregisterversiondefaultvaluefrom0x5409to0x540C46AddedinformationtoSINGLESYNCSOURCEMODEsectiontoclarifythelatencylimitationofSingleSyncSourceMode52Changed1.
2288GHzto983.
04MHzinPLLMODEdescription56ChangeddatainTable556Deleted2xinTable763Changedconfig32toconfig31inPOWER-UPSEQUENCEdescription73ChangedEXAMPLESTART-UPROUTINEinformation74ChangedTable1075ChangesfromRevisionB(September2011)toRevisionCPageChangedPackageoptionsinFEATURES1AddedZAYpackage6AddedZAYpinfunctions7AddedZAYpackagetoORDERINGINFORMATIONsection9AddedZAYpackagetoTHERMALINFORMATIONsection10AddedInputCommonModemaxvalueof1.
6V13AddedinformationtoCLOCKINPUT(DACCLKP/N)inELECTRICALCHARACTERISTICS–DIGITALSPECIFICATIONS13AddedinformationtoOUTPUTSTROBE(OSTRP/N)inELECTRICALCHARACTERISTICS–DIGITALSPECIFICATIONS13ChangedELECTRICALCHARACTERISTICS–ACSPECIFICATIONSACPERFORMANCEinformation16ChangedFigure2120ChangedFigure2221ChangedFigure2321ChangedFigure2421AddedFigure4825AddedFigure4925Changedconfig3toconfig9inINPUTFIFOsection49Copyright2011–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback81ProductFolderLinks:DAC3482DAC3482SLAS748E–MARCH2011–REVISEDJULY2013www.
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comAddedinformationfordouble-charge-pumpcurrenttoPLLMODEsection56ChangedFigure7665Changed+3.
75to–3.
75degreesin1024stepsto+26.
5to–26.
5degreesin4096stepsinGAINANDPHASECORRECTIONsection67ChangesfromRevisionC(June2012)toRevisionDPageAddedthermalinformationtotheAbsoluteMaximumRatingstable9DeletedTJrowfromtopofthermaltable10AddedRecommendedOperatingConditionstable10DeletedOPERATINGRANGEsectionfrombottomofElectricalCharacteristics–DCSpecificationstable11ChangesfromRevisionD(August2012)toRevisionEPageChangedPowerSupplySpecificationTableunderElectricalSpecification.
Thisspecificationdependsontheenhancedproductiontestcoverageandisspecifictodeviceswithcertaindatecode.
RefertoClarificationsforDAC3482PowerSupplyandPhase-LockedLoopSpecificationSectionfordetails12DeletedNote(5)inPowerConsumptionSpecificationtoreflectthelatestDAC3482speedspecification.
12ChangedDACCLKP/NtypicalclockswingspecificationtoreflectcommonlyusedLVPECLdriver13ChangedDACCLKP/NtypicalclockswingspecificationtoreflectcommonlyusedLVPECLdriver13ChangedDACCLKdriverrequirementtoreflectactualdeviceperformanceundercommonlyusedLVPECLdrivers.
.
.
.
.
.
13ChangedAnalogOutputSpecificationTableunderElectricalSpecification.
Thisspecificationdependsontheenhancedproductiontestcoverageandisspecifictodeviceswithcertaindatecode.
RefertoClarificationsforDAC3482PowerSupplyandPhase-LockedLoopSpecificationSectionfordetails16ChangedDigitalLatencySpecificationforQMCtoreflecttheactualDAC3482parameter16ChangedDigitalLatencySpecificationforInverseSinctoreflecttheactualDAC3482parameter16AddedPhase-LockedLoopSpecificationTableunderElectricalSpecification.
Thisspecificationdependsontheenhancedproductiontestcoverageandisspecifictodeviceswithcertaindatecode.
RefertoClarificationsforDAC3482PowerSupplyandPhase-LockedLoopSpecificationSectionfordetails17Changedpll_vco(6:0)topll_vco(5:0)toreflectactualbitwidthintheregister40Changedconfig45,bit12:1defaultvaluetoreflecttheactualdefaultregistervalue45Changedconfig45,bit0descriptiontoclarifyadditionalDAC3482behavior45Changedsyncsel_fifoout(3:0)descriptiontoclarifytheFIFOreadpointerresetcapturemethodandlimitation50ChangedinformationtoSINGLESYNCSOURCEMODEsectiontoclarifythelatencylimitationofSingleSyncSourceMode52Added"theeffectofbypassingtheFIFO"intheBypassModesectiontoclarifytheoperationofFIFO,LVDSFRAME,andLVDSSYNCinFIFOBypassMode53ChangedPLLModesectionwithadditionaloperatingrecommendationsfortheDAC3482on-chipPLL55ChangedinformationtoMULTI-DEVICEOPERATION:SINGLESYNCSOURCEMODEsectiontoclarifythelatencylimitationofSingleSyncSourceMode59ChangedFigure64toclarifythelatencylimitationofSingleSyncSourceMode60ChangedDataPatternCheckersectionwithadditionaloperatingrecommendations69AddedadditionalrequirementsforBlockParitysectionwhenbytewideinputdatamodeisselected72ChangedtheNCOsettingdescriptionintheExampleStart-upSequenceSectiontoreflecttheexampleregisterwrites7582SubmitDocumentationFeedbackCopyright2011–2013,TexasInstrumentsIncorporatedProductFolderLinks:DAC3482PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDAC3482IRKDRACTIVEWQFN-MRRKD882000RoHS&GreenNIPDAULevel-3-260C-168HR-40to85DAC3482IDAC3482IRKDTACTIVEWQFN-MRRKD88250RoHS&GreenNIPDAULevel-3-260C-168HR-40to85DAC3482IDAC3482IZAYACTIVENFBGAZAY196160RoHS&GreenSNAGCULevel-3-260C-168HR-40to85DAC3482IDAC3482IZAYRACTIVENFBGAZAY1961000RoHS&GreenSNAGCULevel-3-260C-168HR-40to85DAC3482I(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709BlowhalogenrequirementsofcombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandPACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page2continuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDAC3482IRKDRWQFN-MRRKD882000330.
016.
49.
39.
31.
512.
016.
0Q2DAC3482IRKDTWQFN-MRRKD88250330.
016.
49.
39.
31.
512.
016.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com9-Aug-2017PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DAC3482IRKDRWQFN-MRRKD882000336.
6336.
628.
6DAC3482IRKDTWQFN-MRRKD88250367.
0367.
038.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com9-Aug-2017PackMaterials-Page2www.
ti.
comPACKAGEOUTLINEC1.
4MAXTYP0.
450.
3510.
4TYP10.
4TYP0.
8TYP0.
8TYP196X0.
550.
45A12.
111.
9B12.
111.
9(0.
8)TYP(0.
8)TYPNFBGA-1.
4mmmaxheightZAY0196APLASTICBALLGRIDARRAY4219823/A09/2015NOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
BALLA1CORNERSEATINGPLANEBALLTYP0.
12C0.
15CAB0.
05CSYMMSYMMBALLA1CORNERPCDEFGHJKLMN1234567891011AB121314SCALE1.
100www.
ti.
comEXAMPLEBOARDLAYOUT196X()0.
4(0.
8)TYP(0.
8)TYP()METAL0.
40.
05MAXSOLDERMASKOPENINGMETALUNDERSOLDERMASK()SOLDERMASKOPENING0.
40.
05MINNFBGA-1.
4mmmaxheightZAY0196APLASTICBALLGRIDARRAY4219823/A09/2015NOTES:(continued)3.
Finaldimensionsmayvaryduetomanufacturingtoleranceconsiderationsandalsoroutingconstraints.
Forinformation,seeTexasInstrumentsliteraturenumberSPRAA99(www.
ti.
com/lit/spraa99).
SYMMSYMMLANDPATTERNEXAMPLESCALE:8X1234567891011BACDEFGHJKLMNP121314NON-SOLDERMASKDEFINED(PREFERRED)SOLDERMASKDETAILSNOTTOSCALESOLDERMASKDEFINEDwww.
ti.
comEXAMPLESTENCILDESIGN(0.
8)TYP(0.
8)TYP()TYP0.
4NFBGA-1.
4mmmaxheightZAY0196APLASTICBALLGRIDARRAY4219823/A09/2015NOTES:(continued)4.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
SOLDERPASTEEXAMPLEBASEDON0.
15mmTHICKSTENCILSCALE:8XSYMMSYMM1234567891011BACDEFGHJKLMNP121314IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
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