IOZ11kk99

DS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013DS99R124Q5-43MHz18-bitColorFPD-LinkIItoFPD-LinkConverterCheckforSamples:DS99R124Q1FEATURESDESCRIPTIONTheDS99R124QconvertsFPD-LinkIItoFPD-Link.
It25–43MHzSupport(140Mbpsto1.
2Gbpstranslatesahigh-speedserializedinterfacewithanSerialLink)embeddedclockoverasinglepair(FPD-LinkII)to4-Channel(3data+1Clock)FPD-LinkLVDSthreeLVDSdata/controlstreamsandoneLVDSclockOutputspair(FPD-Link).
Thisserialbusschemegreatlyeasessystemdesignbyeliminatingskewproblemsbetween3Low-SpeedOver-SampledLVCMOSOutputsclockanddata,reducesthenumberofconnectorACCoupledSTPInterconnectupto10Meterspins,reducestheinterconnectsize,weight,andcost,inLengthandoveralleasesPCBlayout.
Inaddition,internalIntegratedInputTerminationDCbalanceddecodingisusedtosupportAC-coupledinterconnects.
@SpeedLinkBISTModeandReportingPinOptionalI2CCompatibleSerialControlBusTheDS99R124Qconverterrecoversthedata(RGB)andcontrolsignalsandextractstheclockfromaRGB666+VS,HS,DEConvertedfrom1Pairserialstream(FPD-LinkII).
ItisabletolocktothePowerDownModeMinimizesPowerincomingdatastreamwithouttheuseofatrainingDissipationsequenceorspecialSYNCpatternsanddoesnotFASTRandomDataLock;noReferenceClockrequireareferenceclock.
Alinkstatus(LOCK)outputRequiredsignalisprovided.
AdjustableInputReceiveEqualizationAdjustableinputequalizationoftheserialinputstreamprovidescompensationfortransmissionLOCK(RealTimeLinkStatus)ReportingPinmediumlossesofthecableandreducesthemedium-LowEMIFPD-LinkOutputinduceddeterministicjitter.
EMIisminimizedbytheSSCGOptionforLowerEMIuseoflowvoltagedifferentialsignaling,outputstate1.
8Vor3.
3VCompatibleI/OInterfaceselectfeature,andadditionaloutputspreadspectrumgeneration.
AutomotiveGradeProduct:AEC-Q100Grade2QualifiedWithfewerwirestothephysicalinterfaceofthedisplay,FPD-LinkoutputwithLVDStechnologyis>8kVHBMandISO10605ESDRatingidealforhighspeed,lowpowerandlowEMIdatatransfer.
APPLICATIONSTheDS99R124Qisofferedina48-pinWQFNAutomotiveDisplayforNavigationpackageandisspecifiedovertheautomotiveAEC-AutomotiveDisplayforEntertainmentQ100Grade2temperaturerangeof-40Cto+105C.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2010–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
DS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comApplicationsDiagramFigure1.
DS99R124QPinDiagramFigure2.
FPD-LinkIItoFPD-LinkConvertor-DS99R124Q48PinWQFNPackageSeePackageNumberRHS0048A2SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013PINDESCRIPTIONSPinNamePin#I/O,TypeDescriptionFPD-LinkIIInputInterfaceRIN+40I,LVDSTrueinputTheinputmustbeACcoupledwitha100nFcapacitor.
Internaltermination.
RIN-41I,LVDSInvertinginputTheinputmustbeACcoupledwitha100nFcapacitor.
Internaltermination.
CMF42I,AnalogCommon-ModeFilterVCMcenter-tapisavirtualgroundwhichmaybeac-coupledtogroundtoincreasereceivercommonmodenoiseimmunity.
Recommendedvalueis4.
7μForhigher.
FPD-LinkOutputInterfaceTxOUT[2:0]+19,21,23O,LVDSTrueLVDSDataOutputThispairshouldhavea100terminationforstandardLVDSlevels.
TxOUT[2:0]-20,22,24O,LVDSInvertingLVDSDataOutputThispairshouldhavea100terminationforstandardLVDSlevels.
TxCLKOUT+17O,LVDSTrueLVDSClockOutputThispairshouldhavea100terminationforstandardLVDSlevels.
TxCLKOUT-18O,LVDSInvertingLVDSClockOutputThispairshouldhavea100terminationforstandardLVDSlevels.
LVCMOSOutputsOS[2:0]10,11,12O,LVMOSOver-SampledLowFrequencyOutputsThesebitsmaptotheDS99R421'sOS[2:0]over-sampledlow-frequencyinputs.
SignalsmustbeslowertheTxCLK/5.
OntheDS90UR241thesemaptotheDIN[23:21]inputs.
OS0=DIN21,OS1=DIN22,OS2=DIN23.
LOCK27O,LVMOSLOCKStatusOutputLOCK=1,PLLislocked,outputsareactive.
LOCK=0,PLLisunlocked,outputstatesdeterminedbyOSS_SEL.
MaybeusedasaLinkStatusortoflagwhentheVideoDataisactive(ON/OFF).
ControlandConfigurationPDB1I,LVCMOSPowerDownModeInputw/pull-downPDB=1,Deviceisenabled(normaloperation)PDB=0,Deviceisinpower-down,theoutputarecontrolledbythesettings.
ControlregistersareRESET.
VODSEL33I,LVCMOSDifferentialDriverOutputVoltageSelectw/pull-downVODSEL=1,LVDSVODis±400mV,800mVp-p(typ)—LongCable/De-EApplicationsVODSEL=0,LVDSVODis±250mV,500mVp-p(typ)SeeTable2OEN34I,LVCMOSOutputEnableInputw/pull-downOEN=1,FPD-Linkoutputsareenabled(active).
OEN=0,FPD-LinkoutputsareTRI-STATE.
OSS_SEL35I,LVCMOSOutputSleepStateSelectInputw/pull-downSeeTable1LFMODE36I,LVCMOSLowFrequencyMode—PinorRegisterControlw/pull-downLF_MODE=1,lowfrequencymode(TxCLKOUT=5-20MHz)LF_MODE=0,highfrequencymode(TxCLKOUT=20-43MHz)SSC[2:0]7,2,3I,LVCMOSSpreadSpectrumClockGeneration(SSCG)RangeSelectw/pull-downSeeTable3andTable4RES[1:0]37,15I,LVCMOSReservedw/pull-downTieLowControlandConfiguration—STRAPPINForaHighState,usea10kpulluptoVDDIO;foraLowState,theIOincludesaninternalpulldown.
TheSTRAPpinisreaduponpower-upandsetdeviceconfiguration.
PinnumberlistedalongwithsharedLVCMOSOutputnameinsquarebracket.
EQ28[PASS]STRAPEQGainControlofFPD-LinkIIInputI,LVCMOSEQ=1,EQgainisenabled(~13dB)w/pull-downEQ=0,EQgainisdisabled(~1.
625dB)OptionalBISTModeBISTEN29I,LVCMOSBISTEnableInput–Optionalw/pull-downBISTEN=1,BISTModeisenabled.
BISTEN=0,normalmode.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comPINDESCRIPTIONS(continued)PinNamePin#I/O,TypeDescriptionBISTM30I,LVCMOSBISTModeInput–Optionalw/pull-downBISTM=1,selectsPayloadErrorModeBISTM=0,selectsPass/FailResult-OnlyModePASS28O,LVCMOSPASSOutput(BISTMode)–OptionalPASS=1,noerrorsdetectedPASS=0,errorsdetectedLeaveopenifunused.
Routetoatestpoint(pad)recommended.
OptionalSerialBusControlInterfaceSCL5I,LVCMOSSerialControlBusClockInput-OptionalSCLrequiresanexternalpull-upresistortoVDDIO.
SDA4I/O,LVCMOSSerialControlBusDataInput/Output-OptionalOpenDrainSDArequiresanexternalpull-upresistortoVDDIO.
ID[x]16I,AnalogSerialControlBusDeviceIDAddressSelect—OptionalResistortoGroundand10kpull-upto1.
8Vrail.
SeeTable5.
PowerandGroundVDDL6,31PowerLogicPower,1.
8V±5%VDDA38,43PowerAnalogPower,1.
8V±5%VDDP8,46,47PowerSSCGeneratorPower,1.
8V±5%VDDTX13PowerFPD-LinkPower,3.
3V±10%VDDIO25PowerLVCMOSI/OPower,1.
8V±5%OR3.
3V±10%GND9,14,26,GroundGround32,39,44,45,48DAPDAPGroundDAPisthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFNpackage.
Connectedtothegroundplane(GND)withatleast9vias.
BlockDiagramFigure3.
FPD-LinkIItoFPD-LinkConvertorThesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
4SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013AbsoluteMaximumRatings(1)(2)SupplyVoltage–VDDn(1.
8V)0.
3Vto+2.
5VSupplyVoltage–VDDTX(3.
3V)0.
3Vto+4.
0VSupplyVoltage–VDDIO0.
3Vto+4.
0VLVCMOSI/OVoltage0.
3Vto+(VDDIO+0.
3V)ReceiverInputVoltage0.
3Vto(VDD+0.
3V)LVDSOutputVoltage0.
3Vto(VDDTX+0.
3V)JunctionTemperature+150°CStorageTemperature65°Cto+150°CLeadTemperature(Soldering,4s)+260°C48LRHSPackageMaximumPowerDissipationCapacityatDerateabove25°C1/θJA°C/W25°CθJA27.
7°C/WθJC3.
0°C/WESDRating(IEC,powered-uponly),RD=AirDischarge(RIN+,RIN)≥±30kV330Ω,CS=150pFContactDischarge(RIN+,RIN)≥±6kVESDRating(ISO10605),RD=330Ω,CS=AirDischarge(RIN+,RIN)≥±15kV150&330pFContactDischarge(RIN+,RIN)≥±8kVESDRating(ISO10605),RD=2kΩ,CS=150AirDischarge(RIN+,RIN)≥±15kV&330pFContactDischarge(RIN+,RIN)≥±8kVESDRating(HBM)≥±8kVESDRating(CDM)≥±1.
25kVESDRating(MM)≥±250V(1)"AbsoluteMaximumRatings"indicatelimitsbeyondwhichdamagetothedevicemayoccur,includinginoperabilityanddegradationofdevicereliabilityand/orperformance.
Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximumRatingsorotherconditionsbeyondthoseindicatedintheRecommendedOperatingConditionsisnotimplied.
TheRecommendedOperatingConditionsindicateconditionsatwhichthedeviceisfunctionalandthedeviceshouldnotbeoperatedbeyondsuchconditions.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
RecommendedOperatingConditionsMinNomMaxUnitsSupplyVoltage(VDDn)1.
711.
81.
89VLVCMOSSupplyVoltage(VDDIO)1.
711.
81.
89VLVCMOSSupplyVoltage(VDDIO)3.
03.
33.
6VOperatingFreeAirTemperature(TA)40+25+105°CTxCLKClockFrequency543MHzSupplyNoise(1)100mVP-P(1)SupplynoisetestingwasdonewithminimumcapacitorsonthePCB.
AsinusoidalsignalisACcoupledtotheVDDn(1.
8V)supplywithamplitude=100mVp-pmeasuredatthedeviceVDDnpins.
BiterrorratetestingofinputtotheSerandoutputoftheDeswith10metercableshowsnoerrorwhenthenoisefrequencyontheSerislessthan750kHz.
TheDesontheotherhandshowsnoerrorwhenthenoisefrequencyislessthan400kHz.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comDCElectricalCharacteristicsOverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
(1)(2)(3)SymbolParameterConditionsPin/Freq.
MinTypMaxUnitsFPD-LinkLVDSOutputVODSEL=L100250400mVDifferential|VOD|OutputVoltageVODSEL=H200400600mVDifferentialVODSEL=L500mVp-pVODp-pOutputVoltageVODSEL=H800mVp-pA-BTxCLKOUT+,OutputVoltageRL=100ΔVOD150mVTxCLKOUT-,UnbalanceTxOUT[2:0]+,VODSEL=L1.
01.
21.
5VTxOUT[2:0]-VOSOffsetVoltageVODSEL=H1.
2VOffsetVoltageΔVOS150mVUnbalanceOutputShortIOSVout=GND-5mACircuitCurrentOutputTRI-OEN=GND,IOZSTATE-10+10AVout=VDDTX,orGNDCurrent3.
3VI/OLVCMOSDCSPECIFICATIONS–VDDIO=3.
0to3.
6VHighLevelPDB,VIH2.
2VDDIOVInputVoltageVODSEL,OEN,LowLevelVILGND0.
8VOSS_SEL,InputVoltageLFMODE,SSC[2:0],IINInputCurrentVIN=0VorVDDIO15±1+15μABISTEN,BISTMHighLevelVOHIOH=0.
5mAVDDIO-0.
2VDDIOVOutputVoltageLowLevelVOLIOL=+0.
5mAGND0.
2VOutputVoltageLOCK,PASS,OS[2:0]OutputShortIOSVOUT=0V-10mACircuitCurrentTRI-STATEPDB=0V,OSS_SEL=0V,IOZ10+10AOutputCurrentVOUT=0VorVDDIO1.
8VI/OLVCMOSDCSPECIFICATIONS–VDDIO=1.
71to1.
89VHighLevelPDB,0.
7VIHVDDIOVInputVoltageVODSEL,VDDIOOEN,LowLevel0.
35*VILGNDVOSS_SEL,InputVoltageVDDIOLFMODE,SSC[2:0],IINInputCurrentVIN=0VorVDDIO10±1+10μABISTEN,BISTM(1)TheElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommendedOperatingConditionsexceptasotherwisemodifiedorspecifiedbytheElectricalCharacteristicsConditionsand/orNotes.
Typicalspecificationsareestimationsonlyandarenotensured.
(2)TypicalvaluesrepresentmostlikelyparametricnormsatVDDn=1.
8V,VDDTX=3.
3V,VDDIO=1.
8Vor3.
3V,Ta=+25°C,andattheRecommendedOperationConditionsatthetimeofproductcharacterizationandarenotensured.
(3)Currentintodevicepinsisdefinedaspositive.
Currentoutofadevicepinisdefinedasnegative.
VoltagesarereferencedtogroundexceptVOD,ΔVOD,VTHandVTLwhicharedifferentialvoltages.
6SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013DCElectricalCharacteristics(continued)Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
(1)(2)(3)SymbolParameterConditionsPin/Freq.
MinTypMaxUnitsHighLevelVDDIOVOHIOH=0.
1mAVDDIOVOutputVoltage-0.
2LowLevelVOLIOL=+0.
1mAGND0.
2VOutputVoltageLOCK,PASS,OS[2:0]OutputShortIOSVOUT=0V-3mACircuitCurrentTRI-STATEIOZVOUT=0VorVDDIO-15+15AOutputCurrentFPD-LinkIILVDSRECEIVERDCSPECIFICATIONSDifferentialInputVTH+50mVThresholdHighVoltageVCM=+1.
2V(InternalVBIAS)DifferentialInputVTL50mVThresholdLowRIN+,RIN-VoltageCommonVCMModeVoltage,1.
2VInternalVBIASInputRT758092TerminationSUPPLYCURRENTAllVDD(1.
8)IDD1VDDn=1.
89V7080mACheckerBoardpinsSupplyCurrentPattern,(includesloadIDDTX1VDDTX=3.
6VVDDTX3040mAVODSEL=H,current)SSCG=OnVDDIO=1.
89V0.
351mA43MHzClockIDDIO1VDDIOFigure4VDDIO=3.
6V11.
5mAAllVDD(1.
8)IDDZVDD=1.
89V0.
154mApinsPDB=0V,AllSupplyCurrentIDDTXZVDDTX=3.
6VVDDTX0.
010.
05mAotherLVCMOSPowerDownInputs=0VVDDIO=1.
89V0.
10.
4mAIDDIOZVDDIOVDDIO=3.
6V0.
40.
8mASwitchingCharacteristicsOverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
(1)(2)SymbolParameterConditionsPin/Freq.
MinTypMaxUnitsFPD-LinkIItDDLTLockTime(3)SSCG=Off5MHz6msSSCG=On5MHz14msSSCG=Off43MHz5msSSCG=On43MHz8mstDJITInputJitterToleranceEQ=OffJitterFrequency>10MHz>0.
45UIFigure14FPD-LinkOutput(1)TheElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommendedOperatingConditionsexceptasotherwisemodifiedorspecifiedbytheElectricalCharacteristicsConditionsand/orNotes.
Typicalspecificationsareestimationsonlyandarenotensured.
(2)TypicalvaluesrepresentmostlikelyparametricnormsatVDDn=1.
8V,VDDTX=3.
3V,VDDIO=1.
8Vor3.
3V,Ta=+25°C,andattheRecommendedOperationConditionsatthetimeofproductcharacterizationandarenotensured.
(3)tDDLTisthetimerequiredbythedeserializertoobtainlockwhenexitingpower-downstatewithanactivePCLK.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comSwitchingCharacteristics(continued)Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
(1)(2)SymbolParameterConditionsPin/Freq.
MinTypMaxUnitstTLHTLowtoHighTransitionTimeRL=100TxCLKOUT±,0.
30.
6nsTxOUT[2:0]±tTHLTHightoLowTransitionTime0.
30.
6nstDCCJCycle-to-CycleOutputJitter(4)(5)TxCLKOUT=5MHzTxCLKOUT±9002100psTxCLKOUT=43MHz75125pstTTP1TransmitterPulsePositionforTxOUT[2:0]±0UIbit1tTTP0TransmitterPulsePositionfor1UIbit0tTPP6TransmitterPulsePositionfor2UIbit6tTTP5TransmitterPulsePositionfor3UIbit5tTTP4TransmitterPulsePositionfor4UIbit4tTTP3TransmitterPulsePositionfor5UIbit3tTTP2TransmitterPulsePositionfor6UIbit2tTPDDPowerDownDelayactivetoTxCLKOUT=43MHzOFF610nsFigure6tTXZREnableDelayOFFtoactiveTxCLKOUT=43MHz4055nsFigure7LVCMOSOutputstCLHLowtoHighTransitionTimeCL=8pFLOCK,PASS,OS[2:0]1015nsFigure5tCHLHightoLowTransitionTime1015nstPASSBISTPASSValidTime,TxCLKOUT=5MHzPASS560570nsBISTEN=1,Figure12TxCLKOUT=43MHz7075nsSSCGModefDEVSpreadSpectrumSee(6)TxCLKOUT=5to43ClockingDeviationMHz,±0.
5±2%FrequencySSC[3:0]=ONfMODSpreadSpectrumSee(6)TxCLKOUT=5to43ClockingModulationMHz,8100kHzFrequencySSC[3:0]=ON(4)tDCCJisthemaximumamountofjitterbetweenadjacentclockcycles.
(5)Specificationisensuredbycharacterizationandisnottestedinproduction.
(6)Specificationisensuredbydesignandisnottestedinproduction.
RecommendedTimingfortheSerialControlBusOverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitsfSCLSCLClockFrequencyStandardMode0100kHzFastMode0400kHztLOWSCLLowPeriodStandardMode4.
7usFastMode1.
3ustHIGHSCLHighPeriodStandardMode4.
0usFastMode0.
6ustHD;STAHoldtimeforastartoraStandardMode4.
0usrepeatedstartcondition,FastMode0.
6usFigure138SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013RecommendedTimingfortheSerialControlBus(continued)Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitstSU:STASetUptimeforastartoraStandardMode4.
7usrepeatedstartcondition,FastMode0.
6usFigure13tHD;DATDataHoldTime,StandardMode03.
45usFigure13FastMode00.
9ustSU;DATDataSetUpTime,StandardMode250nsFigure13FastMode100nstSU;STOSetUpTimeforSTOPStandardMode4.
0usCondition,Figure13FastMode0.
6ustBUFBusFreeTimeStandardMode4.
7usBetweenSTOPandSTART,FastMode1.
3usFigure13trSCL&SDARiseTime,StandardMode1000nsFigure13FastMode300nstfSCL&SDAFallTime,StandardMode300nsFigure13Fastmode300nsDCandACSerialControlBusCharacteristicsOverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitsVIHInputHighLevelSDAandSCL0.
7*VDDIOVVDDIOVILInputLowLevelVoltageSDAandSCL0.
3*GNDVVDDIOVHYInputHysteresis>50mVVOLSDA,IOL=+0.
5mA00.
36VIinSDAorSCL,Vin=VDDIOorGND-10+10AtRSDARiseTime–READSDA,RPU=X,Cb≤400pF850nstFSDAFallTime–READ120nstSU;DATSetUpTime—READ500nstHD;DATHoldUpTime—READ580nstSPInputFilter50nsCinInputCapacitanceSDAorSCLcomFigure5.
LVCMOSTransitionTimesFigure6.
FPD-Link&LVCMOSPowerdownDelayFigure7.
FPD-LinkOutputsEnableDelayFigure8.
DeserializerPLLLockTimes10SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013Figure9.
FPD-Link(LVDS)Single-endedandDifferentialWaveformsFigure10.
FPD-LinkTransmitterPulsePositionsFigure11.
ReceiverInputJitterToleranceFigure12.
BISTPASSWaveformCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comFigure13.
SerialControlBusTimingDiagram12SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013TypicalPerformanceCharacteristicsFigure14.
TypicalInputJitterToleranceCurveat43MHzFigure15.
TypicalTotalIDDCurrent(1.
8VSupply)asaFunctionofPCLKFigure16.
TypicalIDDTXCurrent(3.
3VSupply)asaFunctionofPCLKCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comFUNCTIONALDESCRIPTIONTheDS99R124Qreceives24-bitsofdataoverasingleserialFPD-LinkIIpairoperatingat140Mbpsto1.
2Gbps.
Theserialstreamalsocontainsanembeddedclock,andtheDC-balanceinformationwhichenhancessignalqualityandsupportsACcoupling.
Thereceivercopnvertstheserialstreamintoa4-channel(3dataand1clock)FPD-LinkLVDSInterface.
ThedeviceisintendedtobeusedwiththeDS90UR241ortheDS99R421FPD-LinkIIserializers.
TheDesconvertsasingleinputserialdatastreamtoaFPD-Linkoutputbus,andalsoprovidesasignalcheckforthechipsetBuiltInSelfTest(BIST)mode.
Thedevicecanbeconfiguredviaexternalpinsorthroughtheoptionalserialcontrolbus.
TheDesfeaturesenhancesignalqualityonthelinkbysupportingtheFPD-LinkIIdatacodingthatprovidesrandomization,scrambling,andDCbalancingofthedata.
TheDesincludesmultiplefeaturestoreduceEMIassociatedwithdisplaydatatransmission.
Thisincludestherandomizationandscramblingofthedata,FPD-LinkLVDSOutputinterface,andalsotheoutputspreadspectrumclockgeneration(SSCG)support.
TheDes'powersavingfeaturesincludeapowerdownmode,andoptionalLVCMOS(1.
8V)interfacecompatibility.
TheDescanattainlocktoadatastreamwithouttheuseofaseparatereferenceclocksource,whichgreatlysimplifiessystemcomplexityandoverallcost.
TheDesalsosynchronizestotheSerregardlessofthedatapattern,deliveringtrueautomatic"plugandlock"performance.
Itcanlocktotheincomingserialstreamwithouttheneedofspecialtrainingpatternsorsynccharacters.
TheDesrecoverstheclockanddatabyextractingtheembeddedclockinformation,validatingandthendeserializingtheincomingdatastream.
TheDS99R421Q/DS99R124Qchipsetsupports18-bitcolordepth,HS,VSandDEvideocontrolsignalsanduptothreeover-sampledlow-speed(generalpurpose)databits.
DATATRANSFERTheDS99R124willreceiveapixelofdatainthefollowingformat:C1andC0representtheembeddedclockintheserialstream.
C1isalwaysHIGHandC0isalwaysLOW.
b[23:0]containthescrambleddata.
DCBistheDC-Balancedcontrolbit.
DCBisusedtominimizetheshortandlong-termDCbiasonthesignallines.
Thisbitdeterminesifthedataisunmodifiedorinverted.
DCAisusedtovalidatedataintegrityintheembeddeddatastream.
BothDCAandDCBcodingschemesaregeneratedbytheSeranddecodedbytheDesautomatically.
Figure17illustratestheserialstreamperPCLKcycle.
Figure17.
FPD-LinkIISerialStream(DS99R421/DS99R124)Thedevicesupportsclocksintherangeof5MHzto43MHz.
Witheveryclockcycle24bitsofpayloadarereceivedalongwiththefouroverheadbits.
Thus,thelinerateis1.
2Gbpsmaximum(140Mbpsminimum)withaneffectivedatarateof1.
03Gbpsmaximum.
Thelinkisextremelyefficientat86%(24/28).
TheFPD-LinkoutputwillpassalongthedatatotheDisplayintheformatshowninFigure18.
Figure18.
FPD-LinkOutputFormat14SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013FPD-LINKIIINPUTCommonModeFilterPin(CMF)—OptionalTheDesprovidesaccesstothecentertapoftheinternaltermination.
Acapacitormaybeplacedonthispinforadditionalcommon-modefilteringofthedifferentialpair.
Thiscanbeusefulinhighnoiseenvironmentsforadditionalnoiserejectioncapability.
A4.
7FcapacitormaybeconnectedtothispintoGround.
OUTPUTINTERFACES(LVCMOS&FPD-LINK)OS[2:0]LVCMOSOutputsAdditionalsignalsmaybereceivedacrosstheseriallinkperPCLK.
Theover-sampledbitsarerestrictedtobelowspeedsignalsandshouldbelessthan1/5ofthefrequencyofthePCLK.
Signalsshouldconveylevelinformationonly,aspulsewidthdistrotionwilloccurbytheoversamplingtechniqueandlocationofthesamplingclock.
ThethreeoversampledbitsareexactlymappedtoDS99R421's;andtoDS90UR421bitsare:OS0=DIN21,OS1=DIN22,andOS2=DIN23.
CLOCK-DATARECOVERYSTATUSFLAG(LOCK)andOUTPUTSTATESELECT(OSS_SEL)WhenPDBisdrivenHIGH,theCDRPLLbeginslockingtotheserialinput,LOCKisLowandtheFPD-LinkinterfacestateisdeterminedbythestateoftheOSS_SELpin.
AftertheDS99R124Qcompletesitslocksequencetotheinputserialdata,theLOCKoutputisdrivenHIGH,indicatingvaliddataandclockrecoveredfromtheserialinputisavailableontheFPD-Linkoutputs.
TheTxCLKoutputisheldatitscurrentstateatthechangefromOSC_CLK(ifthisisenabledviaOSC_SEL)totherecoveredclock(orviceversa).
NotethattheFPD-Linkoutputsmaybeheldinaninactivestate(TRI-STATE)throughtheuseoftheOutputEnablepin(OEN).
Ifthereisalossofclockfromtheinputserialstream,LOCKisdrivenLowandthestateoftheoutputsarebasedontheOSS_SELsetting(configurationpinorregister).
Table1.
OutputStateTableINPUTSOUTPUTSPDBOENOSS_SELLOCKOTHEROUTPUTSLXLZTxCLKOUTisTRI-STATETxOUT[2:0]areTRI-STATEOS[2:0]areTRI-STATEPASSisTRI-STATELXHLTxCLKOUTisTRI-STATETxOUT[2:0]areTRI-STATEOS[2:0]areLOWPASSisTRI-STATEHLLLTxCLKOUTisTRI-STATETxOUT[2:0]areTRI-STATEOS[2:0]areLOWPASSisHIGHHLHLTxCLKOUTisTRI-STATETxOUT[2:0]areTRI-STATEOS[2:0]areLOWPASSisLOWHHLLTxCLKOUTisTRI-STATETxOUT[2:0]areTRI-STATEOS[2:0]areTRI-STATEPASSisHIGHHHHLTxCLKOUTisTRI-STATETxOUT[2:0]areLOWOS[2:0]areLOWPASSisLOWCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comTable1.
OutputStateTable(continued)INPUTSOUTPUTSPDBOENOSS_SELLOCKOTHEROUTPUTSHLXHTxCLKOUTisTRI-STATETxOUT[2:0]areTRI-STATEOS[2:0]areActivePASSisActive(ThissettingallowsthesystemtorunBISTorusetheOS[2:0]bitswhilethepanelisoff)HHXHTxCLKOUTisActiveTxOUT[2:0]areActiveOS[2:0]areActivePASSisActive(Normaloperatingmode)LVCMOS1.
8V/3.
3VVDDIOOperationTheLVCMOSinputsandoutputscanoperatewith1.
8Vor3.
3Vlevels(VDDIO)fortarget(Display)compatibility.
The1.
8Vlevelswillofferalowernoise(EMI)andalsoasystempowersavings.
FPD-LINKOUTPUTVODSELThedifferentialoutputvoltageoftheFPD-LinkinterfaceiscontrolledbytheVODSELinput.
Table2.
VODSELConfigurationTableVODSELResultLVODis250mVTYP(500mVp-p)HVODis400mVTYP(800mVp-p)SSCGGeneration—OptionalTheDesprovidesaninternallygeneratedspreadspectrumclock(SSCG)tomodulateitsoutputs.
Bothclockanddataoutputsaremodulated.
ThiswillaidtolowersystemEMI.
OutputSSCGdeviationsto±2.
0%(4%total)atupto35kHzmodulationsnominallyareavailable.
SeeTable3andTable4.
Thisfeaturemaybecontrolledbypinsorbyregister.
TheLFMODEshouldbesetappropriatelyiftheSSCGisbeingused.
SetLFMODEHighiftheclockfrequencyisbetween5MHzand20MHz,setLFMODELowiftheclockfrequencyisbetween20MHzand43MHz.
Table3.
SSCGConfiguration(LFMODE=L)—DesOutputSSC[2:0]InputsResultLFMODE=L(20-43MHz)SSC2SSC1SSC0fdev(%)fmod(kHz)LLLOFFOFFLLH±0.
9LHL±1.
2CLK/2168LHH±1.
9HLL±2.
3HLH±0.
7HHL±1.
3CLK/1300HHH±1.
716SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013Table4.
SSCGConfiguration(LFMODE=H)—DesOutputSSC[2:0]InputsResultLFMODE=H(5-20MHz)SSC2SSC1SSC0fdev(%)fmod(kHz)LLLOFFOFFLLH±0.
7LHL±1.
3CLK/625LHH±1.
8HLL±2.
2HLH±0.
7HHL±1.
2CLK/385HHH±1.
7Figure19.
SSCGWaveformPOWERSAVINGFEATURESPowerDownFeature(PDB)TheDeshasaPDBinputpintoENABLEorPOWERDOWNthedevice.
Thispincanbecontrolledbythesystemtosavepower,disablingtheDeswhenthedisplayisnotneeded.
Anautodetectmodeisalsoavailable.
Inthismode,thePDBpinistiedHighandtheDeswillenterPOWERDOWNwhentheserialstreamstops.
Whentheserialstreamstartsupagain,theDeswilllocktotheinputstreamandasserttheLOCKpinandoutputvaliddata.
InPOWERDOWNmode,theDataandPCLKoutputstatesaredeterminedbytheOSS_SELstatus.
Note–inPOWERDOWN,theoptionalSerialBusControlRegistersareRESET.
StopStreamSLEEPFeatureTheDeswillenteralowpowerSLEEPstatewhentheinputserialstreamisstopped.
ASTOPconditionisdetectedwhentheembeddedclockbitsarenotpresent.
Whentheserialstreamstartsagain,theDeswillthenlocktotheincomingsignalandrecoverthedata.
Note–inSTOPSTREAMSLEEP,theoptionalSerialBusControlRegistersvaluesareRETAINED.
BuiltInSelfTest(BIST)—OptionalAnoptionalAt-SpeedBuiltInSelfTest(BIST)featuresupportsthetestingofthehigh-speedseriallink.
Thisisusefulintheprototypestage,equipmentproduction,in-systemtestandalsoforsystemdiagnostics.
IntheBISTmodeonlyaninputclockisrequiredalongwithcontroltotheSerandDesBISTENinputpins.
TheSeroutputsatestpattern(PRBS7)anddrivesthelinkatspeed.
TheDesdetectsthePRBS7patternandmonitorsitforerrors.
ThePASSoutputpintogglestoflaganypayloadsthatarereceivedwith1to24biterrors.
TheBISTMpinselectstheoperationalmodeofthePASSpin.
IfBISTM=L,thePASSpinsreportsthefinalresultonly.
IfBISTM=H,thePASSpinscountspayloaderrorsandalsoresultstheresult.
TheresultofthetestisheldonthePASSoutputuntilreset(newBISTtestorPowerDown).
AhighonPASSindicatesNOERRORSweredetected.
ALowonPASSindicatesoneormoreerrorsweredetected.
ThedurationofthetestiscontrolledbythepulsewidthappliedtotheDesBISTENpin.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comFigure20.
BISTModeFlowDiagramSampleBISTSequenceSeeFigure20fortheBISTmodeflowdiagram.
1.
FortheDS99R421FPD-LinkIISerBISTModeisenabledviatheBISTENpin.
FortheDS90UR241Ser,BISTmodeiseneteredbysettingalltheinputdataofthedevicetoLowstate.
APCLKisrequiredforalltheSeroptions.
WhentheDesdetectstheBISTmodepatternandcommand(DCAandDCBcode)theRGBandcontrolsignaloutputsareshutoff.
2.
PlacetheDS99R124QDesinBISTmodebysettingtheBISTEN=H.
TheDesisnowintheBISTmode.
IfBISTM=H,theDeswillchecktheincomingserialpayloadsforerrors.
Ifanerrorinthepayload(1to24)isdetected,thePASSpinwillswitchlowforonehalfoftheclockperiod.
DuringtheBISTtest,thePASSoutputcanbemonitoredandcountedtodeterminethepayloaderrorrate.
3.
ToStoptheBISTmode,theDesBISTENpinissetLow.
TheDesstopscheckingthedata.
ThefinaltestresultisheldonthePASSpin.
Ifthetestranerrorfree,thePASSoutputwillbeHigh.
Iftherewasoneormoreerrorsdetected,thePASSoutputwillbeLow.
ThePASSoutputstateishelduntilanewBISTisrun,thedeviceisRESET,orPoweredDown.
TheBISTdurationisusercontrolledbythedurationoftheBISTENsignal.
4.
Toreturnthelinktonormaloperation,theSerBISTENinputissetLow.
TheLinkreturnstonormaloperation.
Figure21showsthewaveformdiagramofatypicalBISTtestfortwocases.
Case1iserrorfree,andCase2showsonewithmultipleerrors.
Inmostcasesitisdifficulttogenerateerrorsduetotherobustnessofthelink(differentialdatatransmissionetc.
),thustheymaybeintroducedbygreatlyextendingthecablelength,faultingtheinterconnect,reducingsignalconditionenhancements(De-Emphasis,VODSEL,orRxEqualization).
18SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013Figure21.
BISTWaveformsSerialBusControl—OptionalTheDS99R124mayalsobeconfiguredbytheuseofaserialcontrolbusthatisI2Cprotocolcompatible.
Bydefault,theI2Creg_0x00'hissetto00'handallconfigurationissetbycontrol/strappins.
Awriteof01'htoreg_0x00'hwillenable/allowconfigurationbyregisters;thiswilloverridethecontrol/strappins.
Multipledevicesmaysharetheserialcontrolbussincemultipleaddressesaresupported.
SeeFigure22.
Theserialbusiscomprisedofthreepins.
TheSCLisaSerialBusClockInput.
TheSDAistheSerialBusDataInput/Outputsignal.
BothSCLandSDAsignalsrequireanexternalpullupresistortoVDDIO.
Formostapplicationsa4.
7kpullupresistortoVDDIOmaybeused.
Theresistorvaluemaybeadjustedforcapacitiveloadinganddataraterequirements.
ThesignalsareeitherpulledHigh,ordrivenLow.
Figure22.
SerialControlBusConnectionThethirdpinistheID[X]pin.
Thispinsetsoneoffourpossibledeviceaddresses.
Twodifferentconnectionsarepossible.
ThepinmaybepulledtoVDD(1.
8V,NOTVDDIO))witha10kresistor.
Ora10kpullupresistor(toVDD1.
8V,NOTVDDIO))andapulldownresistoroftherecommendedvaluetosetotherthreepossibleaddressesmaybeused.
SeeTable5fortheDes.
TheSerialBusprotocoliscontrolledbySTART,START-Repeated,andSTOPphases.
ASTARToccurswhenSCLtransitionsLowwhileSDAisHigh.
ASTOPoccurswhenSDAtransitionHighwhileSCLisalsoHIGH.
SeeFigure23Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comFigure23.
STARTandSTOPConditionsTocommunicatewitharemotedevice,thehostcontroller(master)sendstheslaveaddressandlistensforaresponsefromtheslave.
Thisresponseisreferredtoasanacknowledgebit(ACK).
Ifaslaveonthebusisaddressedcorrectly,itAcknowledges(ACKs)themasterbydrivingtheSDAbuslow.
Iftheaddressdoesn'tmatchadevice'sslaveaddress,itNot-acknowledges(NACKs)themasterbylettingSDAbepulledHigh.
ACKsalsooccuronthebuswhendataisbeingtransmitted.
Whenthemasteriswritingdata,theslaveACKsaftereverydatabyteissuccessfullyreceived.
Whenthemasterisreadingdata,themasterACKsaftereverydatabyteisreceivedtolettheslaveknowitwantstoreceiveanotherdatabyte.
Whenthemasterwantstostopreading,itNACKsafterthelastdatabyteandcreatesastopconditiononthebus.
AllcommunicationonthebusbeginswitheitheraStartconditionoraRepeatedStartcondition.
AllcommunicationonthebusendswithaStopcondition.
AREADisshowninFigure24andaWRITEisshowninFigure25.
IftheSerialBusisnotrequired,thethreepinsmaybeleftopen(NC).
Table5.
ID[x]ResistorValue–DS99R124QDesResistorAddressAddressRIDk7'b8'b(5%tol)0appended(WRITE)0.
477b'1110001(h'71)8b'11100010(h'E2)2.
77b'1110010(h'72)8b'11100100(h'E4)8.
27b'1110011(h'73)8b'11100110(h'E6)Open7b'1110110(h'76)8b'11101100(h'EC)Figure24.
SerialControlBus—READFigure25.
SerialControlBus—WRITE20SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013Table6.
DS99R124Q—SerialBusControlRegistersADDADDRegisterNameBit(s)R/WDefauFunctionDescription(dec)(hex)lt(bin)00DesConfig17R/W0LFMODESSCGMode–lowfrequencysupport0:20to43MHzOperation1:5to20MHzOperation6R/W0OSS_SELOutputSleepStateSelectTBD5R/W0ReservedReserved4R/W0ReservedReserved3:2R/W00ReservedReserved1R/W0SLEEPNote–notthesamefunctionasPowerDown(PDB)0:normalmode1:SleepMode–Registersettingsretained.
0R/W0REGControl0:Configurationssetfromcontrolpins1:Configurationssetfromregisters(exceptI2C_ID)11SlaveID7R/W0ADD_SEL0:AddressfromID[X]Pin1:AddressfromRegister6:0R/W11100ID[X]SerialBusDeviceID,FourIDsare:007b'1110001(h'71);8b'11100010(h'E2)7b'1110010(h'72);8b'11100100(h'E4)7b'1110011(h'73);8b'11100110(h'E6)7b'1110110(h'76);8b'11101100(h'EC)AllotheraddressesareReserved.
22DesFeatures17R/W0OENOutputEnableInput0:FPD-LinkoutputareTRI-STATE1:FPD-Linkoutputsareenabled(active)6R/W0ReservedReserved5:4R/W00ReservedReserved3R/W0VODSELDifferentialDriverOutputVoltageSelect0:LVDSVODis±250mV,500mVp-p(typ)1:LVDSVODis±400mV,800mVp-p(typ)2:0R/W00OSC_SEL000:OFF001:Reserved010:25MHz±40%011:16.
7MHz±40%100:12.
5MHz±40%101:10MHz±40%110:8.
3MHz±40%111:6.
3MHz±40%Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comTable6.
DS99R124Q—SerialBusControlRegisters(continued)ADDADDRegisterNameBit(s)R/WDefauFunctionDescription(dec)(hex)lt(bin)33DesFeatures27:5R/W000EQGain000:~1.
625dB001:~3.
25dB010:~4.
87dB011:~6.
5dB100:~8.
125dB101:~9.
75dB110:~11.
375dB111:~13dB4R/W0EQEnable0:EQ=disabled1:EQ=enabled3R/W0ReservedReserved2:0R/W000SSCIFLFMODE=0,then:000:SSCGOFF001:fdev=±0.
9%,fmod=CLK/2168010:fdev=±1.
2%,fmod=CLK/2168011:fdev=±1.
9%,fmod=CLK/2168100:fdev=±2.
3%,fmod=CLK/2168101:fdev=±0.
7%,fmod=CLK/1300110:fdev=±1.
3%,fmod=CLK/1300111:fdev=±1.
57%,fmod=CLK/1300IFLFMODE=1,then:000:SSCGOFF001:fdev=±0.
7%,fmod=CLK/625010:fdev=±1.
3%,fmod=CLK/625011:fdev=±1.
8%,fmod=CLK/625100:fdev=±2.
2%,fmod=CLK/625101:fdev=±0.
7%,fmod=CLK/385110:fdev=±1.
2%,fmod=CLK/385111:fdev=±1.
7%,fmod=CLK/38522SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013APPLICATIONSINFORMATIONDISPLAYAPPLICATIONTheDS99R124Q,inconjunctionwiththeDS99R421QorDS90UR241Q,isintendedforinterfacingbetweenahost(graphicsprocessor)andaDisplay.
Itsupportsan18-bitcolordepth(RGB666)anduptoWVGAdisplayformats.
InaRGB666application,18colorbits(R[5:0],G[5:0],B[5:0]),PixelClock(PCLK)andthreecontrolbits(VS,HSandDE)aresupportedacrosstheseriallinkwithPCLKratesfrom5to43MHz.
TYPICALAPPLICATIONCONNECTIONFigure26showsatypicalapplicationoftheDS99R124QQDesinpinmodefora43MHzWVGADisplayApplication.
TheLVDSinputsutilize100nFcouplingcapacitorstothelineandtheReceiverprovidesinternaltermination.
Bypasscapacitorsareplacednearthepowersupplypins.
Ferritebeadsareplacedonthepowerlinesforeffectivenoisesuppression.
Figure26.
DS99R124QTypicalConnectionDiagram—PinControlCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comPOWERUPREQUIREMENTSANDPDBPINTheVDD(VDDn),VDDTXandVDDIOsupplyrampsshouldbefasterthan1.
5mswithamonotonicrise.
Suppliesmaypowerupinanyorder,howeverdeviceoperationshouldbeinitiatedonlyafterallsuppliesareintheirvalidoperatingranges.
Theoptionalserialbusaddressselectionisdoneuponpowerupalso.
Thus,ifusingthisoptionalfeature,thePDBsignalmustbedelayedtoallowtimefortheIDsettingtooccur.
ThedelaymaybedonebysimplyholdingthePDBpinataLow,orwithanexternalRCdelaybasedofftheVDDIOrailwhichwouldthenneedtolagtheothersintime.
IfthePDBpinispulledtoVDDIO,itisrecommendedtousea10kΩpull-upanda10uFcaptoGNDtodelaythePDBinputsignal.
TRANSMISSIONMEDIATheSer/Deschipsetisintendedtobeusedinapoint-to-pointconfiguration,throughaPCBtrace,orthroughtwistedpaircable.
TheSerandDesprovideinternalterminationsprovidingacleansignalingenvironment.
TheinterconnectforLVDSshouldpresentadifferentialimpedanceof100Ohms.
Usecablesandconnectorsthathavematcheddifferentialimpedancetominimizeimpedancediscontinuities.
Shieldedorun-shieldedcablesmaybeuseddependinguponthenoiseenvironmentandapplicationrequirements.
LIVELINKINSERTIONTheSerandDesdevicessupportlivepluggableapplications.
Theautomaticreceiverlocktorandomdata"plug&go"hotinsertioncapabilityallowstheDS99R124Qtoattainlocktotheactivedatastreamduringaliveinsertionevent.
PCBLAYOUTANDPOWERSYSTEMCONSIDERATIONSCircuitboardlayoutandstack-upfortheLVDSSer/Desdevicesshouldbedesignedtoprovidelow-noisepowerfeedtothedevice.
Goodlayoutpracticewillalsoseparatehighfrequencyorhigh-levelinputsandoutputstominimizeunwantedstraynoisepickup,feedbackandinterference.
Powersystemperformancemaybegreatlyimprovedbyusingthindielectrics(2to4mils)forpower/groundsandwiches.
ThisarrangementprovidesplanecapacitanceforthePCBpowersystemwithlow-inductanceparasitics,whichhasprovenespeciallyeffectiveathighfrequencies,andmakesthevalueandplacementofexternalbypasscapacitorslesscritical.
ExternalbypasscapacitorsshouldincludebothRFceramicandtantalumelectrolytictypes.
RFcapacitorsmayusevaluesintherangeof0.
01uFto0.
1uF.
Tantalumcapacitorsmaybeinthe2.
2uFto10uFrange.
Voltageratingofthetantalumcapacitorsshouldbeatleast5Xthepowersupplyvoltagebeingused.
Surfacemountcapacitorsarerecommendedduetotheirsmallerparasitics.
Whenusingmultiplecapacitorspersupplypin,locatethesmallervalueclosertothepin.
Alargebulkcapacitorisrecommendatthepointofpowerentry.
Thisistypicallyinthe50uFto100uFrangeandwillsmoothlowfrequencyswitchingnoise.
Itisrecommendedtoconnectpowerandgroundpinsdirectlytothepowerandgroundplaneswithbypasscapacitorsconnectedtotheplanewithviaonbothendsofthecapacitor.
Connectingpowerorgroundpinstoanexternalbypasscapacitorwillincreasetheinductanceofthepath.
AsmallbodysizeX7Rchipcapacitor,suchas0603,isrecommendedforexternalbypass.
Itssmallbodysizereducestheparasiticinductanceofthecapacitor.
Theusermustpayattentiontotheresonancefrequencyoftheseexternalbypasscapacitors,usuallyintherangeof20-30MHz.
Toprovideeffectivebypassing,multiplecapacitorsareoftenusedtoachievelowimpedancebetweenthesupplyrailsoverthefrequencyofinterest.
Athighfrequency,itisalsoacommonpracticetousetwoviasfrompowerandgroundpinstotheplanes,reducingtheimpedanceathighfrequency.
Somedevicesprovideseparatepowerandgroundpinsfordifferentportionsofthecircuit.
Thisisdonetoisolateswitchingnoiseeffectsbetweendifferentsectionsofthecircuit.
SeparateplanesonthePCBaretypicallynotrequired.
PinDescriptiontablestypicallyprovideguidanceonwhichcircuitblocksareconnectedtowhichpowerpinpairs.
Insomecases,anexternalfiltermanybeusedtoprovidecleanpowertosensitivecircuitssuchasPLLs.
Useatleastafourlayerboardwithapowerandgroundplane.
LocateLVCMOSsignalsawayfromtheLVDSlinestopreventcouplingfromtheLVCMOSlinestotheLVDSlines.
Closely-coupleddifferentiallinesof100OhmsaretypicallyrecommendedforLVDSinterconnect.
Thecloselycoupledlineshelptoensurethatcouplednoisewillappearascommon-modeandthusisrejectedbythereceivers.
Thetightlycoupledlineswillalsoradiateless.
InformationontheWQFNstylepackageisprovidedinTexasInstrumentsNote:AN-1187(SNOA401).
24SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QDS99R124Qwww.
ti.
comSNLS318D–JANUARY2010–REVISEDAPRIL2013LVDSINTERCONNECTGUIDELINESSeeAN-1108(SNLA008)andAN-905(SNLA035)forfulldetails.
Use100ΩcoupleddifferentialpairsUsetheS/2S/3Sruleinspacings–S=spacebetweenthepair–2S=spacebetweenpairs–3S=spacetoLVCMOSsignalMinimizethenumberofViasUsedifferentialconnectorswhenoperatingabove500MbpslinespeedMaintainbalanceofthetracesMinimizeskewwithinthepairTerminateasclosetotheTXoutputsandRXinputsaspossibleAdditionalgeneralguidancecanbefoundintheLVDSOwner'sManual-availableinPDFformatfromtheTIwebsiteat:http://www.
ti.
com/ww/en/analog/interface/lvds.
shtmlCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLinks:DS99R124QDS99R124QSNLS318D–JANUARY2010–REVISEDAPRIL2013www.
ti.
comREVISIONHISTORYChangesfromRevisionC(April2013)toRevisionDPageChangedlayoutofNationalDataSheettoTIformat2526SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS99R124QPACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDS99R124QSQ/NOPBACTIVEWQFNRHS481000RoHS&GreenSNLevel-3-260C-168HR-40to105DS99R124QDS99R124QSQE/NOPBACTIVEWQFNRHS48250RoHS&GreenSNLevel-3-260C-168HR-40to105DS99R124QDS99R124QSQX/NOPBACTIVEWQFNRHS482500RoHS&GreenSNLevel-3-260C-168HR-40to105DS99R124Q(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709BlowhalogenrequirementsofcombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page2InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDS99R124QSQ/NOPBWQFNRHS481000330.
016.
47.
37.
31.
312.
016.
0Q1DS99R124QSQE/NOPBWQFNRHS48250178.
016.
47.
37.
31.
312.
016.
0Q1DS99R124QSQX/NOPBWQFNRHS482500330.
016.
47.
37.
31.
312.
016.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com20-Sep-2016PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DS99R124QSQ/NOPBWQFNRHS481000367.
0367.
038.
0DS99R124QSQE/NOPBWQFNRHS48250210.
0185.
035.
0DS99R124QSQX/NOPBWQFNRHS482500367.
0367.
038.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com20-Sep-2016PackMaterials-Page2www.
ti.
comPACKAGEOUTLINECSEETERMINALDETAIL48X0.
300.
185.
10.
148X0.
50.
30.
80.
7(A)TYP0.
050.
0044X0.
52X5.
52X5.
5A7.
156.
85B7.
156.
850.
300.
180.
50.
3(0.
2)WQFN-0.
8mmmaxheightRHS0048APLASTICQUADFLATPACK-NOLEAD4214990/B04/2018DIMAOPT1OPT2(0.
1)(0.
2)PIN1INDEXAREA0.
08CSEATINGPLANE112253613244837(OPTIONAL)PIN1ID0.
1CAB0.
05EXPOSEDTHERMALPAD49SYMMSYMMNOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
SCALE1.
800DETAILOPTIONALTERMINALTYPICALwww.
ti.
comEXAMPLEBOARDLAYOUT0.
07MINALLAROUND0.
07MAXALLAROUND48X(0.
25)48X(0.
6)(0.
2)TYPVIA44X(0.
5)(6.
8)(6.
8)(1.
25)TYP(5.
1)(R0.
05)TYP(1.
25)TYP(1.
05)TYP(1.
05)TYPWQFN-0.
8mmmaxheightRHS0048APLASTICQUADFLATPACK-NOLEAD4214990/B04/2018SYMM112132425363748SYMMLANDPATTERNEXAMPLEEXPOSEDMETALSHOWNSCALE:12XNOTES:(continued)4.
Thispackageisdesignedtobesolderedtoathermalpadontheboard.
Formoreinformation,seeTexasInstrumentsliteraturenumberSLUA271(www.
ti.
com/lit/slua271).
5.
Viasareoptionaldependingonapplication,refertodevicedatasheet.
Ifanyviasareimplemented,refertotheirlocationsshownonthisview.
Itisrecommendedthatviasunderpastebefilled,pluggedortented.
49SOLDERMASKOPENINGMETALUNDERSOLDERMASKSOLDERMASKDEFINEDEXPOSEDMETALMETALEDGESOLDERMASKOPENINGSOLDERMASKDETAILSNONSOLDERMASKDEFINED(PREFERRED)EXPOSEDMETALwww.
ti.
comEXAMPLESTENCILDESIGN48X(0.
6)48X(0.
25)44X(0.
5)(6.
8)(6.
8)16X(1.
05)(0.
625)TYP(R0.
05)TYP(1.
25)TYP(1.
25)TYP(0.
625)TYPWQFN-0.
8mmmaxheightRHS0048APLASTICQUADFLATPACK-NOLEAD4214990/B04/2018NOTES:(continued)6.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
49SYMMMETALTYPSOLDERPASTEEXAMPLEBASEDON0.
125mmTHICKSTENCILEXPOSEDPAD4968%PRINTEDSOLDERCOVERAGEBYAREAUNDERPACKAGESCALE:15XSYMM112132425363748IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.
Youaresolelyresponsiblefor(1)selectingtheappropriateTIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicablestandards,andanyothersafety,security,orotherrequirements.
Theseresourcesaresubjecttochangewithoutnotice.
TIgrantsyoupermissiontousetheseresourcesonlyfordevelopmentofanapplicationthatusestheTIproductsdescribedintheresource.
Otherreproductionanddisplayoftheseresourcesisprohibited.
NolicenseisgrantedtoanyotherTIintellectualpropertyrightortoanythirdpartyintellectualpropertyright.
TIdisclaimsresponsibilityfor,andyouwillfullyindemnifyTIanditsrepresentativesagainst,anyclaims,damages,costs,losses,andliabilitiesarisingoutofyouruseoftheseresources.
TI'sproductsareprovidedsubjecttoTI'sTermsofSale(www.
ti.
com/legal/termsofsale.
html)orotherapplicabletermsavailableeitheronti.
comorprovidedinconjunctionwithsuchTIproducts.
TI'sprovisionoftheseresourcesdoesnotexpandorotherwisealterTI'sapplicablewarrantiesorwarrantydisclaimersforTIproducts.
MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265Copyright2020,TexasInstrumentsIncorporated