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IS43/46LR16160H11Rev.
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com4Mx16Bitsx4BanksMobileDDRSDRAMDescriptionTheIS43/46LR16160His268,435,456bitsCMOSMobileDoubleDataRateSynchronousDRAMorganizedas4banksof4,194,304wordsx16bits.
Thisproductusesadouble-data-ratearchitecturetoachievehigh-speedoperation.
TheDataInput/Outputsignalsaretransmittedona16-bitbus.
Thedoubledataratearchitectureisessentiallya2NprefetcharchitecturewithaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Opins.
Thisproductoffersfullysynchronousoperationsreferencedtobothrisingandfallingedgesoftheclock.
Thedatapathsareinternallypipelinedand2n-bitsprefetchedtoachieveveryhighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithLVCMOS.
FeaturesJEDECstandard1.
8VpowersupplyVDD=1.
8V,VDDQ=1.
8VFourinternalbanksforconcurrentoperationMRScyclewithaddresskeyprograms-CASlatency2,3(clock)-Burstlength(2,4,8,16)-Bursttype(sequential&interleave)Fullydifferentialclockinputs(CK,/CK)Allinputsexceptdata&DMaresampledattherisingedgeofthesystemclockDataI/OtransactiononbothedgesofdatastrobeBidirectionaldatastrobeperbyteofdata(DQS)DMforwritemaskingonlyEdgealigneddata&datastrobeoutputCenteraligneddata&datastrobeinput64msrefreshperiod(8Kcycle)Auto&selfrefreshConcurrentAutoPrechargeMaximumclockfrequencyupto200MHZMaximumdatarateupto400Mbps/pinPowerSavingsupport-PASR(PartialArraySelfRefresh)-AutoTCSR(TemperatureCompensatedSelfRefresh)-DeepPowerDownMode-ProgrammableDriverStrengthControlbyFullStrengthor3/4,1/2,1/4,or1/8ofFullStrengthStatusRegisterRead(SRR)LVCMOScompatibleinputs/outputs60-BallFBGApackageCopyright2018IntegratedSiliconSolution,Inc.
Allrightsreserved.
ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithoutnotice.
ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.
Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.
IntegratedSiliconSolution,Inc.
doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.
ProductsarenotauthorizedforuseinsuchapplicationsunlessIntegratedSiliconSolution,Inc.
receiveswrittenassurancetoitssatisfaction,that:a.
)theriskofinjuryordamagehasbeenminimized;b.
)theuserassumeallsuchrisks;andc.
)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances2Rev.
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comIS43/46LR16160HFigure1:60BallFBGABallAssignmentABCDEFGHJK123456789VSSDQ15VSSQVDDQDQ13DQ14VSSQDQ11DQ12VDDQDQ9DQ10VSSUDMNCCKECK/CKA9A11A12A6A7A8VSSA4A5VDDQDQ0VDDDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQNCLDMVDD/WE/CAS/RAS/CSBA0BA1A10A0A1A2A3VDDVSSQUDQSDQ8DQ7LDQSVDDQ[TopView]3Rev.
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comIS43/46LR16160HTable2:PinDescriptionsSymbolTypeFunctionDescriptionsCK,/CKInputSystemClockThesystemclockinput.
CKand/CKaredifferentialclockinputs.
AlladdressandcontrolinputsignalsareregisteredonthecrossingoftherisingedgeofCKandfallingedgeof/CK.
InputandoutputdataisreferencedtothecrossingofCKand/CK.
CKEInputClockEnableCKEisclockenablecontrolsinput.
CKEHIGHactivates,andCKELOWdeactivatesinternalclocksignals,anddeviceinputbuffersandoutputdrivers.
CKEissynchronousforallfunctionsexceptforSELFREFRESHEXIT,whichisachievedasynchronously.
/CSInputChipSelect/CSenables(registeredLow)anddisables(registeredHigh)thecommanddecoder.
Allcommandsaremaskedwhen/CSISREGISTEREDhigh.
/CSprovidesforexternalbankselectiononsystemswithmultiplebanks.
/CSisconsideredpartofthecommandcode.
BA0,BA1InputBankAddressBA0andBA1definetowhichbankanACTIVE,READ,WRITE,orPRECHARGEcommandisbeingapplied.
BA0andBA1alsodeterminewhichmoderegister(standardmoderegisterorextendedmoderegister)isloadedduringaLOADMODEREGISTERcommand.
A0~A12InputAddressRowAddress:RA0~RA12ColumnAddress:CA0~CA8AutoPrecharge:A10/RAS,/CAS,/WEInputRowAddressStrobe,ColumnAddressStrobe,WriteEnable/RAS,/CASand/WEdefinetheoperation.
Referfunctiontruthtablefordetails.
LDM,UDMInputDataInputMaskDMisaninputmasksignalforwritedata.
InputdataismaskedwhenDMissampledHIGHalongwiththatinputdataduringaWRITEaccess.
DMissampledonbothedgesofDQS.
AlthoughDMballsareinput-only.
DQ0~DQ15In/OutputDataInput/OutputDatainput/outputpin.
LDQS,UDQSIn/OutputDataInput/OutputStrobeOutputwithreaddata,inputwithwritedata.
DQSisedge-alignedwithreaddata,centeredinwritedata.
Datastrobeisusedtocapturedata.
VDDSupplyPowerSupplyPowersupplyVSSSupplyGroundGroundVDDQSupplyDQPowerSupplyPowersupplyforDQVSSQSupplyDQGroundGroundforDQNCNCNoConnectionNoconnection.
4Rev.
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comIS43/46LR16160HFigure2:FunctionalBlockDiagramUDQS,LDQSExtendedModeRegisterSelfrefreshLogic&timerInternalRowCounterRowPreDecoderColumnPreDecoderColumnAddCounterAddressRegisterModeRegisterDataOutControlBurstCounterAddressBuffersStateMachineRowDecodersRowDecodersRowDecodersRowDecoders8Mx16BANK18Mx16BANK0MemoryCellArrayColumnDecoders8Mx16BANK28Mx16BANK3WriteDataRegister2-bitPrefetchUnitSenseAMP&I/OGateOutputBuffer&LogicDQ0.
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DQ15DataStrobeTransmitterDataStrobeReceiverInputBuffer&Logic||16||||32||DSDSX16X32PASRRowActiveRefreshColumnActiveBankSelectBurstLengthCASLatencyA0A1A12BA0BA1LDM/UDM/WE/CAS/RAS/CSCKECK/CK5Rev.
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comIS43/46LR16160HFigure3:SimplifiedStateDiagramACT=ActiveBST=BurstCKEL=EnterPower-DownCKEH=ExitPower-DownDPDS=EnterDeepPower-DownDPDSX=ExitDeepPower-DownEMRS=Ext.
ModeReg.
SetMRS=ModeRegisterSetPRE=PrechargePREALL=PrechargeAllBanksREFA=AutoRefreshREFS=EnterSelfRefreshREFSX=ExitSelfRefreshREAD=Readw/oAutoPrechargeREADA=ReadwithAutoPrechargeSRR=StatusRegisterReadWRITE=Writew/oAutoPrechargeWRITEA=WritewithAutoPrechargePowerOnPrechargeAllBanksMRSEMRSActivePowerDownDeepPowerDownIdleAllBanksPrechargedAutoRefreshRowActivePrechargePREALLWRITEWRITEAREADREADABurstStopPrechargePowerDownDPDSPowerAppliedDPDSXMRSREFAACTCKEHCKELREFSREFSXSelfRefreshPRECKELCKEHWRITEREADBSTPREPREPREWRITEAWRITEREADREADAREADWRITEAREADAAutomaticsequenceSRRMRSRead6Rev.
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comIS43/46LR16160HBurstTypeAccesseswithinagivenburstmaybeprogrammedtobeeithersequentialorinterleaved;thisisreferredtoasthebursttypeandisselectedviabitM3.
Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttypeandthestartingcolumnaddress,asshowninTable3.
M3BurstType0Sequential1InterleaveM6M5M4CASLatency000Reserved001Reserved01020113100Reserved101Reserved110Reserved111ReservedM2M1M0BurstLengthM3=0M3=1000ReservedReserved0012201044011881001616101ReservedReserved110ReservedReserved111ReservedReservedAddressBusA0A1A2A3A4A5A6A7A8A9A10A11Figure4:ModeRegisterSet(MRS)DefinitionBA0BA11413121110987654321000000000CASLatencyBTBurstLengthNote:M14(BA1)=0andM13(BA0)=0toselectModeRegisterModeRegister(Mx)A127Rev.
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comIS43/46LR16160HTable3:BurstDefinitionBurstLengthStartingColumnAddressOrderofAccesswithinaBurstA3A2A1A0SequentialModeInterleaveMode2xxx00-10-1xxx11-01-04xx000-1-2-30-1-2-3xx011-2-3-01-0-3-2xx102-3-0-12-3-0-1xx113-0-1-23-2-1-08x0000-1-2-3-4-5-6-70-1-2-3-4-5-6-7x0011-2-3-4-5-6-7-01-0-3-2-5-4-7-6x0102-3-4-5-6-7-0-12-3-0-1-6-7-4-5x0113-4-5-6-7-0-1-23-2-1-0-7-6-5-4x1004-5-6-7-0-1-2-34-5-6-7-0-1-2-3x1015-6-7-0-1-2-3-45-4-7-6-1-0-3-2x1106-7-0-1-2-3-4-56-7-4-5-2-3-0-1x1117-0-1-2-3-4-5-67-6-5-4-3-2-1-01600000-1-2-3-4-5-6-7-8-9-10-11-12-13-14-150-1-2-3-4-5-6-7-8-9-10-11-12-13-14-1500011-2-3-4-5-6-7-8-9-10-11-12-13-14-15-01-0-3-2-5-4-7-6-9-8-11-10-13-12-15-1400102-3-4-5-6-7-8-9-10-11-12-13-14-15-0-12-3-0-1-6-7-4-5-10-11-8-9-14-15-12-1300113-4-5-6-7-8-9-10-11-12-13-14-15-0-1-23-2-1-0-7-6-5-4-11-10-9-8-15-14-13-1201004-5-6-7-8-9-10-11-12-13-14-15-0-1-2-34-5-6-7-0-1-2-3-12-13-14-15-8-9-10-1101015-6-7-8-9-10-11-12-13-14-15-0-1-2-3-45-4-7-6-1-0-3-2-13-12-15-14-9-8-11-1001106-7-8-9-10-11-12-13-14-15-0-1-2-3-4-56-7-4-5-2-3-0-1-14-15-12-13-10-11-8-901117-8-9-10-11-12-13-14-15-0-1-2-3-4-5-67-6-5-4-3-2-1-0-15-14-13-12-11-10-9-810008-9-10-11-12-13-14-15-0-1-2-3-4-5-6-78-9-10-11-12-13-14-15-0-1-2-3-4-5-6-710019-10-11-12-13-14-15-0-1-2-3-4-5-6-7-89-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6101010-11-12-13-14-15-0-1-2-3-4-5-6-7-8-910-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5101111-12-13-14-15-0-1-2-3-4-5-6-7-8-9-1011-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4110012-13-14-15-0-1-2-3-4-5-6-7-8-9-10-1112-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3110113-14-15-0-1-2-3-4-5-6-7-8-9-10-11-1213-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2111014-15-0-1-2-3-4-5-6-7-8-9-10-11-12-1314-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1111115-0-1-2-3-4-5-6-7-8-9-10-11-12-13-1415-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0Note:1.
Foraburstlengthoftwo,A1-A8selecttheblockoftwoburst;A0selectsthestartingcolumnwithintheblock.
2.
Foraburstlengthoffour,A2-A8selecttheblockoffourburst;A0-A1selectthestartingcolumnwithintheblock.
3.
Foraburstlengthofeight,A3-A8selecttheblockofeightburst;A0-A2selectthestartingcolumnwithintheblock.
4.
Foraburstlengthofsixteen,A4-A8selecttheblockofeightburst;A0-A3selectthestartingcolumnwithintheblock.
5.
Wheneveraboundaryoftheblockisreachedwithinagivensequenceabove,thefollowingaccesswrapswithintheblock.
8Rev.
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comIS43/46LR16160HFigure5:ExtendedModeSet(EMRS)RegisterAddressBusExtendedModeRegister(Ex)A0A1A2A3A4A5A6A7A8A9A10A11E2E1E0SelfRefreshCoverage000FourBanks001TwoBank(BA1=0)010OneBank(BA1=BA0=0)011Reserved100Reserved101OneEighthofTotalBank(BA1=BA0=RowAddressMSB=0)110OneSixteenthofTotalBank(BA1=BA0=RowAddress2MSBs=0)111ReservedE7E6E5DriverStrength000FullStrength0011/2Strength0101/4Strength0111/8Strength1003/4Strength101Reserved110Reserved111ReservedBA0BA1141312111098765432101000000DS00PASRNote:1.
E14(BA1)=1andE13(BA0)=0toselectExtendedModeRegisterA129Rev.
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comIS43/46LR16160HThe256MbMobileDDRSDRAMisahigh-speedCMOS,dynamicrandom-accessmemorycontaining268,435,456-bits.
Itisinternallyconfiguredasaquad-bankDRAM.
The256MbMobileDDRSDRAMusesadoubledataratearchitecturetoachievehighspeedoperation.
Thedoubledataratearchitectureisessentiallya2n-prefetcharchitecture,withaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Oballs,singlereadorwriteaccessforthe256MbMobileDDRSDRAMconsistsofasingle2n-bitwide,one-clock-cycledatatransferattheinternalDRAMcoreandtwocorrespondingn-bitwide,one-half-clock-cycledatatransfersattheI/Oballs.
ReadandWriteaccessestotheMobileDDRSDRAMareburstoriented;accessesstartataselectedlocationandcontinueforaprogrammednumberoflocationsinaprogrammedsequence.
AccessesbeginwiththeregistrationofanACTIVEcommand,whichisthenfollowedbyaREADorWRITEcommand.
TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowtobeaccessed(BA0,BA1selectthebank;A0–A12selecttherow).
TheaddressbitsregisteredcoincidentwiththeREADorWRITEcommandareusedtoselectthestartingcolumnlocationfortheburstaccess.
ItshouldbenotedthattheDLLsignalthatistypicallyusedonstandardDDRdevicesisnotnecessaryontheMobileDDRSDRAM.
Ithasbeenomittedtosavepower.
Priortonormaloperation,theMobileDDRSDRAMmustbepoweredupandinitialized.
Thefollowingsectionsprovidedetailedinformationcoveringdeviceinitialization,registerdefinition,commanddescriptionsanddeviceoperation.
PowerupandInitializationMobileDDRSDRAMmustbepoweredupandinitializedinapredefinedmanner.
PowermustbeappliedtoVDDandVDDQ(simultaneously).
Afterpowerup,aninitialpauseof200usecisrequired.
AndaprechargeallcommandwillbeissuedtotheMobileDDR.
Then,2ormoreAutorefreshcycleswillbeprovided.
AftertheAutorefreshcyclesarecompleted,aModeRegisterSet(MRS)commandwillbeissuedtoprogramthespecificmodeofoperation(CasLatency,Burstlength,etc.
)AndaExtendedModeRegisterSet(EMRS)commandwillbeissuedtoPartialArraySelfRefresh(PASR).
Thefollowingthesecycles,theMobileDDRSDRAMisreadyfornormaloperation.
Toensuredevicefunctionality,thereisapredefinedsequencethatmustoccuratdevicepoweruporifthereisanyinterruptionofdevicepower.
ToproperlyinitializetheMobileDDRSDRAM,thissequencemustbefollowed:1.
Topreventdevicelatch-up,itisrecommendedthecorepower(VDD)andI/Opower(VDDQ)befromthesamepowersourceandbroughtupsimultaneously.
Ifseparatepowersourcesareused,VDDmustleadVDDQ.
2.
OncepowersupplyvoltagesarestableandtheCKEhasbeendrivenHIGH,itissafetoapplytheclock.
3.
Oncetheclockisstable,a200μs(minimum)delayisrequiredbytheMobileDDRSDRAMpriortoapplyinganexecutablecommand.
Duringthistime,NOPorDESELECTcommandsmustbeissuedonthecommandbus.
4.
IssueaPRECHARGEALLcommand.
5.
IssueNOPorDESELECTcommandsforatleasttRPtime.
6.
IssueanAUTOREFRESHcommandfollowedbyNOPorDESELECTcommandsforatleasttRFCtime.
IssueasecondAUTOREFRESHcommandfollowedbyNOPorDESELECTcommandsforatleasttRFCtime.
Aspartoftheindividualizationsequence,twoAUTOREFRESHcommandsmustbeissued.
Typically,bothofthesecommandsareissuedatthisstageasdescribedabove.
7.
UsingtheLOADMODEREGISTERcommand,loadthestandardmoderegisterasdesired.
8.
IssueNOPorDESELECTcommandsforatleasttMRDtime.
9.
UsingtheLOADMODEREGISTERcommand,loadtheextendedmoderegistertothedesiredoperatingmodes.
Notethattheorderinwhichthestandardandextendedmoderegistersareprogrammedisnotcritical.
10.
IssueNOPorDESELECTcommandsforatleasttMRDtime.
11.
TheMobileDDRSDRAMhasbeenproperlyinitializedandisreadytoreceiveanyvalidcommand.
FunctionalDescription10Rev.
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comIS43/46LR16160HNotes:1.
PCG=PRECHARGEcommand,MRS=LOADMODEREGISTERcommand,AREF=AUTOREFRESHcommand,ACT=ACTIVEcommand,RA=Rowaddress,BA=Bankaddress.
2.
NOPorDESELECTcommandsarerequiredforatleast200μs.
3.
Othervalidcommandsarepossible.
4.
NOPsorDESELECTsarerequiredduringthistime.
Figure6:PowerupsequenceACTBABA0=L,BA1=HBA0=L,BA1=LAllBanksMRSMRSAREFAREFPCGNOPNOP2NOP3CLK/CLKCKET0Command1T1Ta0tCLDMA0~A9,A11,A12Tb0Tc0Td0Te0Tf0tCKLVCMOSHIGHLEVELA10BA0,BA1DQS,DQHigh-ZT=200stISRACODECODEtIStIHRACODECODEtIStIHtIStIHtRP4tRFC4tRFC4tMRD4tMRD4tIHVDDQVDDtIStIHLoadStandardModeRegisterLoadExtendedModeRegisterPower-up:VDDandCLKstableDon'tcare11Rev.
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comIS43/46LR16160HModeRegisterThemoderegisterisusedtodefinethespecificmodeofoperationoftheMobileDDRSDRAM.
Thisdefinitionincludestheselectionofaburstlength,abursttype,aCASlatency.
ThemoderegisterisprogrammedviatheLOADMODEREGISTERcommandandwillretainthestoredinformationuntilprogrammedagain,thedevicegoesintodeeppower-downmode,orthedevicelosespower.
ModeregisterbitsA0-A2specifytheburstlength,A3specifiesthetypeofburst(sequentialorinterleaved),A4-A6specifytheCASlatency,andA7-A12shouldbesettozero.
BA0andBA1mustbezerotoaccessthemoderegister.
Themoderegistermustbeloadedwhenallbanksareidle,andthecontrollermustwaitthespecifiedtimebeforeinitiatingthesubsequentoperation.
Violatingeitheroftheserequirementswillresultinunspecifiedoperation.
BurstLengthReadandwriteaccessestotheMobileDDRSDRAMareburstoriented,withtheburstlengthbeingprogrammable,asshowninFigure(ModeRegisterSetDefinition).
TheburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcanbeaccessedforagivenREADorWRITEcommand.
Burstlengthsof2,4,8or16areavailableforboththesequentialandtheinterleavedbursttypes.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfutureversionsmayresult.
WhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.
Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwillwrapwithintheblockifaboundaryisreached.
TheblockisuniquelyselectedbyA1-A8whentheburstlengthissettotwo;byA2-A8whentheburstlengthissettofour;byA3-A8whentheburstlengthissettoeight;andbyA4-A8whentheburstlengthissettosixteen.
Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestartinglocationwithintheblock.
TheprogrammedburstlengthappliestobothREADandWRITEbursts.
CASLatencyTheCASlatencyisthedelay,inclockcycles,betweentheregistrationofaREADcommandandtheavailabilityofthefirstbitofoutputdata.
Thelatencycanbesetto2,3clocks,asshowninFigure(StandardModeRegisterDefinition).
ForCL=3,iftheREADcommandisregisteredatclockedgen,thenthedatawillbeavailableat(n+2clocks+tAC).
ForCL=2,iftheREADcommandisregisteredatclockedgen,thenthedatawillbeavailableat(n+1clock+tAC).
Figure7:CASLatency(BL=4)/CKCKCommandT0T1T2T3T1nT2nT3nREADNOPNOPNOPDQSDQtACCL=3DOUTn+1tRPRE2tCKT4T4nNOPtRPSTDOUTnDOUTn+2DOUTn+3Don'tcareDQSDQtACCL=2DOUTn+1tRPRE1tCKtRPSTDOUTnDOUTn+2DOUTn+3LL12Rev.
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comIS43/46LR16160HExtendedModeRegisterTheExtendedModeRegistercontrolsthefunctionsbeyondthosecontrolledbytheModeRegister.
TheseadditionalfunctionsarespecialfeaturesoftheMobileDDRSDRAM.
TheyincludePartialArraySelfRefresh(PASR)andDriverStrength(DS).
TheExtendedModeRegisterisprogrammedviatheModeRegisterSetcommand(BA0=0,BA1=1)andretainsthestoredinformationuntilprogrammedagain,thedevicegoesintodeeppower-downmode,orthedevicelosespower.
TheExtendedModeRegistermustbeprogrammedwithA8throughA12setto"0".
TheExtendedModeRegistermustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimebeforeinitiatinganysubsequentoperation.
Violatingeitheroftheserequirementsresultsinunspecifiedoperation.
PartialArraySelfRefreshForfurtherpowersavingsduringSELFREFRESH,thePASRfeatureallowsthecontrollertoselecttheamountofmemorythatwillberefreshedduringSELFREFRESH.
Therefreshoptionsareasfollows:Fullarray:banks0,1,2,and3Halfarray:banks0and1Quarterarray:bank0Oneeightharray:halfofbank0Onesixteentharray:quarterofbank0WRITEandREADcommandscanstilloccurduringstandardoperation,butonlytheselectedbankswillberefreshedduringSELFREFRESH.
Datainbanksthataredisabledwillbelost.
OutputDriverStrengthBecausetheMobileDDRSDRAMisdesignedforuseinsmallersystemsthataremostlypointtopoint,anoptiontocontrolthedrivestrengthoftheoutputbuffersisavailable.
Drivestrengthshouldbeselectedbasedontheexpectedloadingofthememorybus.
BitsA5,A6andA7oftheextendedmoderegistercanbeusedtoselectthedriverstrengthoftheDQoutputs.
Therearefiveallowablesettingsfortheoutputdrivers.
TemperatureCompensatedSelfRefreshIntheMobileDDRSDRAM,atemperaturesensorisimplementedforautomaticcontroloftheselfrefreshoscillatoronthedevice.
TemperatureCompensatedSelfRefreshallowsthecontrollertoprogramtheRefreshintervalduringSELFREFRESHmode,accordingtothecasetemperatureoftheMobileSDRAMdevice.
ThisallowsgreatpowersavingsduringSELFREFRESHduringmostoperatingtemperatureranges.
OnlyduringextremetemperatureswouldthecontrollerhavetoselectaTCSRlevelthatwillguaranteedataduringSELFREFRESH.
EverycellintheDRAMrequiresrefreshingduetothecapacitorlosingitschargeovertime.
Therefreshrateisdependentontemperature.
Athighertemperaturesacapacitorloseschargequickerthanatlowertemperatures,requiringthecellstoberefreshedmoreoften.
Historically,duringSelfRefresh,therefreshratehasbeensettoaccommodatetheworstcase,orhighesttemperaturerangeexpected.
Thus,duringambienttemperatures,thepowerconsumedduringrefreshwasunnecessarilyhigh,becausetherefreshratewassettoaccommodatethehighertemperatures.
ThistemperaturecompensatedrefreshratewillsavepowerwhentheDRAMisoperatingatnormaltemperatures.
ItisnotsupportedforanytemperaturegradewithTAabove+85C13Rev.
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comIS43/46LR16160HCommandsThefollowingCOMMANDSTruthTableandDMOperationTruthTableprovidequickreferenceofavailablecommands.
Thisisfollowedbyawrittendescriptionofeachcommand.
DeselectTheDESELECTfunction(/CSHIGH)preventsnewcommandsfrombeingexecutedbytheMobileDDRSDRAM.
TheMobileDDRSDRAMiseffectivelydeselected.
Operationsalreadyinprogressarenotaffected.
NOOperation(NOP)TheNOOPERATION(NOP)commandisusedtoinstructtheselectedDDRSDRAMtoperformaNOP(/CS=LOW,/RAS=/CAS=/WE=HIGH).
Thispreventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.
Operationsalreadyinprogressarenotaffected.
ActiveTheACTIVEcommandisusedtoopen(oractivate)arowinaparticularbankforasubsequentaccess.
ThevalueontheBA0,BA1inputsselectsthebank,andtheaddressprovidedoninputsA0–A12selectstherow.
Thisrowremainsactive(oropen)foraccessesuntilaPRECHARGEcommandisissuedtothatbank.
APRECHARGEcommandmustbeissuedbeforeopeningadifferentrowinthesamebank.
ReadTheREADcommandisusedtoinitiateaburstreadaccesstoanactiverow.
ThevalueontheBA0,BA1inputsselectsthebank,andtheaddressprovidedoninputsA0–A8selectsthestartingcolumnlocation.
ThevalueoninputA10determineswhetherornotautoprechargeisused.
Ifautoprechargeisselected,therowbeingaccessedwillbeprechargedattheendoftheREADburst;ifautoprechargeisnotselected,therowwillremainopenforsubsequentaccesses.
WriteTheWRITEcommandisusedtoinitiateaburstwriteaccesstoanactiverow.
ThevalueontheBA0,BA1inputsselectsthebank,andtheaddressprovidedoninputsA0-A8selectsthestartingcolumnlocation.
ThevalueoninputA10determineswhetherornotautoprechargeisused.
Ifautoprechargeisselected,therowbeingaccessedwillbeprechargedattheendoftheWRITEburst;ifautoprechargeisnotselected,therowwillremainopenforsubsequentaccesses.
InputdataappearingontheDQsiswrittentothememoryarraysubjecttotheDMinputlogiclevelappearingcoincidentwiththedata.
IfagivenDMsignalisregisteredLOW,thecorrespondingdatawillbewrittentomemory;iftheDMsignalisregisteredHIGH,thecorrespondingdatainputswillbeignored,andaWRITEwillnotbeexecutedtothatbyte/columnlocation.
PrechargeThePRECHARGEcommandisusedtodeactivatetheopenrowinaparticularbankortheopenrowinallbanks.
Thebank(s)willbeavailableforasubsequentrowaccessaspecifiedtime(tRP)aftertheprechargecommandisissued.
Exceptinthecaseofconcurrentautoprecharge,whereaREADorWRITEcommandtoadifferentbankisallowedaslongasitdoesnotinterruptthedatatransferinthecurrentbankanddoesnotviolateanyothertimingparameters.
InputA10determineswhetheroneorallbanksaretobeprecharged,andinthecasewhereonlyonebankistobeprecharged,inputsBA0,BA1selectthebank.
OtherwiseBA0,BA1aretreatedas"Don'tCare.
"Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITEcommandsbeingissuedtothatbank.
APRECHARGEcommandwillbetreatedasaNOPifthereisnoopenrowinthatbank(idlestate),orifthepreviouslyopenrowisalreadyintheprocessofprecharging.
14Rev.
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comIS43/46LR16160HAutoPrechargeAutoprechargeisafeaturewhichperformsthesameindividual-bankprechargefunctiondescribedabove,butwithoutrequiringanexplicitcommand.
ThisisaccomplishedbyusingA10toenableautoprechargeinconjunctionwithaspecificREADorWRITEcommand.
Aprechargeofthebank/rowthatisaddressedwiththeREADorWRITEcommandisautomaticallyperformeduponcompletionoftheREADorWRITEburst.
AutoprechargeisnonpersistentinthatitiseitherenabledordisabledforeachindividualREADorWRITEcommand.
Thisdevicesupportsconcurrentautoprechargeifthecommandtotheotherbankdoesnotinterruptthedatatransfertothecurrentbank.
Autoprechargeensuresthattheprechargeisinitiatedattheearliestvalidstagewithinaburst.
This"earliestvalidstage"isdeterminedasifanexplicitPRECHARGEcommandwasissuedattheearliestpossibletime,withoutviolatingtRAS(MIN).
Theusermustnotissueanothercommandtothesamebankuntiltheprechargetime(tRP)iscompleted.
BurstTerminateTheBURSTTERMINATEcommandisusedtotruncateREADbursts(withautoprechargedisabled).
ThemostrecentlyregisteredREADcommandpriortotheBURSTTERMINATEcommandwillbetruncated.
TheopenpagewhichtheREADburstwasterminatedfromremainsopen.
AutoRefreshAUTOREFRESHisusedduringnormaloperationoftheMobileDDRSDRAMandisanalogousto/CAS-BEFORE-/RAS(CBR)REFRESHinFPM/EDODRAMs.
Thiscommandisnonpersistent,soitmustbeissuedeachtimearefreshisrequired.
Theaddressingisgeneratedbytheinternalrefreshcontroller.
Thismakestheaddressbitsa"Don'tCare"duringanAUTOREFRESHcommand.
The256MbMobileDDRSDRAMrequiresAUTOREFRESHcyclesatanaverageintervaloftREFI(maximum).
Toallowforimprovedefficiencyinschedulingandswitchingbetweentasks,someflexibilityintheabsoluterefreshintervalisprovided.
AlthoughnotaJEDECrequirement,toprovideforfuturefunctionalityfeatures,CKEmustbeactive(HIGH)duringtheautorefreshperiod.
TheautorefreshperiodbeginswhentheAUTOREFRESHcommandisregisteredandendstRFClater.
SelfRefreshTheSELFREFRESHcommandcanbeusedtoretaindataintheMobileDDRSDRAM,eveniftherestofthesystemispowereddown.
Whenintheselfrefreshmode,theMobileDDRSDRAMretainsdatawithoutexternalclocking.
TheSELFREFRESHcommandisinitiatedlikeanAUTOREFRESHcommandexceptCKEisdisabled(LOW).
AllcommandandaddressinputsignalsexceptCKEare"Don'tCare"duringSELFREFRESH.
DuringSELFREFRESH,thedeviceisrefreshedasidentifiedintheexternalmoderegister(seePASRsetting).
Forathefullarrayrefresh,allfourbanksarerefreshedsimultaneouslywiththerefreshfrequencysetbyaninternalselfrefreshoscillator.
Thisoscillatorchangesduetothetemperaturesensorsinput.
AsthecasetemperatureoftheMobileDDRSDRAMincreases,theoscillationfrequencywillchangetoaccommodatethechangeoftemperature.
ThishappensbecausetheDRAMcapacitorslosechargefasterathighertemperatures.
Toensureefficientpowerdissipationduringselfrefresh,theoscillatorwillchangetorefreshattheslowestratepossibletomaintainthedevicesdata.
TheprocedureforexitingSELFREFRESHrequiresasequenceofcommands.
First,ClockmustbestablepriortoCKEgoingbackHIGH.
OnceCKEisHIGH,theMobileDDRSDRAMmusthaveNOPcommandsissuedfortXSRisrequiredforthecompletionofanyinternalrefreshinprogress.
TheSelfRefreshcommandisnotapplicableforoperationwithTA>85C.
DeepPower-downDeepPowerDownisanoperatingmodetoachievemaximumpowerreductionbyeliminatingthepowerofthewholememoryarrayofthedevices.
DatawillnotberetainedoncethedeviceentersDeepPowerDownMode.
Thismodeisenteredbyhavingallbanksidlethen/CSand/WEheldlowwith/RASand/CASheldhighattherisingedgeoftheclock,whileCKEislow.
ThismodeisexitedbyassertingCKEhigh.
AfterapplyingNOPcommandsfor200s,thepowerupandInitializationsequencemustbefollowed.
ThismodeisnotapplicableforoperationwithTA>85C.
15Rev.
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comIS43/46LR16160HS10S9S8RefreshMultipliers000Reserved001Reserved010Reserved0112x1001x101Reserved1100.
25x111ReservedS3S2S1S0ManufacturerID1011ISSIAllothersOthermanufacturersDataBus(DQ)DQ0DQ1DQ2DQ3DQ4DQ5DQ7DQ9Figure8:StatusRegisterRead(SRR)1514131211109876543210DensityDTDWRefreshMultiplierRevisionIDManufacturerModeRegister(Sx)StatusRegisterReadTheStatusRegisterRead(SRR)commandallowstheusertoaccessthemanfacturerdeviceinformation.
Itisoptionalfortheuser.
The16-bitencodeddataisstoredintheStatusRegister,andcanbeoutputontoDQ0~DQ15,withafixedburstlength(BL)of2.
TheManufacturer'sIDisonS0~S3,theDeviceRevisionIDisonS4~S7,theRefreshRateisonS8~S10,theDataWidthisonS11,theDeviceTypeisonS12,andtheDensityisonS13~S15.
TheSRRcommandsequenceisasfollows:Allbanksmustbeidle,andReadsandWritescompletedAModeRegisterSet(MRS)commandisissuedwithBA0=1,BA1=0,andA0~A12=0toinitiateSRRAfteratimeperiodtSRR,aReadcommandisissuedtoanybankoraddressThenextvalidcommandmaybeissuedatimeperiodtSRCaftertheReadcommandTheReadcommandcausestheStatusRegisterdatatobeoutputaftertwoorthreeclockcycles,whichevercorrespondstotheCASLatencysetting.
InthesecondhalfoftheReadburst,theDQ0~DQ15valuesare"Don'tCare".
DQ6DQ8DQ10DQ11DQ12DQ13DQ14DQ15S11DeviceWidth0x161x32S12DeviceType0mDDR1LPDDR2S15S14S13Density000128Mb001256Mb010512Mb0111Gb1002Gb101Reserved110Reserved111Reserved16Rev.
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comIS43/46LR16160HNote:1.
Allstatesandsequencesnotshownareillegalorreserved.
2.
DESLECTandNOParefunctionallyinterchangeable.
3.
Autoprechargeisnon-persistent.
A10HighenablesAutoprecharge,whileA10LowdisablesAutoprecharge4.
BurstTerminateappliestoonlyReadburstswithautoprechargedisabled.
ThiscommandisundefinedandshouldnotbeusedforReadwithAutoprechargeenabled,andforWritebursts.
5.
ThiscommandisBURSTTERMINATEifCKEisHighandDEEPPOWERDOWNentryifCKEisLow.
6.
IfA10islow,bankaddressdetermineswhichbankistobeprecharged.
IfA10ishigh,allbanksareprechargedandBA0-BA1aredon'tcare.
7.
ThiscommandisAUTOREFRESHifCKEisHigh,andSELFREFRESHifCKEislow.
8.
AlladdressinputsandI/Oare''don'tcare''exceptforCKE.
InternalrefreshcounterscontrolBankandRowaddressing.
9.
AllbanksmustbeprechargedbeforeissuinganAUTO-REFRESHorSELFREFRESHcommand.
10.
BA0andBA1valueselectamongModeRegister(MRS),ExtendedModeRegister(EMRS),orStatusRegisterRead(SRR).
11.
Usedtomaskwritedata,providedcoincidentwiththecorrespondingdata.
12.
CKEisHIGHforallcommandsshownexceptSELFREFRESHandDEEPPOWER-DOWN.
Function/CS/RAS/CAS/WEBAA10/APADDRNoteDESELECT(NOP)HXXXXXX2NOOPERATION(NOP)LHHHXXX2ACTIVE(SelectBankandactivateRow)LLHHVRowRowREAD(Selectbankandcolumnandstartreadburst)LHLHVLColREADwithAP(ReadBurstwithAutorecharge)LHLHVHCol3WRITE(Selectbankandcolumnandstartwriteburst)LHLLVLColWRITEwithAP(WriteBurstwithAutorecharge)LHLLVHCol3BURSTTERMINATEorenterDEEPPOWERDOWNLHHLXXX4,5PRECHARGE(DeactivateRowinselectedbank)LLHLVLX6PRECHARGEALL(Deactivaterowsinallbanks)LLHLXHX6AUTOREFRESHorenterSELFREFRESHLLLHXXX7,8,9MODEREGISTERSETLLLLVOp_Code10FunctionDMDQNoteWriteEnableLValid11WriteInhibitHX11Table5:DMTruthTableTable4:CommandTruthTable17Rev.
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comIS43/46LR16160HNote:1.
CKEnisthelogicstateofCKEatclockedgen;CKEn-1wasthestateofCKEatthepreviousclockedge.
2.
CurrentstateisthestateofMobileDDRimmediatelypriortoclockedgen.
3.
COMMANDnisthecommandregisteredatclockedgen,andACTIONnistheresultofCOMMANDn.
4.
Allstatesandsequencesnotshownareillegalorreserved.
5.
DESELECTandNOParefunctionallyinterchangeable.
6.
PowerDownexittime(tXP)shouldelapsebeforeacommandotherthanNOPorDESELECTisissued.
7.
SELFREFRESHexittime(tXSR)shouldelapsebeforeacommandotherthanNOPorDESELECTisissued.
8.
TheDeepPower-DownexitproceduremustbefollowedasdiscussedintheDeepPower-DownsectionoftheFunctionalDescription.
9.
TheclockmusttoggleatleastonetimeduringthetXPperiod.
10.
TheclockmusttoggleatleastonceduringthetXSRtime.
SeetheotherTruthTablesHHEnterDeepPowerDownBURSTTERMINATEAllBanksIdleLHSelfRefreshEntryAUTOREFRESHAllBanksIdleLH5ActivePowerDownEntryNOPorDESELECTBank(s)ActiveLH5PrechargePowerDownentryNOPorDESELECTAllBanksIdleLH5,8ExitDeepPowerDownNOPorDESELECTDeepPowerDownHL5,7,10ExitSelfRefreshNOPorDESELECTSelfRefreshHL5,6,9ExitPowerDownNOPorDESELECTPowerDownHLMaintainDeepPowerDownXDeepPowerDownLLMaintainSelfRefreshXSelfRefreshLLMaintainPowerDownXPowerDownLLNoteACTIONnCOMMANDnCurrentStateCKEnCKEn-1Table6:CKETruthTable18Rev.
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comIS43/46LR16160HNote:1.
ThetableapplieswhenbothCKEn-1andCKEnareHIGH,andaftertXSRortXPhasbeenmetifthepreviousstatewasSelfRefreshorPowerDown.
2.
DESELECTandNOParefunctionallyinterchangeable.
3.
Allstatesandsequencesnotshownareillegalorreserved.
4.
Thiscommandmayormaynotbebankspecific.
Ifallbanksarebeingprecharged,theymustbeinavalidstateforprecharging.
5.
AcommandotherthanNOPshouldnotbeissuedtothesamebankwhileaREADorWRITEBurstwithautoprechargeisenabled.
6.
ThenewReadorWritecommandcouldbeautoprechargeenabledorautoprechargedisabled.
7.
CurrentStateDefinitions:Idle:Thebankhasbeenprecharged,andtRPhasbeenmet.
RowActive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.
Nodatabursts/accessesandnoregisteraccessesareinprogress.
Read:AREADbursthasbeeninitiated,withAUTOPRECHARGEdisabled,andhasnotyetterminatedorbeenterminated.
Write:aWRITEbursthasbeeninitiated,withAUTOPRECHARGEdisabled,andhasnotyetterminatedorbeenterminated.
8.
Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.
DESELECTorNOPcommandsorallowablecommandstotheotherbankshouldbeissuedonanyclockedgeoccurringduringthesestates.
AllowablecommandstotheotherbankaredeterminedbyitscurrentstateandTruthTable3,andaccordingtoTruthTable4.
Precharging:StartswiththeregistrationofaPRECHARGEcommandandendswhentRPismet.
OncetRPismet,thebankwillbeintheidlestate.
RowActivating:StartswithregistrationofanACTIVEcommandandendswhentRCDismet.
OncetRCDismet,thebankwillbeinthe''rowactive''state.
ReadwithAPEnabled:StartswiththeregistrationoftheREADcommandwithAUTOPRECHARGEenabledandendswhentRPhasbeenmet.
OncetRPhasbeenmet,thebankwillbeintheidlestate.
WritewithAPEnabled:StartswithregistrationofaWRITEcommandwithAUTOPRECHARGEenabledandendswhentRPhasbeenmet.
OncetRPismet,thebankwillbeintheidlestate.
Table7:CurrentStateBANKnTruthTable(COMMANDTOBANKn)CurrentStateCommandActionNote/CS/RAS/CAS/WEDescriptionAnyHXXXDESELECT(NOP)ContinuepreviousOperationLHHHNOPContinuepreviousOperationIdleLLHHACTIVESelectandactivaterowLLLHAUTOREFRESHAutorefresh10LLLLMODEREGISTERSETModeregisterset10LLHHPRECHARGENoactionifbankisidleRowActiveLHLHREADSelectColumn&startreadburstLHLLWRITESelectColumn&startwriteburstLLHLPRECHARGEDeactivateRowinbank(orbanks)4Read(withoutAutorecharge)LHLHREADTruncateRead&startnewReadburst5,6LHLLWRITETruncateRead&startnewWriteburst5,6,13LLHLPRECHARGETruncateRead,startPrechargeLHHLBURSTTERMINATEBurstterminate11Write(withoutAutoprecharge)LHLHREADTruncateWrite&startnewReadburst5,6,12LHLLWRITETruncateWrite&startnewWriteburst5,6LLHLPRECHARGETruncateWrite,startPrecharge1219Rev.
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comIS43/46LR16160H9.
Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;DESELECTorNOPcommandsmustbeappliedtoeachpositiveclockedgeduringthesestates.
Refreshing:StartswithregistrationofanAUTOREFRESHcommandandendswhentRFCismet.
OncetRFCismet,theMobileDDRwillbeinan''allbanksidle''state.
AccessingModeRegister:StartswithregistrationofaMODEREGISTERSETcommandandendswhentMRDhasbeenmet.
OncetMRDismet,theMobileDDRwillbeinan''allbanksidle''state.
PrechargingAll:StartswiththeregistrationofaPRECHARGEALLcommandandendswhentRPismet.
OncetRPismet,thebankwillbeintheidlestate.
10.
Notbank-specific;requiresthatallbanksareidleandnoburstsareinprogress.
11.
Notbank-specific.
BURSTTERMINATEaffectsthemostrecentREADburst,regardlessofbank.
12.
RequiresappropriateDMmasking.
13.
AWRITEcommandmaybeappliedafterthecompletionoftheREADburst;otherwise,aBurstterminatemustbeusedtoendtheREADpriortoassertingaWRITEcommand.
20Rev.
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comIS43/46LR16160HTable8:CurrentStateBANKnTruthTable(COMMANDTOBANKm)CurrentStateCommandActionNote/CS/RAS/CAS/WEDescriptionAnyHXXXDESELECT(NOP)ContinuepreviousOperationLHHHNOPContinuepreviousOperationIdleXXXXANYAnycommandallowedtobankmRowActivating,Active,orPrechargingLLHHACTIVEActivateRowLHLHREADStartREADburst8LHLLWRITEStartWRITEburst8LLHLPRECHARGEPrechargeReadwithAutoPrechargedisabledLLHHACTIVEActivateRowLHLHREADStateREADburst8LHLLWRITEStartWRITEburst8,10LLHLPRECHARGEPrechargeWritewithAutoprechargedisabledLLHHACTIVEActivateRowLHLHREADStartREADburst8,9LHLLWRITEStartWRITEburst8LLHLPRECHARGEPrechargeReadwithAutoPrechargeLLHHACTIVEActivateRowLHLHREADStartREADburst5,8LHLLWRITEStartWRITEburst5,8,10LLHLPRECHARGEPrechargeWritewithAutoprechargeLLHHACTIVEActivateRowLHLHREADStartREADburst5,8LHLLWRITEStartWRITEburst5,8LLHLPRECHARGEPrecharge21Rev.
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comIS43/46LR16160HNote:1.
ThetableapplieswhenbothCKEn-1andCKEnareHIGH,andaftertXSRortXPhasbeenmetifthepreviousstatewasSelfRefreshorPowerDown.
2.
DESELECTandNOParefunctionallyinterchangeable.
3.
Allstatesandsequencesnotshownareillegalorreserved.
4.
CurrentStateDefinitions:Idle:Thebankhasbeenprecharged,andtRPhasbeenmet.
RowActive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.
Nodatabursts/accessesandnoregisteraccessesareinprogress.
Read:AREADbursthasbeeninitiated,withAUTOPRECHARGEdisabled,andhasnotyetterminatedorbeenterminated.
Write:aWRITEbursthasbeeninitiated,withAUTOPRECHARGEdisabled,andhasnotyetterminatedorbeenterminated.
5.
ReadwithAPenabledandWritewithAPenabled:ThereadwithAutoprechargeenabledorWritewithAutoprechargeenabledstatescanbebrokenintotwoparts:theaccessperiodandtheprechargeperiod.
ForReadwithAP,theprechargeperiodisdefinedasifthesameburstwasexecutedwithAutoPrechargedisabledandthenfollowedwiththeearliestpossiblePRECHARGEcommandthatstillaccessesallthedataintheburst.
ForWritewithAutoprecharge,theprechargeperiodbeginswhentWRends,withtWRmeasuredasifAutoPrechargewasdisabled.
Theaccessperiodstartswithregistrationofthecommandandendswheretheprechargeperiod(ortRP)begins.
Duringtheprechargeperiod,oftheReadwithAutoprechargeenabledorWritewithAutoprechargeenabledstates,ACTIVE,PRECHARGE,READ,andWRITEcommandstotheotherbankmaybeapplied;duringtheaccessperiod,onlyACTIVEandPRECHARGEcommandstotheotherbanksmaybeapplied.
Ineithercase,allotherrelatedlimitationsapply(e.
g.
contentionbetweenREADdataandWRITEdatamustbeavoided).
6.
AUTOREFRESH,SELFREFRESH,andMODEREGISTERSETcommandsmayonlybeissuedwhenallbankareidle.
7.
ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;Itappliestothebankrepresentedbythecurrentstateonly.
8.
READsorWRITEslistedintheCommandcolumnincludeREADsandWRITEswithAUTOPRECHARGEenabledandREADsandWRITEswithAUTOPRECHARGEdisabled.
9.
RequiresappropriateDMmasking.
10.
AWRITEcommandmaybeappliedafterthecompletionofdataoutput,otherwiseaBURSTTERMINATEcommandmustbeissuedtoendtheREADpriortoassertingaWRITEcommand.
22Rev.
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comIS43/46LR16160HTable9:AbsoluteMaximumRatingParameterSymbolRatingUnitStorageTemperatureTSTG-55~150CVoltageonAnyPinrelativetoVSSVIN,VOUT-0.
3~2.
7VVoltageonVDDrelativetoVSSVDD,VDDQ-0.
3~2.
7VShortCircuitOutputCurrentIOS50mAPowerDissipationPD0.
7WNote:Stressesgreaterthanthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.
Thisisastressratingonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
Table10:OperatingTemperatureParameterSymbolMinTypMaxUnitNotePowerSupplyVoltageVDD1.
71.
81.
95VPowerSupplyVoltageVDDQ1.
71.
81.
95V2InputHighVoltageVIH(DC)0.
7xVDDQVDDQ+0.
3VInputLowVoltageVIL(DC)-0.
30.
3xVDDQVInputDifferentialVoltage,forCK,/CKinputsVID(DC)0.
4xVDDQVDDQ+0.
6V3OutputHighVoltageVOH(DC)0.
9xVDDQ-VIOH=-0.
1mAOutputLowVoltageVOL(DC)-0.
1xVDDQVIOL=0.
1mAInputLeakageCurrentILI-22uAOutputLeakageCurrentILO-55uAInputHighVoltage,allinputsVIH(AC)0.
8xVDDQVDDQ+0.
3VInputLowVoltage,allinputsVIL(AC)-0.
30.
2xVDDQVInputDifferentialVoltage,forCK,/CKinputsVID(AC)0.
6xVDDQVDDQ+0.
6V3InputDifferentialCrosspointVoltageforCKand/CKinputsVIX(AC)0.
4xVDDQ0.
6xVDDQV4Table11:AC/DCOperatingConditions(1)Notes:1.
AllVoltagesarereferencedtoVSS=0V2.
VDDandVDDQmusttrackeachother,andVDDQmustnotexceedthelevelofVDD.
3.
ThemagnitudeofdifferencebetweeninputlevelonCKandinputlevelon/CK.
4.
ThevalueofVIXisexpectedtoequal0.
5*VDDQofthetransmittingdeviceandmusttrackvariationsintheDClevelofthesame.
ParameterSymbolRatingUnitAmbientTemperature(Automotive,A2)TA-40~105CAmbientTemperature(Automotive,A1)-40~85AmbientTemperature(Industrial)-40~85AmbientTemperature(Commercial)0~7023Rev.
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comIS43/46LR16160HTable13:ACOperatingTestConditionParameterSymbolValueUnitACInputHigh/LowLevelVoltageVIH/VIL0.
8xVDDQ/0.
2xVDDQVInputTimingMeasurementReferenceLevelVoltageVTRIP0.
5xVDDQVInputRise/FallTimetR/tF1/1nsOutputTimingMeasurementReferenceLevelVoltageVOUTREF0.
5xVDDQVOutputLoadCapacitanceforAccessTimeMeasurementCL20pFFigure10:OutputloadcircuitTable12:Capacitance(TA=25C,f=1MHz,VDD=1.
8V)ParameterPinSymbolMinMaxUnitInputCapacitanceCK,/CKCI11.
57.
0pFA0~A12,BA0~BA1,CKE,/CS,/RAS,/CAS,/WECI21.
56.
0pFDM0~DM3CI324.
5pFData&DQSInput/OutputCapacitanceDQ0~DQ31,DQS0~DQS3CIO24.
5pFTable14:ACOvershoot/UndershootSpecificationParameterSpecificationMaximumPeakAmplitudeallowedforOvershootArea0.
9VMaximumPeakAmplitudeallowedforUndershootArea0.
9VMaximumOvershootAreaaboveVDD/VDDQ3V-nsMaximumUndershootAreabelowVSS/VSSQ3V-nsFigure11:ACOvershoot/UndershootDefinitionMaximumAmplitudeVDD/VDDQVSS/VSSQVoltage[V]MaximumAmplitudeTime[ns]OvershootAreaUndershootArea10.
6K13.
9KVDDQ20pFOutput20pF50VTT=0.
5xVDDQZ0=50DCOutputLoadCircuitACOutputLoadCircuit24Rev.
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comIS43/46LR16160HTable15B:DCCharacteristic(DCoperatingconditionsunlessotherwisenoted)Note:1.
Measuredwithoutputsopen2.
Refreshperiodis64ms,applicableforTA0tRC=tRC(min),tCK=tCK(min),CKEisHIGH,/CSisHIGHbetweenvalidcommands,addressinputsareSWITCHING,databusinputsareSTABLE655550mA1Prechargepower-downstandbycurrentIDD2PAllbanksidle,CKEisLOW,/CSisHIGH,tCK=tCK(min),addressandcontrolinputsareSWITCHING,databusinputsareSTABLE300APrechargepower-downstandbycurrentwithclockstopIDD2PSAllbanksidle,CKEisLOW,/CSisHIGH,CK=LOW,/CK=HIGH,addressandcontrolinputsareSWITCHING,databusinputsareSTABLE300APrechargenonpower-downstandbycurrentIDD2NAllbanksidle,CKEisHIGH,/CSisHIGH,tCK=tCK(min),addressandcontrolinputsareSWITCHING,databusinputsareSTABLE12mAPrechargenonpower-downstandbycurrentwithclockstopIDD2NSAllbanksidle,CKEisHIGH,/CSisHIGH,CK=LOW,/CK=HIGH,addressandcontrolinputsareSWITCHING,databusinputsareSTABLE6mAActivepower-downstandbycurrentIDD3POnebankactive,CKEisLOW,/CSisHIGH,tCK=tCK(min),addressandcontrolinputsareSWITCHING,databusinputsareSTABLE10mAActivepower-downstandbycurrentwithclockstopIDD3PSOnebankactive,CKEisLOW,/CSisHIGH,CK=LOW,/CK=HIGH,addressandcontrolinputsareSWITCHING,databusinputsareSTABLE10mAActivenonpower-downstandbycurrentIDD3NOnebankactive,CKEisHIGH,/CSisHIGH,tCK=tCK(min),addressandcontrolinputsareSWITCHING,databusinputsareSTABLE30mAActivenonpower-downstandbycurrentwithclockstopIDD3NSOnebankactive,CKEisHIGH,/CSisHIGH,CK=LOW,/CK=HIGH,addressandcontrolinputsareSWITCHING,databusinputsareSTABLE15mAOperatingburstreadcurrentIDD4ROnebankactive,BL=4,CL=3,tCK=tCK(min),continuousreadbursts,IOUT=0mA,addressinputsareSWITCHING,50%datachangeeachbursttransfer1009080mA1OperatingburstwritecurrentIDD4WOnebankactive,BL=4,tCK=tCK(min),continuouswritebursts,addressinputsareSWITCHING,50%datachangeeachbursttransfer555045mA1AutoRefreshCurrentIDD5tRC=tRFC(min),tCK=tCK(min),burstrefresh,CKEisHIGH,addressandcontrolinputsareSWITCHING,databusinputsareSTABLE80mA2SelfRefreshCurrentPASRTCSRIDD6CKEisLOWCK=LOW,/CK=HIGHtCK=tCK(min)ExtendedModeRegistersettoall0's,addressandcontrolinputsareSTABLE,databusinputsareSTABLEuA4banks85C50045C4502Banks85C48045C4401Bank85C46045C430HalfBank85C44045C410QuarterBank85C42045C400StandbyCurrentinDeepPowerDownModeIDD8AddressandcontrolinputsareSTABLE,databusinputsareSTABLE30uA425Rev.
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comIS43/46LR16160HParameterSymbol-5UnitNoteMinMaxSystemClockCycletimeCL=3tCK51000ns1CL=210ns1DQOutputaccesstimefromCK,/CKCL=3tAC2.
05.
0nsCL=22.
08.
0ClockHighpulsewidthtCH0.
450.
55tCKClockLowpulsewidthtCL0.
450.
55tCKCKEmin.
pulsewidth(High/Lowpulsewidth)tCKE1tCKDQandDMInputSetuptimetDS0.
48ns2,3,4DQandDMInputHoldtimetDH0.
48ns2,3,4DQandDMInputPulsewidthtDIPW1.
6ns5AddressandControlInputSetuptimetIS0.
9ns4,6,7AddressandControlInputHoldtimetIH0.
9ns4,6,7AddressandControlInputPulseWidthtIPW2.
3ns5DQ&DQSLow-impedancetimefromCK,/CKtLZ1.
0ns8DQ&DQSHigh-impedancetimefromCK,/CKtHZ5.
0ns8DQS-DQSkewtDQSQ0.
4ns9HalfClockPeriodtHPtCH,tCLnsDataHoldSkewFactortQHS0.
5nsDQ/DQSOutputHoldtimefromDQStQHtHP-tQHSnsWriteCommandtofirstDQSLatchingTransitiontDQSS0.
751.
25tCKDQSInputHighpulseWidthtDQSH0.
350.
6tCKDQSInputLowpulseWidthtDQSL0.
350.
6tCKDQSFallingEdgetoCKSetupTimetDSS0.
2tCKDQSFallingEdgeHoldTimeFromCKtDSH0.
2tCKAccessWindowofDQSfromCK,/CKCL=3tDQSCK2.
05.
0nsCL=22.
08.
0nsACTIVEtoPRECHARGECommandPeriodtRAS40nsACTIVEtoACTIVECommandPeriodtRC55nsModeRegisterSetcommandcycletimetMRD2tCKSRRtoReadtSRR2tCKReadofSRRtonextvalidcommandtSRCCL+1tCKRefreshPeriodtREF64ms15AverageperiodicrefreshintervaltREFI7.
8us10,15AutoRefreshPeriodtRFC80nsActivetoReadorWritedelaytRCD15nsPrechargecommandperiodtRP15nsActiveBankAtoActiveBankBDelaytRRD10nsWriteRecoverytimetWR15nsAutoPrechargeWriteRecovery+PrechargetimetDAL(tWR/tCK)+(tRP/tCK)InternalWritetoReadCommandDelaytWTR1tCKDQSReadpreambleCL=3tRPRE0.
91.
1tCK11CL=20.
51.
1tCK11DQSReadpostambletRPST0.
40.
6tCKDQSWritepreambletWPRE0.
25tCKDQSWritepreamblesetuptimetWPRES0ns12DQSWritepostambletWPST0.
40.
6tCK13ExitPowerDowntonextvalidcommandDelaytXP1tCK14SelfRefreshExittonextvalidCommandDelaytXSR120nsTable16:ACCharacteristic(ACoperationconditionsunlessotherwisenoted)26Rev.
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comIS43/46LR16160HParameterSymbol-6-75UnitNoteMinMaxMinMaxSystemClockCycletimeCL=3tCK610007.
51000ns1CL=21010ns1DQOutputaccesstimefromCK,/CKCL=3tAC2.
05.
52.
06.
0nsCL=22.
08.
02.
08.
0ClockHighpulsewidthtCH0.
450.
550.
450.
55tCKClockLowpulsewidthtCL0.
450.
550.
450.
55tCKCKEmin.
pulsewidth(High/Lowpulsewidth)tCKE11tCKDQandDMInputSetuptimetDS0.
60.
9ns2,3,4DQandDMInputHoldtimetDH0.
60.
9ns2,3,4DQandDMInputPulsewidthtDIPW1.
82.
0ns5AddressandControlInputSetuptimetIS1.
01.
3ns4,6,7AddressandControlInputHoldtimetIH1.
01.
3ns4,6,7AddressandControlInputPulseWidthtIPW2.
73.
0ns5DQ&DQSLow-impedancetimefromCK,/CKtLZ1.
01.
0ns8DQ&DQSHigh-impedancetimefromCK,/CKtHZ5.
56ns8DQS-DQSkewtDQSQ0.
50.
6ns9HalfClockPeriodtHPtCH,tCLtCH,tCLnsDataHoldSkewFactortQHS0.
650.
75nsDQ/DQSOutputHoldtimefromDQStQHtHP-tQHStHP-tQHSnsWriteCommandtofirstDQSLatchingTransitiontDQSS0.
751.
250.
751.
25tCKDQSInputHighpulseWidthtDQSH0.
350.
60.
40.
6tCKDQSInputLowpulseWidthtDQSL0.
350.
60.
40.
6tCKDQSFallingEdgetoCKSetupTimetDSS0.
20.
2tCKDQSFallingEdgeHoldTimeFromCKtDSH0.
20.
2tCKAccessWindowofDQSfromCK,/CKCL=3tDQSCK2.
05.
52.
06.
0nsCL=22.
08.
02.
08.
0nsACTIVEtoPRECHARGECommandPeriodtRAS4245nsACTIVEtoACTIVECommandPeriodtRC6075nsModeRegisterSetcommandcycletimetMRD22tCKSRRtoReadtSRR22tCKReadofSRRtonextvalidcommandtSRCCL+1CL+1tCKRefreshPeriodtREF6464ms15AverageperiodicrefreshintervaltREFI7.
87.
8us10,15AutoRefreshPeriodtRFC8080nsActivetoReadorWritedelaytRCD1822.
5nsPrechargecommandperiodtRP1822.
5nsActiveBankAtoActiveBankBDelaytRRD1215nsWriteRecoverytimetWR1515nsAutoPrechargeWriteRecovery+PrechargetimetDAL(tWR/tCK)+(tRP/tCK)InternalWritetoReadCommandDelaytWTR11tCKDQSReadpreambleCL=3tRPRE0.
91.
10.
91.
1tCK11CL=20.
51.
10.
51.
1tCK11DQSReadpostambletRPST0.
40.
60.
40.
6tCKDQSWritepreambletWPRE0.
250.
25tCKDQSWritepreamblesetuptimetWPRES00ns12DQSWritepostambletWPST0.
40.
60.
40.
6tCK13ExitPowerDowntonextvalidcommandDelaytXP11tCK14SelfRefreshExittonextvalidCommandDelaytXSR120120nsTable16:ACCharacteristic(ACoperationconditionsunlessotherwisenoted)27Rev.
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comIS43/46LR16160HNote:1.
Theclockfrequencymustremainconstant(stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfortheclockpin)duringaccessorprechargestates(READ,WRITE,includingtDPL,andPRECHARGEcommands).
CKEmaybeusedtoreducethedatarate.
2.
ThetransitiontimeforDQ,DMandDQSinputsismeasuredbetweenVIL(DC)toVIH(AC)forrisinginputsignals,andVIH(DC)toVIL(AC)forfallinginputsignals.
3.
DQS,DMandDQinputslewrateisspecifiedtopreventdoubleclockingofdataandpreservesetupandholdtimes.
SignaltransitionsthroughtheDCregionmustbemonotonic.
4.
Inputslewrate≥0.
5V/nsand0V/ns.
5.
Theseparametersguaranteedevicetimingbuttheyarenotnecessarilytestedoneachdevice.
6.
ThetransitiontimeforaddressandcommandinputsismeasuredbetweenVIHandVIL.
7.
ACK,/CKslewratemustbe≥1.
0V/ns(2.
0V/nsifmeasureddifferentially)isassumedforthisparameter.
8.
tHZandtLZtransitionsoccurinthesameaccesstimewindowsasvaliddatatransitions.
Theseparametersarenotreferredtoaspecificvoltagelevel,butspecifywhenthedeviceisnolongerdriving(HZ),orbeginsdriving(LZ).
9.
tDQSQconsistsofdatapinskewandoutputpatterneffects,andp-channelton-channelvariationoftheoutputdriversforanygivencycle.
10.
AmaximumofeightRefreshcommandscanbepostedtoanygivenLow-PowerDDRSDRAM,meaningthatthemaximumabsoluteintervalbetweenanyRefreshcommandandthenextRefreshcommandis8*tREFI.
11.
AlowlevelonDQSmaybemaintainedduringHigh-Zstates(DQSdriversdisabled)byaddingaweakpull-downelementinthesystem.
Itisrecommendedtoturnofftheweakpull-downelementduringreadandwritebursts(DQSdriversenabled).
12.
ThespecificrequirementisthatDQSbevalid(HIGH,LOW,orsomepointonavalidtransition)onorbeforethisCKedge.
Avalidtransitionisdefinedasmonotonicandmeetingtheinputslewratespecificationsofthedevice.
Whennowriteswerepreviouslyinprogressonthebus,DQSwillbetransitioningfromHi-ZtologicLOW.
Ifapreviouswritewasinprogress,DQScouldbeHIGH,LOW,ortransitioningfromHIGHtoLOWatthistime,dependingontDQSS.
13.
Themaximumlimitforthisparameterisnotadevicelimit.
Thedeviceoperateswithagreatervalueforthisparameter,butsystemperformance(busturnaround)willdegradeaccordingly.
14.
AtleastoneclockpulseisrequiredduringtXP.
15.
ThespecificationsinthetableforTREFandTREFIareapplicableforalltemperaturegradeswithTA85C,andthesevaluesmustbefurtherconstrainedwithTREFmaxof32ms,andTREFImaxof3.
9s.
Inputsetup/holdslewrate[V/ns]tDS/tIS[ps]tDH/tIH[ps]1.
0000.
5+150+150CK,/CKsetup/holdslewrate[V/ns]tDS/tIS[ps]tDH/tIH[ps]1.
00028Rev.
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comIS43/46LR16160HTimingDiagramBank/rowActivationTheActivecommandisusedtoactivatearowinparticularbankforasubsequentReadorWriteaccess.
ThevalueoftheBA0,BA1inputsselectsthebank,andtheaddressprovidedonA0-A12(orthehighestaddressbit)selectstherow.
BeforeanyREADorWRITEcommandscanbeissuedtoabankwithintheMobileDDRSDRAM,arowinthatbankmustbeopened.
ThisisaccomplishedviatheACTIVEcommand,whichselectsboththebankandtherowtobeactivated.
TherowremainsactiveuntilaPRECHARGE(orREADwithAUTOPRECHARGEorWRITEwithAUTOPRECHARGE)commandisissuedtothebank.
APRECHARGE(orREADwithAUTOPRECHARGEorWRITEwithAUTOPRECHARGE)commandmustbeissuedbeforeopeningadifferentrowinthesamebank.
Figure12:tRCD,tRRD,tRCOncearowisOpen(withanACTIVEcommand)aREADorWRITEcommandmaybeissuedtothatrow,subjecttothetRCDspecification.
tRCD(min)shouldbedividedbytheclockperiodandroundeduptothenextwholenumbertodeterminetheearliestclockedgeaftertheACTIVEcommandonwhichaREADorWRITEcommandcanbeentered.
AsubsequentACTIVEcommandtoadifferentrowinthesamebankcanonlybeissuedafterthepreviousactiverowhasbeenclosed(precharge).
TheminimumtimeintervalbetweensuccessiveACTIVEcommandstothesamebankisdefinedbytRC.
AsubsequentACTIVEcommandtoanotherbankcanbeissuedwhilethefirstbankisbeingaccessed,whichresultsinareductionoftotalrow-accessoverhead.
TheminimumtimeintervalbetweensuccessiveACTIVEcommandstodifferentbanksisdefinedbytRRD.
Figure11:ActivecommandNotes:1.
RA:Rowaddress2.
BA:BankaddressCLK/CLKCKE/CS/RAS/CAS/WERABAA0~A12BA0,BA1Don'tcareRD/WTwithAPACTNOPNOPNOPBankaROWACTNOP/CLKCLKCommandT0T1T2T3A0-A12BA0,BA1COLBankaT4Ta0Ta1tRCDDon'tcareROWBankbtRRDBankaROWACTtRCTa2tCHtCLtIStIHtCK29Rev.
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comIS43/46LR16160HReadTheREADcommandisusedtoinitiateaBurstReadtoanactiverow.
ThevalueofBA0andBA1selectsthebankandaddressinputsselectthestartingcolumnlocation.
ThevalueofA10determineswhetherornotauto-prechargeisused.
Ifauto-prechargeisselected,therowbeingaccessedwillbeprechargedattheendofthereadburst;ifautoprechargeisnotselected,therowwillremainopenforsubsequentaccess.
Thevaliddata-outelementswillbeavailableCASlatencyaftertheREADcommandisissued.
TheMobileDDRdrivestheDQSduringreadoperations.
TheinitiallowstateoftheDQSisknownasthereadpreambleandthelastdata-outelementiscoincidentwiththereadpostamble.
DQSisedge-alignedwithreaddata.
Uponcompletionofaburst,assumingnonewREADcommandshavebeeninitiated,theI/O'swillgohigh-Z.
Figure13:ReadcommandNotes:1.
CA:Columnaddress2.
BA:Bankaddress3.
A10=High:EnableAutoprechargeA10=Low:DisableAutoprechargeFigure14:ReadDataouttiming(BL=4)Notes:1.
BL=42.
ShownwithnominaltAC,tDQSCKandtDQSQCLK/CLKCKE/CS/RAS/CAS/WECAA0~A8A10BABA0,BA1Don'tcareBankaCOLn/CLKCLKCommandT0T1T2T3T1nT2nT3nREADNOPNOPNOPDQSDQCL=3DOUTn+1tRPRET4T4nNOPtRPSTDOUTnDOUTn+2DOUTn+3Don'tcareAddresstACtDQSCKtQHtLZtHZtDQSQDQSDQCL=2DOUTn+1DOUTnDOUTn+2DOUTn+3tRPREtACtRPST30Rev.
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comIS43/46LR16160HFigure15:ConsecutiveReadbursts(BL=4)Figure16:Non-ConsecutiveReadbursts(BL=4)Notes:1.
Doutnorm=Data-OutfromColumnnorm2.
BL=4,8,16(if4,theburstsareconcatenated;If8or16,thesecondburstinterruptsthefirst)3.
ShownwithnominaltAC,tDQSCKandtDQSQNotes:1.
Doutnorm=Data-OutfromColumnnorm2.
BL=4,8,16(if4,theburstsareconcatenated;If8or16,thesecondburstinterruptsthefirst)3.
ShownwithnominaltAC,tDQSCKandtDQSQDOUTmBankaCOLmBankaCOLnNOPREADNOPNOPNOPREADT0T1T2T3AddressT4T5/CLKCLKDQCL=3CommandDQSDon'tcareDOUTn+1DOUTnDOUTn+2DOUTn+3DOUTm+1BankaCOLmBankaCOLnNOPREADNOPNOPNOPREADT0T1T2T3AddressT4T5/CLKCLKDQCL=3CommandDQSDon'tcareDOUTn+1DOUTnDOUTn+2DOUTn+3CL=3NOPDOUTmDOUTm+131Rev.
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comIS43/46LR16160HFigure18:ReadBurstterminate(BL=4,8or16)TruncatedReadsDatafromanyREADburstmaybetruncatedwithaBURSTTERMINATEcommand,asshowninFigure16.
TheBURSTTERMINATElatencyisequaltotheREAD(CAS)latency,i.
e.
,theBURSTTERMINATEcommandshouldbeissuedxcyclesaftertheREADcommand,wherexequalsthenumberofdesireddataelementpairs(pairsarerequiredbythe2n-prefetcharchitecture).
DatafromanyREADburstmustbecompletedortruncatedbeforeasubsequentWRITEcommandcanbeissued.
Iftruncationisnecessary,theBURSTTERMINATEcommandmustbeused.
AREADburstmaybefollowedby,ortruncatedwith,aPRECHARGEcommandtothesamebankprovidedthatautoprechargewasnotactivated.
ThePRECHARGEcommandshouldbeissuedxcyclesaftertheREADcommand,wherexequalsthenumberofdesireddataelementpairs(pairsarerequiredbythen-prefetcharchitecture).
ThisisshowninFigure(READtoPRECHARGE).
FollowingthePRECHARGEcommand,asubsequentcommandtothesamebankcannotbeissueduntiltRPismet.
Figure17:RandomReadaccessNotes:1.
Doutnorm,p,q=Data-OutfromColumnnorm,p,q2.
BL=2,4,8,16(if4,8or16,thefollowingburstinterruptstheprevious)3.
ReadsaretoanActiverowinanybank.
4.
ShownwithnominaltAC,tDQSCKandtDQSQNotes:1.
Doutn=Data-OutfromColumnn2.
CKE=high3.
ShownwithnominaltAC,tDQSCKandtDQSQBankaCOLmBankaCOLpDOUTpBankaCOLqBankaCOLnREADREADREADNOPNOPREADT0T1T2T3AddressT4T5/CLKCLKDQCL=3CommandDQSDon'tcareDOUTn+1DOUTnDOUTmDOUTm+1NOPDOUTqDOUTq+1DOUTp+1BankaCOLnNOPREADBSTNOPNOPT0T1T2T3AddressT4/CLKCLKDQCL=3CommandDQSDon'tcareDOUTn+1DOUTn32Rev.
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comIS43/46LR16160HFigure20:ReadtoPrecharge(BL=4)Figure19:Readtowriteterminate(BL=4,8or16)Notes:1.
Doutn=Data-OutfromColumnn,Dinm=Data-InfromColumnm.
2.
CKE=high3.
ShownwithnominaltAC,tDQSCKandtDQSQNotes:1.
Doutn=Data-OutfromColumnn.
2.
ReadtoPrechargeequals2tCK,whichallows2datapairsofData-Out.
3.
ShownwithnominaltAC,tDQSCKandtDQSQBankaCOLmNOPBankaCOLnNOPREADBSTWRITENOPT0T1T2T3AddressT4/CLKCLKDQCL=3CommandDQSDon'tcareDOUTn+1DOUTntDQSS(NOM)DINmDINm+1T5Banka(a,orall)BankaCOLnPCGREADNOPACTNOPNOPT0T1T2T3ADDRESST4T5/CLKCLKDQCL=3CommandDQSBankaRowtRPDon'tcareDOUTn+1DOUTnDOUTn+2DOUTn+333Rev.
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comIS43/46LR16160HFigure22:WriteBurst(BL=4)WriteTheWRITEcommandisusedtoinitiateaBurstWriteaccesstoanactiverow.
ThevalueofBA0,BA1selectsthebankandaddressinputsselectthestartingcolumnlocation.
ThevalueofA10determineswhetherornotautoprechargeisused.
Ifautoprechargeisselected,therowbeingaccessedwillbeprechargedattheendofthewriteburst;ifautoprechargeisnotselected,therowwillremainopenforsubsequentaccess.
Inputdataappearingonthedatabus,iswrittentothememoryarraysubjecttotheDMinputlogiclevelappearingcoincidentwiththedata.
IfagivenDMsignalisregisteredlow,thecorrespondingdatawillbewrittentothememory;iftheDMsignalisregisteredhigh,thecorrespondingdata-inputswillbeignored,andawritewillnotbeexecutedtothatbyte/columnlocation.
ThememorycontrollerdrivestheDQSduringwriteoperations.
TheinitiallowstateoftheDQSisknownasthewritepreambleandthelowstatefollowingthelastdata-inelementiswritepostamble.
Uponcompletionofaburst,assumingnonewcommandshavebeeninitiated,theI/O'swillstayhigh-Zandanyadditionalinputdatawillbeignored.
Figure21:WritecommandNotes:1.
CA:Columnaddress2.
BA:Bankaddress3.
A10=High:EnableAutoprechargeA10=Low:DisableAutoprechargeNotes:1.
Dinn=Data-InfromColumnn.
CLK/CLKCKE/CS/RAS/CAS/WECAA0~A8A10BABA0,BA1Don'tcareBankaCOLmBankaCOLnWRITENOPWRITE/CLKCLKT0T1T2T3T1nT2nDQtDQSStWPSTDon'tcareDQStWPREStWPREtDHtDSDMDINnDINn+1DINn+2DINn+3AddressCommandtDQSH34Rev.
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comIS43/46LR16160HFigure23:ConsecutiveWritetowrite(BL=4)Figure24:Non-ConsecutiveWritetowrite(BL=4)Notes:1.
Dinn=Data-InfromColumnn.
2.
EachWritecommandmaybetoanybanks.
Notes:1.
Dinn=Data-InfromColumnn.
2.
EachWritecommandmaybetoanybanks.
WRITEWRITENOPNOPNOPNOPBankaCOLnDINmBankaCOLmT0T1T2T3AddressT4T5/CLKCLKDQSDQtDQSS(NOM)CommandDMDINnDINn+1DINn+2DINn+3DINm+1DINm+2DINm+3Don'tcareNOPWRITENOPNOPWRITENOPBankaCOLnDINmT0T1T2T3AddressT4T5/CLKCLKDQSDQtDQSS(NOM)CommandDMDINnDINn+1DINn+2DINn+3DINm+1DINm+2DINm+3Don'tcareBankaCOLmtDQSS(NOM)NOP35Rev.
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comIS43/46LR16160HFigure25:RandomWritetowriteFigure26:WritetoRead(Uninterrupting)Notes:1.
Dinn,p,m,q=Data-InfromColumnn,p,m,q.
2.
EachWritecommandmaybetoanybanks.
Notes:1.
Dinn=Data-InfromColumnn,Doutm=Data-OutfromColumnm.
2.
tWTRisreferencedfromthefirstpositiveCKedgeafterthelastdata-inpair.
3.
ReadandWritecommandcanbedirectedtodifferentbanks,inwhichcasetWTRisnotrequiredandtheReadcommandcouldbeappliedealier.
DINq+1BankaCOLqBankaCOLpWRITEWRITEWRITEWRITENOPBankaCOLnDINmBankaCOLmT0T1T2T3AddressT4/CLKCLKDQSDQtDQSS(NOM)CommandDMDINnDINn+1DINpDINp+1DINm+1DINqDon'tcareNOPWRITEBankaCOLmNOPNOPREADNOPBankaCOLnT0T1T2T3AddressT4T5/CLKCLKDQSDQtDQSS(NOM)CommandDMDINnDINn+1DINn+2DINn+3Don'tcareCL=3NOPNOPDOUTm+1DOUTmtWTRDOUTm+2T6T736Rev.
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comIS43/46LR16160HFigure27:WritetoRead(Interrupting)Figure28:WritetoRead(OddnumberofdataInterrupting)Notes:1.
Dinn=Data-InfromColumnn,Doutm=Data-OutfromColumnm.
2.
tWTRisreferencedfromthefirstpositiveCKedgeafterthelastdata-inpair.
Notes:1.
Dinn=Data-InfromColumnn,Doutm=Data-OutfromColumnm.
2.
tWTRisreferencedfromthefirstpositiveCKedgeafterthelastdata-inpair.
WRITENOPT6T7NOPNOPREADNOPBankaCOLnT0T1T2T3AddressT4T5/CLKCLKDQSDQtDQSS(NOM)CommandDMDINnDINn+1Don'tcareBankaCOLmCL=3NOPNOPDOUTm+1DOUTmDOUTm+2DOUTm+3tWTRT6T7T0T1T2T3T4T5DQSDQtDQSS(NOM)DMDINnDon'tcareCL=3DOUTm+1DOUTmDOUTm+2DOUTm+3tWTRWRITENOPNOPNOPREADNOPBankaCOLnAddress/CLKCLKCommandBankaCOLmNOPNOP37Rev.
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comIS43/46LR16160HFigure29:WritetoPrecharge(Uninterrupting)Figure30:WritetoPrecharge(Interrupting)Notes:1.
Dinn=Data-InfromColumnn.
2.
tWRisreferencedfromthefirstpositiveCKedgeafterthelastdata-inpair.
3.
ReadandWritecommandcanbedirectedtodifferentbanks,inwhichcasetWRisnotrequiredandtheReadcommandcouldbeappliedealier.
Notes:1.
Dinn=Data-InfromColumnn.
2.
tWRisreferencedfromthefirstpositiveCKedgeafterthelastdata-inpair.
3.
ReadandWritecommandcanbedirectedtodifferentbanks,inwhichcasetWRisnotrequiredandtheReadcommandcouldbeappliedealier.
PCGNOPWRITENOPNOPNOPBankaCOLnT0T1T2T3AddressT4T5/CLKCLKDQSDQtDQSS(NOM)CommandDMDINnDINn+1DINn+2DINn+3Don'tcaretWRNOPWRITENOPNOPPCGNOPBankaCOLnT0T1T2T3AddressT4T5/CLKCLKDQSDQtDQSS(NOM)CommandDMDINnDINn+1tWRDon'tcare38Rev.
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comIS43/46LR16160HFigure31:WritetoPrecharge(OddnumberofdataInterrupting)Notes:1.
Dinn=Data-InfromColumnn.
2.
tWRisreferencedfromthefirstpositiveCKedgeafterthelastdata-inpair.
3.
ReadandWritecommandcanbedirectedtodifferentbanks,inwhichcasetWRisnotrequiredandtheReadcommandcouldbeappliedealier.
Don'tcareNOPWRITENOPNOPPCGNOPBankaCOLnT0T1T2T3AddressT4T5/CLKCLKDQSDQtDQSS(NOM)CommandDMDINntWR39Rev.
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comIS43/46LR16160HPrechargeThePrechargecommandisusedtodeactivatetheopenrowinaparticularbankortheopenrowinallbanks.
Thebankswillbeavailableforsubsequentrowaccesssomespecifiedtime(tRP)afterthePrechargecommandissued.
InputA10determineswhetheroneorallbanksaretobeprecharged.
Inthecasewhereonlyonebankistobeprecharged(A10=Low),inputsBA0,BA1selectthebanks.
Whenallbanksaretobeprecharged(A10=High),inputsBA0,BA1aretreatedasa"Don'tCare".
Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivedpriortoanyReadorWritecommandsbeingissuedtothatbank.
Figure32:PrechargecommandNotes:1.
BA:BankaddressModeRegisterThemoderegistercontainsthespecificmodeofoperationoftheMobileDDRSDRAM.
Thisregisterincludestheselectionofaburstlength(2,4,8,16),acaslatency(2,3),abursttype.
Themoderegistersetmustbedonebeforeanyactivatecommandafterthepowerupsequence.
Anycontentsofthemoderegisterbealteredbyre-programmingthemoderegisterthroughtheexecutionofmoderegistersetcommand.
tCK2CKmin012345678/CLKCLK910CMDtRPPrechargeAllBankModeResisterSetCommand(any)Figure33:ModeResisterSetCLK/CLKCKE/CS/RAS/CAS/WEBAA10BA0,BA1Don'tcare40Rev.
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comIS43/46LR16160HFigure35:SelfrefreshSelfrefreshThisstateretainsdataintheMobileDDR,eveniftherestofthesystemispowereddown(evenwithoutexternalclocking).
NoterefreshintervaltimingwhileinSelfRefreshmodeisscheduledinternallyintheMobileDDRandmayvaryandmaynotmeettREFItime.
"Don'tCare"exceptCKE,whichmustremainlow.
AninternalrefreshcycleisscheduledonSelfRefreshentry.
TheprocedureforexitingSelfRefreshmoderequiresaseriesofcommands.
FirstclockmustbestablebeforeCKEgoinghigh.
NOPcommandsshouldbeissuedforthedurationoftherefreshexittime(tXSR),becausetimeisrequiredforthecompletionofanyinternalrefreshinprogress.
TheuseofSELFREFRESHmodeintroducesthepossibilitythataninternallytimedeventcanbemissedwhenCKEisraisedforexitfromselfrefreshmode.
Figure34:AutorefreshAutorefreshTheAutorefreshcommandisusedduringnormaloperationoftheMobileDDR.
Itisnonpersistent,somustbeissuedeachtimearefreshisrequired.
Therefreshaddressingisgeneratedbytheinternalrefreshcontroller.
TheMobileDDRrequiresAUTOREFRESHcommandsatanaverageperiodicintervaloftREFI.
Toallowforimprovedefficiencyinschedulingandswitchingbetweentasks,someflexibilityintheabsoluterefreshintervalisprovided.
AmaximumofeightAUTOREFRESHcommandscanbepostedtoanygivenMobileDDR,andthemaximumabsoluteintervalbetweenanyAUTOREFRESHcommandandthenextAUTOREFRESHcommandis8*tREFI.
AREFNOPNOPNOPAREFPCGNOP/CLKCLKCKET0CommandT1T3tCHtCLDQS,DQ,DMTb0tIStIHA10tCKT2T4Ta0tRPDon'tcareVALIDA0~A9,A11,A12AllBanksOneBankBABA0,BA1ACTNOPTb0RATa2BARANOPVALIDtRFCtRFCtIStIHVALIDNOPAREFNOP/CLKCLKCKET0CommandT1Ta0DQS,DQ,DMTb0tIStIHTa1tRPDon'tcareAddresstXSRtIStIHtIStISVALIDSelf-refreshmodeentrySelf-refreshmodeexit41Rev.
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comIS43/46LR16160HFigure36:Powerdown(ActiveorPrecharge)Figure37:DeepPowerdownPowerdownPowerdownoccursifCKEissetlowcoincidentwithDeviceDeselectorNOPcommandandwhennoaccessesareinprogress.
Ifpowerdownoccurswhenallbanksareidle,itisPrechargePowerDown.
IfPowerdownoccurswhenoneormorebanksareActive,itisreferredtoasActivepowerdown.
Thedevicecannotstayinthismodeforlongerthantherefreshrequirementsofthedevice,withoutlosingdata.
ThepowerdownstateisexitedbysettingCKEhighwhileissuingaDeviceDeselectorNOPcommand.
AvalidcommandcanbeissuedaftertXP.
DeepPowerdownTheDeepPower-Down(DPD)modeenablesverylowstandbycurrents.
AllinternalvoltagegeneratorsinsidetheMobileDDRarestoppedandallmemorydataislostinthismode.
AlltheinformationintheModeRegisterandtheExtendedModeRegisterislost.
NextFigure,DEEPPOWER-DOWNCOMMANDshowstheDEEPPOWER-DOWNcommandAllbanksmustbeinidlestatewithnoactivityonthedatabuspriortoenteringtheDPDmode.
Whileinthisstate,CKEmustbeheldinaconstantlowstate.
ToexittheDPDmode,CKEistakenhighaftertheclockisstableandNOPcommandmustbemaintainedforatleast200us.
VALIDNOPNOPVALID/CLKCLKCKET0CommandT1Ta0tCHtCLDQS,DQ,DMtIStIHVALIDAddresstCKVALIDtIStIStIHtIStIHT2Ta1Tb0MustnotexceedrefreshdevicelimitsDon'tcarePower-downmodeentryPower-downmodeexittXPVALIDNOPNOPDPDNOP/CLKCLKCKET0CommandT1Ta0DQS,DQ,DMTb0AddresstCKEVALIDtIST2Ta1Ta2Don'tcareDeepPower-downmodeentryDeepPower-downmodeexitT=200us42Rev.
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comIS43/46LR16160HClockStopModeClockstopmodeisafeaturesupportedbyMobileDDRSDRAMdevices.
Itreducesclock-relatedpowerconsumptionduringidleperiodsofthedevice.
Conditions:theMobileDDRSDRAMsupportsclockstopincase:Thelastaccesscommand(ACTIVE,READ,WRITE,PRECHARGE,AUTOREFRESHorMODEREGISTERSET)hasexecutedtocompletion,includinganydata-outduringreadbursts;thenumberofrequiredclockpulsesperaccesscommanddependsonthedevice'sACtimingparametersandtheclockfrequency;Therelatedtimingcondition(tRCD,tWR,tRP,tRFC,tMRD)hasbeenmet;CKEisheldHIGH.
Whenallconditionshavebeenmet,thedeviceiseitherin''idle''or''rowactive''state,andclockstopmodemaybeenteredwithCKheldLOWand/CKheldHIGH.
Clockstopmodeisexitedwhentheclockisrestarted.
NOPscommandhavetobeissuedforatleastoneclockcyclebeforethenextaccesscommandmaybeapplied.
Additionalclockpulsesmightberequireddependingonthesystemcharacteristics.
Figure38illustratestheclockstopmode:Initiallythedeviceisinclockstopmode;TheclockisrestartedwiththerisingedgeofT0andaNOPonthecommandinputs;WithT1avalidaccesscommandislatched;thiscommandisfollowedbyNOPcommandsinordertoallowforclockstopassoonasthisaccesscommandhascompleted;TnisthelastclockpulserequiredbytheaccesscommandlatchedwithT1.
ThetimingconditionofthisaccesscommandismetwiththecompletionofTn;thereforeTnisthelastclockpulserequiredbythiscommandandtheclockisthenstopped.
Figure38:ClockStopModeDQ,DQS(High–Z)ExitClockStopModeEnterClockStopModeVailCommandCKET0T1T2Tn/CLKCLKADDTimingConditionCMDClockstoppedDon'tCareNOPCMDNOPNOPNOPValideHigh43Rev.
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comIS43/46LR16160HNotes:1.
PCG=PRECHARGEcommand,SRR=StatusRegisterReadcommand,ACT=ACTIVEcommand,RA=Rowaddress,BA=Bankaddress.
2.
Othervalidcommandsarepossible.
3.
NOPsorDESELECTsarerequiredduringthistime.
4.
DOUT1=DataOut,DOUT2=dummydata.
5.
Dataoutputoccurs3cyclesafterReadforCL3,or2cyclesafterReadforCL2.
Figure39:StatusRegisterReadNOP3NOP3NOP3READNOP3SRRNOPPCGACT2CLK/CLKCKECommand1tCLDQA0~A9,A11,A12tCKA10BA0,BA1DQSHighZtSRRtSRCtIStIHDon'tcare00RARABADOUT4BA0=HBA1=LCL=3DOUT2+144Rev.
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comIS43/46LR16160HConfigurationFrequency(MHz)Speed(ns)OrderPartNo.
Package16Mx162005IS43LR16160H-5BL60-ballBGA,Lead-free1666IS43LR16160H-6BL60-ballBGA,Lead-freeOrderingInformation–VDD=1.
8VCommercialRange:(0oCto+70oC)ConfigurationFrequency(MHz)Speed(ns)OrderPartNo.
Package16Mx162005IS43LR16160H-5BLI60-ballBGA,Lead-free1666IS43LR16160H-6BLI60-ballBGA,Lead-freeIndustrialRange:(-40oCto+85oC)Note:The-6speedoptionsupports-75timingspecificationsConfigurationFrequency(MHz)Speed(ns)OrderPartNo.
Package16Mx162005IS46LR16160H-5BLA160-ballBGA,Lead-free1666IS46LR16160H-6BLA160-ballBGA,Lead-freeAutomotiveA1Range:(-40oCto+85oC)ConfigurationFrequency(MHz)Speed(ns)OrderPartNo.
Package16Mx162005IS46LR16160H-5BLA260-ballBGA,Lead-free1666IS46LR16160H-6BLA260-ballBGA,Lead-freeAutomotiveA2Range:(-40oCto+105oC)45Rev.
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comIS43/46LR16160HMouserElectronicsAuthorizedDistributorClicktoViewPricing,Inventory,Delivery&LifecycleInformation:ISSI:IS43LR16160H-6BLIIS43LR16160H-6BLI-TRIS43LR16160H-6BLIS43LR16160H-6BL-TR