oCios8.1.3
ios8.1.3 时间:2021-05-25 阅读:()
Thisdocumentisageneralproductdescriptionandissubjecttochangewithoutnotice.
Hynixdoesnotassumeanyresponsibilityforuseofcircuitsdescribed.
Nopatentlicensesareimplied.
Rev.
1.
0/Aug.
20091128MbSynchronousDRAMbasedon2Mx4Bankx16I/ODocumentTitle4Bankx2Mx16bitsSynchronousDRAMRevisionHistoryRevisionNo.
HistoryDraftDateRemark0.
1InitialDraftJul.
2009Preliminary1.
0ReleaseAug.
2009Rev.
1.
0/Aug.
20092SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesDESCRIPTIONTheHynixH57V1262GFRseriesisa134,217,728bitCMOSSynchronousDRAM,ideallysuitedforthememoryapplica-tionswhichrequirewidedataI/Oandhighbandwidth.
H57V1262GFRseriesisorganizedas4banksof2,097,152x16.
H57V1262GFRisofferingfullysynchronousoperationreferencedtoapositiveedgeoftheclock.
Allinputsandoutputsaresynchronizedwiththerisingedgeoftheclockinput.
Thedatapathsareinternallypipelinedtoachieveveryhighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithLVTTL.
Programmableoptionsincludethelengthofpipeline(Readlatencyof2or3),thenumberofconsecutivereadorwritecyclesinitiatedbyasinglecontrolcommand(Burstlengthof1,2,4,8orfullpage),andtheburstcountsequence(se-quentialorinterleave).
Aburstofreadorwritecyclesinprogresscanbeterminatedbyaburstterminatecommandorcanbeinterruptedandreplacedbyanewburstreadorwritecommandonanycycle.
(Thispipelineddesignisnotre-strictedbya'2N'rule)FEATURESThisproductisincompliancewiththedirectivepertainingofRoHS.
ORDERINGINFORMATION1.
H57V1262GFR-XXCSeries:Normalpower,CommercialTemp.
(0oCto70oC)2.
H57V1262GFR-XXISeries:Normalpower,IndustrialTemp.
(-40oCto85oC)3.
H57V1262GFR-XXLSeries:Lowpower,CommercialTemp.
(0oCto70oC)4.
H57V1262GFR-XXJSeries:Lowpower,IndustrialTemp.
(-40oCto85oC)PartNo.
ClockFrequencyOrganizationInterfacePackageH57V1262GFR-50X200MHz4Banksx2Mbitsx16LVTTL54BallFBGAH57V1262GFR-60X166MHzH57V1262GFR-70X143MHzH57V1262GFR-75X133MHzVoltage:VDDandVDDQ3.
3VsupplyvoltageAlldevicepinsarecompatiblewithLVTTLinterface54BallFBGA(LeadorLeadFreePackage)AllinputsandoutputsreferencedtopositiveedgeofsystemclockDatamaskfunctionbyUDQM,LDQMInternalfourbanksoperationAutorefreshandselfrefresh4096Refreshcycles/64msProgrammableBurstLengthandBurstType-1,2,4,8orfullpageforSequentialBurst-1,2,4or8forInterleaveBurstProgrammableCASLatency;2,3ClocksBurstReadSingleWriteoperationOperationtemperatureHY5V26F(L)F(P)-XXSeries:0~70oCHY5V26F(L)F(P)-X(I)Series:-40~85oCRev.
1.
0/Aug.
20093SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBALLCONFIGURATION54BallFBGA0.
8mmBallPitch987321ABCDEFGHJ54BallFBGA0.
8mmBallPitch987321ABCDEFGHJHJBCDAGFEVSSDQ14DQ12DQ10DQ8UDQMNCA8VSSDQ15DQ13DQ11DQ9NCCLKA11A7A5VSSQVDDQVSSQVDDQVSSCKEA9A6A4VDDQVSSQVDDQVSSQVDD/CASBA0A0A3DQ0DQ2DQ4DQ6LDQM/RASBA1A1A2VDDDQ1DQ3DQ5DQ7/WE/CSA10VDD123789Rev.
1.
0/Aug.
20094SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesFUNCTIONALBLOCKDIAGRAM2Mbitx4banksx16I/OSynchronousDRAMInternalRowCounterColumnPreDecoderColumnAddCounterSelfrefreshlogic&timerSenseAMP&I/OGateI/OBuffer&LogicAddressRegisterBurstCounterModeRegisterStateMachineAddressBuffersBankSelectColumnActiveRowActiveCASLatencyCLKCKECSRASCASWEU/LDQMA0A1BA1BA0A11RowPreDecoderRefreshDQ0DQ15X-DecoderX-DecoderX-DecoderX-DecoderY-Decoder2Mx16BANK02Mx16BANK12Mx16BANK22Mx16BANK3MemoryCellArrayDataOutControlPipeLineControlRev.
1.
0/Aug.
20095SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBASICFUNCTIONALDESCRIPTIONModeRegisterBA1BA0A11A10A9A8A7A6A5A4A3A2A1A00000OPCode00CASLatencyBTBurstLengthOPCodeA9WriteMode0BurstReadandBurstWrite1BurstReadandSingleWriteBurstTypeA3BurstType0Sequential1InterleaveBurstLengthA2A1A0BurstLengthA3=0A3=100011001220104401188100ReservedReserved101ReservedReserved110ReservedReserved111FullPageReservedCASLatencyA6A5A4CASLatency000Reserved001101020113100Reserved101Reserved110Reserved111ReservedRev.
1.
0/Aug.
20096SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesABSOLUTEMAXIMUMRATINGNotes:1.
Commercial(0~70oC)2.
Industrial(-40~85oC)DCOPERATINGCONDITIONNotes:1.
AllvoltagesarereferencedtoVSS=0V2.
VIH(max)isacceptable5.
6VACpulsewidthwith1ns,then[(tR+tF)/2-1]nsshouldbeaddedtotheparameter.
2.
Accesstimetobemeasuredwithinputsignalsof1V/nsedgerate,from0.
8Vto0.
2V.
IftR>1ns,then(tR/2-0.
5)nsshouldbeaddedtotheparameter.
ParameterSym-bol567HUnitNoteMinMaxMinMaxMinMaxMinMaxSystemClockCycleTimeCL=3tCK35.
010006.
010007.
010007.
51000nsCL=2tCK2---10nsClockHighPulseWidthtCHW1.
75-2.
0-2.
0-2.
5-ns1ClockLowPulseWidthtCLW1.
75-2.
0-2.
0-2.
5-ns1AccessTimeFromClockCL=3tAC3-4.
5-5.
4-5.
4-5.
4ns2CL=2tAC26.
0nsData-outHoldTimetOH2.
0-2.
0-2.
5-2.
7-nsData-InputSetupTimetDS1.
5-1.
5-1.
5-1.
5-ns1Data-InputHoldTimetDH0.
8-0.
8-0.
8-0.
8-ns1AddressSetupTimetAS1.
5-1.
5-1.
5-1.
5-ns1AddressHoldTimetAH0.
8-0.
8-0.
8-0.
8-ns1CKESetupTimetCKS1.
5-1.
5-1.
5-1.
5-ns1CKEHoldTimetCKH0.
8-0.
8-0.
8-0.
8-ns1CommandSetupTimetCS1.
5-1.
5-1.
5-1.
5-ns1CommandHoldTimetCH0.
8-0.
8-0.
8-0.
8-ns1CLKtoDataOutputinLow-ZTimetOLZ1.
0-1.
0-1.
5-1.
5-nsCLKtoDataOutputinHigh-ZTimeCL=3tOHZ3-4.
5-5.
4-5.
4-5.
4nsCL=2tOHZ26.
0nsRev.
1.
0/Aug.
200910SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesACCHARACTERISTICSII(ACoperatingconditionsunlessotherwisenoted)Note:1.
AnewcommandcanbegiventRRCafterselfrefreshexit.
ParameterSymbol567HUnitNoteMinMaxMinMaxMinMaxMinMaxRASCycleTimeOperationtRC55-60-63-63-nsRASCycleTimeAutoRefreshtRRC55-60-63-63-nsRAStoCASDelaytRCD15-18-20-20-nsRASActiveTimetRAS38.
7100K42100K42100K42120KnsRASPrechargeTimetRP15-18-20-20-nsRAStoRASBankActiveDelaytRRD10-12-14-15-nsCAStoCASDelaytCCD1-1-1-1-CLKWriteCommandtoData-InDelaytWTL0-0-0-0-CLKData-intoPrechargeCommandtDPL2-2-2-2-CLKData-IntoActiveCommandtDALtDPL+tRPDQMtoData-OutHi-ZtDQZ2-2-2-2-CLKDQMtoData-InMasktDQM0-0-0-0-CLKMRStoNewCommandtMRD2-2-2-2-CLKPrechargetoDataOutputHigh-ZCL=3tPROZ33-3-3-3-CLKCL=2tPROZ22-CLKPowerDownExitTimetDPE1-1-1-1-CLKSelfRefreshExitTimetSRE1-1-1-1-CLK1RefreshTimetREF-64-64-64-64msRev.
1.
0/Aug.
200911SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesCOMMANDTRUTHTABLECommandCKEn-1CKEnCSRASCASWEDQMADDRA10/APBANoteModeRegisterSetHXLLLLXOPcodeNoOperationHXHXXXXXLHHHBankActiveHXLLHHXRAVReadHXLHLHXCALVReadwithAutoprechargeHWriteHXLHLLXCALVWritewithAutoprechargeHPrechargeAllBanksHXLLHLXXHXPrechargeselectedBankLVBurstStopHXLHHLXXDQMHXVXAutoRefreshHHLLLHXXBurst-Read-Single-WRITEHXLLLLXA9ballHigh(OtherballsOPcode)MRSModeSelfRefresh1EntryHLLLLHXXExitLHHXXXXLHHHPrechargepowerdownEntryHLHXXXXXLHHHExitLHHXXXXLHHHClockSuspendEntryHLHXXXXXLVVVExitLHXXRev.
1.
0/Aug.
200912SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesPACKAGEINFORMATION54BallFBGA8.
0mmx8.
0mmUnit[mm]0.
8±0.
1BottomView0.
35+0.
025/-0.
050.
80Typ.
0.
80Typ.
1.
0max0.
45+/-0.
05A1INDEXMARK1.
608.
00Typ.
0.
8±0.
18.
00Typ.
6.
46.
4
Hynixdoesnotassumeanyresponsibilityforuseofcircuitsdescribed.
Nopatentlicensesareimplied.
Rev.
1.
0/Aug.
20091128MbSynchronousDRAMbasedon2Mx4Bankx16I/ODocumentTitle4Bankx2Mx16bitsSynchronousDRAMRevisionHistoryRevisionNo.
HistoryDraftDateRemark0.
1InitialDraftJul.
2009Preliminary1.
0ReleaseAug.
2009Rev.
1.
0/Aug.
20092SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesDESCRIPTIONTheHynixH57V1262GFRseriesisa134,217,728bitCMOSSynchronousDRAM,ideallysuitedforthememoryapplica-tionswhichrequirewidedataI/Oandhighbandwidth.
H57V1262GFRseriesisorganizedas4banksof2,097,152x16.
H57V1262GFRisofferingfullysynchronousoperationreferencedtoapositiveedgeoftheclock.
Allinputsandoutputsaresynchronizedwiththerisingedgeoftheclockinput.
Thedatapathsareinternallypipelinedtoachieveveryhighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithLVTTL.
Programmableoptionsincludethelengthofpipeline(Readlatencyof2or3),thenumberofconsecutivereadorwritecyclesinitiatedbyasinglecontrolcommand(Burstlengthof1,2,4,8orfullpage),andtheburstcountsequence(se-quentialorinterleave).
Aburstofreadorwritecyclesinprogresscanbeterminatedbyaburstterminatecommandorcanbeinterruptedandreplacedbyanewburstreadorwritecommandonanycycle.
(Thispipelineddesignisnotre-strictedbya'2N'rule)FEATURESThisproductisincompliancewiththedirectivepertainingofRoHS.
ORDERINGINFORMATION1.
H57V1262GFR-XXCSeries:Normalpower,CommercialTemp.
(0oCto70oC)2.
H57V1262GFR-XXISeries:Normalpower,IndustrialTemp.
(-40oCto85oC)3.
H57V1262GFR-XXLSeries:Lowpower,CommercialTemp.
(0oCto70oC)4.
H57V1262GFR-XXJSeries:Lowpower,IndustrialTemp.
(-40oCto85oC)PartNo.
ClockFrequencyOrganizationInterfacePackageH57V1262GFR-50X200MHz4Banksx2Mbitsx16LVTTL54BallFBGAH57V1262GFR-60X166MHzH57V1262GFR-70X143MHzH57V1262GFR-75X133MHzVoltage:VDDandVDDQ3.
3VsupplyvoltageAlldevicepinsarecompatiblewithLVTTLinterface54BallFBGA(LeadorLeadFreePackage)AllinputsandoutputsreferencedtopositiveedgeofsystemclockDatamaskfunctionbyUDQM,LDQMInternalfourbanksoperationAutorefreshandselfrefresh4096Refreshcycles/64msProgrammableBurstLengthandBurstType-1,2,4,8orfullpageforSequentialBurst-1,2,4or8forInterleaveBurstProgrammableCASLatency;2,3ClocksBurstReadSingleWriteoperationOperationtemperatureHY5V26F(L)F(P)-XXSeries:0~70oCHY5V26F(L)F(P)-X(I)Series:-40~85oCRev.
1.
0/Aug.
20093SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBALLCONFIGURATION54BallFBGA0.
8mmBallPitch987321ABCDEFGHJ54BallFBGA0.
8mmBallPitch987321ABCDEFGHJHJBCDAGFEVSSDQ14DQ12DQ10DQ8UDQMNCA8VSSDQ15DQ13DQ11DQ9NCCLKA11A7A5VSSQVDDQVSSQVDDQVSSCKEA9A6A4VDDQVSSQVDDQVSSQVDD/CASBA0A0A3DQ0DQ2DQ4DQ6LDQM/RASBA1A1A2VDDDQ1DQ3DQ5DQ7/WE/CSA10VDD123789Rev.
1.
0/Aug.
20094SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesFUNCTIONALBLOCKDIAGRAM2Mbitx4banksx16I/OSynchronousDRAMInternalRowCounterColumnPreDecoderColumnAddCounterSelfrefreshlogic&timerSenseAMP&I/OGateI/OBuffer&LogicAddressRegisterBurstCounterModeRegisterStateMachineAddressBuffersBankSelectColumnActiveRowActiveCASLatencyCLKCKECSRASCASWEU/LDQMA0A1BA1BA0A11RowPreDecoderRefreshDQ0DQ15X-DecoderX-DecoderX-DecoderX-DecoderY-Decoder2Mx16BANK02Mx16BANK12Mx16BANK22Mx16BANK3MemoryCellArrayDataOutControlPipeLineControlRev.
1.
0/Aug.
20095SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesBASICFUNCTIONALDESCRIPTIONModeRegisterBA1BA0A11A10A9A8A7A6A5A4A3A2A1A00000OPCode00CASLatencyBTBurstLengthOPCodeA9WriteMode0BurstReadandBurstWrite1BurstReadandSingleWriteBurstTypeA3BurstType0Sequential1InterleaveBurstLengthA2A1A0BurstLengthA3=0A3=100011001220104401188100ReservedReserved101ReservedReserved110ReservedReserved111FullPageReservedCASLatencyA6A5A4CASLatency000Reserved001101020113100Reserved101Reserved110Reserved111ReservedRev.
1.
0/Aug.
20096SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesABSOLUTEMAXIMUMRATINGNotes:1.
Commercial(0~70oC)2.
Industrial(-40~85oC)DCOPERATINGCONDITIONNotes:1.
AllvoltagesarereferencedtoVSS=0V2.
VIH(max)isacceptable5.
6VACpulsewidthwith1ns,then[(tR+tF)/2-1]nsshouldbeaddedtotheparameter.
2.
Accesstimetobemeasuredwithinputsignalsof1V/nsedgerate,from0.
8Vto0.
2V.
IftR>1ns,then(tR/2-0.
5)nsshouldbeaddedtotheparameter.
ParameterSym-bol567HUnitNoteMinMaxMinMaxMinMaxMinMaxSystemClockCycleTimeCL=3tCK35.
010006.
010007.
010007.
51000nsCL=2tCK2---10nsClockHighPulseWidthtCHW1.
75-2.
0-2.
0-2.
5-ns1ClockLowPulseWidthtCLW1.
75-2.
0-2.
0-2.
5-ns1AccessTimeFromClockCL=3tAC3-4.
5-5.
4-5.
4-5.
4ns2CL=2tAC26.
0nsData-outHoldTimetOH2.
0-2.
0-2.
5-2.
7-nsData-InputSetupTimetDS1.
5-1.
5-1.
5-1.
5-ns1Data-InputHoldTimetDH0.
8-0.
8-0.
8-0.
8-ns1AddressSetupTimetAS1.
5-1.
5-1.
5-1.
5-ns1AddressHoldTimetAH0.
8-0.
8-0.
8-0.
8-ns1CKESetupTimetCKS1.
5-1.
5-1.
5-1.
5-ns1CKEHoldTimetCKH0.
8-0.
8-0.
8-0.
8-ns1CommandSetupTimetCS1.
5-1.
5-1.
5-1.
5-ns1CommandHoldTimetCH0.
8-0.
8-0.
8-0.
8-ns1CLKtoDataOutputinLow-ZTimetOLZ1.
0-1.
0-1.
5-1.
5-nsCLKtoDataOutputinHigh-ZTimeCL=3tOHZ3-4.
5-5.
4-5.
4-5.
4nsCL=2tOHZ26.
0nsRev.
1.
0/Aug.
200910SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesACCHARACTERISTICSII(ACoperatingconditionsunlessotherwisenoted)Note:1.
AnewcommandcanbegiventRRCafterselfrefreshexit.
ParameterSymbol567HUnitNoteMinMaxMinMaxMinMaxMinMaxRASCycleTimeOperationtRC55-60-63-63-nsRASCycleTimeAutoRefreshtRRC55-60-63-63-nsRAStoCASDelaytRCD15-18-20-20-nsRASActiveTimetRAS38.
7100K42100K42100K42120KnsRASPrechargeTimetRP15-18-20-20-nsRAStoRASBankActiveDelaytRRD10-12-14-15-nsCAStoCASDelaytCCD1-1-1-1-CLKWriteCommandtoData-InDelaytWTL0-0-0-0-CLKData-intoPrechargeCommandtDPL2-2-2-2-CLKData-IntoActiveCommandtDALtDPL+tRPDQMtoData-OutHi-ZtDQZ2-2-2-2-CLKDQMtoData-InMasktDQM0-0-0-0-CLKMRStoNewCommandtMRD2-2-2-2-CLKPrechargetoDataOutputHigh-ZCL=3tPROZ33-3-3-3-CLKCL=2tPROZ22-CLKPowerDownExitTimetDPE1-1-1-1-CLKSelfRefreshExitTimetSRE1-1-1-1-CLK1RefreshTimetREF-64-64-64-64msRev.
1.
0/Aug.
200911SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesCOMMANDTRUTHTABLECommandCKEn-1CKEnCSRASCASWEDQMADDRA10/APBANoteModeRegisterSetHXLLLLXOPcodeNoOperationHXHXXXXXLHHHBankActiveHXLLHHXRAVReadHXLHLHXCALVReadwithAutoprechargeHWriteHXLHLLXCALVWritewithAutoprechargeHPrechargeAllBanksHXLLHLXXHXPrechargeselectedBankLVBurstStopHXLHHLXXDQMHXVXAutoRefreshHHLLLHXXBurst-Read-Single-WRITEHXLLLLXA9ballHigh(OtherballsOPcode)MRSModeSelfRefresh1EntryHLLLLHXXExitLHHXXXXLHHHPrechargepowerdownEntryHLHXXXXXLHHHExitLHHXXXXLHHHClockSuspendEntryHLHXXXXXLVVVExitLHXXRev.
1.
0/Aug.
200912SynchronousDRAMMemory128Mbit(8Mx16bit)H57V1262GFRSeriesPACKAGEINFORMATION54BallFBGA8.
0mmx8.
0mmUnit[mm]0.
8±0.
1BottomView0.
35+0.
025/-0.
050.
80Typ.
0.
80Typ.
1.
0max0.
45+/-0.
05A1INDEXMARK1.
608.
00Typ.
0.
8±0.
18.
00Typ.
6.
46.
4
Megalayer新加坡服务器国际带宽线路测评
前几天有关注到Megalayer云服务器提供商有打算在月底的时候新增新加坡机房，这个是继美国、中国香港、菲律宾之外的第四个机房。也有工单询问到官方，新加坡机房有包括CN2国内优化线路和国际带宽，CN2优化线路应该是和菲律宾差不多的。如果我们追求速度和稳定性的中文业务，建议还是选择CN2优化带宽的香港服务器。这里有要到Megalayer新加坡服务器国际带宽的测试服务器，E3-1230配置20M国际带...
远程登录VNC无法连接出现
今天有网友提到自己在Linux服务器中安装VNC桌面的时候安装都没有问题，但是在登录远程的时候居然有出现灰色界面，有三行代码提示"Accept clipboard from viewers,Send clipboard to viewers,Send primary selection to viewers"。即便我们重新登录也不行，这个到底如何解决呢？这里找几个可以解决的可能办法，我们多多尝试。...
ZJI(月付450元)，香港华为云线路服务器、E3服务器起
ZJI发布了9月份促销信息，针对香港华为云线路物理服务器华为一型提供立减300元优惠码，优惠后香港华为一型月付仅450元起。ZJI是原来Wordpress圈知名主机商家：维翔主机，成立于2011年，2018年9月更名为ZJI，提供中国香港、台湾、日本、美国独立服务器(自营/数据中心直营)租用及VDS、虚拟主机空间、域名注册等业务，商家所选数据中心均为国内访问质量高的机房和线路，比如香港阿里云、华为...
ios8.1.3为你推荐
-
蓝牙ios6formgraph支持ipad司机苹果5phpecho为什么在PHP中使用echo FALSE;什么也输出不了？应该如何输出FALSE？谢谢！google中国地图强大的谷歌地图，为什么中国不用起来重庆电信宽带管家重庆电信宽带安装收费google图片搜索如何用google搜索空间照片苹果5.1完美越狱iOS5.1.1完美越狱教程苹果5.1完美越狱ios5.1能不能完美越狱？