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101InnovationDriveSanJose,CA95134www.
altera.
comALTDLLandALTDQ_DQSMegafunctionsUserGuideSoftwareVersion:9.
1DocumentVersion:5.
0DocumentDate:February2012Copyright2010AlteraCorporation.
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UG-01032-5.
0February2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideContentsChapter1.
AbouttheseMegafunctionsDeviceSupport1–1Features1–2Chapter2.
GettingStartedDesignFlow2–1BuildtheDatapath2–1SimulatetheDesign2–3CreateTimingConstraints2–3CompiletheDesignandVerifyTiming2–3AdjustConstraints2–4DesignExample:ImplementingReadPathsUsingStratixIIIDevices2–4GeneratetheMegafunctions2–5CompileandSimulatetheDesign2–12Chapter3.
ParameterSettingsALTDLLParameterEditor3–1ALTDQ_DQSParameterEditor3–5Chapter4.
FunctionalDescriptionCustomExternalMemoryInterfaceDatapathsOverview4–1ALTDLLMegafunction4–3DLLblockandDLLoffsetcontrolblock4–3ALTDQ_DQSMegafunction4–4DQSInputPath4–6DQInputPath4–8DQOutput/OEPath4–10DQSOutput/OEPath4–12DQ/DQSOCTPath4–14DelayChains4–15DeskewDelayChains4–16ALTIOBUFMegafunctionandDelayChainsIntegration4–18DQS_CONFIG/IO_CONFIGBlock4–22ConfiguringDynamicDelayChainsUsingtheIO_CONFIGBlock4–22ALTDLLMegafunctionPorts4–31ALTDQ_DQSMegafunctionPorts4–33DQSInputPathMegafunctionPorts4–33DQSOutputPathMegafunctionPorts4–35DQSOEPathMegafunctionPorts4–36DQ/DQSOCTPathMegafunctionPorts4–37DQInputPathMegafunctionPorts4–38DQOutputPathMegafunctionPorts4–40DQOEPathMegafunctionPorts4–42DQSnI/OPathPorts4–43DQS_CONFIG/IO_CONFIGMegafunctionPorts4–45CorrectSettingsforExternalMemoryInterfaces4–46ivALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevices4–49Procedure4–49UnderstandingtheSimulationResults4–60AppendixA.
ClearBoxGeneratorUsingClearBoxGeneratorA–1ClearBoxGeneratorOptionsA–2ClearBoxParametersA–3AdditionalInformationRevisionHistoryInfo–1HowtoContactAlteraInfo–1TypographicConventionsInfo–2February2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide1.
AbouttheseMegafunctionsTheALTDLLandALTDQ_DQSmegafunctionsprovideacustomexternalmemoryinterfacesolutiontoaccessanFPGA'sarchitectureandallowyoutobuildyourowncustomexternalmemoryinterfacephysicallayer(PHY)blocks.
AlterarecommendsthatyouusetheALTDLLandALTDQ_DQSmegafunctionswhenimplementingaspecializedorcustomizedintellectualproperty(IP)foranAltera-supportedexternalmemoryinterfacethatisnotsupportedinAltera'sIPoraproprietaryinterfacethatisnotsupportedbyAltera.
TheALTDLLandALTDQ_DQScustomexternalmemoryinterfacesolutionoffersmoreefficientlogicsynthesisanddeviceimplementation,andsavesvaluabledesigntimeifyouchoosetocodeyourownlogic.
TheALTDLLmegafunctionconfiguresthededicatedDQSphase-shiftcircuitry,andtheALTDQ_DQSmegafunctionimplementsthereadandwritePHYrequiredfortheinterface.
WhiletheALTDLLandALTDQ_DQScustomexternalmemoryinterfacesolutionisprimarilyforbuildingcustommemoryinterfacePHYblocks,youcanalsousethissolutiontointerfacewithanyexternaldevice,suchasASIC,ASSPoranotherFPGA,throughthedoubledatarate(DDR)interface.
1TheALTDLLandALTDQ_DQSmegafunctionsarespecificallyformemoryinterfacesthatsupportmemoryburstlengthsoftwo.
Forcommonmemoryinterfacesthatsupportmemoryburstlengthsoffour,AlterarecommendsthatyouusetheALTMEMPHY-orUniPHY-basedmemorycontrollerstotakeadvantageofthebenefitsofAltera'sIPandtimingclosuremethodologies.
fFormoreinformationabouttheALTMEMPHY-orUniPHY-basedmemorycontrollersthatAlteraoffers,refertothevolume3oftheExternalMemoryInterfaceHandbook.
DeviceSupportTheALTDLLandALTDQ_DQSmegafunctionssupportthefollowingAlteradevicefamilies:ArriaIIGXHardCopyIIIHardCopyIVStratixIIIStratixIV1–2Chapter1:AbouttheseMegafunctionsFeaturesALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFeaturesTheALTDLLandALTDQ_DQSmegafunctionsofferthefollowingfeatures:ALTDLLAdelay-lockedloop(DLL)blocktocenter-alignthereadstrobewithreaddata.
Phaseoffsetcontrolblockstofine-tunethedelaytimeonthereadstrobeusingstaticordynamicoffset.
ALTDQ_DQSSupportsRLDRAMIImemoryinterface.
DDRregistersontheinputandoutputpathstoreadorwritetoanexternalDDRinterface.
Half-rateregisterstoenablesuccessfuldatatransfersbetweentheI/Oregistersandthecorelogic.
Accesstodynamicon-chiptermination(OCT)controlstoswitchbetweenparallelterminationduringreadstoseriesterminationduringwrites.
AccesstoI/Odelaychainstofine-tunedelaysonthedataorstrobesignalsstaticallyordynamically.
Figure1–1showsahigh-leveloverviewofhowyoucanconnecttheALTDQ_DQSmegafunctionwithothermegafunctionssuchasALTPLL,ALTDLL,andALTIOBUF,tocreateafullcustomexternalmemoryinterface.
Figure1–1showsa36-bitinterfacecreatedwithALTDQ_DQSinstantiations,whereeachinstantiationisconfiguredinthe*9mode.
Figure1–1.
System-LevelViewALTIOBUF(DQS/DQSN)ALTIOBUF(BIDIR_DQ)ALTIOBUF(INPUT_DQ)ALTIOBUF(OUTPUT_DQ)ALTDQ_DQSx9ALTDQ_DQSx9ALTDQ_DQSx9ALTDQ_DQSx9ALTDLLALTPLLFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide2.
GettingStartedDesignFlowThischapterdescribestheFPGAdesignflowtoimplementacustommemoryinterfacedatapathusingtheALTDLLandALTDQ_DQSmegafunctionsandAltera'sFPGAhardwarefeatures.
Figure2–1showsthedesignflowforcreatingacustommemorydatapathsystemwiththeALTDLLandALTDQ_DQSmegafunctionsandtheQuartusIIsoftware.
BuildtheDatapathAfteryouidentifytherequirementsforyourcustomexternalmemoryinterface,thefirststageistobuildadatapathtointerfacewiththememoryblocks.
Tobuildthedatapath,youmustperformthefollowingsteps:1.
CreateaprojectintheQuartusIIsoftwarethattargetsthepreferredAlteradevice.
2.
InstantiatetheALTPLLmegafunctiontoprovidetherequiredclockingschemeforthecustomPHY.
fFormoreinformationaboutinstantiatingmegafunctionsandtheclockingscheme,refertoInstantiatetheALTPLLMegafunctionsectioninvolume5oftheExternalMemoryInterfaceHandbook.
FormoreinformationaboutusingPLLs,refertotheALTPLLMegafunctionUserGuide.
3.
InstantiatetheALTDLLmegafunctiontoimplementtheDLL.
Figure2–1.
DesignFlowchartBuildtheDatapathSimulatetheDesignCreateTimingConstraintsCompiletheDesignandVerifyTimingAdjustConstraintsChapter2:GettingStarted2–2DesignFlowFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide4.
InstantiatetheALTDQ_DQSmegafunctiontoimplementthereadandwritePHYrequiredfortheinterface.
5.
IntegratethecustomPHYwithuserlogic,andacustomorthirdpartymemorycontrollerifneeded.
6.
InstantiatetheALTIOBUFmegafunctiontousetheI/Obuffersforpinconnections.
ThismegafunctionenablesdynamicOCTcapabilitiesfortherespectiveinterfacepins.
fFormoreinformationaboutthepinconnections,referto"ALTIOBUFMegafunctionandDelayChainsIntegration"onpage4–18.
FormoreinformationabouttheALTIOBUFmegafunction,refertoI/OBuffer(ALTIOBUF)MegafunctionUserGuide.
7.
ConnectalltheinstancesofALTPLL,ALTDLL,ALTDQ_DQS,ALTIOBUF,andothercustommemorycontrollersintheQuartusIIsoftware.
Thefollowingsectionsdiscussothermegafunctionsorcustomizedcontrollerlogicthatareusedinsomecases.
ALTOCTMegafunctionIfyouusetheOCTcapabilitiesinthetargeteddevices,youeliminatetheneedforexternalseriesorparallelterminationresistors,andyousimplifythedesignofaPCB.
IftheI/Oinyourdesignusescalibratedseries,parallel,ordynamictermination,yourdesignrequiresacalibrationblock.
ThisblockrequiresapairofRUPandRDNpinslocatedinabankthatsharesthesameVCCIOvoltageasyourmemoryinterface.
ThiscalibrationblockisnotrequiredtobeinthesamebankorsideofthedeviceastheI/Oelementsitisserving.
TousethesecapabilitiesintheFPGA,youmustturnontheUsedynamicOCTpathoptionwhenparameterizingtheALTDQ_DQSmegafunction,andinstantiatetheALTOCTmegafunction.
fFormoreinformationabouttheOCTcapabilitiesintheDQ/DQSpath,referto"DQ/DQSOCTPath"onpage4–14.
CustomizedControllerLogicInsomecases,yourequireacustomizedcontrollerlogictocontrolthePHYcreatedwiththeALTDLLandALTDQ_DQSinstances.
Youmustcreateacontrollerlogicforthefollowinginstances:Controllerlogicfordata,data_valid,andstrobepinsforthecustomexternalmemoryinterface.
Ifyouusecalibratedtermination,controllerlogicforallpinsintheALTOCTinstancesassociatedwiththecustomexternalmemoryinterface.
fFormoreinformationaboutcalibratedtermination,refertoDynamicCalibratedOn-ChipTermination(ALTOCT)MegafunctionUserGuide.
2–3Chapter2:GettingStartedDesignFlowALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationSimulatetheDesignAfterinstantiatingthemegafunctions,theQuartusIIsoftwaregeneratesdesignsourcefilesandVerilogorVHDLsimulationmodelfiles.
SimulatethesefilesinModelsim-AE,ModelsimSE,orotherthird-partyfunctionalsimulatortools.
fForinformationaboutfunctionalandgate-leveltimingsimulations,refertoSimulatingAlteraDesignschapterinvolume3oftheQuartusIIHandbook.
CreateTimingConstraintsTheALTDLLandALTDQ_DQSmegafunctionsdonotprovideautomatictimingscriptsforcustomexternalmemoryinterfaces.
Youmustcreateyourowntimingconstraintsforthefollowingpathsandclocks:TimingpathsfromFPGAI/Otoexternaldevice.
TimingpathsfromI/Oregisterstocorelogic.
PLLandotherclockconstraints.
Aftercreatingyourconstraints,performthetiminganalysisusingtheTimeQuesttiminganalyzerintheQuartusIIsoftware.
fBecausethetiminganalysisforcustomexternalmemoryinterfacesarethesameasthetiminganalysisforsource-synchronousinterfaces,refertotheTimingAnalysissectioninvolume3oftheQuartusIIHandbookandAN433:ConstrainingandAnalyzingSource-SynchronousInterfaces.
TheALTDLLandALTDQ_DQScustomPHYsolutionsupportstiminganalysisusingtheTimeQuesttiminganalyzerwithSynopsysDesignConstraints(SDC)assignments.
Youcanderivethetimingconstraintsfromtheexternaldevicedatasheetandtolerancesfromtheboardlayout.
fFormoreinformationabouttimingconstraints,referto"AppendixD:InterfaceTimingAnalysis"sectioninAN328:InterfacingDDR2SDRAMwithStratixII,StratixIIGX,andArriaGXDevices.
FormoreinformationaboutcreatingtimingconstraintsinSDCformatfortheTimeQuesttiminganalyzer,refertotheTheQuartusIITimeQuestTimingAnalyzerchapteroftheQuartusIIHandbook.
Dependingonwhichsimulationtoolyouareusing,refertotheappropriatechapterintheSimulationsectioninvolume3oftheQuartusIIHandbook.
CompiletheDesignandVerifyTimingAfterconstrainingyourdesign,compileyourdesignintheQuartusIIsoftwaretogeneratetimingreportstoverifywhethertiminghasbeenmet.
AftercompilingyourdesignintheQuartusIIsoftware,runtheverifyingtimingscripttoproducethetimingreportfordifferentpaths,suchaswritedata,readdata,addressandcommand,andcore(entireinterface)timingpathsinyourdesign.
Chapter2:GettingStarted2–4DesignExample:ImplementingReadPathsUsingStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideThetiminganalyzerreportsmarginsonthefollowingpaths:AddressandcommandsetupandholdmarginHalf-rateaddressandcommandsetupandholdmarginCoresetupandholdmarginCoreresetandremovalsetupandholdmarginWritesetupandholdmarginReadcapturesetupandholdmarginfFormoreinformationabouttiminganalysisandreportingusingtheALTDLLandALTDQ_DQSexternalmemorysolution,refertotheAnalyzingTimingofMemoryIPchapterinvolume2oftheExternalMemoryInterfaceHandbook.
AdjustConstraintsThetimingreportshowstheworstcasesetupandholdmarginforthedifferentpathsinyourdesign.
Ifthesetupandholdmargindonotmeettimingrequirements,adjustthephasesettingoftheclocksthatlatchthedata.
Forexample,theaddressandcommandoutputsareclockedbyanaddressandcommandclockthatmaybedifferentthanthesystemclock,whichis0°.
Thesystemclockclockstheclockoutputsgoingtothememory.
Ifthereporttimingscriptindicatesthatusingthedefaultphasesettingfortheaddressandcommandclockresultsinmoreholdtimethansetuptime,adjusttheaddressandcommandclocktobelessnegativethanthedefaultphasesettingtoensurethatthereislessholdmargin.
Similarly,adjusttheaddressandcommandclocktobemorenegativethanthedefaultphasesettingifthereismoresetupmargin.
DesignExample:ImplementingReadPathsUsingStratixIIIDevicesThissectionprovidesawalkthroughofasimpledesignexample.
ThedesignexampledemonstratesaStratixIIIdevicereadingfromanexternalDDR2SDRAM.
TheDDR2externalmemoryinterfaceisimplementedusingtheALTDLLandALTDQ_DQSmegafunctions.
Thisdesignrequires1DQSand8DQinputpins.
TheDQSfrequencyforthedesignis150MHzandthedatarateis300Mbps.
1Foramorecomplexdesignexample,referto"DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevices"onpage4–49.
fThedesignexamplesareavailablenexttotheALTDLLandALTDQ_DQSMegafunctionsUserGuideontheDocumentation:UserGuidespageoftheAlterawebsite.
2–5Chapter2:GettingStartedDesignExample:ImplementingReadPathsUsingStratixIIIDevicesALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationGeneratetheMegafunctionsCreateaQuartusIIprojectandgeneratethefollowingmegafunctions:ALTPLLmegafunctionALTDLLmegafunctionALTDQ_DQSmegafunctionALTIOBUFmegafunctionCreateaQuartusIIProjectCreateaprojectintheQuartusIIsoftwarethattargetstheEP3SL150F1152-C2devicefortheDDR2SDRAMbyperformingthefollowingsteps:1.
Openthealtdll_altdq_dqs_DesignExample_ex1.
zipfileandextractthealtdll_altdq_dqs_design_ex1.
qarfile.
2.
IntheQuartusIIsoftware,restorethealtdll_altdq_dqs_design_ex1.
qarfileintoyourworkingdirectory.
3.
Openthealtdll_altdq_dqs_design_ex1.
bdffile.
GeneratetheALTPLLMegafunctionBeforegeneratingtheALTDLLandALTDQ_DQSmegafunctions,youmustgeneratetheALTPLLmegafunctionfirstbyperformingthefollowingsteps:1.
Double-clickanywhereontheBlockEditorwindow.
TheSymbolwindowappears.
2.
ClickMegaWizardPlug-InManager.
Page1oftheMegaWizardPlug-InManagerappears.
3.
SelectCreateanewcustommegafunctionvariation.
4.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
5.
SelectCreateanewcustommegafunctionvariation.
6.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
SelectALTPLL,andVerilogHDL,andtypethefilenameasPLL_50MHz.
v.
7.
OntheParameterSettingstab,ontheGeneral/Modespage,specifytheparametersasshowninTable2–1.
TheseparametersconfigurethegeneralsettingsfortheALTPLLinstance.
Table2–1.
ALTPLLParameterSettingsSettingsValueCurrentlyselecteddevicefamilyStratixIIIMatchproject/defaultTurnedon.
Whatisthefrequencyoftheinclock0input50MHzHowwillthePLLoutputsbegeneratedWithnocompensationThisoptionisselectedbecausethePLLisusedtoclocktheALTDLLinstanceonly.
Chapter2:GettingStarted2–6DesignExample:ImplementingReadPathsUsingStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide8.
OntheOutputClockstab,ontheclkc0page,specifytheparametersasshowninTable2–2.
Youdon'thavetoparameterizetheotherpagesontheOutputClockstabbecauseyouonlyuseoneclockforthisdesign.
9.
ClickFinish.
10.
ClickFinish.
TheALTPLLinstanceisgenerated.
11.
ClickOKtoclosetheSymbolwindow.
12.
Placetheinstanceonthealtdll_altdq_dqs_design_ex1.
bdfBlockEditor.
GeneratetheALTDLLMegafunctionTogeneratetheALTDLLmegafunction,performthefollowingsteps:1.
Double-clickanywhereontheBlockEditorwindow.
TheSymbolwindowappears.
2.
ClickMegaWizardPlug-InManager.
Page1oftheMegaWizardPlug-InManagerappears.
3.
SelectCreateanewcustommegafunctionvariation.
4.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
5.
SelectCreateanewcustommegafunctionvariation.
6.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
SelectALTDLL,andVerilogHDL,andtypethefilenameasdll_150MHz.
v.
7.
OntheParameterSettingstab,ontheGeneralpage,specifytheparametersasshowninTable2–3.
TheseparametersconfigurethegeneralsettingsfortheALTDLLinstance.
Table2–2.
ALTPLLOutputClocks/clkc0SettingsSettingsValueUsethisclockTurnedonEnteroutputclockfrequency150MhzClockphaseshift0degClockdutycycle(%)50Table2–3.
ALTDLLGeneraLSettingsSettingsValueCurrentlyselecteddevicefamilyStratixIIIMatchproject/defaultTurnedon.
NumberofDelayChains12RefertoStratixIIIDeviceDatasheet:DCandSwitchingCharacteristicsofStratixIIIDeviceschapterintheStratixIIIDeviceHandbook,andpickaDLLmodethatsupports150MHzandfindtheDLLsetting.
2–7Chapter2:GettingStartedDesignExample:ImplementingReadPathsUsingStratixIIIDevicesALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporation8.
OntheDLLOffsetControls/OptionalPortspage,specifytheparametersasshowninTable2–4.
9.
ClickFinish.
10.
ClickFinish.
TheALTDLLinstanceisgenerated.
11.
ClickOKtoclosetheSymbolwindow.
12.
PlacetheinstanceontheBlockEditor.
GeneratetheALTDQ_DQSMegafunctionTogeneratetheALTDQ_DQSmegafunction,performthefollowingsteps:1.
Double-clickanywhereontheBlockEditorwindow.
TheSymbolwindowappears.
2.
ClickMegaWizardPlug-InManager.
Page1oftheMegaWizardPlug-InManagerappears.
3.
SelectCreateanewcustommegafunctionvariation.
4.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
SelectALTDQ_DQS,andVerilogHDL,andtypethefilenameasdq_dqs_input_path.
v.
5.
OntheParameterSettingspage,specifytheparametersasshowninTable2–5.
TheseparametersconfigurethegeneralsettingsfortheALTDQ_DQSinstance.
DQSDelayBufferModeLowRefertoStratixIIIDeviceDatasheet:DCandSwitchingCharacteristicsofStratixIIIDeviceschapterintheStratixIIIDeviceHandbook,andpickaDLLmodethatsupports150MHzandfindtheDLLsetting.
InputClockFrequency150MHzTurnonjitterreductionTurnedoff.
Table2–4.
ALTDLLParameterSettings/DLLOffsetControls/OptionalPortsSettingsSettingsValueDLLPhaseOffsetControlAInstantiatedll_offset_ctrlblockTurnedoff.
Thedesignisintendedtorunslow,soyoudonotneedtoselectthisparameter.
However,ifthereadtimingisunbalanced,youcanfine-tunetheDQSphaseshiftusingthisparameter.
DLLPhaseOffsetControlBInstantiatedll_offset_ctrlblockTurnedoff.
OptionalPortsCreateadll_aloadportTurnedoff.
OptionalPortsCreateadll_dqsupdateportTurnedoff.
Table2–3.
ALTDLLGeneraLSettingsSettingsValueChapter2:GettingStarted2–8DesignExample:ImplementingReadPathsUsingStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide.
6.
OntheAdvancedOptionstab,ontheDQSINpage,specifytheparametersasshowninTable2–6.
TheseparametersconfiguretheDQSinputpathoftheALTDQ_DQSinstance.
Table2–5.
ParameterSettingsParameterValueRLDRAMIIModeNONENumberofbidirectionalDQ0NumberofinputDQ8NumberofoutputDQ0Numberofstagesindqs_delay_chain3DQSinputfrequency150MHzUsehalf-ratecomponentsTurnedoff.
Thedesignusesfull-ratememorycomponents,soyoudonotselectthisoption.
UseDynamicOCTTurnedoff.
DynamicOCTisnotusedforinputpaths.
AddmemoryinterfacespecificfittergroupingassignmentsTurnedon.
Table2–6.
AdvanceOptions(DQSIN)ParameterSub-optionsValueEnableDQSInputPath—Turnedon.
Enabledqs_delay_chain—Selected.
AdvanceddelaychainoptionsSelectdynamicallyusingconfigurationregistersTurnedoff.
DQSdelaychain'delayctrlin'portsourceDLLTheDQSdelay-chainsettingsisbasedontheDLL.
DQSDelayBufferModeLowUsethesamemodeselectedintheDLLsettings.
DQSPhaseShift9000.
.
Specifya90°DQSphaseshift.
Thephase-shiftvaluemustinter-relatewiththeselecteddqs_delay_chainstage.
EnableDQSoffsetcontrolTurnedoff.
DisableDQSdelayfine-tuningusingoffsetfeature.
EnableDQSdelaychainlatchesTurnedoff.
2–9Chapter2:GettingStartedDesignExample:ImplementingReadPathsUsingStratixIIIDevicesALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporation7.
OntheDQSOUT/OEpage,turnofftheEnableDQSoutputpathoption.
WhenyoudeselecttheEnableDQSoutputpathoption,theotheroptionsonthispagearedisabled.
8.
OntheDQINpage,specifytheparametersasshowninTable2–7.
TheseparametersconfiguretheDQinputpathoftheALTDQ_DQSinstance.
9.
OntheDQOUT/OEpage,alltheoptionsareautomaticallydisabledbecausethedesignisnotusingoutputDQ.
TheparametersonthispageconfiguretheDQoutputandOEpathsoftheALTDQ_DQSinstance.
10.
OntheHalf-ratepage,fortheIOClockDividerInvertPhaseparameter,turnonNeverbecausethedesignrequiresfull-ratecomponents.
Theotheroptionsareautomaticallydisabled.
Theparametersonthispageconfigurethehalf-ratesettingsoftheALTDQ_DQSinstance.
11.
OntheOCTPathpage,alltheoptionsareautomaticallydisabledbecausethedesignisnotusinginputandoutputDQSorbidirectionalDQ.
TheparametersonthispageconfiguretheOCTpathoftheALTDQ_DQSinstance.
12.
OntheDQSnI/Opage,turnofftheUseDQSnI/OoptionbecausethedesignisnotusingDQSn.
WhenyouturnofftheUseDQSnI/Ooption,theotheroptionsonthispagearedisabled.
13.
IntheReset/ConfigPortstab,tunoffalltheparameters.
14.
ClickFinish.
15.
ClickFinish.
TheALTDQ_DQSinstanceisgenerated.
16.
ClickOKtoclosetheSymbolwindow.
17.
PlacetheinstanceontheBlockEditor.
EnableDQSbusoutdelaychain—Turnedon.
EnableDQSenableblock—Turnedon.
Table2–7.
AdvanceOptions(DQIN)OptionsValueDQinputregistermodeDDIOSelectDDIOtoenabledoubledataratecaptureforDQ.
DQinputregisterclocksourcedqs_bus_outportandturnoffConnectDDIOclkntoDQS_BUSfromcomplementaryDQSnUseDQinputphasealignmentTurnedoff.
Thefeatureisforhalf-ratecomponents;thedesignusesfull-ratememorycomponents.
UseDQinputdelaychainTurnedon.
Table2–6.
AdvanceOptions(DQSIN)ParameterSub-optionsValueChapter2:GettingStarted2–10DesignExample:ImplementingReadPathsUsingStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideGeneratetheALTIOBUFMegafunctionYoumustgeneratetheALTIOBUFmegafunctiontosetthefollowingI/Obuffersettings:1inputbufferforinputDQSpin8inputbuffersforinputDQpinsTogeneratetheALTIOBUFmegafunction,performthefollowingsteps:1.
Double-clickanywhereontheBlockEditorwindow.
TheSymbolwindowappears.
2.
ClickMegaWizardPlug-InManager.
Page1oftheMegaWizardPlug-InManagerappears.
3.
SelectCreateanewcustommegafunctionvariation.
4.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
SelectALTIOBUF,andVerilogHDL,andtypethefilenameasibuf_input_dqs.
v(forDQSpin)oribuf_input_dq.
v(forDQpins).
5.
OntheParameterSettingspage,specifytheparametersasshowninTable2–8.
TheseparametersconfigurethegeneralsettingsfortheALTIOBUFinstance.
6.
OntheDynamicDelayChainspage,specifytheparametersasshowninTable2–9.
Table2–8.
ALTIOBUFGeneralSettingsSettingsValue1inputbufferfortheinputDQSpins8inputbufferfortheinputDQpinsCurrentlyselecteddevicefamilyStratixIIIStratixIIIHowdoyouwanttoconfigurethismoduleAsaninputbufferAsaninputbufferWhatisthenumberofbufferstobeinstantiated18UsebusholdcircuitryTurnedoff.
Turnedoff.
UsedifferentialmodeTurnedoff.
Turnedon.
UseopendrainoutputTurnedoff.
Turnedoff.
UseoutputenableportTurnedoff.
Turnedoff.
UsedynamicterminationcontrolTurnedoff.
Turnedoff.
UseseriesandparallelterminationcontrolTurnedoff.
Turnedoff.
Table2–9.
ALTIOBUFDynamicDelayChainSettingsSettingsValue1inputbufferfortheinputDQSpins8inputbufferfortheinputDQpinsEnableinputbufferdynamicdelaychainTurnedoff.
Turnedoff.
Enableoutputbufferdynamicdelaychain1Turnedoff.
Turnedoff.
Enableoutputbufferdynamicdelaychain2Turnedoff.
Turnedoff.
Createa'clkena'portTurnedoffTurnedoff.
Chapter2:GettingStarted2–11DesignExample:ImplementingReadPathsUsingStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide7.
ClickFinish.
8.
ClickFinish.
TheALTIOBUFinstanceisgenerated.
9.
ClickOKtoclosetheSymbolwindow.
10.
PlacetheinstanceontheBlockEditor.
fFormoreinformationaboutconnectingalltheinstances,referto"IntegratetheI/OBufferModuleswiththeALTDQ_DQSmodules"onpage4–55.
11.
OntheBlockEditor,connectalltheinstancesasshowninFigure2–2onpage2–11.
Figure2–2.
BlockDiagramoftheDesignExample2–12Chapter2:GettingStartedDesignExample:ImplementingReadPathsUsingStratixIIIDevicesALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationCompileandSimulatetheDesignOntheProcessingmenu,clickStartCompilationtocompilethedesign.
Afterthedesigniscompiled,youcanviewtheimplementionintheRTLViewer.
YoucanalsoviewtheresourceusageintheCompilationReport.
Afteryoucompileyourdesign,simulatethedesignintheModelSim-Alterasoftwaretogenerateawaveformdisplayofthedevicebehavior.
SetupandsimulatethedesignintheModelSim-Alterasoftwarebyperformingthefollowingsteps:1.
Unzipthealtdll_altdq_dqs_ex1_msim.
zipfiletoyourpreferredworkingdirectoryonyourPC.
2.
StarttheModelSim-Alterasoftware.
3.
OntheFilemenu,clickChangeDirectory.
4.
Selectthefolderinwhichyouunzippedthefilesinthealtdll_altdq_dqs_ex1_msim.
zipfolder.
5.
ClickOK.
6.
OntheToolsmenu,pointtoTclandclickExecuteMacro.
7.
Selectthealtdll_altdq_dqs_ex1_msim.
dofileandclickOpen.
ThisisascriptfilefortheModelSim-Alterasoftwaretoautomateallthenecessarysettingsforthesimulation.
8.
Verifytheresultswiththesimulationwaveform.
1Youcanrearrange,removeandaddsignals,andchangetheradixbymodifyingthescriptinthealtdll_altdq_dqs_ex1_msim.
dofile.
February2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide3.
ParameterSettingsTheQuartusIIsoftwareprovidestheMegaWizardPlug-InManagerthathelpsyouquicklycustomizeyourmegafunctionvariation.
Theparametereditorprovidesalistofmegafunctionsandavailableoptionsforeachvariation.
AlterarecommendsthatyouusetheparametereditortoinstantiatetheALTDLLandALTDQ_DQSmegafunctions.
However,foradvancedusers,ifyouwanttobypasstheMegaWizardPlug-InManagerandusethemegafunctionsasdirectlyparameterizedinstantiationsinyourdesign,youcanusetheclearboxgenerator.
Formoreinformationabouttheclearboxgenerator,refertoAppendixA,ClearBoxGenerator.
1Someadvancedparameterscanonlybemodifiedthroughtheclearboxparameters.
ALTDLLParameterEditorThissectionprovidesinformationabouttheALTDLLMegaWizardparameters.
1Foradvanceduserswhomayusetheclearboxgenerator,theclearboxparameternamesareprovidedforthecorrespondingMegaWizardparameters.
TheALTDLLParameterSettingspageintheALTDLLparametereditorallowsyoutoconfiguretheparametersinthefollowingpages:GeneralDLLOffsetControls/OptionalPortsTable3–1showstheoptionsavailableontheGeneralpage.
3–2Chapter3:ParameterSettingsALTDLLParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTable3–1.
OptionsonGeneralSettingsPageParameterNameLegalValueClearBoxParameterNameDescriptionNumberofDelayChains6,8,10,12,or16DELAY_CHAIN_LENGTHRepresentsthenumberofdelaybuffersinthedelayloop.
TheDLLconsistsof6,8,10,12,or16DLL-controlleddelaybufferschainedtogether.
ThetotaldelayintheDLLdelaychainiscomputedwiththefollowingequation:delay=delay_chain_lengthxdelay_buffer_delayTheDLLusesthedelaychaintoimplementa360°phaseshift.
Bycomparingtheincomingclocktothe360°-shiftedclock,theDLLdeterminesthedelaysettingtoimplementanactual360°phaseshiftinitsdelaychain.
Becauseeachdelaybufferisidentical,eachbufferinthedelaychainimplementsaphaseshiftthatisequalto(360/delay_chain_length)°.
Thedefaultvalueis12.
DQSDelayBufferModeLoworHighDELAY_BUFFER_MODESpecifiesthefrequencymodeforthevariabledelaybuffers.
IfyouselectLow,thedll_offset_ctrl_a_offsetctrlout[5.
.
0]ordll_offset_ctrl_b_offsetctrlout[5.
.
0]outputislimitedtoamaximumvalueof63.
IfyouselectHigh,theoutputislimitedtoamaximumvalueof31.
ThedefaultvalueisLow.
InputClockFrequencyINPUT_FREQUENCYSpecifiesthefrequencyoftheclock(inMHz)thatisconnectedtotheclkinputport.
Thisfrequencymustbewithinthevalidrangeforthedeviceyouareusing.
Youcanspecifyadurationinps.
Thevalueisinfloating-pointformatwithnodecimalpointlimit.
Thedefaultvalueis300MHz.
ForinformationabouttheclockrangefortheAlteradevices,refertotherespectivedevicehandbook.
Turnonjitterreduction—JITTER_REDUCTIONEnablesthejitterreductioncircuit.
JitteraffectsthesignalintegrityoftheclocksignalfromaPLLclocksourceoranexternalclockpin.
Ifyouturnonthisparameter,thejitterreductioncircuitisenabledonthedll_delayctrlout[5.
.
0]anddll_offset_ctrl_a_offsetctrlout[5.
.
0],orthedll_offset_ctrl_b_offsetctrlout[5.
.
0]outputport.
Whenthejitterreductioncircuitisenabled,theDLLmayrequireupto1,024clockcyclestolock.
Whenthejitterreductioncircuitisdisabled,theDLLrequiresonlyupto256clockcyclestolock.
Chapter3:ParameterSettings3–3ALTDLLParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTheDLLOffsetControls/OptionalPortspageallowsyoutoinstantiatetheDLLoffsetcontrolblocks(AandB),specifywhethertousestaticoffset,andcreatethedll_aloadanddll_dqsupdateoptionalports.
Table3–2showstheoptionsavailableonDLLOffsetControls/OptionalPortspage.
.
Table3–2.
OptionsonDLLOffsetControls/OptionalPortsPage(Part1of2)ParameterNameLegalValueClearBoxParameterNameDescriptionDLLPhaseOffsetControlAInstantiatedll_offset_ctrlblockSetstaticallytoorSetdynamicallyusingoffsetinputportUSE_DLL_OFFSET_CTRL_AInstantiatesDLL_OFFSET_CTRL_Ablock.
Theblockcanbeplacedeitheratthetop,bottom,orsideoftheFPGAdevice,dependingonhowtheQuartusIIFitterplacesit.
Ifyouturnonthisparameter,youmustspecifywhetheryouwanttosettheblocksstaticallyordynamically.
–63to63DLL_OFFSET_CTRL_A_STATIC_OFFSETTheSetstaticallytooptionisasignedinteger.
Turnonthisoptionifyouwantafixedoffsetvalue,andkeyinthevalueyouwant.
ThisfixedvalueisaddedtotheDLLfeedbackcounterandtheoutputisgeneratedonthedll_offset_ctrl_a_offsetctrlout[5.
.
0]outputport.
Thedefaultvalueis0.
—DLL_OFFSET_CTRL_A_USE_OFFSETTheSetdynamicallyusingoffsetinputportoptiondeterminestheoutputofthedll_offset_ctrl_a_offsetctrlout[5.
.
0]outputport.
Turnonthisoptionifyouwantadynamicoffsetvalue.
Ifyouturnonthisoption,dependingonwhetherthedll_offset_ctrl_a_addnsubsignalisassertedornot,thephaseoffsetspecifiedontheoffsetinputbusisaddedorsubtractedfromtheDLLfeedbackcounteroutputtogetthedll_offset_ctrl_a_offsetctrlout[5.
.
0]output.
3–4Chapter3:ParameterSettingsALTDLLParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTheSimulationModelpageallowsyoutooptionallygeneratesimulationmodelfiles.
TheSummarypagedisplaysalistofthetypesoffilestobegenerated.
Theautomaticallygeneratedvariationfilecontainswrappercodeinthelanguageyouspecifiedearlier.
Onthispage,youcanspecifyadditionaltypesoffilestobegenerated.
DLLPhaseOffsetControlBInstantiatedlloffset_ctrlblockSetstaticallytoorSetdynamicallyusingoffsetinputportUSE_DLL_OFFSET_CTRL_BInstantiatesDLL_OFFSET_CTRL_Bblock.
Theblockcanbeplacedeitheratthetop,bottom,orsideoftheFPGAdevice,dependingonhowtheQuartusIIFitterplacesit.
Ifyouturnonthisoption,youmustspecifywhetheryouwanttosettheblocksstaticallyordynamically.
–63to63DLL_OFFSET_CTRL_B_STATIC_OFFSETTheSetstaticallytooptionisasignedinteger.
Turnonthisoptionifyouwantafixedoffsetvalue,andkeyinthevalueyouwant.
ThisfixedvalueisaddedtotheDLLfeedbackcounterandtheoutputisgeneratedonthedll_offset_ctrl_b_offsetctrlout[5.
.
0]outputport.
Thedefaultvalueis0.
—DLL_OFFSET_CTRL_B_USE_OFFSETTheSetdynamicallyusingoffsetinputportoptiondeterminestheoutputofthedll_offset_ctrl_b_offsetctrlout[5.
.
0]outputbus.
Turnonthisoptionifyouwantadynamicoffsetvalue.
Ifyouturnonthisoption,dependingonwhetherthedll_offset_ctrl_b_addnsubsignalisassertedornot,thephaseoffsetspecifiedontheoffsetinputbusisaddedorsubtractedfromtheDLLfeedbackcounteroutputtogetthedll_offset_ctrl_b_offsetctrlout[5.
.
0]output.
OptionalPortsCreateadll_aloadport—DLL_ALOADEnablestheasynchronous-loadsignalfortheDLLupordowncounter.
Whenthedll_aloadsignalishigh,thecounterisasynchronouslyloadedwiththeinitialdelaysettingof16inlow-frequencymodewhenyouselectLowfortheDQSDelayBufferModeparameter,or32inhigh-frequencymodewhenyouselectHighfortheDQSDelayBufferModeparameter.
ThisinputdefaultstoGND.
OptionalPortsCreatea'dll_dqsupdate'port—DLL_DQSUPDATEEnablestheupdate-enablesignalforthedelay-settinglatchesintheDQSpins.
ThissignalonlyfeedsthedqsupdateenportoftheALTDQ_DQSmegafunction.
Tousethedll_dqsupdatesignal,youmustturnontheEnableDQSdelaychainlatchesoptionontheDQSINpageintheALTDQ_DQSparametereditor.
Table3–2.
OptionsonDLLOffsetControls/OptionalPortsPage(Part2of2)ParameterNameLegalValueClearBoxParameterNameDescriptionChapter3:ParameterSettings3–5ALTDQ_DQSParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideChoosefromthefollowingfiletypes:QuartusIIIPfile(.
qip)Instantiationtemplatefile(.
v)VerilogHDLblackboxfile(_bb.
v)AHDLIncludefile(.
inc)VHDLcomponentdeclarationfile(.
cmp)QuartusIIsymbolfile(.
bsf)IfyouselectGeneratenetlistontheSimulationModelpage,thefileforthatnetlistisalsoavailable.
Agraycheckmarkindicatesafilethatisautomaticallygenerated,andagreencheckmarkindicatesgenerationofanoptionalfileALTDQ_DQSParameterEditorThissectionprovidesinformationabouttheALTDQ_DQSMegaWizardparameters.
1Foradvanceduserswhomayusetheclearboxgenerator,theclearboxparameternamesareprovidedforthecorrespondingMegaWizardparameters.
TheParameterSettingspageintheALTDQ_DQSparametereditorallowsyoutoconfiguretheparametersinTable3–3.
3–6Chapter3:ParameterSettingsALTDQ_DQSParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporation.
Table3–3.
OptionsonParameterSettingsPage(Part1of2)ParameterNameLegalValueClearBoxParameterNameDescriptionRLDRAMIImodeNONE,x9,x18,orx36RLDRAMII_MODEEnablesRLDRAMIIsupportforALTDQ_DQSinstance.
Ifyouselectx9orx18mode,theDKpinsdonothavegroupassignments,buttheymustbeplacedinthesamebankorchipedgeastheotherpinsintheinterface.
Ifyouselectx36mode,theDK/DK#pinsmustbeplacedmanuallyinDQSlocations.
Ifyouselectx18mode,placetheDMpinsineithergroup0orgroup1,whichforcesQVLDtotheothergroup.
Ifyouselectx36mode,placetheDMpinsingroup0or1,andQVLDtobeingroup0or1.
Allcombinationsareallowed.
NotsupportedinArriaIIGX.
DatamaskpingroupNONE,GROUP0,orGROUP1DM_LOCSpecifiesthegroupassignmentfortheDMpingroup.
IfyouselectNONEfortheRLDRAMIImodeoption,thenthisoptiondefaultstoNONE.
Ifyouselectx9fortheRLDRAMIImodeoption,thenthisoptiondefaultstoNONE.
Ifyouselectx18fortheRLDRAMIImodeoption,thenforthisoptionyoucanselecteitherNONE,GROUP0,orGROUP1.
IfyouselectGROUP0,thenGROUP1isusedfortheQvalidsignalgroupoption,andifyouselectGROUP1,thenGROUP0isusedfortheQvalidsignalgroupoption.
Ifyouselectx36fortheRLDRAMIImodeoption,thenforthisoptionyoucanselecteitherNONE,GROUP0,orGROUP1.
NotsupportedinArriaIIGXdevices.
QvalidsignalgroupNONE,GROUP0,orGROUP1QVLD_LOCSpecifiesthegroupassignmentfortheQvalidsignalgroup.
IfyouselectNONEfortheRLDRAMIImodeoption,thenthisoptiondefaultstoNONE.
Ifyouselectx9fortheRLDRAMIImodeoption,thenthisoptiondefaultstoGROUP0.
Ifyouselectx18fortheRLDRAMIImodeoption,thenthisoptiondependsontheDatamaskpingroupoption.
IfyouselectGROUP0fortheDatamaskpingroupoption,thenGROUP1isdefaultedforthisoption,andifyouselectGROUP1fortheDatamaskpingroupoption,thenGROUP0isdefaultedforthisoption.
Ifyouselectx36fortheRLDRAMIImodeoption,thenforthisoptionyoucanselecteitherNONE,GROUP0,orGROUP1.
NotsupportedinArriaIIGXdevices.
NumberofbidirectionalDQ0–48NUMBER_OF_BIDIR_DQSpecifiesthenumberofbidirectionalDQportsusedintheALTDQ_DQSinstance.
Chapter3:ParameterSettings3–7ALTDQ_DQSParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTheAdvancedOptionspageallowsyoutoconfiguretheparametersinthefollowingpages:DQSINDQSOUT/OEDQINDQOUT/OEHalf-rateOCTPathDQSnI/ONumberofinputDQ0–48NUMBER_OF_INPUT_DQSpecifiesthenumberofinputDQportsusedintheALTDQ_DQSinstance.
NumberofoutputDQ0–48NUMBER_OF_OUTPUT_DQSpecifiesthenumberofoutputDQportsusedintheALTDQ_DQSinstance.
Numberofstagesindqs_delay_chain1,2,3,and4DQS_DELAY_CHAIN_PHASE_SETTINGSpecifiesthestagesofDQS_DELAY_CHAIN.
Thenumberofstagesdependsontheintendedphaseshiftthatyouwanttoclockfor_DDIO_INblockintheDQinputpath.
Thebiggerthevalueyouspecify,thelongerthedelay.
Thecoarsephaseshiftdependsonthisoption.
Forexample,inStratixIVdevices,ifyousetthefrequencymodeto1,youwillgetaphaseshiftof20°,60°,90°,or120°.
IfyousetNumberofstagesindqs_delay_chainvalueto2,youwillget60°phaseshiftandifyousettheNumberofstagesindqs_delay_chainvalueto1,youwillget30°phaseshift.
DQSinputfrequency—DQS_INPUT_FREQUENCYSpecifiestheinputfrequencyoftheDQSstrobeinMHz.
TheinputfrequencymustmatchtheDLL(ALTDLL)inputfrequency.
Usehalfratecomponents—USE_HALF_RATEInstantiatesthehalf-rateblocksintheALTDQ_DQSinstance.
Thisparameterisusedonlywhentheexternalmemoryinterfacerequireshalf-ratemode.
NotsupportedinArriaIIGXdevices.
UsedynamicOCTpath—USE_DYNAMIC_OCTInstantiatesthedynamicOCTblocksintheALTDQ_DQSinstance.
ThisparameterenablesaccesstodynamicOCTpathsonbothDQandDQSpaths.
ThedynamicOCTfeaturesenableparalleltermination(Rt)duringreadsfromtheexternalmemoryanddisableRtduringwritestotheexternalmemory.
NotsupportedinArriaIIGXdevices.
Addmemoryinterfacespecificfittergroupingassignments—ADD_MEM_FITTER_GROUP_ASSIGNMENTSEnablestheQuartusIIFittertoautomaticallyassignthememoryinterfaceI/OportstothememoryinterfaceI/OpinsontheFPGA.
Table3–3.
OptionsonParameterSettingsPage(Part2of2)ParameterNameLegalValueClearBoxParameterNameDescription3–8Chapter3:ParameterSettingsALTDQ_DQSParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationReset/ConfigPortsTable3–4describestheoptionsavailableontheDQSINpage.
ThispageallowsyoutoconfiguretheDQSinputpath.
FormoreinformationabouttheDQSinputpath,referto"DQSInputPath"onpage4–6.
Table3–4.
OptionsonDQSINPage(Part1of3)ParameterNameLegalValueClearBoxParameterNameDescriptionEnableDQSInputPath—USE_DQS_INPUT_PATHInstantiatestheDQSinputpath.
EnableDQSInputPath—USE_DQS_INPUT_PATHInstantiatestheDQSinputpath.
Delaychainusage:Enabledynamicdelaychain—USE_DQS_INPUT_DELAY_CHAINEnables_INPUT_DELAY_CHAIN(D1)ontheDQSinputpath.
Ifyouturnonthisparameter,DQS_DELAY_CHAINblockinthepathisdisabled.
D1isarun-timeadjustabledelaychain.
Toconfiguredelaychainsdynamically,referto"DelayChains"onpage4–15.
Delaychainusage:Enabledqs_delay_chain—USE_DQS_DELAY_CHAINEnablesDQS_DELAY_CHAINblock.
TheDQSdelaychainisaDLL-controlleddelaychainusedtophaseshifttheDQSreadclock.
EnableDQSbusoutdelaychain—USE_DQSBUSOUT_DELAY_CHAINEnablesDQSBUSOUT_DELAY_CHAIN(Da).
Thisbusoutdelaychainfine-tunestheoutputsofDQS_DELAY_CHAINblocksothattheDQSstrobetimingmatchestheDQSenablesignal.
TheDQSstrobehas15steppabledelays,witheachstephaving50psofdelay.
Daisarun-timeadjustabledelaychain.
EnableDQSenableblock—USE_DQS_ENABLEEnablesDQS_ENABLEblock.
ThisblockgroundstheDQSinputstrobewhenthestrobegoestohighimpedancestate(Z)afteraDDRreadpostamble.
EnableDQSenablecontrolblock—USE_DQS_ENABLE_CTRLEnablesDQS_ENABLE_CTRLblockthatcontrolsaDQSenablecircuitry.
Youmustdetermineanefficientworkingresync_postamble_clkclockphasewhichclocksthisblocktoensuresmoothdatatransfer.
TheALTDQ_DQSmegafunctioncannotdeterminethephaseforthedatatransfer.
Useroundtripdelay(RTD)analysisorcreateacustomdatatrainingcircuitrytowriteandreadbackatrainingpatterntoandfromthememorydeviceandthendynamicallyadjustthePLL'sresyncronizationclockphasetofindanefficientworkingphase.
EventhoughthisblockcontrolstheDQSenablesignal,themegafunctiondoesnotconsiderthenecessarytimingforthissignal.
Refertotheexternalmemoryinterfacerequirementsforthenecessarytiming.
Chapter3:ParameterSettings3–9ALTDQ_DQSParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideEnableDQSenableblockdelaychain——EnablesDQS_ENABLE_DELAY_CHAIN(Db)thatfine-tunestheoutputsofDQS_ENABLE_CTRLblocksothattheDQSenablesignaltimingmatchestheDQSstrobe.
Dbisarun-timeadjustabledelaychain.
AdvancedDelayChainOptionsSetdynamicallyusingconfigurationregisters—USE_DQS_DELAY_CHAIN_PHASECTRLINDeterminesthephasectrlininputforthephasesetting.
Ifyouturnonthisoption,itdynamicallychoosesthephaseappliedtothedqsbusoutoutputduringtheFPGAruntime.
Ifyouturnoffthisoption,thephasesettingisdeterminedbytheNumberofstagesindqs_delay_chainoptionintheParameterSettingspage.
Thisdelaychainfine-tunestheDQSstrobesignal.
AdvancedDelayChainOptionsDQSdelaychaindelayctrlinportsourceDLLorCoreDQS_DELAY_CHAIN_DELAYCTRLIN_SOURCEDetermineswhetheryouwantthedelayctrlinporttobecontrolledbyDLL(outputs)orfromtheCore(FPGA).
IfyouselectDLL,thedll_delayctrlin[5.
.
0]portisconnectedtothedll_delayctrlout[5.
.
0]portoftheDLL.
TheDLLoptionadjuststhedelaysettinginDQS_DELAY_CHAINblockacrosspressure,volume,andtemperature(PVT).
AlterarecommendsthatyoualwaysselectDLLtooptimizethereadcaptureattheDQinputregister.
IfyouselectCore,thecore_delayctrlinportisfedbythecore.
AdvancedDelayChainOptionsDQSDelayBufferModeLoworHighDELAY_BUFFER_MODESpecifieswhetherthevariabledelaybuffersintheDQS_DELAY_CHAINworkinlow-frequencyorhigh-frequencymode.
ThefrequencymodemustmatchthefrequencymodeyouselectfortheDQSDelayBufferModeparameterontheParameterSettingspageintheALTDLLparametereditor.
AdvancedDelayChainOptionsDQSPhaseShift0–36,000DQS_PHASE_SHIFTSpecifiesthephaseshiftbetweenthedelayedDQSsignalandtheinputDQSsignalinunitsofhundredsofdegrees,forexample,a90°phaseshiftisrepresentedas9,000.
Usethisparameterforstatictiminganalysisonlybecausetiminganalysiscannotdeterminethephaseshiftthroughthedelayctrlin[5.
.
0],phasectrlin[2.
.
0],andoffsetctrlin[5.
.
0]portsonthemegafunctionthewayasimulationcan.
Thisisanoptionalfieldanddefaultsto0.
AdvancedDelayChainOptionsEnableDQSoffsetcontrol—DQS_OFFSETCTRL_ENABLEEnablesoffsetvaluestobeaddedtoDQS_DELAY_CHAINblock.
Ifyouturnonthisoption,makesurethattheALTDLLinstanceissettousetheDLLoffsetcontrolblocks.
ThisoptionconnectstheoutputsfromtheDLLoffsetcontrolblockstotheDQSdelaychainblock.
Thisparameterisoptionalandturnedoffbydefault.
Table3–4.
OptionsonDQSINPage(Part2of3)ParameterNameLegalValueClearBoxParameterNameDescription3–10Chapter3:ParameterSettingsALTDQ_DQSParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTable3–5describesoptionsavailableontheDQSOUT/OEpage.
ThispageallowsyoutoconfiguretheDQSoutputandoutputenable(OE)paths.
FormoreinformationabouttheDQSoutputandOEpaths,referto"DQSOutput/OEPath"onpage4–12.
AdvancedDelayChainOptionsEnableDQSdelaychainlatches—DQS_CTRL_LATCHES_ENABLEEnablesthedelayctrlin[5.
.
0]andoffsetctrlin[5.
.
0]inputstoberegisteredbythedqsupdateensignal.
TheDLLcontinueschangingitsdelaysettingsvalueduetothefeedbacksystem.
TheseDLLvaluesarepropagatedthroughthedelayctrloutandoffsetctrloutsignalsoftheDLLandDLLoffsetcontrolblockstoDQS_DELAY_CHAINblocktocalibratethenecessarydelaysettings.
Thesevaluesareupdatedbasedonthedll_dqsupdateportfromtheDLL,whichisconnectedtothedqsupdateenport.
Tousethisoption,youmustturnontheCreatea'usedll_dqsupdate'portoptionontheDLLOffsetControls/OptionalPortspageintheALTDLLparametereditor.
AdvancedEnableControlOptionsDQSEnableControlPhaseSettingSetstaticallytoorSetdynamicallyusingconfigurationregistersDQS_ENABLE_CTRL_PHASE_SETTINGIfyouturnontheSetstaticallytooption,youcanselectthephasesettingforthedelaychainsfrom0upto4tofine-tunetheDQSenablesignal.
IfyouturnontheSelectdynamicallyusingconfigurationregistersoption,thephasesettingisdeterminedbythephasectrlininputforthedelaychains.
AdvancedEnableControlOptionsDQSEnableControlInvertPhaseAlways,Never,orBasedonconfigurationregistersDQS_ENABLE_CTRL_INVERT_PHASEIfyouturnonAlways,thephaseoutputisinverted.
IfyouturnonNever,thephaseoutputisnotinverted.
IfyouturnonBasedonconfigurationregisters,thephaseinvertctrlinputdetermineswhetherornottheinverterisused.
Theinvertercanbeusedtoincreasethenumberofavailablephases.
ThisisanoptionalfieldanddefaultstoNever.
EnableDQSenableblockdelaychain—USE_DQSENABLE_DELAY_CHAINEnablesDQS_ENABLE_DELAY_CHAIN.
Thisdelaychainfine-tunestheoutputsofDQS_ENABLE_CTRLblocksothattheDQSenablesignaltimingmatchestheDQSstrobe.
Thisdelaychainisarun-timeadjustabledelaychain.
Table3–4.
OptionsonDQSINPage(Part3of3)ParameterNameLegalValueClearBoxParameterNameDescriptionTable3–5.
OptionsonDQSOUT/OEPage(Part1of2)ParameterNameLegalValueClearBoxParameterNameDescriptionEnableDQSoutputpath—USE_DQS_OUTPUT_PATHInstantiatestheDQSoutputpath.
EnableDQSoutputpath—USE_DQS_OUTPUT_PATHInstantiatestheDQSoutputpath.
Chapter3:ParameterSettings3–11ALTDQ_DQSParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTable3–6describesoptionsavailableontheDQINpage.
ThispageallowsyoutoconfiguretheDQinputpath.
FormoreinformationabouttheDQinputpath,referto"DQInputPath"onpage4–8.
DQSOutputPathOptionsEnableDQSoutputdelaychain1—USE_DQS_OUTPUT_DELAY_CHAIN1EnablesDQS_OUTPUT_DELAY_CHAIN1(D5)intheDQSoutputpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D5isarun-timeadjustabledelaychain.
DQSOutputPathOptionsEnableDQSoutputdelaychain2—USE_DQS_OUTPUT_DELAY_CHAIN2EnablesDQS_OUTPUT_DELAY_CHAIN2(D6)intheDQSoutputpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D6isarun-timeadjustabledelaychain.
DQSOutputPathOptionsDQSoutputregistermodeNotused,FF,orDDIODQS_OUTPUT_REG_MODEEnablestheDQS_OUTPUT_FForDQS_OUTPUT_DDIO_OUToutputregisters.
SelectFFifyouwantflip-flopoutputregistersorDDIOifyouwantdoubledatarateI/Oregisters.
DQSOutputEnableOptionsEnableDQSoutputenable—USE_DQS_OE_PATHInstantiatesDQSoutputenablepath.
DQSOutputEnableOptionsEnableDQSoutputenabledelaychain1—USE_DQS_OE_DELAY_CHAIN1EnablesDQS_OUTPUT_DELAY_CHAIN1(D5)intheDQSOEpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D6isarun-timeadjustabledelaychain.
DQSOutputEnableOptionsEnableDQSoutputenabledelaychain2—USE_DQS_OE_DELAY_CHAIN2EnablesDQS_OUTPUT_DELAY_CHAIN2(D6)intheDQSOEpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D6isarun-timeadjustabledelaychain.
DQSOutputEnableOptionsDQSoutputenableregistermodeNotused,FF,orDDIODQS_OE_REG_MODEEnablestheDQS_OUTPUT_FForDQS_OUTPUT_DDIO_OUToutputregisters.
SelectFFifyouwantflip-flopregistersorDDIOifyouwantdoubledatarateI/Oregisters.
Table3–5.
OptionsonDQSOUT/OEPage(Part2of2)ParameterNameLegalValueClearBoxParameterNameDescription3–12Chapter3:ParameterSettingsALTDQ_DQSParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTable3–6.
OptionsonDQINPage(Part1of3)ParameterNameLegalValueClearBoxParameterNameDescriptionDQInputRegisterOptionsDQinputregistermodeNotused,FF,orDDIODQ_INPUT_REG_MODEEnablestheDQinputregisters(_INPUT_FFor_DDIO_INregisters).
SelectFFifyouwantflip-flopregistersorDDIOifyouwantdoubledatarateI/Oregisters.
DQInputRegisterOptionsDQinputregisterclocksource'dqs_bus_out'port,Inverted'dqs_bus_out'port,orCoreDQ_INPUT_REG_CLK_SOURCESpecifieshowtheDQinputregistersshouldbeclocked.
Youcaneitherclockitfromthe'dqs_bus_out'port(DQSinputpath),theInverted'dqs_bus_out'port(DQSinputpath),ordirectlyfromtheCore(FPGA).
Alterarecommendsthatyouturnonthe'dqs_bus_out'portoptiontoclocktheDQinputregister.
Whenreadingfromtheexternalmemory,theDQdatathatcomesintotheDDIOmustbecenter-alignedwiththeDQSstrobethatgoesthroughtheDQSinputpathandcomesoutthedqs_bus_outport.
Bycenter-aligningtheDDIOwithDQSstrobe,youmaximizethesetupandholdmarginsattheDQinputregister.
Youcanalsoconnectthedqs_bus_outporttothefull-rateDQinputregisterforcomplementaryclockingpurposeasusedinQDRandQDRIIapplications.
Youcanconnectthedqs_bus_outportbyturningontheConnectDDIOclkntoDQS_BUSfromcomplementaryDQSnoption.
DQInputRegisterOptionsUseDQinputphasealignment—USE_DQ_IPAEnablestheinputphasealignment(_IPA_LOWor_IPA_HIGH)blocks.
Theinputphasealignmentblocksrepresentthecircuitryrequiredtophase-shifttheinputsignaltheDQdataforresynchronizationandalignmentpurpose.
TheresynchronizationandalignmentaredonetomatchthearrivaldelayoftheDQS(triggeredbythefly-byclockonaDDR-DIMM)tothelatestarrivaldelayofaDQSfromtheDIMM.
Becausethisblockismeantforresynchronization,theALTDQ_DQSmegafunctiondoesnotconsidertheclockingrequirementsofthisblock.
YoumustfiguretheclockingrequirementsusingtheRTDanalysisorcreateacustomdatatrainingcircuitrytoreadorwritebackatrainingpatterntoandfromthememorydevice,andthendynamicallyadjustthePLL'sresyncronizationclockphasetofindagoodworkingphase.
Formorecomponentinformationabouttheavailablealignmentandresynchronizationregistersinthisblock,refertothe"I/OElement(IOE)Registers"sectionintheExternalMemoryInterfacechapteroftherespectivedevicehandbooks.
Fortheavailablelevellingdelaychainsinthisblock,refertothe"LevelingCircuitry"sectionintheExternalMemoryInterfacechapteroftherespectivedevicehandbooks.
Chapter3:ParameterSettings3–13ALTDQ_DQSParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQInputRegisterOptionsUseDQresyncregister—DQ_RESYNC_REG_MODEEnablestheDQresynchronizationregister.
SupportedinArriaIIGXdevicesonly.
DQInputRegisterOptionsUseDQhalfrate'dataoutbypass'port—DQ_HALF_RATE_USE_DATAOUTBYPASSIfyouturnonthisparameter,thedataoutbypassinputdynamicallyroutesthedirectininputtothedataoutoutputfor_HALF_RATE_INPUTblock.
Usingthisparameter,youcanbypassthehalf-rateregistersin_HALF_RATE_INPUTblockdynamicallyduringtheFPGArun-time.
NotsupportedinArriaIIGXdevices.
AdvancedDQIPAOptionsDQInputPhaseAlignmentPhaseSettingSetstaticallytoorSetdynamicallyusingconfigurationregistersDQ_IPA_PHASE_SETTINGIfyouturnontheSetstaticallytooption,thephasesettingcanbeselectedfromvalues0to7forthedelaychains.
IfyouturnontheSelectdynamicallyusingconfigurationregistersoption,thephasesettingisdeterminedbythephasectrlininputforthedelaychains.
Thisparameterfine-tunestheresynchronizationphasefortheDQinputdata.
Thephasesettingsarealsocalledthelevellingdelaychainsthathandlethefly-byclocktopologyinDDR3interfaces.
AdvancedDQIPAOptionsAddDQInputPhaseAlignmentInputCycleDelayAlways,Never,orBasedonconfigurationregistersDQ_IPA_ADD_INPUT_CYCLE_DELAYIfyouturnonAlways,asinglecycledelayisaddedtotheinputpath.
IfyouturnonNever,nodelayisadded.
IfyouturnonBasedonconfigurationregisters,theenainputcycledelaysettinginputcontrolswhetherornotasinglecycledelayisaddedtotheinputpath.
AdvancedDQIPAOptionsInvertDQInputPhaseAlignmentPhaseAlways,Never,orBasedonconfigurationregistersDQ_IPA_INVERT_PHASEIfyouturnonAlways,thephaseoutputisinverted.
IfyouturnonNever,thephaseoutputisnotinverted.
IfyouturnonBasedonconfigurationregisters,thephaseinvertctrlinputdetermineswhetherornottheinverterisused.
Theinverterisusedtoincreasethenumberofavailablephases.
AdvancedDQIPAOptionsRegisterDQinputphasealignmentbypassoutput—DQ_IPA_BYPASS_OUTPUT_REGISTERControlstheoutputregisterintheDQinputpath.
Ifyouturnonthisoption,theoutputdatabypassestheoutputregister.
Ifyouturnoffthisoption,thenthedatagoesthroughtheoutputregister.
Table3–6.
OptionsonDQINPage(Part2of3)ParameterNameLegalValueClearBoxParameterNameDescription3–14Chapter3:ParameterSettingsALTDQ_DQSParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTable3–7describesoptionsavailableontheDQOUT/OEpage.
ThispageallowsyoutoconfiguretheDQoutputandOEpaths.
FormoreinformationabouttheDQoutputandOEpaths,referto"DQOutput/OEPath"onpage4–10.
AdvancedDQIPAOptionsRegisterDQinputphasealignmentaddphasetransfer—DQ_IPA_ADD_PHASE_TRANSFER_REGIfyouturnonthisoption,anegativeedge-triggeredregisterisaddedinthedatapathfortheclockphasetransfer.
Ifyouturnoffthisoption,noregisterisadded.
Thenegative-edgeregisterisusedtoguaranteethesetupandholdtimeforaphasetransfer.
UseDQinputdelaychain—USE_DQ_INPUT_DELAY_CHAINEnables_INPUT_DELAY_CHAIN(D1).
ThisparameterisusedfordeskewpurposesorSSNreductionontheDQinputpath.
NotsupportedinArriaIIGXdevices.
Formoreinformationaboutconfiguringdelaychainsdynamically,referto"DelayChains"onpage4–15.
Table3–6.
OptionsonDQINPage(Part3of3)ParameterNameLegalValueClearBoxParameterNameDescriptionTable3–7.
OptionsonDQOUT/OEPage(Part1of2)ParameterNameLegalValueClearBoxParameterNameDescriptionDQOutputPathOptionsEnableDQoutputdelaychain1—USE_DQ_OUTPUT_DELAY_CHAIN1Enables_OUTPUT_DELAY_CHAIN1(D5)intheDQoutputpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D5isarun-timeadjustabledelaychain.
Formoreinformationaboutconfiguringdelaychainsdynamically,referto"DelayChains"onpage4–15.
DQOutputPathOptionsEnableDQoutputdelaychain2—USE_DQ_OUTPUT_DELAY_CHAIN2Enables_OUTPUT_DELAY_CHAIN2(D6)intheDQoutputpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D6isarun-timeadjustabledelaychain.
Formoreinformationaboutconfiguringdelaychainsdynamically,referto"DelayChains"onpage4–15.
DQOutputPathOptionsDQoutputregistermodeNotused,FF,orDDIODQ_OUTPUT_REG_MODEEnablesthefull-rateDQoutputregisters(_OUTPUT_FFor_OUTPUT_DDIO_OUTregisters).
DQOutputEnableOptionsEnableDQoutputenable—USE_DQ_OE_PATHInstantiatestheDQoutputenablepath.
DQOutputEnableOptionsEnableDQoutputenabledelaychain1—USE_DQ_OE_DELAY_CHAIN1Enables_OE_DELAY_CHAIN1(D5)intheDQOEpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D5isarun-timeadjustabledelaychain.
Formoreinformationaboutconfiguringdelaychainsdynamically,referto"DelayChains"onpage4–15.
Chapter3:ParameterSettings3–15ALTDQ_DQSParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTable3–8describestheoptionsavailableontheHalf-ratepage.
DQOutputEnableOptionsEnableDQoutputenabledelaychain2—USE_DQ_OE_DELAY_CHAIN2Enables_OE_DELAY_CHAIN2(D6)intheDQOEpath.
ThisparameterisusedfordeskewpurposesorSSNreduction.
D6isarun-timeadjustabledelaychain.
Formoreinformationaboutconfiguringdelaychainsdynamically,referto"DelayChains"onpage4–15.
DQOutputEnableOptionsDQoutputenableregistermodeNotused,FF,orDDIODQ_OE_REG_MODEEnablesthefull-rateDQoutput-enableregisters(_OE_FFor_OE_DDIO_OEregisters).
SelectFFifyouwantflip-flopregistersorDDIOifyouwantdoubledatarateI/Oregisters.
Table3–7.
OptionsonDQOUT/OEPage(Part2of2)ParameterNameLegalValueClearBoxParameterNameDescriptionTable3–8.
OptionsonHalf-RatePage(Part1of2)ParameterNameLegalValueClearBoxParameterNameDescriptionIOClockDividerSourceCore,'dqs_bus_out'port,orInverted'dqs_bus_out'portIO_CLOCK_DIVIDER_CLK_SOURCESpecifiestheI/OclockdividerclocksourcewhichcanbefromtheCore(FPGA),the'dqs_bus_out'port(DQSinputpath),ortheInverted'dqs_bus_out'port(DQSinputpath).
Alterarecommendsthatyouturnonthe'dqs_bus_out'portoptiontoclocktheDQinputregister.
Whenreadingfromtheexternalmemory,theDQdatathatcomesfromthefull-rateDQinputregistersmustbesynchronizedtothehalf-rateinputblock,ifhalf-rateinterfacesareused.
Ifthefull-rateDQinputregistersareclockedbytheDQSinputpathviathedqs_bus_outport,thentheI/Oclockdivider(andotherclocksourcesettings)mustalsobeclockedviathedqs_bus_outport.
Create'io_clock_divider_masterin'inputport—USE_IO_CLOCK_DIVIDER_MASTERINEnablesthemasterininputtosynchronizethisdividerwithanotherI/Oclockdivider.
Ifyouturnoffthisoption,thisdivideroperatesindependently.
Thismodeismeantforthemasterdividerofagroupofdividers.
TurnonthisparameterwhenyouchaintheI/OclockdividerblocksfrommultipleALTDQ_DQSinstances.
Create'io_clock_divider_clkout'outputport——Dividestheclockoutputsignalbytwo.
Theclockoutsignalcanbeconnectedtotheclockinputofahalf-rateInputblockorfedtotheFPGAcore.
3–16Chapter3:ParameterSettingsALTDQ_DQSParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTable3–9onpage3–16describestheoptionsavailableontheOCTPathpage.
ThispageallowsyoutoconfiguretheDQandDQSOCTpaths.
FormoreinformationabouttheDQandDQSOCTpaths,referto"DQ/DQSOCTPath"onpage4–14.
Create'io_clock_divider_slaveout'outputport—USE_IO_CLOCK_DIVIDER_SLAVEOUTEnablestheoutputofthedivider'sDflip-flop(DFF).
TheoutputsignalcanonlybeconnectedtothemasterininputofanotherI/Oclockdividerblockanditcannothavemorethanonefan-out.
TurnonthisparameterwhenyouchaintheI/OclockdividerblocksfrommultipleALTDQ_DQSinstances.
IOClockDividerInvertPhaseAlways,Never,orBasedonregisterconfigurationIO_CLOCK_DIVIDER_INVERT_PHASEIfyouturnonAlways,thephaseoutputisinverted.
IfyouturnonNever,thephaseoutputisnotinverted.
IfyouturnonBasedonregisterconfiguration,thephaseinvertctrlinputdetermineswhetherornottheinverterisused.
Theinvertercanbeusedtoincreasethenumberofavailablephases.
Table3–8.
OptionsonHalf-RatePage(Part2of2)ParameterNameLegalValueClearBoxParameterNameDescriptionTable3–9.
OptionsonOCTPathPageParameterNameLegalValueClearBoxParameterNameDescriptionDynamicTerminationControlOptionsEnableDynamicDelay-chain1—USE_OCT_DELAY_CHAIN1Enables_OCT_DELAY_CHAIN1(D5)onboththeDQandDQSdynamicOCTpaths.
TheexternalmemoryinterfacessynchronizethetimingoftheturningonandoffoftheparallelterminationduringreadsandwritesfromboththeDQandDQSpins,andtoimproveoveralltimingmargins.
D5isarun-timeadjustabledelaychain.
Formoreinformationaboutconfiguringdelaychainsdynamically,referto"DelayChains"onpage4–15.
DynamicTerminationControlOptionsEnableDynamicDelay-chain2—USE_OCT_DELAY_CHAIN2Enables_OCT_DELAY_CHAIN2(D6)onboththeDQandDQSdynamicOCTpaths.
TheexternalmemoryinterfacessynchronizethetimingofturningonandoffoftheparallelterminationduringreadsandwritesfromboththeDQandDQSpins,andtoimproveoveralltimingmargins.
D6isarun-timeadjustabledelaychain.
Formoreinformationaboutconfiguringdelaychainsdynamically,referto"DelayChains"onpage4–15.
OCTregistermodeNotused,FF,orDDIOOCT_REG_MODEEnablesthefull-ratedynamicOCTregisters(_OCT_FFor_OCT_DDIOregisters)onboththeDQandDQSdynamicOCTpaths.
SelectFFifyouwantflip-flopregistersorDDIOifyouwantdoubledatarateI/Oregisters.
Formorecomponentinformationaboutthisblock,refertothe"DynamicOn-ChipTerminationControl"sectionintheExternalMemoryInterfacechapteroftherespectivedevicehandbooks.
Chapter3:ParameterSettings3–17ALTDQ_DQSParameterEditorFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTable3–10describestheoptionsavailableontheDQSnI/Opage.
ThispageallowsyoutoconfiguretheDQSandDQSnI/OpinsfortheALTDQ_DQSinstance.
Theseoptionsareusedformemoryinterfacesthatneeddifferentialorcomplementarystrobes.
Table3–11describestheoptionsavailableontheReset/ConfigPortspage.
Formoreinformationaboutresetandconfigports,referto"ALTDQ_DQSMegafunctionPorts"onpage4–33.
Table3–10.
OptionsonDQS/DQSnI/OPageParameterNameLegalValueClearBoxParameterNameDescriptionUseDQSnI/O—DQS_DQSN_MODEEnablesaccesstotheDQSI/Othatisconfiguredaseitherdifferentialorcomplementary.
AlterarecommendsthatyouusedifferentialDQSforDDR3interfacestoimprovesignalintegrity.
IftheDQSnI/Oisdisabled,thevaluefortheDQS_DQSN_MODEparameterisnone.
Whenenabled,thevaluemayeitherComplementarypairorDifferentialpair.
DQSandDQSnIOConfigurationmodeDifferentialpairorComplementarypairDQS_DQSN_MODEIfyouturnontheDifferentialpairoption,theDQSnI/OpinisconfiguredinadifferentialpairalongwiththeDQSI/Opin.
ThismeansthattheOEandOCTpathsareconfiguredfortheDQSnI/Opin,whichissimilartotheDQSI/Opin.
TheinputandoutputpathsaresharedwiththeDQSI/Opin.
ThismodeisusedmainlyforDDR2andDDR3SDRAM,andRLDRAMIIapplications.
IfyouturnontheComplementarypairoption,theDQSnI/OpinisconfiguredinacomplementarypairalongwiththeDQSI/Opin.
Inthismode,theDQSnI/OpinisconfiguredsimilarlytotheDQSI/Opin.
ThismodeisusedmainlyforQDR/QDRIIapplications.
Table3–11.
OptionsonReset/ConfigPortsPage(Part1of2)ParameterNameLegalValueClearBoxParameterNameDescriptionResetportsCreate'dqs_areset'inputport——EnablestheasynchronousresetportthatasynchronouslyresetsallregistersintheDQSoutputorDQSOEpath.
ResetportsCreate'dqs_sreset'inputport——EnablessynchronousresetportthatsynchronouslyresetsallregistersintheDQSoutputorDQSOEpath.
ResetportsCreate'input_dq_areset'inputport——EnablesasynchronousresetportthatasynchronouslyresetsallregistersintheDQinputpath.
3–18Chapter3:ParameterSettingsALTDQ_DQSParameterEditorALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTheSimulationModelpageallowsyoutooptionallygeneratesimulationmodelfiles.
TheSummarypagedisplaysalistofthetypesoffilestobegenerated.
Theautomaticallygeneratedvariationfilecontainswrappercodeinthelanguageyouspecifiedearlier.
Onthispage,youcanspecifyadditionaltypesoffilestobegenerated.
ChoosefromtheAHDLIncludefile(.
inc),VHDLcomponentdeclarationfile,.
cmp),QuartusIIsymbolfile(.
bsf),Instantiationtemplatefile(.
v),andVerilogHDLblackboxfile(_bb.
v).
IfyouselectGeneratenetlistontheSimulationModelpage,thefileforthatnetlistisalsoavailable.
Agraycheckmarkindicatesafilethatisautomaticallygenerated,andaredcheckmarkindicatesgenerationofanoptionalfile.
ResetportsCreate'input_dq_sreset'inputport——EnablessynchronousresetportthatsynchronouslyresetsallregistersintheDQinputpath.
ResetportsCreate'output_dq_areset'inputport——EnablesasynchronousresetportthatasynchronouslyresetsallregistersintheDQoutputorDQOEpath.
ResetportsCreate'output_dq_sreset'inputport——EnablessynchronousresetportsynchronouslyresetsallregistersintheDQoutputorDQOEpath.
ResetportsCreate'bidir_dq_areset'inputport——EnablesasynchronousresetportthatasynchronouslyresetsallregistersinthebidirectionalDQI/Opath.
ResetportsCreate'bidir_dq_sreset'inputport——EnablessynchronousresetportthatsynchronouslyresetsallregistersinthebidirectionalDQI/Opath.
ConfigportsCreate'config_clk'inputport——EnablesinputclockportthatfeedsIO_CONFIGblockforuser-drivendynamicdelaychain.
Thisinputportisusedastheclocksignaloftheshiftregisterblock.
Themaximumfrequencyforthisclockis30MHz.
ConfigportsCreate'config_datain'inputport——EnablesinputportthatfeedstheinputdatatotheserialloadshiftregisterinIO_CONFIGblockforuser-drivendynamicdelaychain.
ConfigportsCreate'config_update'inputport——EnablesinputportthatfeedsIO_CONFIGblockupdateportforuser-drivendynamicdelaychain.
Whenasserted,theserialloadshiftregisterbitsfeedtheparallelloadregister.
Table3–11.
OptionsonReset/ConfigPortsPage(Part2of2)ParameterNameLegalValueClearBoxParameterNameDescriptionFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide4.
FunctionalDescriptionThissectiondescribesthefunctionalityofthevariousblocksandportsintheALTDLLandALTDQ_DQSmegafunctions.
Thissectionalsodescribestheuseofdelaychainstoachievebettertimingmargins.
Thissectionalsoincludesanimplementationexampleshowingthesemegafunctionsinacustomexternalmemoryinterface.
CustomExternalMemoryInterfaceDatapathsOverviewThissectiondescribesthefunctionalityofthevariousblocksintheexternalmemorydatapathsthatthemegafunctionscontrol.
Figure4–1showsthemappingoftheALTDLLandALTDQ_DQSmegafunctionstothededicatedI/OelementforexternalmemoryinterfacesinStratixIVdevices.
.
1ThefollowingblocksarenotavailableinArriaIIGXdevices:DynamicOCTblocksHalf-rateblocksI/OandDQSconfigurationblocksFigure4–1.
MappingofALTDLLandALTDQ_DQSMegafunctionstotheDedicatedI/OCircuitryFPGAALTPLLPostambleClockDQSInputPathALTDLLResynchronizationClockDQInputPathDQOutputPathDQOutputEnablePathDQSOutputPathDQSOutputEnablePathALTDQ_DQSDQWriteClockDQSWriteClockAlignmentClockDLLClockExternalMemoryDQ(Read)DQ(Write)DQS(Read)DQS(Write)ALTIOBUFALTIOBUFALTIOBUFALTIOBUFDLLDelayedClockDQ/DQSOCTPathDQ/DQSOCTPathDLLChapter4:FunctionalDescription4–2CustomExternalMemoryInterfaceDatapathsOverviewFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuidefFormoreinformationabouttheblocksavailableinthedatapathsforyourtargetdevicefamily,refertothefollowingchaptersinthedevicehandbook:ExternalMemoryInterfacesinHardCopyIIIDeviceschapterinvolume1oftheHardCopyIIIDeviceHandbookExternalMemoryInterfacesinHardCopyIVDeviceschapterinvolume1oftheHardCopyIVDeviceHandbookExternalMemoryInterfacesinArriaIIGXDeviceschapterinvolume1oftheArriaIIGXDeviceHandbookExternalMemoryInterfacesinStratixIVDeviceschapterinvolume1oftheStratixIVDeviceHandbookExternalMemoryInterfacesinStratixIIIDeviceschapterinvolume1oftheStratixIIIDeviceHandbook1TheDQ/DQSreadandwritesignalsinFigure4–1maybebidirectionalorunidirectional,dependingonthememorystandard.
Whenbidirectional,thesignalisactiveduringbothreadandwriteoperations.
Table4–2liststhemegafunctionblocksinFigure4–1:Table4–1.
MegafunctionBlocksMegafunctionBlockDescriptionALTDLLTheALTDLLmegafunctioncontrolstheDLLandDLLoffsetblocks.
FormoreinformationabouttheDLLblocks,referto"ALTDLLMegafunction"onpage4–3.
ALTDQ_DQSTheALTDQ_DQSmegafunctioncontrolsthefollowingmemoryinterfacedatapaths:DQSInputPathDQInputPathDQOutput/OEPathDQSOutput/OEPathDQ/DQSOCTPathFormoreinformationaboutthedatapaths,referto"ALTDQ_DQSMegafunction"onpage4–4.
ALTPLLTheALTPLLmegafunctionblockprovidestheclockingschemeusedinthecustomexternalmemoryinterfaceforhalf-rateorfull-rateinterface.
FormoreinformationaboutusingPLLs,refertotheALTPLLMegafunctionUserGuide.
ALTIOBUFTheALTIOBUFmegafunctionprovidesI/ObuffervariationstoconnecttheALTDQ_DQSinstancetotheFPGApinsandtosupportdynamicOCTfeature.
4–3Chapter4:FunctionalDescriptionALTDLLMegafunctionALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationALTDLLMegafunctionThissectiondescribestheDLLblockandtheDLLoffsetcontrolblocksassociatedwiththeALTDLLmegafunction.
DLLblockandDLLoffsetcontrolblockTheALTDLLmegafunctioncontrolstheDLLanditstwoassociatedphase-offsetcontrolblocks.
TheALTDLLmegafunctionalsocontrolsthedelay-chainsettingstoachieveacompensateddelayforPVT.
Forexample,aDQSreadstrobe/clockthatisedge-alignedtoitsassociatedreaddatacanbeusedtoclockthedataintoI/Oregistersifthedataisdelayedbeforereachingtheregister.
TheDLLconsistsoftwophase-offsetcontrolblocks—oneforeachedgeadjacenttotheDLL,whichresidesinthecornerofthedevice.
Bothphase-offsetcontrolblockscannotfeedthesameedge.
TheDLLblockcomputesthenecessarydelaysettingsbycomparingtheperiodofaninputreferenceclocktothedelaythroughaninternaldelaychain.
YoucanthenusetheDLLoffsetcontrolblocktofine-tunethedelaysetting.
Ataminimum,theDLLhasasingleinputthatisconnectedtoadedicatedPLLoutputorinputpin,andsixgray-codedoutputsthatareconnectedtotheDQSdelaychainblock,whichispartoftheALTDQ_DQSmegafunction.
Figure4–2showsthecomponentsoftheALTDLLmegafunction.
TheDLL_OFFSET_CTRL_Ablockisthefirstphase-offsetcontrolblock,andtheDLL_OFFSET_CTRL_Bblockisthesecondphase-offsetcontrolblock.
Thesetwophase-offsetcontrolblocksareconnectedtogethertoformtheALTDLLmegafunction.
EachoffsetcontrolblockcanonlycontroltheDQSdelaychainsononeedgeofthedevice.
TofeedthesameoffsettotheDQSdelaychainsontwoedges,youmustusebothphase-offsetcontrolblocks.
Figure4–2.
ALTDLLMegafunctionDLLDLL_OFFSET_CTRL_ADLL_OFFSET_CTRL_Boffsetdelayctrlinclkaloadaloadclkoffsetdelayctrlinoffsetdelayctrlclkoutoffsetdelayctrloutdelayctrloutdqsupdateclkaloadoffsetdll_offset_ctrl_a_offset[]addnsubdll_offset_ctrl_a_addnsuboffsetctrloutoffsetctrloutoffsetdll_offset_ctrl_b_offset[]addnsubdll_offset_ctrl_b_addnsubdll_clkdll_aloaddll_offset_ctrl_a_offsetctrlout[]dll_delayctrlout[]dll_dqsupdatedll_offset_ctrl_b_offsetctrlout[]ALTDLLChapter4:FunctionalDescription4–4ALTDQ_DQSMegafunctionFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideThenamesDLL_OFFSET_CTRL_AandDLL_OFFSET_CTRL_Barelogicalanddonotdenotetheplacementoftheactualphase-offsetblocks.
Withlocationassignments,youcanassigntheseblockstothetop,bottom,orsideoftheFPGA,dependingonwhichDLLyourdesignuses.
Iflocationassignmentsarenotused,theQuartusIIFitterplacestheseblocksonthetop,bottom,orsideoftheFPGAdevice.
TheDLLandDLLoffsetblocksintheDQSphaseshiftcircuitrygeneratethecontrolsignalstoshifttheDQSdelaychaindelaystocenteraligntheDQSstrobewiththeincomingDQdataattheIOEregisters.
Thisiscommonwhenreadingfromexternalmemoryinterfaces.
FormoreinformationabouttheDLLoffsetcontrolblocksintheDQSphaseshiftcircuitry,refertotheDQSPhaseShiftCircuitrysectionintherespectivedevicehandbooks.
FormoreinformationabouttheALTDLLmegafunctionports,referto"ALTDLLMegafunctionPorts"onpage4–31.
ALTDQ_DQSMegafunctionThissectiondescribestheDQ/DQSdatapathsandtheassociatedblocksoftheALTDQ_DQSmegafunction.
Thefiguresinthesubsequentsectionsshowthemegafunctionblocksusedtoconstructthedatapathandtheirconnectionsofthetop-levelportswiththeblocksthatconfigurethepaths.
Youmustsettheappropriateparametersusingtheparametereditortoenabletheblocksandthedesiredconfigurationsinthepaths.
Table4–2listthecommonblocksthatareusedintheDQ/DQSinputandoutputpaths:1Thevaluefordependsonyourselectionintheparametereditor.
ThepossiblevaluesareBIDIR_DQandINPUT_DQ.
Table4–2.
CommonBlocksintheDQ/DQSInputandOutputPaths(Part1of2)BlockNameDescriptionDQS_DELAY_CHAINDQS_INPUT_DELAY_CHAIN(D1)DQSBUSOUT_DELAY_CHAIN(Da)DQS_ENABLE_DELAY_CHAIN(Db)_INPUT_DELAY_CHAIN(D1)_OUTPUT_DELAY_CHAIN1(D5)_OUTPUT_DELAY_CHAIN2(D6)DQS_OUTPUT_DELAY_CHAIN1(D5)DQS_OUTPUT_DELAY_CHAIN2(D6)_OE_DELAY_CHAIN1(D5)_OE_DELAY_CHAIN2(D6)DQS_OE_DELAY_CHAIN1(D5)DQS_OE_DELAY_CHAIN2(D6)_OCT_DELAY_CHAIN1(D5OCT)_OCT_DELAY_CHAIN2(D6OCT)DelayChainsRepresentsthedelaychainsusedtodelaysignals.
FormoreinformationabouttheDQSdelaychainblock,refertotheDQSDelayChainsectionoftherespectivedevicehandbooks.
Formoreinformationaboutthedelaychaintypesandsettings,referto"DelayChains"onpage4–15.
4–5Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDQS_CONFIGDQSConfigurationBlockAshiftregisterthatdynamicallychangesthesettingsofvariousdeviceconfigurationbits.
Theshiftregisterspoweruplow.
TheIO_CONFIGblockisusedtoconfigurethesettingsforallI/Opins.
TheIO_CONFIGblockcannotconfigurethedynamicdelaychainsontheOCTpathorontheDQSinputpath(D2,D3_0,D3_1,D4,D5OCT,andD6OCT)thatarecontrolledbytheDQS_CONFIGblock.
TheDQS_CONFIGblockisusedtoconfigurethesettingsoftheDQ/DQSI/Opins.
NotethattheseblocksareonlyavailableforStratixIIIandStratixIVdevices.
FormoreinformationabouttheDQS_CONFIG/IO_CONFIGblocks,referto"DQS_CONFIG/IO_CONFIGBlock"onpage4–22.
IO_CONFIGI/OConfigurationBlockIO_CLOCK_DIVIDERI/OClockDividerBlockRepresentsadivide-by-2clockdividerfortransferringdatatothecoreatonehalfthespeedoftheI/Oinputoroutputclock.
Eachdividerfeedsuptosixpins(a*4DQSgroup)inthedevice.
TofeedwiderDQSgroups,youneedtochainmultipleclockdividerstogetherbyfeedingtheslaveoutoutputofonedividertothemasterininputoftheneighboringpins'divider.
TheIO_CLOCK_DIVIDERblockisusedintheDQandDQSinputpathswhenyouenabletheUsehalf-ratecomponentsoptionintheparametereditor.
NotethatthisblockisonlyavailableforStratixIIIandStratixIVdevices.
Formoreinformationaboutthisblock,refertotheI/OElement(IOE)RegisterssectionintheExternalMemoryInterfaceschapteroftherespectivedevicehandbooks.
Table4–2.
CommonBlocksintheDQ/DQSInputandOutputPaths(Part2of2)BlockNameDescriptionChapter4:FunctionalDescription4–6ALTDQ_DQSMegafunctionFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQSInputPathThispathreceivestheDQSstrobesignalfromtheexternalmemoryduringreadoperations.
Figure4–3showstheavailableblocksintheDQSinputpath.
Figure4–3.
DQSInputPath(Note1),(2)NotestoFigure4–3:(1)Thedqs_input_data_inportmustbeconnectedtotheoutputportoftheinputbuffer.
(2)Thedll_offsetctrlin,dll_delayctrlin,anddqsupdateenportsmustbeconnectedtotheDLL.
DQS_INPUT_DELAY_CHAIN(D1)DQS_DELAY_CHAINDQSBUSOUT_DELAY_CHAIN(Da)dqs_input_data_indqs_enable_ctrl_hr_datainhidqsupdateteendll_offsetctrlincore_delayctrlindqs_enable_indll_delayctrlindqs_enable_ctrl_clkdqs_enable_ctrl_indqs_enable_ctrl_hr_datainloio_clk_divider_clkio_clk_divider_masterinDQS_ENABLE_CTRLDQS_ENABLE_CTRL_HR_DDIO_OUTIO_CLOCK_DIVIDERDQS_ENABLE_DELAY_CHAIN(Db)DQS_ENABLEdqs_bus_outio_clock_divider_clkoutio_clock_divider_slaveoutDQS_CONFIGclkoutdelayctrlinoedqs_input_data_outDQSInputPath4–7Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTheDQSinputpathconsistsofthefollowingblocks:Table4–3.
DQSInputPathBlockNameDescriptionDQS_ENABLE_CTRLDQSEnableControlBlockRepresentsthecircuitrytocontroltheDQSenableblock.
EachDQSenableblockcanbecontrolledbyaDQSenablecontrolblock.
FormoreinformationabouttheDQSenablecontrol,refertotheDQSPostambleCircuitrysectionintheExternalMemoryInterfacechapteroftherespectivedevicehandbooks.
DQS_ENABLE_CTRL_HR_DDIO_OUTDQSEnableControlHalfRateBlockRepresentsthecircuitrytotransferinputtotheDQS_ENABLE_CTRLblockfromahalf-rateclocktoafull-rateclock.
DQS_ENABLEDQSEnableBlockRepresentstheAND-gatecontrolontheDQSinputusedtogroundtheDQSinputstrobewhenthestrobegoestoZafteraDDRreadpostamble.
TheDQS_ENABLEblockenablestheregisterstoallowenoughtimefortheDQSdelaysettingstotravelfromtheDQSphase-shiftcircuitryorcorelogictoalltheDQSlogicblocksbeforethenextchange.
FormoreinformationabouttheDQSenableblock,refertotheUpdateEnableCircuitrysectionintheExternalMemoryInterfaceschapteroftherespectivedevicehandbooks.
DQS_DELAY_CHAINDQSDelayChainBlockFormoreinformationaboutthesedelaychains,refertoTable4–2onpage4–4.
DQSBUSOUT_DELAY_CHAINDQSBusoutDelayChainDQS_ENABLE_DELAY_CHAINDQSEnableDelayChainDQS_CONFIGDQSConfigurationBlocksFormoreinformationaboutDQS_CONFIGblock,refertoTable4–2onpage4–4.
IO_CLOCK_DIVIDERI/OClockDividerBlockFormoreinformationaboutI/Oclockdividerblock,refertoTable4–2onpage4–4.
Chapter4:FunctionalDescription4–8ALTDQ_DQSMegafunctionFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQInputPathThispathreceivestheDQsignalfromtheexternalmemoryduringreadoperations.
Instantiatethispathforallinput-onlyandbidirectionalDQI/Opins.
Figure4–4showstheavailableblocksintheDQinputpathandtheconnectionswiththeALTDQ_DQSports.
1Thevaluefordependsonyourselectionintheparametereditor.
ThepossiblevaluesareBIDIR_DQandINPUT_DQ.
Figure4–4.
DQInputPath(Note1),(2),(3)NotestoFigure4–4:(1)The_input_data_inportmustbeconnectedtotheoutputportoftheinputbuffer.
(2)Thedll_delayctrlinportmustbeconnectedtotheDLL.
(3)TheIO_CLOCK_DIVIDER,_HALF_RATE_INPUT,_IPA_LOW,and_IPA_HIGHblocksarehalf-ratecomponents.
_INPUT_DELAY_CHAIN(D1)_INPUT_FF_DDIO_IN_IPA_LOWand_IPA_HIGHdq_input_reg_clkdqs_busdqs_input_reg_clkena_areset_sresetDQS_CONFIG_CONFIG_HALF_RATE_INPUT_hr_input_data_outdq_ipa_clkdll_delayctrlin_sresetIO_CLOCK_DIVIDER_input_data_out_low_input_data_out_high_input_data_out_input_data_inandDQInputPath4–9Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTheDQinputpathconsistsofthefollowingblocks:Table4–4.
DQInputPathBlockNameDescription_INPUT_FFDQInputregisterblocksSamplestheDQsignalduringareadoperation.
Theseblocksareclockedbythecoreorbyaclockpin.
The_INPUT_FFblockrepresentsagroupofflip-flopsregistersintheDQinputpath.
The_DDIO_INrepresentsagroupofdoubledatarateinputregistersintheDQinputpath.
_DDIO_IN_IPA_LOWand_IPA_HIGHInputPhaseAlignment(IPA)BlockRepresentsthecircuitryrequiredtophaseshifttheinputsignal.
ThisisprimarilyusedtomatchthearrivaldelayoftheDQS(triggeredbythefly-byclockonaDDR3-DIMM)tothelatestarrivaldelayofaDQSfromtheDIMM.
TheinputphasealignmentblocklevelsoralignstheDQgroupsignalsinthecoreusingdifferentphaseshifts.
Formoreinformationaboutinputphasealignment,refertotheLevelingCircuitrysectionintheExternalMemoryInterfacechapteroftherespectivedevicehandbooks.
_HALF_RATE_INPUTHalf-rateinputregistersblockRepresentsthecircuitryrequiredtotransfertheinputsignalfromafull-rateclocktoahalf-rateclock.
NotethatthisblockisonlyavailableinStratixIIIandStratixIVdevices.
INPUT_DELAY_CHAINInputDelayChainFormoreinformationabouttheinputdelaychain,refertoTable4–2onpage4–4.
DQS_CONFIGDQSConfigurationBlockFormoreinformationabouttheDQS_CONFIGblock,refertoTable4–2onpage4–4.
IO_CONFIGI/O/ConfigurationBlockFormoreinformationabouttheIO_CONFIGblock,refertoTable4–2onpage4–4.
IO_CLOCK_DIVIDERI/OClockDividerBlockFormoreinformationaboutI/Oclockdividerblock,refertoTable4–2onpage4–4.
Chapter4:FunctionalDescription4–10ALTDQ_DQSMegafunctionFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQOutput/OEPathThispathsendstheDQsignaltotheexternalmemoryforwritingoperations.
Figure4–5showstheavailableblocksintheDQOutputandOEpathandtheconnectionswiththeALTDQ_DQSports.
1Thevaluefordependsonyourselectionintheparametereditor.
ThepossiblevaluesareBIDIR_DQandOUTPUT_DQ.
Figure4–5.
DQOutputandOEPath(Note1),(2),(3)NotestoFigure4–5:(1)The_output_data_outportmustbeconnectedtotheinputportoftheoutputbuffer.
(2)The_oe_outportmustbeconnectedtotheoutputenableportoftheoutputbuffer.
(3)The_OE_HR_DDIO_OUT,_OUTPUT_HR_DDIO_OUT_HIGHand_OUTPUT_HR_DDIO_OUT_LOWblocksarehalf-ratecomponents.
_OUTPUT_DELAY_CHAIN2(D6)IO_CONFIG_output_data_out_OUTPUT_DELAY_CHAIN1(D5)_OUTPUT_FF_OUTPUT_DDIO_OUT_OUTPUT_HR_DDIO_OUT_HIGH_hr_output_data_indq_output_reg_clk_aresetand_OUTPUT_HR_DDIO_OUT_LOW_sreset_aresetdq_output_reg_clkenadq_output_reg_clk_OE_DELAY_CHAIN2(D6)IO_CONFIG_oe_out_OE_DELAY_CHAIN1(D5)_OE_FF_OE_DDIO_OE_OE_HR_DDIO_OUT_hr_oe_indq_hr_output_reg_clk_areset_sreset_aresetdq_output_reg_clkenadq_output_reg_clk_output_data_in_output_data_in_high_output_data_in_lowandDQOUTPUTPATH_oe_inDQOEPATH4–11Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTheDQoutputandOEpathconsistofthefollowingblocks:Table4–5.
DQOutputandOEPathBlockNameDescription_OUTPUT_FFDQoutputregisterblocksSendsdatadirectlytotheexternalmemoryDQpinsduringawriteoperationthroughtheoutputbuffer.
TheseblocksareclockedbytheDQwriteclock.
The_OUTPUT_FFblockrepresentsagroupofflip-flopregistersintheDQoutputpath.
The_OUTPUT_DDIO_OUTrepresentsagroupofdoubledatarateoutputregistersintheDQoutputpath.
_OUTPUT_DDIO_OUT_OE_FFDQoutputenableregisterblocksSendsoutputenablesignaltotheoutputbuffer.
TheseblocksareclockedbytheDQwriteclock.
The_OE_FFblockrepresentsagroupofflip-flopregistersintheDQOEpath.
The_OE_DDIO_OErepresentsagroupofdoubledatarateregistersintheDQOEpath.
_OE_DDIO_OE_OUTPUT_HR_DDIO_OUT_HIGHand_OUTPUT_HR_DDIO_OUT_LOWHalf-rateoutputregisterblockRepresentstheDDIOregistersthatareusedtotransferDQsignalsfromthecoreduringhalf-ratewriteoperation.
TheseblocksareclockedbytheDQwriteclock.
_OE_HR_DDIO_OUTHalf-rateoutputenableregisterblockRepresentstheDDIOregistersthatareusedtotransferhalf-rateDQoutputenablesignalstotheoutputbuffer.
_OUTPUT_DELAY_CHAIN1(D5)DQoutputdelaychainsFormoreinformationabouttheDQoutputandOEdelaychains,refertoTable4–2onpage4–4.
_OUTPUT_DELAY_CHAIN2(D6)_OE_DELAY_CHAIN1(D5)DQOEdelaychains_OE_DELAY_CHAIN2(D6)IO_CONFIGI/OConfigurationBlockFormoreinformationabouttheIO_CONFIGblock,refertoTable4–2onpage4–4.
Chapter4:FunctionalDescription4–12ALTDQ_DQSMegafunctionFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQSOutput/OEPathThispathsendstheDQSstrobesignaltotheexternalmemoryforwritingoperations.
Figure4–6showstheavailableblocksintheDQSoutputandOEpathandtheconnectionswiththeALTDQ_DQSports.
Figure4–6.
DQSOutputandOEPath(Note1),(2),(3)NotestoFigure4–6:(1)Thedqs_output_data_outportmustbeconnectedtotheinputportoftheoutputbuffer.
(2)Thedqs_oe_outportmustbeconnectedtotheoutputenableportoftheoutputbuffer.
(3)TheDQS_OE_HR_DDIO_OUT,DQS_OUTPUT_HR_DDIO_OUT_HIGHandDQS_OUTPUT_HR_DDIO_OUT_LOWblocksarehalf-ratecomponents.
DQS_OUTPUT_DELAY_CHAIN2(D6)IO_CONFIGdqs_output_data_outDQS_OUTPUT_DELAY_CHAIN1(D5)DQS_OUTPUT_FFDQS_OUTPUT_DDIO_OUTDQS_OUTPUT_HR_DDIO_OUT_HIGHdqs_hr_output_data_indqs_output_reg_clkdqs_aresetandDQS_OUTPUT_HR_DDIO_OUT_LOWdqs_sresetdqs_aresetdqs_output_reg_clkenadqs_output_reg_clkDQS_OE_DELAY_CHAIN2(D6)IO_CONFIGdqs_oe_outDQS_OE_DELAY_CHAIN1(D5)DQS_OE_FFDQS_OE_DDIO_OEDQS_OE_HR_DDIO_OUTdqs_hr_oe_indqs_hr_output_reg_clkdqs_aresetdqs_sresetdqs_aresetdqs_output_reg_clkenadqs_output_reg_clkdqs_output_data_indqs_output_data_in_highdqs_output_data_in_lowandDQSOUTPUTPATHdqs_oe_inDQSOEPATH4–13Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTheDQSoutputandOEpathconsistofthefollowingblocks:Table4–6.
DQSOutputandOEPathBlockNameDescriptionDQS_OUTPUT_FFDQSoutputregisterblocksSendsdatadirectlytotheexternalmemoryDQspinsduringawriteoperationthroughtheoutputbuffer.
TheseblocksareclockedbytheDQSwriteclock.
TheDQS_OUTPUT_FFblockrepresentsagroupofflip-flopregistersintheDQSoutputpath.
TheDQS_OUTPUT_DDIO_OUTrepresentsagroupofdoubledatarateoutputregistersintheDQSoutputpath.
DQS_OUTPUT_DDIO_OUTDQS_OE_FFDQSoutputenableregisterblocksSendsoutputenablesignaltotheoutputbuffer.
TheseblocksareclockedbytheDQSwriteclock.
TheDQS_OE_FFblockrepresentsagroupofflip-flopregistersintheDQSOEpath.
TheDQS_OE_DDIO_OErepresentsagroupofdoubledatarateregistersintheDQSOEpath.
DQS_OE_DDIO_OEDQS_OUTPUT_HR_DDIO_OUT_HIGHandDQS_OUTPUT_HR_DDIO_OUT_LOWHalf-rateoutputregisterblockRepresentstheDDIOregistersthatareusedtotransferDQSsignalsfromthecoreduringhalf-ratewriteoperation.
TheseblocksareclockedbytheDQSwriteclock.
DQS_OE_HR_DDIO_OUTHalf-rateoutputenableregisterblockRepresentstheDDIOregistersthatareusedtotransferhalf-rateDQSoutputenablesignalstotheoutputbuffer.
DQS_OUTPUT_DELAY_CHAIN1(D5)DQSoutputdelaychainsFormoreinformationabouttheDQSoutputandOEdelaychains,refertoTable4–2onpage4–4.
DQS_OUTPUT_DELAY_CHAIN2(D6)DQS_OE_DELAY_CHAIN1(D5)DQSOEdelaychainsDQS_OE_DELAY_CHAIN2(D6)IO_CONFIGI/OConfigurationBlockFormoreinformationabouttheIO_CONFIGblock,refertoTable4–2onpage4–4.
Chapter4:FunctionalDescription4–14ALTDQ_DQSMegafunctionFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQ/DQSOCTPathFigure4–7showstheavailableblocksintheDQ/DQSOCTpathsandtheconnectionswiththeALTDQ_DQSports.
UsethispathtoutilizeOCTcapabilitiesattheDQandDQSoutputpaths.
1Thevaluedependsonyourselectionintheparametereditor.
ThepossiblevaluesareDQS,DQSn,BIDIR_DQ,andOUTPUT_DQ.
TheDQ/DQSOCTpathconsistsofthefollowingblocks:fFormoreinformationaboutusingthedynamiccalibrationblocksfortermination,refertoDynamicCalibratedOn-ChipTermination(ALTOCT)MegafunctionUserGuide.
FormoreinformationaboutimplementingcalibrateddynamicOCT,refertoAN465:ImplementingOCTCalibrationinStratixIIIDevices.
Figure4–7.
DQ/DQSOCTPath(Note)NotestoFigure4–7:(1)The_oct_outportmustbeconnectedtotheinputportoftheoutputbuffer.
(2)The_OCT_HR_DDIOblockisahalf-ratecomponent.
_OCT_DELAY_CHAIN2(D6OCT)DQS_CONFIG_oct_out_OCT_DELAY_CHAIN1(D5OCT)_OCT_FF_OCT_DDIOE_OCT_HR_DDIO_hr_oct_in[1]_hr_oct_in[0]hr_oct_reg_clkoct_reg_clk_oct_inDQ/DQSOCTPathTable4–7.
DQ/DQSOCTPathBlockNameDescription_OCT_FFOCTregisterblocksThe_OCT_FFblockrepresentsagroupofflip-flopregistersintheDQ/DQSOCToutputpath.
The_OCT_DDIOErepresentsagroupofDDIOregistersintheDQ/DQSOCToutputpath.
_OCT_DDIOE_OCT_HR_DDIOHalf-rateOCTblockRepresentsagroupofDDIOregistersrequiredtotransferthecalibratedoutputsignalinhalf-ratemode.
_OCT_DELAY_CHAIN1(D5OCT)OCTdelaychainblocksFormoreinformationabouttheOCToutputdelaychainblocks,refertoTable4–2onpage4–4_OCT_DELAY_CHAIN2(D6OCT)DQS_CONFIGDQSConfigurationBlockFormoreinformationabouttheDQS_CONFIGblock,refertoTable4–2onpage4–4.
4–15Chapter4:FunctionalDescriptionDelayChainsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDelayChainsTheALTDQ_DQSmegafunctionusesvarioustypesofdelaychains.
Youcancontroldelaychainsdynamicallytoprovideabettersamplingwindowforexternalmemoryinterfaces.
Table4–8showsthedelaychaintypeandtheirrespectivesettings.
1Eachstepvalueiseither50or400ps.
Settingthenumberofstagesinthedelaychainto10means10*50ps=500psofdelay.
1Theminimumdelayvaluefactorsinonlyvariabledelays,butnottheintrinsicdelaypresentinthedelaychain.
Formoreinformationaboutintrinsicdelays,refertotherespectiveArriaIIGX,HardCopyIII,HardCopyIV,StratixIII,andStratixIVdevicehandbookordatasheet.
Table4–8.
DelayElementsandSettingsDelayChainTypeFunctionPossibleSettingsStepValue(ps)MaximumDelayValue(ps)D1TunestheDQdelay(readcalibration)inDDRapplications.
Thereare16possiblesettingsforthisdelaychainbecausethedelaycontrolinthechainis4bitswide.
500D5andD5OCTD5istheoutputregister-to-I/Obufferdelay.
D5OCTistheOCTtoI/Obufferdelay.
ThesedelaychainsareforwritecalibrationinDDRapplications.
D5iscascadedtogetherwithD6togeneratethesumofdelays.
Thereare16possiblesettingsforthisdelaychainbecausethedelaycontrolinthechainis4bitswide.
500D6andD6OCTD6istheoutputregister-to-I/Obufferdelay.
D6OCTistheOCTtoI/Obufferdelay.
Thisdelaychainisusedtoreducesimultaneousswitchingnoise(SSN).
Thesedelaychainscanbeadjustedonagroupbasisfornon-DDR3applications.
Thisdelaychainworkswithawrite-levelingclocktoadjustthedelayamonggroupsforDDR3applications.
D6iscascadedtogetherwithD5togeneratethesumofdelays.
FormoreinformationaboutreducingSSN,referto"DeskewDelayChains"onpage4–16.
Thereare8possiblesettingsforthisdelaychainbecausethedelaycontrolinthechainis3bitswide.
500Chapter4:FunctionalDescription4–16DelayChainsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDeskewDelayChainsThedeskewdelaychainfeatureinStratixIIIorStratixIVdevicesisusefulinexternalmemoryinterfaces,suchasDDRorDDR2externalmemoryinterfaces.
RefertoFigure4–8.
ThisfeatureisusefulindeskewingtheDQbusforboardtracemismatchesbetweentheFPGAandexternalmemoryinterface.
Thegraphontheleftisobtainedwhennodeskewdelaychainsareused.
Thecapturewindowissmallbecauseoftheboardtracedelays.
ThegraphontherightisobtainedwhendeskewdelaychainsareusedtodeskewtheDQbusappropriately,basedontheboardtracedelays,tomaximizethecapturewindow.
ThedeskewdelaychainsreduceSSNbydelayingtheDQbusbysmallamountsofdelaycomparedtotheperiodofthesignalonadjacentDQpins.
RefertoFigure4–8.
Figure4–8.
DeskewDelayChains0153045607590105120135150165180dq0dq1dq2dq3dq4dq5dq6dq7IncomingDQSstrobephasePriortode-skew-smallvalidcapturewindowIncomingDQdatabusDQS0153045607590105120135150165180dq0dq1dq2dq3dq4dq5dq6dq7DQSAfterde-skew-maximizevalidcapturewindow4–17Chapter4:FunctionalDescriptionDelayChainsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTheSSNisinducedwhenadjacentpinsinaDQbusthattoggleatthesametime(especiallyatahighfrequency)inducesnoisethataffectssignalintegrity.
ToensurethattheadjacentpinsinaDQbusarenottoggledatthesametime,deskewdelaychainsareusedtoprovidesmallamountsofdelay.
RefertoFigure4–9.
YoucanaccessthesedelaychainsintheALTDQ_DQSmegafunctionfortheDQInputPath(D1)andDQOutputPath(D5andD6).
These50psstepdelaychainsprovidesmallamountsofdelay.
1YoumustcreateacustomcalibrationcircuittocontrolthesedelaychainstoreduceSSN.
Figure4–9.
ReduceSSNUsingDeskewDelayChains700ps5ns5nsChapter4:FunctionalDescription4–18ALTIOBUFMegafunctionandDelayChainsIntegrationFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideALTIOBUFMegafunctionandDelayChainsIntegrationYoumustinstantiatetheALTIOBUFmegafunctionseparatelytoconfiguretheinputbufferblock,outputbufferblock,anddifferentialoutputbufferblockthatareusedtogetherwiththeALTDQ_DQSmegafunction.
TheseI/Obuffersareusedsothattheimpedancebetweenthesystemandtheexternalcircuitrymatches.
Thisimplementationmaximizesthepowertransferandminimizesreflectionsfromtheexternalcircuitry.
cTheALTIOBUFmegafunctionmustnotbeusedtoconfigureanydynamicdelaychains.
TheALTIOBUFmustonlybeusedtoconfiguretheI/ObufferstoavoidconflictbetweenthedynamicconfigurationanddelaychaincircuitryintheALTDQ_DQSmegafunction.
ThedynamicdelaychainsarecontrolledbytheconfigurationcircuitryencapsulatedintheALTDQ_DQSmegafunction.
EachinstanceoftheI/ObufferusestheD1,D5,andD6delaychains.
ThesedelaychainsaredynamicallyconfiguredbytheIO_CONFIGandDQS_CONFIGblocks.
TheIO_CONFIGandDQS_CONFIGblocksareashiftregistersthatchangethedelaysettingsintheI/ObuffersthatareconnectedtotheI/OpinsandDQandDQSI/Opins,respectively.
TheIO_CONFIGblockcannotconfigurethedynamicdelaychainsontheOCTpathortheDQSinputpathbecausethesedelaychainsareconfiguredbytheDQS_CONFIGblock.
fFormoreinformationabouttheIO_CONFIGandDQS_CONFIGblocks,referto"DQS_CONFIG/IO_CONFIGBlock"onpage4–22.
fFormoreinformationaboutinputbuffer,outputbuffer,orbidirectionalbuffer,refertotheI/OBuffer(ALTIOBUF)MegafunctionUserGuide.
Figure4–10throughFigure4–17showthevariousconfigurationsoftheALTDQ_DQSmegafunctionwhencombinedwiththeALTIOBUFmegafunction.
TheseconfigurationsapplytoboththeDQandDQSI/Opins.
Theuseofthedatainanddatoutsignalsinthesefiguresaregeneric.
Thesesignalsrepresenteitherdata,clock,orstrobeinexternalmemoryinterfaces.
Figure4–10.
InputOnly—Single-EndedFigure4–11.
InputOnly—DifferentialALTIOBUFALTDQ_DQSdataindataoutIO_IBUFALTIOBUFdataindataoutdatain_nIO_IBUFALTDQ_DQS4–19Chapter4:FunctionalDescriptionALTIOBUFMegafunctionandDelayChainsIntegrationALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFigure4–12.
InputOnly—ComplementaryALTIOBUFdatain_pdataout_pdatain_nIO_IBUFALTDQ_DQSALTIOBUFdataout_nIO_IBUFFigure4–13.
OutputOnly—Single-EndedNotetoFigure4–13:(1)Theoeportisoptional.
Figure4–14.
OutputOnly—DifferentialNotetoFigure4–14:(1)Theoe_pandoe_nportsareoptional.
ALTIOBUFoe(1)dataoutALTDQ_DQSdatainIO_OBUFALTIOBUFoe_p(1)oe_n(1)dataoutALTDQ_DQSdataindataout_nIO_OBUFIO_OBUFPSEUDO_DIFF_OUTChapter4:FunctionalDescription4–20ALTIOBUFMegafunctionandDelayChainsIntegrationFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideFigure4–15.
OutputOnly—ComplementaryNotetoFigure4–15:(1)Theoe_pandoe_nportsareoptional.
Figure4–16.
Bidirectional—Single-EndedNotetoFigure4–16:(1)Thedyn_term_ctrlportisoptional.
ALTIOBUFoe_p(1)dataout_pdatain_nIO_IBUFALTDQ_DQSALTIOBUFdataout_nIO_IBUFdatain_poe_n(1)ALTIOBUFdyn_term_ctrl(1)dataoutdataioALTDQ_DQSoedatainIO_IBUFIO_OBUF4–21Chapter4:FunctionalDescriptionALTIOBUFMegafunctionandDelayChainsIntegrationALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFigure4–17.
Bidirectional—DifferentialNotetoFigure4–17:(1)Thedyn_term_ctrl_panddyn_term_ctrl_nportsareoptional.
Figure4–18.
Bidirectional—ComplementaryNotetoFigure4–17:(1)Thedyn_term_ctrl_panddyn_term_ctrl_nportsareoptional.
ALTIOBUFdyn_term_ctrl_p(1)dataoutdataiodataindyn_term_ctrl_n(1)oe_nIO_OBUFPSEUDO_DIFF_OUToe_pdataioIO_IBUFIO_OBUFALTDQ_DQSALTIOBUFdyn_term_ctrl_p(1)dataout_pdataio_pdatain_pIO_OBUFoe_pIO_IBUFALTDQ_DQSALTIOBUFdyn_term_ctrl_n(1)dataout_ndataio_ndatain_nIO_OBUFoe_nIO_IBUFChapter4:FunctionalDescription4–22DQS_CONFIG/IO_CONFIGBlockFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQS_CONFIG/IO_CONFIGBlockTheDQS_CONFIGandIO_CONFIGblocksdynamicallychangethesettingsofvariousconfigurationbits.
OneIO_CONFIGblockisconfiguredperI/O,whereasoneDQS_CONFIGblockisconfiguredperx4groupofI/Os(similartoIO_CLOCK_DIVIDERs).
Theseblockssharethedatain,clk,andupdatesignalseventhoughtheyhaveindividualenablesignals.
Whendynamicdelaychainsareenabled,twokeyblocksareusedtogetherwiththeI/Obufferblock(inputbuffer,outputbuffer,orbidirectionalbuffer),theI/Oconfigblockandthedelaychainblock.
TheIO_CONFIGblockcontrolstheconfigurationofthenecessarydelaysettings.
Thenecessarydelaysettingsaresetintotherespectivedelaychainblock(D1,D5,andD6).
ThesedelaysettingsdelaydatathatpassesthroughthedelaychainbeforegoingthroughtheI/Obufferblock.
TheALTDQ_DQSmegafunctionallowsyoutocontrolthedelaychainusingthefollowingI/Oconfigsignals:config_datainconfig_clkconfig_update_io_config_ena.
dependsonwhichI/Opiniscontrolled—input,output,bidirectional,DQS,orDQSnI/O.
fFormoreinformationabouttheDQSblockortheDQSnI/Oblockandthesequenceoftheshiftregisters,refertotheI/OConfigurationBlockandDQSConfigurationBlocksectioninChapter7:ExternalMemoryInterfacesinStratixIVDevicesoftheStratixIVDevicesHandbook.
fFormoreinformationabouttheseports,refertothe"DQS_CONFIG/IO_CONFIGMegafunctionPorts"onpage4–45.
ConfiguringDynamicDelayChainsUsingtheIO_CONFIGBlockTheIO_CONFIGblockseriallyshiftsthevalueofconfig_datainonlywhen_io_config_enaisasserted,duringwhichyoushiftinthevalueofconfig_dataintoashiftregister.
Becausea11-bitshiftregisterisusedintheIO_CONFIGblock,youmusthold_io_config_enaassertedfor11configurationclockcycles(config_clk).
Whentheshiftregistersarefullyloaded,theshiftregisterhasitsbitsarrangedincorrespondencewiththevaluesfordatain:datainvaluessetduringthefirstfourconfigurationclockcyclescorrespondstothe4–bitinputdelaychainvalues(D1).
datainvaluessetduringthenextthreeconfigurationclockcyclescorrespondstothe3–bitoutputdelaychainvalues(D6).
datainvaluessetduringthelastfourconfigurationclockcyclescorrespondstothe4–bitoutputdelaychainvalues(D5).
4–23Chapter4:FunctionalDescriptionDQS_CONFIG/IO_CONFIGBlockALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationInallcases,themostsignificantbit(MSB)ofthedelaychainvaluesisshiftedinfirstandtheleastsignificantbit(LSB)isshiftedinlast.
Forexample,inthefirstfourconfigurationclockcycles,thefirstconfigurationclockcyclecorrespondstotheMSBoftheinputdelaychainvalueandthefourthconfigurationclockcyclecorrespondstotheLSB.
Thedelayonlytakeseffectwhentheconfig_updatesignalisassertedforoneconfigurationclockcycle,inwhichallthebitsintheserialshiftregisterfeedsan11–bit,parallel-loadedregister.
Rightafterthesignalisdeasserted,youcanobservethedelayfromdatain(ofthedelaychainprimitive)todataout(ofthedelaychainblock).
Foralldelaychains,eachdelaysettingincrementaddsapproximately50psofdelay(theactualvaluedependsonthedevicespeedgrade);therefore,thetotaldelayvalueisequaltothenumberofstagesinthedelaychain*50ps.
Forexample,ifyousetthenumberofstagesinthedelaychaintofive,thenthetotaldelayvalueisfivetimes50ps,whichis250ps.
Figure4–19throughFigure4–23aresimulationexamplesthatshowtheresultsofvaryingthedelayattheinputdelaychain(D1).
fFormoreinformationaboutcontrollingthesedelaychainsandhowtovarytheoutputdelaychains(D5andD6),refertotheDesignExample1:DynamicallyChangingDelayChainsinOutputBufferofStratixIIIsectionoftheI/OBufferALTIOBUFMegafunctionUserGuide.
SettingtheInputDelayChain(D1)toZeroDelay(default)Figure4–19showsthattherearenotimingdifferencewiththecursorat70nswhenD1issettozerodelay.
Thecursorat70nsrepresentsthepathfromthebidirectionalbuffer(bidir_dq_input_data_in)throughtheinputdelaychain(bidir_dq_0_input_delay_chain_inst).
Youcanviewtheeffectsofthedelaychainbycomparingthedatainportandthedataoutportofthebidir_dq_0_input_delay_chain_inst.
Chapter4:FunctionalDescription4–24DQS_CONFIG/IO_CONFIGBlockFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideFigure4–19showsthesimulationresultsforD1withzerodelay.
Figure4–19.
SimulationResults—D1isSettoZeroDelay(Default)4–25Chapter4:FunctionalDescriptionDQS_CONFIG/IO_CONFIGBlockALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationSettingtheInputDelayChainto50psDelayInFigure4–20,cursor3(255ns)tocursor4(1355ns)showthatthedelaychainisconfiguredto50ps.
Theconfig_clocktakes11(1,100ns)clockcyclestoloadtheintendeddelayvaluesintotheIO_CONFIGblockbecauseofthefirstfourclockcycles(fortheinputdelaychain,D1),thenextthreeclockcycles(fortheoutputdelaychain2,D6)andthelast4clockcycles(fortheoutputdelaychain1,D5).
Thefollowingstepsdescribehowtheinputdelaychainchanges:1.
Becausethereisa11-bitshiftregisterintheIO_CONFIGblock,bidir_core_dq_confiq_enable(0)isassertedfor11clockcycles.
Whentheshiftregistersarefullyloaded,theshiftregistershavetheirbitsarrangestocorrespondwithdatainvalues.
2.
Theconfig_datainsignalisassertedatthe4thclockcycletochangetheinputdelaychainvalue.
3.
Thedelayonlytakeseffectwhentheconfig_updatesignalisassertedforoneclockcycleat1455,000ps(Cursor5).
4.
Aftertheconfig_updatesignalisdeasserted,thedelayfrombidir_dq_0_input_delay_chain_inst/datainat1630,000ps(Cursor7)tobidir_dq_0_input_delay_chain_inst/dataoutat1630,050ps(Cursor8)isnoticeable,whichis50ps.
RefertoFigure4–21.
Chapter4:FunctionalDescription4–26DQS_CONFIG/IO_CONFIGBlockFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideFigure4–20showsthefirstpartofthesimulationwhenyousettheinputdelaychainto50psdelay.
Figure4–20.
FirstPartoftheSimulationResults—D1issetto50psDelay4–27Chapter4:FunctionalDescriptionDQS_CONFIG/IO_CONFIGBlockALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFigure4–21showsthesecondpartofthesimulationresultswhentheeffectsofthe50psdelayhasbeenpropagated.
Figure4–21.
SecondPartoftheSimulationResults—D1isSetto50psChapter4:FunctionalDescription4–28DQS_CONFIG/IO_CONFIGBlockFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideSettingtheInputDelayChainto750psDelayCursor9(1,755ns)tocursor10(2,855ns)inFigure4–22showthattheinputdelaychainisconfiguredto750ps.
Theconfig_clocktakes11(1,100ns)clockcyclestoloadtheintendeddelayvaluesintotheIO_CONFIGblockbecauseofthefirstfourclockcycles(fortheinputdelaychain,D1),thenextthreeclockcycles(fortheoutputdelaychain2,D6)andthelastfourclockcycles(fortheoutputdelaychain1,D5).
Thefollowingstepsdescribehowtheinputdelaychainchanges:1.
Becausethereisa11-bitshiftregisterintheIO_CONFIGblock,bidir_core_dq_confiq_enable(0)isassertedfor11clockcycles.
Whentheshiftregistersarefullyloaded,theshiftregistershavetheirbitsarrangestocorrespondwithdatainvalues.
2.
Theconfig_datainsignalisassertedatthenext4clockcyclestochangetheinputdelaychainvalue.
3.
Thedelayonlytakeseffectwhentheconfig_updatesignalisassertedforoneclockcycleat2955,000ps(Cursor11).
4.
Aftertheconfig_updatesignalisdeasserted,thedelayfrombidir_dq_0_input_delay_chain_inst/datainat3230,000ps(Cursor13)tobidir_dq_0_input_delay_chain_inst/dataoutat3230,750ps(Cursor14)isnoticeable,whichis750ps.
RefertoFigure4–23.
4–29Chapter4:FunctionalDescriptionDQS_CONFIG/IO_CONFIGBlockALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFigure4–21showsthethirdpartofthesimulationresultswhenyousettheinputdelaychainto750psdelay.
Figure4–22.
ThirdPartoftheSimulationResults—InputDelayChainissetto750psDelayChapter4:FunctionalDescription4–30DQS_CONFIG/IO_CONFIGBlockFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideFigure4–23showsthefourthpartofthesimulationresultswhentheeffectsofthe750psdelayhasbeenpropagated.
Figure4–23.
FourthPartoftheSimulationResults—D1isSetto750psDelay4–31Chapter4:FunctionalDescriptionALTDLLMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationALTDLLMegafunctionPortsThissectiondescribestheportsoftheALTDLLmegafunction.
Table4–9liststheinputportsfortheALTDLLmegafunction.
Table4–9.
ALTDLLMegafunctionInputPortsPortNameOptional/RequiredDefaultDescriptiondll_aloadOptionalGNDAsynchronousloadsignalfortheDLLcounter.
Whendll_aloadisHIGH,thecounterisasynchronouslyloadedwiththeinitialdelaysettingof16inlow-frequencymode(whentheparameterDELAY_BUFFER_MODEissettoLOW),or32inhigh-frequencymode(whentheparameterDELAY_BUFFER_MODEissettoHIGH).
dll_clkRequiredGNDDLLreferenceclockthatmatchesthefrequencyoftheDQSclockusedtodeterminethedelayforthephaseshift.
FeedthisinputbyaninputpinoraPLLoutput.
Thisinputmustmatchthepolarityofitssourceandcannotbeinverted.
dll_offset_ctrl_a_addnsubOptionalVCCAddition/subtractioncontrolportforDLL_OFFSET_CTRL_Ablock.
Thisportcontrolswhetherthedelay-offsetsettingAisaddedorsubtracted.
IgnorethisinputiftheDLL_OFFSET_CTRL_A_USE_OFFSETparameterissettoFALSE.
IftheinputisVCC,theoffsetisadded;ifitisGND,theoffsetissubtracted.
dll_offset_ctrl_a_offset[5.
.
0]Optional0ThisistheoffsetinputsettingforDLL_OFFSET_CTRL_Ablock.
ThisisaGray-codedoffsetaddedorsubtractedfromthecurrentvalueoftheDLL'sdelaysettingtogetthedll_offset_ctrl_a_offsetctrloutresult.
IgnorethisinputiftheDLL_OFFSET_CTRL_A_USE_OFFSETparameterissettoFALSE.
Theoffsetislimitedtoaminimumvalueof0andamaximumvalueof63inlow-frequencymode,andamaximumvalueof31inhigh-frequencymode.
dll_offset_ctrl_b_addnsubOptionalVCCThisistheaddition/subtractioncontrolportforDLL_OFFSET_CTRL_Bblock.
Thisportcontrolswhetherthedelay-offsetsettingBisaddedorsubtracted.
IgnorethisinputiftheDLL_OFFSET_CTRL_B_USE_OFFSETparameterissettoFALSE.
IftheinputisVCC,theoffsetisadded;ifitisGND,theoffsetissubtracted.
ThisinputdefaultstoVCC.
dll_offset_ctrl_b_offset[5.
.
0]Optional0ThisistheoffsetinputsettingforDLL_OFFSET_CTRL_Bblock.
ThisisaGray-codedoffsetaddedorsubtractedfromthecurrentvalueoftheDLL'sdelaysettingtogetthedll_offset_ctrl_b_offsetctrloutresult.
IgnorethisinputiftheDLL_OFFSET_CTRL_B_USE_OFFSETparameterissettoFALSE.
Theoffsetislimitedtoaminimumvalueof0andamaximumvalueof63inlow-frequencymode,andamaximumvalueof31inhigh-frequencymode.
Chapter4:FunctionalDescription4–32ALTDLLMegafunctionPortsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTable4–10liststheoutputportsoftheALTDLLmegafunction.
Table4–10.
ALTDLLMegafunctionOutputPortsPortNameOptional/RequiredDefaultFunctiondll_delayctrlout[5.
.
0]Required—ThisistheDLL'sdelaysettingoutput.
Thisisa1-cycle-delayedvalueofthecurrentdelaychainsettingoftheDLL.
ThissignalisGray-codedtominimizejitterduetotoggling.
Thissignalcanfeedthedll_delayctrlininputportoftheALTDQ_DQSmegafunctionorthecorelogic.
ThisoutputisavailableforSignalTapIIEmbeddedLogicAnalyzer.
dll_dqsupdateOptional—Thisisanupdate-enablesignalforthedelay-settinglatchesoftheDQSpins.
ThissignalcanfeedthedqsupdateeninputportoftheALTDQ_DQSmegafunction.
ThisoutputisnotavailableforSignalTapIIEmbeddedLogicAnalyzer.
dll_offset_ctrl_a_offsetctrlout[5.
.
0]Optional—ThisistheoffsetctrloutoutputsettingforDLL_OFFSET_CTRL_Ablock.
ThisisaregisteredGray-codedvalueofthedelay-offsetsettingA.
Thisoutputcanbeadjustedbasedonthevalueofthedll_offset_ctrl_a_use_offsetparameter.
ThissignalcanfeedtheoffsetctrlininputportoftheALTDQ_DQSmegafunction.
ThissignalisnotavailableforSignalTapIIEmbeddedLogicAnalyzer.
dll_offset_ctrl_b_offsetctrlout[5.
.
0]Optional—ThisistheoffsetctrloutoutputsettingforDLL_OFFSET_CTRL_Bblock.
ThisisaregisteredGray-codedvalueofthedelay-offsetsettingB.
Thisoutputcanbeadjustedbasedonthevalueofthedll_offset_ctrl_b_use_offsetparameter.
ThissignalcanfeedtheoffsetctrlininputportoftheALTDQ_DQSmegafunction.
ThissignalisnotavailableforSignalTapIIEmbeddedLogicAnalyzer.
4–33Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationALTDQ_DQSMegafunctionPortsTable4–11toTable4–19describestheportsoftheALTDQ_DQSmegafunctionthatyoucanusetoconfiguretheDQSinputpath,DQSoutputpath,DQSOEpath,DQ/DQSOCTpath,DQinputpath,DQoutputpath,DQOEpath,DQSNIOpath,andDQS_CONFIG/IO_CONFIGpath.
DQSInputPathMegafunctionPortsTable4–11summarizesalltheportsonthemegafunctiontoconfiguretheDQSinputpath.
nb=numberofbidirectionalDQno=numberofoutputDQni=numberofinputDQnc=numberofclockdividerTable4–11.
MegafunctionPortstoConfigureDQSInputPath(Part1of2)PortNameTypeOptional/RequiredDefaultDescriptioncore_delayctrlin[5.
.
0]InputOptionalGNDThisportreceivestheGray-codeddelaychainsettingfortheDQSreadpathfromtheFPGAcore.
Thisportdoesnotneedtomatchthepolarityofitssourceandcanbeinverted.
dll_delayctrlin[5.
.
0]InputOptionalGNDThisportreceivestheGray-codeddelaychainsettingfortheDQSreadpathfromtheALTDLL:delayctrlout[5.
.
0]port.
Thisportmustmatchthepolarityofitssourceandcannotbeinverted.
dqs_bus_outOutputOptional—ThisportreceivesthepossiblydelayedDQSoutputsignalfromtheDQS_ENABLE:dqsbusout,DQSBUSOUT_DELAY_CHAIN:dataout,orDQS_DELAY_CHAIN:dqsbusoutport.
dqs_enable_ctrl_clkInputOptionalVCCThisportisconnectedtotheDQS_ENABLE_CTRL:clkportthatisusedtocapturetheDQS_ENABLE_CTRL:dqsenableinsignal.
dqs_enable_ctrl_hr_datainhiInputOptionalGNDThisportisconnectedtotheDQS_ENABLE_CTRL_HR_DDIO_OUT:datainhiport.
Thisportreceivesthehalf-ratedatafortherisingedgeoftheIO_CLOCK_DIVIDER:clkoutsignal.
dqs_enable_ctrl_hr_datainloInputOptionalGNDThisportisconnectedtotheDQS_ENABLE_CTRL_HR_DDIO_OUT:datainloport.
Thisportreceivesthehalf-ratedataforthefallingedgeoftheIO_CLOCK_DIVIDER:clkoutsignal.
dqs_enable_ctrl_inInputOptionalVCCThisactive-highportisconnectedtotheDQS_ENABLE_CTRL:dqsenableinportthatisusedtoenableordisabletheDQS_ENABLE_CTRL:dqsenableoutport.
Chapter4:FunctionalDescription4–34ALTDQ_DQSMegafunctionPortsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuidedqs_enable_inInputOptionalVCCThisactive-highportisconnectedtotheDQS_ENABLE:dqsenablethatisusedtoenableordisabletheDQS_ENABLE:dqsbusoutport.
Whenthedqs_enable_inportisconnectedtoGND,theDQS_ENABLE:dqsbusoutsignalisGNDonthenextfallingedgeoftheDQS_ENABLE:dqsinsignal.
TheDQS_ENABLE:dqsbusoutisconnecteddirectlytothedqs_bus_outport.
dqs_input_data_inInputOptionalGNDThisportreceivestheincomingDQSsignalfortheDQSinputpathdqs_input_data_outOutputOptional—ThisportreceivestheoutgoingDQSsignalfromtheDQS_INPUT_DELAY_CHAIN:busoutport,ordirectlyfromthedqs_input_data_inportdqsupdateenInputOptionalGNDThisactive-highportisconnectedtotheDQS_DELAY_CHAIN:dqsupdateenportthatisusedtolatchtheDQS_DELAY_CHAIN:delayctrlin[5.
.
0]andDQS_DELAY_CHAIN:offsetctrlin[5.
.
0]signals.
ThedqsupdateenportisfedbytheALTDLL:dll_dqsupdateport,orthecore.
Io_clock_divider_clkInputOptionalGNDThisportisconnectedtotheIO_CLOCK_DIVIDER:clkportthatistheclockinputportforthatblock.
Io_clock_divider_clkout[nc-1.
.
0]OutputOptional—ThisportisconnectedtotheIO_CLOCK_DIVIDER:clkoutportthatisusedtooutputclocksignalthatishalfthefrequencyoftheIO_CLOCK_DIVIDER:clksignal.
Io_clock_divider_masterinInputOptionalGNDThisportisconnectedtotheIO_CLOCK_DIVIDER:masterinportthatisusedwhenyouneedtochainmultipleclockdividerstogethertofeedwiderDQSgroups.
Io_clock_divider_slaveoutOutputOptional—ThisportisconnectedtotheIO_CLOCK_DIVIDER:slaveoutportthatisusedwhenyouneedtochainmultipleclockdividerstogethertofeedwiderDQSgroups.
Thisportmustnothavemorethanonefan-outandmustonlybeconnectedtotheio_clock_divider_masterinportofanotherALTDQ_DQSmegafunction.
offsetctrlin[5.
.
0]InputOptionalGNDThisportreceivestheGray-codedfine-tunedelaychainsettingfortheDQSoutputpathfromtheALTDLL:dll_offset_ctrl_a_offsetctrlout[5.
.
0]portorALTDLL:dll_offset_ctrl_b_offsetctrlout[5.
.
0].
Thisportmustmatchthepolarityofitssourceandcannotbeinverted.
Table4–11.
MegafunctionPortstoConfigureDQSInputPath(Part2of2)PortNameTypeOptional/RequiredDefaultDescription4–35Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDQSOutputPathMegafunctionPortsTable4–12summarizesalltheportsonthemegafunctionthatconfiguretheDQSoutputpath.
Table4–12.
MegafunctionPortstoConfigureDQSOutputPathPortNameTypeOptional/RequiredDefaultDescriptiondqs_aresetInputOptionalGNDThisportisconnectedtotheDQS_OUTPUT_FF:clrn,DQS_OUTPUT_DDIO_OUT:areset,andDQS_OUTPUT_HR_DDIO_OUT_HIGH/_LOW:aresetportsthatisusedtoasynchronouslyresetallregistersinthoseblocks.
dqs_hr_output_data_in[3.
.
0]InputOptionalGNDThisportfeedsthehalf-ratedatatotheDQS_OUTPUT_HR_DDIO_OUT_HIGH:datainhi/datainloandDQS_OUTPUT_HR_DDIO_OUT_LOW:datainhi/datainloports.
dqs_hr_output_reg_clkInputOptionalGNDThisportfeedstheclocksignalfortheDQS_OUTPUT_HR_DDIO_OUT_HIGH:clkh/clklo/muxselandDQS_OUTPUT_HR_DDIO_OUT_LOW:clkhi/clklo/muxselports.
dqs_output_data_inInputOptionalGNDThisportfeedstheDQS_OUTPUT_FF:d,DQS_OUTPUT_DELAY_CHAIN1:datain,DQS_OUTPUT_DELAY_CHAIN2:datain,ordqs_output_data_outport.
dqs_output_data_in_highInputOptionalGNDThisportfeedstheDQS_OUTPUT_DDIO_OUT:datainhiportthatisthefull-ratedatafortherisingedge.
dqs_output_data_in_lowInputOptionalGNDThisportfeedstheDQS_OUTPUT_DDIO_OUT:datainloportthatisthefull-ratedataforthefallingedge.
dqs_output_data_outOutputOptional—ThisportcanbedrivenbytheDQS_OUTPUT_DELAY_CHAIN2:dataout,DQS_OUTPUT_DELAY_CHAIN1:dataout,DQS_OUTPUT_FF:q,DQS_OUTPUT_DDIO_OUT:dataout,ordqs_output_data_inport.
dqs_output_reg_clkInputOptionalGNDThisportisconnectedtotheDQS_OUTPUT_FF:clkandtheDQS_OUTPUT_DDIO_OUT:clkhi/clklo/muxselportsthatisusedtoclocktheregistersinthoseblocks.
dqs_output_reg_clkenaInputOptionalVCCThisportisconnectedtotheDQS_OUTPUT_FF:enaandtheDQS_OUTPUT_DDIO_OUT:enaportsthatisusedasoutputenablefortheregistersinthoseblock.
dqs_sresetInputOptionalGNDThisportisconnectedtotheDQS_OUTPUT_FF:sclrandDQS_OUTPUT_DDIO_OUT:sresetportsthatisusedtosynchronouslyresetallregistersinthoseblocks.
Chapter4:FunctionalDescription4–36ALTDQ_DQSMegafunctionPortsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQSOEPathMegafunctionPortsTable4–13summarizesalltheportsonthemegafunctionthatconfiguretheDQSOEpath.
Table4–13.
MegafunctionPortstoConfigureDQSOEPathPortNameTypeOptional/RequiredDefaultDescriptiondqs_aresetInputOptionalGNDThisportisconnectedtotheDQS_OE_FF:clrn,DQS_OE_DDIO_OE:areset,andDQS_OE_HR_DDIO_OUT:aresetportsthatisusedtoasynchronouslyresetallregistersinthoseblocks.
dqs_hr_oe_in[1.
.
0]InputOptionalGNDThis2-bitportisconnectedtotheDQS_OE_HR_DDIO_OUT:datainhi/datainloportthatisusedastheoutputenableforthehalf-rateregistersinthatblock.
dqs_hr_output_reg_clkInputOptionalGNDThisportisconnectedtotheDQS_OE_HR_DDIO_OUT:clkhi/clklo/muxselportsthatisusedtoclockthehalf-rateregistersinthoseblocks.
dqs_oe_inInputOptionalGNDThisportfeedstheDQS_OE_FF:d,DQS_OE_DDIO_OE:oe,DQS_OE_DELAY_CHAIN1:datain,DQS_OE_DELAY_CHAIN2:datain,ordqs_oe_outport.
Forinformationabouthowtoenabletheseblocks,referto"ParameterSettings"onpage3–1.
dqs_oe_outOutputOptional—ThisportreceivestheoutputsignalfromtheDQS_OE_DELAY_CHAIN2:dataout,DQS_OE_DELAY_CHAIN1:dataout,DQS_OE_FF:q,DQS_OE_DDIO_OE:dataout,ordqs_oe_inport.
Forinformationabouthowtoenabletheseblocks,referto"ParameterSettings"onpage3–1.
dqs_output_reg_clkInputOptionalGNDThisportisconnectedtotheDQS_OE_FF:clkandtheDQS_OE_DDIO_OE:clkportsthatisusedtoclocktheregistersinthoseblocks.
dqs_output_reg_clkenaInputOptionalVCCThisportisconnectedtotheDQS_OE_FF:enaandtheDQS_OE_DDIO_OE:enaportsthatisusedasoutputenablefortheregistersinthoseblock.
dqs_sresetInputOptionalGNDThisportisconnectedtotheDQS_OE_FF:sclrandDQS_OE_DDIO_OE:sresetportsthatisusedtosynchronouslyresetallregistersinthoseblocks.
4–37Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDQ/DQSOCTPathMegafunctionPortsTable4–14summarizesalltheportsonthemegafunctionthatconfiguretheOCTpath.
ThepossiblevaluesforareDQS,DQSn,BIDIR_DQ,andOUTPUT_DQ.
Table4–14.
MegafunctionPortstoConfigureOCTPath(Part1of2)PortNameTypeOptional/RequiredDefaultDescriptionbidir_dq_hr_oct_in[2*nb-1.
.
0]InputOptionalGNDThisportfeedsthehalf-ratebidirectionalDQsignalfortheBIDIR_DQ_OCT_HR_DDIO_OUT:datainhi/datainloports.
bidir_dq_oct_in[nb-1.
.
0]InputOptionalGNDThisportfeedsthefull-ratebidirectionalDQsignalfortheBIDIR_DQ_OCT_FF:d,BIDIR_DQ_OCT_DDIO_OE:oe,BIDIR_DQ_OCT_DELAY_CHAIN1:datain,BIDIR_DQ_OCT_DELAY_CHAIN2:datain,orbidir_dq_oct_outport.
bidir_dq_oct_out[nb-1.
.
0]OutputOptional—ThisportoutputssignalfromtheBIDIR_DQ_OCT_DELAY_CHAIN2:dataout,BIDIR_DQ_OCT_DELAY_CHAIN1:dataout,BIDIR_DQ_OCT_FF:q,BIDIR_DQ_OCT_DDIO_OE:dataout,orbidir_dq_oct_inport.
dqs_hr_oct_in[1.
.
0]InputOptionalGNDThisportfeedsthehalf-rateDQSsignalfortheDQS_OCT_HR_DDIO_OUT:datainhi/datainloports.
dqs_oct_inInputOptionalGNDThisportfeedsthefull-rateDQSsignalfortheDQS_OCT_FF:d,DQS_OCT_DDIO_OE:oe,DQS_OCT_DELAY_CHAIN1:datain,DQS_OCT_DELAY_CHAIN2:datain,ordqs_oct_outport.
dqs_oct_outOutputOptional—ThisportoutputssignalfromtheDQS_OCT_DELAY_CHAIN2:dataout,DQS_OCT_DELAY_CHAIN1:dataout,DQS_OCT_FF:q,DQS_OCT_DDIO_OE:dataout,ordqs_oct_inport.
dqsn_hr_oct_in[1.
.
0]InputOptionalGNDThisportfeedsthehalf-rateDQSnsignalfortheDQSN_OCT_HR_DDIO_OUT:datainhi/datainloports.
dqsn_oct_inInputOptionalGNDThisportfeedsthefull-rateDQSnsignalfortheDQSN_OCT_FF:d,DQSN_OCT_DDIO_OE:oe,DQSN_OCT_DELAY_CHAIN1:datain,DQSN_OCT_DELAY_CHAIN2:datain,ordqsn_oct_outport.
dqsn_oct_outOutputOptional—ThisportoutputssignalfromtheDQSN_OCT_DELAY_CHAIN2:dataout,DQSN_OCT_DELAY_CHAIN1:dataout,DQSN_OCT_FF:q,DQSN_OCT_DDIO_OE:dataout,ordqsn_oct_inport.
hr_oct_reg_clkInputOptionalGNDThisportfeedsthehalf-rateclocksignalforthe_OCT_HR_DDIO_OUT:clkhi/clklo/muxsel.
Chapter4:FunctionalDescription4–38ALTDQ_DQSMegafunctionPortsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQInputPathMegafunctionPortsTable4–15summarizesalltheportsonthemegafunctionthatconfiguretheDQinputpath.
ThepossiblevaluesforareBIDIR_DQandINPUT_DQ.
oct_reg_clkInputOptionalGNDThisportfeedsthefull-rateclocksignaltothe_OCT_FF:clkand_OCT_DDIO_OE:clkports.
output_dq_hr_oct_in[2*no-1.
.
0]InputOptionalGNDThisportfeedsthehalf-rateoutputDQsignalfortheOUTPUT_DQ_OCT_HR_DDIO_OUT:datainhi/datainloports.
output_dq_oct_in[no-1.
.
0]InputOptionalGNDThisportfeedsthefull-rateoutputDQsignalfortheOUTPUT_DQ_OCT_FF:d,OUTPUT_DQ_OCT_DDIO_OE:oe,OUTPUT_DQ_OCT_DELAY_CHAIN1:datain,OUTPUT_DQ_OCT_DELAY_CHAIN2:datain,oroutput_dq_oct_outport.
output_dq_oct_out[no-1.
.
0]OutputOptional—ThisportoutputssignalfromtheOUTPUT_DQ_OCT_DELAY_CHAIN2:dataout,OUTPUT_DQ_OCT_DELAY_CHAIN1:dataout,OUTPUT_DQ_OCT_FF:q,OUTPUT_DQ_OCT_DDIO_OE:dataout,oroutput_dq_oct_inport.
Table4–14.
MegafunctionPortstoConfigureOCTPath(Part2of2)PortNameTypeOptional/RequiredDefaultDescriptionTable4–15.
MegafunctionPortstoConfigureDQInputPath(Part1of2)PortNameTypeOptional/RequiredDefaultDescriptionbidir_dq_areset[nb-1.
.
0]InputOptionalGNDThisportisconnectedtoallaresetportinthebidirectionalDQIOprimitivesthatisusedtoasynchronouslyresettheregistersinthoseprimitives.
bidir_dq_hr_input_data_out[4*nb-1.
.
0]OutputOptional—Thisportoutputsthehalf-rateDDRbidirectionalDQsignalfromtheBIDIR_DQ_HALF_RATE_INPUT:dataoutport.
bidir_dq_input_data_in[nb-1.
.
0]InputOptionalGNDThisportfeedsthebidirectionalDQsignalfortheBIDIR_DQ_INPUT_DELAY_CHAIN:datain,BIDIR_DQ_INPUT_FF:d,BIDIR_DQ_DDIO_IN:datain,orbidir_dq_input_data_outport.
bidir_dq_input_data_out_high[nb-1.
.
0]OutputOptional—Thisportoutputsthefull-rateDDRbidirectionalDQsignal(risingedge)fromtheBIDIR_DQ_IPA_HIGH:dataoutorBIDIR_DQ_DDIO_IN:regouthi.
bidir_dq_input_data_out_low[nb-1.
.
0]OutputOptional—Thisportoutputsthefull-rateDDRbidirectionalDQsignal(fallingedge)fromtheBIDIR_DQ_IPA_LOW:dataoutorBIDIR_DQ_DDIO_IN:regoutlo.
4–39Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationbidir_dq_input_data_out[nb-1.
.
0]OutputOptional—ThisportoutputsthebidirectionalDQsignalfromtheBIDIR_DQ_INPUT_DELAY_CHAIN:dataout,BIDIR_DQ_INPUT_FF:q,orbidir_dq_input_data_inport.
bidir_dq_sresetnb-1.
.
0]InputOptionalGNDThisportisconnectedtoallsresetportinthebidirectionalDQIOprimitivesthatisusedtosynchronouslyresettheregistersinthoseprimitives.
dll_delayctrlin5.
.
0]InputOptionalGNDThisportreceivestheGray-codeddelaychainsettingfortheDQreadpathfromthedelayctrlout[5.
.
0]portoftheALTDLL.
dq_input_reg_clkInputOptionalGNDThisportfeedstheclocksignalforthe_INPUT_FF:clkand_DDIO_IN:clkports.
dq_input_reg_clkenaInputOptionalVCCThisportfeedstheoutputenablesignalforthe_INPUT_FF:enaand_DDIO_IN:enaports.
dq_ipa_clkInputOptionalGNDThisportfeedstheclocksignalforthe_IPA_HIGH:clkand_IPA_LOW:clkports.
input_dq_areset[ni-1.
.
0]InputOptionalGNDThisportisconnectedtoallaresetportintheinputDQIOprimitivesthatisusedtoasynchronouslyresettheregistersinthoseprimitives.
input_dq_hr_input_data_out[4*ni-1.
.
0]OutputOptional—Thisportoutputsthehalf-rateDDRinputDQsignalfromtheINPUT_DQ_HALF_RATE_INPUT:dataoutport.
input_dq_input_data_in[ni-1.
.
0]InputOptionalGNDThisportfeedstheinputDQsignalfortheINPUT_DQ_INPUT_DELAY_CHAIN:datain,INPUT_DQ_INPUT_FF:d,INPUT_DQ_DDIO_IN:datain,orinput_dq_input_data_outport.
input_dq_input_data_out_high[ni-1.
.
0]OutputOptional—Thisportoutputsthefull-rateDDRinputDQsignal(risingedge)fromtheINPUT_DQ_IPA_HIGH:dataoutorINPUT_DQ_DDIO_IN:regouthi.
input_dq_input_data_out_low[ni-1.
.
0]OutputOptional—Thisportoutputsthefull-rateDDRinputDQsignal(fallingedge)fromtheINPUT_DQ_IPA_LOW:dataoutorINPUT_DQ_DDIO_IN:regoutlo.
input_dq_input_data_out[ni-1.
.
0]OutputOptional—ThisportoutputstheinputDQsignalfromtheINPUT_DQ_INPUT_DELAY_CHAIN:dataout,INPUT_DQ_INPUT_FF:q,orinput_dq_input_data_inport.
input_dq_sreset[ni-1.
.
0]InputOptionalGNDThisportisconnectedtoallsresetportsintheinputDQIOprimitivesthatisusedtosynchronouslyresettheregistersinthoseprimitives.
Table4–15.
MegafunctionPortstoConfigureDQInputPath(Part2of2)PortNameTypeOptional/RequiredDefaultDescriptionChapter4:FunctionalDescription4–40ALTDQ_DQSMegafunctionPortsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQOutputPathMegafunctionPortsTable4–16summarizesalltheportsonthemegafunctionthatconfiguretheDQOutputpath.
ThepossiblevaluesforareBIDIR_DQandOUTPUT_DQ.
Table4–16.
MegafunctionPortstoConfigureDQOutputPath(Part1of2)PortNameTypeOptional/RequiredDefaultDescriptionbidir_dq_areset[nb-1.
.
0]InputOptionalGNDThisportisconnectedtoallaresetportsinthebidirectionalDQIOprimitivesthatisusedtoasynchronouslyresettheregistersinthoseprimitives.
bidir_dq_hr_output_data_in[4*nb-1.
.
0]InputOptionalGNDThisportfeedsthehalf-rateDDRbidirectionalDQsignalfortheBIDIR_DQ_OUTPUT_HR_DDIO_OUT_HIGH:datainhi/datainloandBIDIR_DQ_OUTPUT_HR_DDIO_OUT_LOW:datainhi/datainloports.
bidir_dq_output_data_in[nb-1.
.
0]InputOptionalGNDThisportfeedsthebidirectionalDQsignalfortheBIDIR_DQ_OUTPUT_FF:d,BIDIR_DQ_OUTPUT_DELAY_CHAIN1:datain,BIDIR_DQ_OUTPUT_DELAY_CHAIN2:datain,orbidir_dq_output_data_outportbidir_dq_output_data_in_high[nb-1.
.
0]InputOptionalGNDThisportfeedsthefull-rateDDRbidirectionalDQsignal(risingedge)fortheBIDIR_DQ_OUTPUT_DDIO_OUT:datainhiport.
bidir_dq_output_data_in_low[nb-1.
.
0]InputOptionalGNDThisportfeedsthefull-rateDDRbidirectionalDQsignal(fallingedge)fortheBIDIR_DQ_OUTPUT_DDIO_OUT:datainloport.
bidir_dq_output_data_out[nb-1.
.
0]OutputOptional—ThisportoutputsthebidirectionalDQsignalfromtheBIDIR_DQ_OUTPUT_DELAY_CHAIN2:dataout,BIDIR_DQ_OUTPUT_DELAY_CHAIN1:dataout,BIDIR_DQ_OUTPUT_FF:q,BIDIR_DQ_OUTPUT_DDIO_OUT:dataout,orbidir_dq_output_data_inport.
bidir_dq_sreset[nb-1.
.
0]InputOptionalGNDThisportisconnectedtoallsresetportinthebidirectionalDQIOprimitivesthatisusedtosynchronouslyresettheregistersinthoseprimitives.
dq_hr_output_reg_clkInputOptionalGNDThisportfeedstheoutputenablesignalforthe_OUTPUT_FF:enaand_OUTPUT_DDIO_OUT:enaports.
dq_output_reg_clkInputOptionalGNDThisportfeedstheclocksignalforthe_OUTPUT_FF:clkand_OUTPUT_DDIO_OUT:clkhi/clklo/muxselports.
4–41Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationdq_output_reg_clkenaInputOptionalVCCThisportfeedstheoutputenablesignalforthe_OUTPUT_FF:enaand_OUTPUT_DDIO_OUT:enaports.
output_dq_areset[no-1.
.
0]InputOptionalGNDThisportisconnectedtoallaresetportintheoutputDQIOprimitivesthatisusedtoasynchronouslyresettheregistersinthoseprimitives.
output_dq_hr_output_data_in[4*no-1.
.
0]InputOptionalGNDThisportfeedsthehalf-rateDDRoutputDQsignalfortheOUTPUT_DQ_OUTPUT_HR_DDIO_OUT_HIGH:datainhi/datainloandOUTPUT_DQ_OUTPUT_HR_DDIO_OUT_LOW:datainhi/datainloports.
output_dq_output_data_in_high[no-1.
.
0]InputOptionalGNDThisportfeedsthefull-rateDDRoutputDQsignal(risingedge)fortheOUTPUT_DQ_OUTPUT_DDIO_OUT:datainhiport.
output_dq_output_data_in_low[no-1.
.
0]InputOptionalGNDThisportfeedsthefull-rateDDRoutputDQsignal(fallingedge)fortheOUTPUT_DQ_OUTPUT_DDIO_OUT:datainloport.
output_dq_output_data_in[no-1.
.
0]InputOptionalGNDThisportfeedstheoutputDQsignalfortheOUTPUT_DQ_OUTPUT_FF:d,OUTPUT_DQ_OUTPUT_DELAY_CHAIN1:datain,OUTPUT_DQ_OUTPUT_DELAY_CHAIN2:datain,oroutput_dq_output_data_outport.
output_dq_output_data_out[no-1.
.
0]OutputOptional—ThisportoutputstheoutputDQsignalfromtheOUTPUT_DQ_OUTPUT_DELAY_CHAIN2:dataout,OUTPUT_DQ_OUTPUT_DELAY_CHAIN1:dataout,OUTPUT_DQ_OUTPUT_FF:q,OUTPUT_DQ_OUTPUT_DDIO_OUT:dataout,oroutput_dq_output_data_inport.
output_dq_sreset[no-1.
.
0]InputOptionalGNDThisportisconnectedtoallsresetportsintheoutputDQIOprimitivesthatisusedtosynchronouslyresettheregistersinthoseprimitives.
Table4–16.
MegafunctionPortstoConfigureDQOutputPath(Part2of2)PortNameTypeOptional/RequiredDefaultDescriptionChapter4:FunctionalDescription4–42ALTDQ_DQSMegafunctionPortsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideDQOEPathMegafunctionPortsTable4–17summarizesalltheportsonthemegafunctionthatconfiguretheDQOEpath.
ThepossiblevaluesforareBIDIR_DQandOUTPUT_DQ.
Table4–17.
MegafunctionPortstoConfigureDQOEPath(Part1of2)PortNameTypeOptional/RequiredDefaultDescriptionbidir_dq_areset[nb-1.
.
0]InputOptionalGNDThisportisconnectedtoallaresetportinthebidirDQIOprimitivesthatisusedtoasynchronouslyresettheregistersinthoseprimitives.
bidir_dq_hr_oe_in[2*nb-1.
.
0]InputOptionalGNDThisportfeedsthehalf-ratebidirectionalDQOEsignalfortheBIDIR_DQ_OE_HR_DDIO_OUT:datainhi/datainloports.
bidir_dq_oe_in[nb-1.
.
0]InputOptionalGNDThisportfeedsthebidirectionalDQOEsignalfortheBIDIR_DQ_OE_FF:d,BIDIR_DQ_OE_DDIO_OE:oe,BIDIR_DQ_OE_DELAY_CHAIN1:datain,BIDIR_DQ_OE_DELAY_CHAIN2:datain,orbidir_dq_oe_outport.
bidir_dq_oe_out[nb-1.
.
0]OutputOptional—ThisportisdrivenbytheBIDIR_DQ_OE_DELAY_CHAIN2:dataout,BIDIR_DQ_OE_DELAY_CHAIN1:dataout,BIDIR_DQ_OE_FF:q,BIDIR_DQ_OE_DDIO_OE:dataout,orbidir_dq_oe_inport.
bidir_dq_sreset[nb-1.
.
0]InputOptionalGNDThisportisconnectedtoallsresetportinthebidirDQIOprimitivesthatisusedtosynchronouslyresettheregistersinthoseprimitives.
dq_hr_output_reg_clkInputOptionalGNDThisportfeedsthehalf-rateclocksignalforthe_OE_HR_DDIO_OUT:clkhi/clklo/muxselports.
Theclocksignalisforthehalf-rateDDIOregisters.
dq_output_reg_clkInputOptionalGNDThisportfeedstheclocksignalforthe_OE_FF:clkand_OE_DDIO_OE:clkports.
dq_output_reg_clkenaInputOptionalVCCThisportfeedstheoutputenablesignalforthe_OE_FF:enaand_OE_DDIO_OE:enaports.
output_dq_areset[no-1.
.
0]InputOptionalGNDThisportisconnectedtoallaresetportsintheoutputDQIOprimitivesthatisusedtoasynchronouslyresettheregistersinthoseprimitives.
output_dq_hr_oe_in[2*no-1.
.
0]InputOptionalGNDThisportfeedsthehalf-rateoutputDQOEsignalfortheOUTPUT_DQ_OE_HR_DDIO_OUT:datainhi/datainloports.
4–43Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDQSnI/OPathPortsTable4–18summarizesalltheportsthatarespecifictotheDQSnI/O.
AllotherportsaresharedwiththeDQSIO.
output_dq_oe_in[no-1.
.
0]InputOptionalGNDThisportfeedsthebidirectionalDQOEsignalfortheOUTPUT_DQ_OE_FF:d,OUTPUT_DQ_OE_DDIO_OE:oe,OUTPUT_DQ_OE_DELAY_CHAIN1:datain,OUTPUT_DQ_OE_DELAY_CHAIN2:datain,oroutput_dq_oe_outport.
output_dq_oe_out[no-1.
.
0]OutputOptional—ThisportisdrivenbytheOUTPUT_DQ_OE_DELAY_CHAIN2:dataout,OUTPUT_DQ_OE_DELAY_CHAIN1:dataout,OUTPUT_DQ_OE_FF:q,OUTPUT_DQ_OE_DDIO_OE:dataout,oroutput_dq_oe_inport.
output_dq_sreset[no-1.
.
0]InputOptionalGNDThisportisconnectedtoallsresetportsintheoutputDQIOprimitivesthatisusedtosynchronouslyresettheregistersinthoseprimitives.
Table4–17.
MegafunctionPortstoConfigureDQOEPath(Part2of2)PortNameTypeOptional/RequiredDefaultDescriptionTable4–18.
MegafunctionPortstoConfigureDQSNIOPath(Part1of2)PortNameTypeOptional/RequiredDefaultDescriptiondqsn_aresetInputOptionalGNDThisportisconnectedtoallaresetportsintheDQSnIOprimitivesthatisusedtoasynchronouslyresettheregistersinthoseprimitives.
dqsn_bus_outOutputOptional—ThisportoutputsthesignalfromDQSN_ENABLE:dqsbusout,DQSNBUSOUT_DELAY_CHAIN:dataout,orDQSN_DELAY_CHAIN:dqsbusoutport.
dqsn_hr_oe_in[1.
.
0]InputOptionalGNDThisportfeedsthehalf-rateDDRsignaltotheDQSnOEpath.
ThisportisconnectedtotheDQSN_OE_HR_DDIO_OUT:datainhi/datainloport.
dqsn_hr_output_data_in[3.
.
0]InputOptionalGNDThisportfeedsthehalf-rateDDRinputsignaltotheDQSnoutputpath.
ThisportisconnectedtotheDQSN_OUTPUT_HR_DDIO_OUT_HIGH:datainhi/datainloandDQSN_OUTPUT_HR_DDIO_OUT_LOW:datainhi/datainloports.
dqsn_input_data_inInputOptionalGNDThisportfeedstheinputsignaltotheDQSninputpath.
ThisportisconnectedtotheDQSN_DELAY_CHAIN:dqsin,DQSN_INPUT_DELAY_CHAIN:datain,ordqsn_input_data_outport.
Chapter4:FunctionalDescription4–44ALTDQ_DQSMegafunctionPortsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuidedqsn_input_data_outOutputOptional—ThisportoutputsthesignalfromtheDQSninputpath.
ThisportisconnectedtotheDQSN_INPUT_DELAY_CHAIN:dataoutordqsn_input_data_inport.
dqsn_oe_inInputOptionalGNDThisportfeedstheinputsignalfortheDQSnOEpath.
ThisportisconnectedtotheDQSN_OE_FF:d,DQSN_OE_DDIO_OE:oe,DQSN_OE_DELAY_CHAIN1:datain,DQSN_OE_DELAY_CHAIN2:datain,dqsn_oe_outport.
dqsn_oe_outOutputOptional—ThisportisfedbytheoutputsignalfromDQSnOEpath.
ThisportcanbedrivenbytheDQSN_OE_DELAY_CHAIN2:dataout,DQSN_OE_DELAY_CHAIN1:dataout,DQSN_OE_FF:q,DQSN_OE_DDIO_OE:dataout,dqsn_oe_inport.
dqsn_output_data_inInputOptionalGNDThisportfeedstheinputsignalforDQSnoutputpath.
ThisportisconnectedtotheDQSN_OUTPUT_FF:d,DQSN_OUTPUT_DELAY_CHAIN1:datain,DQSN_OUTPUT_DELAY_CHAIN2:datain,ordqsn_output_data_outport.
dqsn_output_data_in_highInputOptionalGNDThisportfeedsthefull-rateDDRinputsignal(risingedge)totheDQSnoutputpath.
ThisportisconnectedtotheDQSN_OUTPUT_DDIO_OUT:datainhiport.
dqsn_output_data_in_lowInputOptionalGNDThisportfeedsthefull-rateDDRinputsignal(fallingedge)totheDQSnoutputpath.
ThisportisconnectedtotheDQSN_OUTPUT_DDIO_OUT:datainloport.
dqsn_output_data_outOutputOptional—ThisportoutputstheoutputsignalfromtheDQSnoutputpath.
ThisportcanbedrivenbyDQSN_OUTPUT_DELAY_CHAIN2:dataout,DQSN_OUTPUT_DELAY_CHAIN1:dataout,DQSN_OUTPUT_FF:q,DQSN_OUTPUT_DDIO_OUT:dataout,ordqsn_output_data_inport.
dqsn_sresetInputOptionalGNDThisportisconnectedtoallsresetportsintheDQSnIOprimitivesthatisusedtosynchronouslyresettheregistersinthoseprimitives.
Table4–18.
MegafunctionPortstoConfigureDQSNIOPath(Part2of2)PortNameTypeOptional/RequiredDefaultDescription4–45Chapter4:FunctionalDescriptionALTDQ_DQSMegafunctionPortsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDQS_CONFIG/IO_CONFIGMegafunctionPortsTable4–19summarizesalltheportsonthemegafunctionthatconfiguretheDQS_CONFIG/IO_CONFIGpath.
Table4–19.
MegafunctionPortstoConfigureDQS_CONFIG/IO_CONFIGPathPortNameTypeOptional/RequiredDefaultDescriptionbidir_dq_io_config_ena[nb-1.
.
0]InputOptionalVCCEnablesignalfortheBIDIR_DQ_IO_CONFIGblock.
config_clkInputOptionalGNDClocksignalfortheDQS_CONFIGandIO_CONFIGblocks.
config_datainInputOptionalGNDInputsignalfortheDQS_CONFIGandIO_CONFIGblocks.
config_updateInputOptionalGNDUpdatesignalfortheDQS_CONFIGandIO_CONFIGblocks.
dqs_config_enaInputOptionalVCCEnablesignalfortheDQS_CONFIGblock.
dqs_io_config_enaInputOptionalVCCEnablesignalfortheDQS_IO_CONFIGblock.
dqsn_io_config_enaInputOptionalVCCEnablesignalfortheDQSN_IO_CONFIGblock.
input_dq_io_config_ena[nb-1.
.
0]InputOptionalVCCEnablesignalfortheINPUT_DQ_IO_CONFIGblock.
output_dq_io_config_ena[nb-1.
.
0]InputOptionalVCCEnablesignalfortheOUTPUT_DQ_IO_CONFIGblock.
Chapter4:FunctionalDescription4–46CorrectSettingsforExternalMemoryInterfacesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideCorrectSettingsforExternalMemoryInterfacesTable4–20showsthecorrectsettingsrequiredfortheALTDLLandALTDQ_DQSmegafunctionstoworkintheDDR,QDR,andRLDRAMinterfaces.
fnrepresentsthenumberofpinsinapath.
Thevalueofnrangesfrom0to48,butvariesaccordingtothememoryinterfaceused.
Todeterminethevalueofnforaparticularmemoryinterface,theExternalMemoryInterfacechapteroftherespectivedevicehandbooks.
Table4–20.
CorrectSettingsforDDR,QDR,andRLDRAMInterfacesParameterDDRQDRRLDRAMreadwritereadwriteRLDRAMIImodeUnusedUnusedTurnedon.
Refertothe"ALTDQ_DQSParameterEditor"onpage3–5.
DatamaskpingroupUnusedUnusedQvalidsignalgroupUnusedUnusedNumberofbidirectionalDQn00nNumberofinputDQ0n00NumberofoutputDQ00n0EnableDQoutputenablepathTurnedonTurnedoffTurnedonTurnedonUsehalf-ratecomponentsForfull-ratecontroller:TurnedoffForhalf-ratecontroller:TurnedonUsedynamicOCTpathTurnedonTurnedonEnableDQSinputpathTurnedonTurnedonTurnedoffTurnedonTurnedoffEnableDQSoutputpathTurnedonTurnedoffTurnedoffEnableDQSOEpathTurnedonTurnedoffTurnedoffDQS/DQSnIOconfigurationmodeIfused:DifferentialpairIfsingle_ended:TurnedoffComplementarypairDifferentialpairDQSinputfrequencyMHz(e.
g.
400MHz)DQSdelaychainphasesetting=phase_shift/360xDLL_delay_chain_lengthDQSdelaychain'delayctrlin'portsourceDLLEnableDQSinputdelaychainDefault:TurnedoffIfused:TurnedonDelaybuffermodeHighorLow(dependingontheALTDLLinstantiationsettings)EnableDQSdelaychainTurnedon4–47Chapter4:FunctionalDescriptionCorrectSettingsforExternalMemoryInterfacesALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTable4–2showsthecorrectportuseforDDR,QDR,andRLDRAMinterfaces.
Table4–21.
CorrectPortUseforDDR,QDRandRLDRAMInterfacesPortNameControllersFull-RateHalf-RateINPUT_DQ_INPUT_DATA_INUsedUsedINPUT_DQ_INPUT_DATA_OUT_HIGHUsedUnusedINPUT_DQ_INPUT_DATA_OUT_LOWUsedUnusedINPUT_DQ_HR_INPUT_DATA_OUTUnusedUsedOUTPUT_DQ_OUTPUT_DATA_OUTUsedUsedOUTPUT_DQ_OUTPUT_DATA_IN_LOWUsedUnusedOUTPUT_DQ_OUTPUT_DATA_IN_HIGHUsedUnusedOUTPUT_DQ_HR_OUTPUT_DATA_INUnusedUsedOUTPUT_DQ_HR_OE_INUnusedUsedOUTPUT_DQ_OE_INUsedUnusedOUTPUT_DQ_OE_OUTUsedUsedBIDIR_DQ_INPUT_DATA_INUsedUsedBIDIR_DQ_HR_INPUT_DATA_OUTUnusedUsedBIDIR_DQ_OUTPUT_DATA_OUTUsedUsedBIDIR_DQ_HR_OUTPUT_DATA_INUnusedUsedDQS_INPUT_DATA_INUsedUsedDQS_HR_OUTPUT_DATA_INUnusedUsedDQSN_INPUT_DATA_INUsedUsedDQSN_HR_OUTPUT_DATA_INUnusedUsedDQS_BUS_OUTUsedUsedDQS_OUTPUT_DATA_OUTUsedUsedDQ_INPUT_REG_CLKUsedUsedDQ_OUTPUT_REG_CLKUsedUnusedDQ_HR_OUTPUT_REG_CLKUnusedUsedDLL_DELAYCTRLINUsedUsedIO_CLOCK_DIVIDER_CLKUsedUsedChapter4:FunctionalDescription4–48CorrectSettingsforExternalMemoryInterfacesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTable4–22showsthecorrectOCTparametersettingsfortheDDR,QDR,andRLDRAMinterfaces.
Table4–23showsthecorrectOCTportusefortheDDR,QDR,andRLDRAMinterfaces.
Table4–22.
GeneralOCTParameterSettingsforDDR,QDR,andRLDRAMInterfacesParameterControllerFull-RateHalf-RateEnableDynamicOCTTurnedonTurnedonEnableOCTdelaychain1Turnedon/TurnedoffTurnedon/TurnedoffEnableOCTdelaychain2Turnedon/TurnedoffTurnedon/TurnedoffOCTregistermodeFFFFTable4–23.
GeneralOCTPortsforDDR,QDR,andRLDRAMInterfacesParameterControllerFull-RateHalf-RateDQS_OCT_INUsedUsedDQSN_OCT_INUsedUsedBIDIR_DQ_OCT_INUsedifDQpinisbidirectionalUsedifDQpinisbidirectionalINPUT_OCT_INUsedforDQpinasinputUsedforDQpinasinputOUTPUT_OCT_INUsedforDQpinasoutputUsedforDQpinasoutputDQS_HR_OCT_INUsedUnusedDQSN_HR_OCT_INUsedUnusedBIDIR_DQ_HR_OCT_INUsedUnusedINPUT_DQ_HR_OCT_INUsedUnusedOUTPUT_DQ_HR_OCT_INUsedUnusedOCT_REG_CLKUsedUsedHR_OCT_REG_CLKUsedifcontrollerisathalf-rateUnusedDQS_OCT_OUTUsedUsedDQSN_OCT_OUTUsedUsedBIDIR_DQ_OCT_OUTUsedifDQpinisbidirectionalUsedifDQpinisbidirectionalINPUT_DQ_OCT_OUTUsedforDQpinasinputUsedifDQpinisbidirectionalOUTPUT_DQ_OCT_OUTUsedforDQpinasoutputUsedifDQpinisbidirectional4–49Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesThissectiondescribesadesignexamplethatusestheDLLandDQ/DQScircuitrywithhalf-rateDDR2externalmemoryinterfaceinStratixIIIdevices.
Thememoryinterfaceisrunningat333.
333MHzwith8-bitbidirectionalDQpins,a1-bitoutputDQpin,anda1-bitdifferentialDQSpin.
fThedesignexamplesareavailablenexttotheALTDLLandALTDQ_DQSMegafunctionUserGuidesontheDocumentation:UserGuidespageoftheAlterawebsite.
ProcedureThisexampledescribesthefollowingsteps:InstantiatetheALTDLLMegafunctionInstantiatetheALTDQ_DQSMegafunctionInstantiatetheALTIOBUFMegafunctionSimulatetheDesignInstantiatetheALTDLLMegafunctionToinstantiatetheALTDLLmegafunction,performthefollowingsteps:1.
Openthealtdll_altdq_dqs_DesignExample_ex2.
zipprojectandextractthealtdll_altdq_dqs_design_ex2.
qarfile.
2.
IntheQuartusIIsoftware,openthealtdll_altdq_dqs_design_ex2.
qarfileandrestorethearchivedfileintoyourworkingdirectory.
3.
OntheToolsmenu,clickMegaWizardPlug-InManager.
Page1oftheMegaWizardPlug-InManagerappears.
4.
SelectCreateanewcustommegafunctionvariation.
5.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
SelectALTDLL,andVerilogHDL,andtypethefilenameasdll_inst.
v.
6.
OntheParameterSettingstab,ontheGeneralpage,specifytheparametersasshowninTable4–24.
TheseparametersconfigurethegeneralsettingsfortheALTDLLinstance.
Table4–24.
GeneralSettings(Part1of2)SettingsValueCurrentlyselecteddevicefamilyStratixIIIMatchproject/defaultTurnedonNumberofDelayChains10DQSDelayBufferModeHighInputClockFrequency333MHzTurnonjitterreductionTurnedoffChapter4:FunctionalDescription4–50DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide7.
OntheDLLOffsetControls/OptionalPortspage,specifytheparametersasshowninTable4–25.
8.
ClickFinish.
1WhenyouarepromptedtoaddtheQuartusIIIPfile(.
qip)toyourproject,clickYes.
TheALTDLLinstanceisnowgenerated.
9.
Browsetoyourworkingdirectoryandopentheinput.
txtfile.
10.
ChangethevalueoftheCBX_OUTPUT_DIRECTORYparametertothepathofyourworkingdirectory.
11.
Savethefile.
12.
Copytheinput.
txtfiletothe\quartus\bin\directory.
DLLPhaseOffsetControlAInstantiatedll_offset_controlblockTurnedoffDLLPhaseOffsetControlBInstantiatedll_offset_controlblockTurnedoffOptionalPortsCreateadll_aloadportTurnedoffOptionalPortsCreateadll_dqsupdateportTurnedoffTable4–25.
ALTDLLParameterSettings/DLLOffsetControls/OptionalPortsSettingsSettingsValueDLLPhaseOffsetControlAInstantiatedll_offset_controlblockTurnedoffDLLPhaseOffsetControlBInstantiatedll_offset_controlblockTurnedoffOptionalPortsCreateadll_aloadportTurnedoffOptionalPortsCreateadll_dqsupdateportTurnedoffTable4–24.
GeneralSettings(Part2of2)SettingsValue4–51Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationInstantiatetheALTDQ_DQSMegafunctionToinstantiatetheALTDQ_DQSmegafunction,performthefollowingsteps:1.
OntheToolsmenu,clickMegaWizardPlug-InManager.
Page1oftheMegaWizardPlug-InManagerappears.
2.
SelectCreateanewcustommegafunctionvariation.
3.
ClickNext.
Page2aoftheMegaWizardPlug-InManagerappears.
SelectALTDQ_DQS,andVerilogHDL,andtypethefilenameasdq_dqs_inst.
v.
4.
OntheParameterSettingspageoftheALTDQ_DQSparametereditor,specifytheparametersasshowninTable4–26.
5.
IntheAdvancedOptionstaboftheALTDQ_DQSparametereditor,ontheDQSINpage,specifytheparametersasshowninTable4–27.
TheseparametersconfiguretheDQSinputpathoftheALTDQ_DQSinstance.
Table4–26.
ParameterSettingsParameterValueRLDRAMIIModeNONEDatamaskpingroupNONEQvalidsignalgroupNONENumberofbidirectionalDQ8NumberofinputDQ0NumberofoutputDQ1Numberofstagesindqs_delay_chain2DQSInputFrequency333MHzUsehalf-ratecomponentsTurnedonUseDynamicOCTTurnedoffAddmemoryinterfacespecificfittergroupingassignmentsTurnedoffTable4–27.
AdvancedOptions(DQSIN)(Part1of2)ParameterSub-optionsValueEnableDQSInputPath—TurnedonEnableDynamicDelayChain—NotselectedEnabledqs_delay_chain—SelectedAdvanceddelaychainoptionsSelectdynamicallyusingconfigurationregistersTurnedoffDQSdelaychain'delayctrlin'portsourceDLLDQSDelayBufferModeHIGHDQSPhaseShift9000.
.
EnableDQSoffsetControlTurnedoffEnableDQSdelaychainlatchesTurnedoffEnableDQSbusoutdelaychain—TurnedonEnableDQSenableblock—TurnedonEnableDQSenablecontrolblock—TurnedonChapter4:FunctionalDescription4–52DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide6.
OntheDQSOUT/OEpage,specifytheparametersasshowninTable4–28.
TheseparametersconfiguretheDQSOUTPUTandDQSOEpathoftheALTDQ_DQSinstance.
7.
OntheDQINpage,specifytheparametersasshowninTable4–29.
TheseparametersconfiguretheDQinputpathoftheALTDQ_DQSinstance.
AdvancedenablecontroloptionsDQSEnableControlPhasesettingSetStaticallyto'0'DQSEnableControlInvertPhaseNeverEnableDQSenableblockdelaychain—TurnedonTable4–28.
AdvanceOptions(DQSOUT/OE)ParameterValueEnableDQSOutputPathTurnedonEnableDQSoutputdelaychain1TurnedonEnableDQSoutputdelaychain2Turnedon]DQSoutputregistermodeDDIOEnableDQSoutputenableTurnedonEnableDQSoutputenabledelaychain1TurnedonEnableDQSoutputenabledelaychain2TurnedonDQSoutputenableregistermodeDDIOTable4–29.
AdvanceOptions(DQIN)(Part1of2)ParameterSub-optionsValueDQinputregistermode—DDIODQInputRegisterOptionsDQinputregisterclocksource—'dqs_bus_out'port—TurnedoffConnectDDIOclkntoDQS_BUSfromcomplementaryDQSnUseDQinputphasealignment—TurnedonAdvancedDQIPAOptionsDQInputPhaseAlignmentPhaseSettingSetstaticallyto'0'AddDQInputPhaseAlignmentInputCycleDelayNeverInvertDQInputPhaseAlignmentPhaseNeverRegisterDQinputphasealignmentbypassoutputTurnedonRegisterDQinputphasealignmentaddphasetransferTurnedoffUseDQresyncregister—TurnedoffTable4–27.
AdvancedOptions(DQSIN)(Part2of2)ParameterSub-optionsValue4–53Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporation8.
OntheDQOUT/OEpage,specifytheparametersasshowninTable4–30.
TheseparametersconfiguretheDQOUTPUTandDQOEpathoftheALTDQ_DQSinstance.
9.
OntheHalf-ratepage,specifytheparametersasshowninTable4–31.
Theseparametersconfigurethehalf-ratesettingsoftheALTDQ_DQSinstance.
10.
OntheDQSnI/Opage,specifytheparametersasshowninTable4–32.
.
11.
OntheReset/ConfigPortspage,specifytheparametersasshowninTable4–33.
UseDQhalfrate'dataoutbypass'port—TurnedoffUseDQinputdelaychain—TurnedonTable4–30.
AdvanceOptions(DQOUT/OE)ParameterValueEnableDQoutputdelaychain1TurnedonEnableDQoutputdelaychain2TurnedonDQoutputregistermodeDDIOEnableDQoutputenableTurnedonEnableDQoutputenabledelaychain1TurnedonEnableDQoutputenabledelaychain2TurnedonDQoutputenableregistermodeDDIOTable4–31.
AdvanceOptions(Half-Rate)ParameterValueIOClockDividerSourceCoreCreate'io_clock_divider_masterin'inputportTurnedoffCreate'io_clock_divider_clkout'outputportTurnedonCreate'io_clock_divider_slaveout'outputportTurnedoffIOClockDividerInvertPhaseNeverTable4–32.
AdvancedOptions(DQS/DQSnIO)ParameterValueUseDQSnIOTurnedonDQSandDQSnIOConfigurationmodeDifferentialPairTable4–33.
AdvancedOptions(ResetandConfigPorts)(Part1of2)ParameterValueCreate'dqs_areset'inputportTurnedonCreate'dqs_sreset'inputportTurnedonCreate'input_dq_areset'inputportTurnedoffCreate'input_dq_sreset'inputportTurnedoffCreate'output_dq_areset'inputportTurnedoffTable4–29.
AdvanceOptions(DQIN)(Part2of2)ParameterSub-optionsValueChapter4:FunctionalDescription4–54DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide12.
ClickFinish.
Thedq_dqs_instmodule(dq_dqs_inst.
v)isgenerated.
InstantiatetheALTIOBUFMegafunctionAfterinstantiatingtheALTDLLandALTDQ_DQSmegafunctions,youmustinstantiatetheALTIOBUFmegafunctionwiththefollowingI/Obuffersettings:1bidirectionalbufferforthedifferentialDQSpins1outputbufferfortheoutputDQpins8bidirectionalbuffersforthebidirectionalDQpinsToinstantiatethesethreetypesofI/Obuffers,performthefollowingsteps:1.
IntheQuartusIIsoftware,ontheToolsmenu,clickMegaWizardPlug-InManager.
2.
Onpage1,selectCreateanewcustommegafunctionvariation.
ClickNext.
Page2aappears.
3.
Onpage2a,selectorverifytheconfigurationsettingsshowninTable4–34.
ClickNexttoadvancefromonepagetothenext.
4.
OntheParameterSettingspage,specifytheparametersasshowninTable4–35.
TheseparametersconfigurethegeneralsettingsfortheALTIOBUFinstance.
Create'output_dq_sreset'inputportTurnedoffCreate'bidir_dq_areset'inputportTurnedonCreate'bidir_dq_sreset'inputportTurnedonCreate'config_clk'inputportTurnedonCreate'config_datain'inputportTurnedonCreate'config_update'inputportTurnedonTable4–33.
AdvancedOptions(ResetandConfigPorts)(Part2of2)ParameterValueTable4–34.
ALTIOBUFConfigurationSettingsSettingsValue1bidirectionalbufferforthedifferentialDQSpins1outputbufferfortheoutputDQpins8bidirectionalbuffersforthebidirectionalDQpinsWhichdevicefamilywillyoubeusingStratixIIIStratixIIIStratixIIIWhichmegafunctionwouldyouliketocustomizeALTIOBUFALTIOBUFALTIOBUFWhichtypeofoutputfiledoyouwanttocreateVerilogHDLVerilogHDLVerilogHDLWhatnamedoyouwantfortheoutputfiledqs_iobuf_inst.
voutput_dq_iobuf_inst.
vbidir_dq_iobuf_inst.
v4–55Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporation5.
OntheDynamicDelayChainspage,specifytheparametersasshowninTable4–36.
6.
ClickFinish.
TheI/Obuffermodule(dqs_iobuf_inst.
v/output_dq_iobuf_inst.
v/bidir_dq_iobuf_inst.
v)isgenerated.
7.
OntheFilemenu,clickSave.
IntegratetheI/OBufferModuleswiththeALTDQ_DQSmodulesTointegratetheI/ObuffermoduleswiththeALTDQ_DQSmodules,performthefollowingsteps:1.
Openthetest_dq_dqs.
bdffileintheQuartusIIBlockEditorsoftware.
2.
ToinserttheI/Obuffermodules,double-clickontheBlockEditorwindow.
TheSymbolwindowappears.
3.
UnderName,browsetotheI/Obufferdqs_iobuf_inst.
bsffile.
4.
ClickOK.
TheI/ObuffermoduleisinsertedintotheBlockEditorwindow.
Table4–35.
ALTIOBUFGeneralSettingsSettingsValue1bidirectionalbufferforthedifferentialDQSpins1outputbufferfortheoutputDQpins8bidirectionalbuffersforthebidirectionalDQpinsCurrentlyselecteddevicefamilyStratixIIIStratixIIIStratixIIIHowdoyouwanttoconfigurethismoduleAsbidirectionalbufferAsoutputbufferAsbidirectionalbufferWhatisthenumberofbufferstobeinstantiated118UsebusholdcircuitryTurnedoffTurnedoffTurnedoffUsedifferentialmodeTurnedonTurnedoffTurnedoffUseopendrainoutputTurnedoffTurnedoffTurnedoffUseoutputenableportTurnedoffTurnedonTurnedonUsedynamicterminationcontrolTurnedoffTurnedoffTurnedoffUseseriesandparallelterminationcontrolTurnedoffTurnedoffTurnedoffTable4–36.
ALTIOBUFDynamicDelayChainSettingsSettingsValue1bidirectionalbufferforthedifferentialDQSpins1outputbufferfortheoutputDQpins8bidirectionalbuffersforthebidirectionalDQpinsEnableinputbufferdynamicdelaychainTurnedoffTurnedoffTurnedoffEnableoutputbufferdynamicdelaychain1TurnedoffTurnedoffTurnedoffEnableoutputbufferdynamicdelaychain2TurnedoffTurnedoffTurnedoffCreatea'clkena'portTurnedoffTurnedoffTurnedoffChapter4:FunctionalDescription4–56DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide5.
Repeatsteps1to4toinsertotherI/Obuffermodules.
6.
UsetheappropriateconnectorsfromtheBlockEditortoolbartoconnecttheI/Obuffermodulestothedq_dqs_inst.
vmoduleasshowninFigure4–24.
fFormoreinformationabouttheQuartusIIBlockEditor,referto"UsingtheBlockEditor"intheQuartusIIHelp.
4–57Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFigure4–24showsablockdiagramofthedesignexample,whichconsistsofsixblocks.
Figure4–24.
BlockDiagramofDesignExampleChapter4:FunctionalDescription4–58DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTable4–37providesthedescriptionforeachblockinthedesignexample.
Table4–37.
BlocksinDesignExampleBlockNameDescriptionpll_inst:inst1ThisblockrepresentstheStratixIIIPLLwiththefollowingsettings:inclk=200MHzc0=3,000ps,50%dutycyclec1=3,000ps,50%dutycyclec2=3,000ps,50%dutycyclec3=6,000ps,50%dutycycledll_inst:inst5ThisblockrepresentstheDLLcircuitryusedduringareadfromtheexternalmemory.
ThisblockisclockedbythePLLwiththefollowingsettings:delaychainlength=10delaybuffermode=Highinputfrequency=333MHzjitterreduction=Turnedoffdq_dqs_inst:instThisblockrepresentstheDQandDQScircuitrythatinterfaceswiththeexternalmemory.
Thesettingsarespecifiedintheinput.
txtfile.
Theblockiscustomizedforahalf-rateoperationandrepresentstheinterfacebetweentheFPGAcoreandtheI/Obuffersthatareconnectedtotheexternalmemorypins.
dqs_iobuf_inst:inst2ThisblockrepresentsthebidirectionalI/ObufferthatisusedastheDQSstrobe/clocksignalforinterfacingwiththeexternalmemory.
Thisblockisindifferentialmodeandis1bitwide.
Itisconnectedtothedq_dqs_instblock.
bidir_dq_iobuf_inst:inst3ThisblockrepresentsthebidirectionalI/ObufferthatisusedastheDQdatasignalsforinterfacingwiththeexternalmemory.
Thisblockis8bitswide.
Itisconnectedtothedq_dqs_instblock.
output_dq_iobuf_inst:inst4ThisblockrepresentstheoutputI/ObufferthatisusedastheDQdatasignalsforinterfacingwiththeexternalmemory.
Thisblockis1bitwide.
Itisconnectedtothedq_dqs_instblock.
4–59Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationSimulatetheDesignAfterinstantiatingthemegafunctions,performthefollowingstepstocompileyourdesign.
1.
IntheQuartusIIsoftware,ontheProjectmenu,clickAdd/RemoveFilesinProject.
2.
IntheCategorylist,selectFiles.
3.
NexttotheFilenamebox,click.
.
.
tobrowsetoyourworkingdirectory.
Selectthedll_inst.
vfileandclickOpen.
4.
ClickAddtoaddthedll_inst.
vfiletoyourproject.
5.
Repeatsteps3and4toaddthedq_dqs_inst.
vandtest_dq_dqs.
bdffiles.
6.
ClickOK.
7.
OntheFilemenu,clickSave.
8.
OntheProcessingmenu,clickStartCompilationtocompilethedesign.
Afterthedesigniscompiled,youcanviewimplementationintheRTLViewer.
YoucanalsoviewtheresourceusageintheCompilationReport.
Afteryoucompileyourdesign,simulatethedesignintheModelSim-Alterasoftwaretogenerateawaveformdisplayofthedevicebehavior.
SetupandsimulatethedesignintheModelSim-Alterasoftwarebyperformingthefollowingsteps:1.
Unzipthealtdll_altdq_dqs_ex2_msim.
zipfiletoanyworkingdirectoryonyourPC.
2.
StarttheModelSim-Alterasoftware.
3.
OntheFilemenu,clickChangeDirectory.
4.
Selectthefolderinwhichyouunzippedthefiles.
5.
ClickOK.
6.
OntheToolsmenu,pointtoTCLandclickExecuteMacro.
7.
Selectthealtdll_altdq_dqs_ex2_msim.
dofileandclickOpen.
ThisisascriptfilefortheModelSim-Alterasoftwaretoautomateallthenecessarysettingsforthesimulation.
8.
Verifytheresultswiththewaveform.
Youcanrearrangesignals,removesignalsandaddsignals,andchangetheradixbymodifyingthescriptinthealtdll_altdq_dqs_ex2_msim.
dofile.
Chapter4:FunctionalDescription4–60DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideUnderstandingtheSimulationResultsThissectiondescribesthesimulationresultsof"DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevices"onpage4–49.
WritingDatatotheExternalMemoryThefollowingsequencedescribesthetransferringofdatafromtheFPGAcoretothebidirectionalDQpinswithvariousdelaychainsettings(refertoFigure4–25onpage4–63):1.
ThesimulationbeginswhenthePLLislocked,asindicatedbytheassertionofthelockedsignalat225,000ps(refertoFigure4–25).
Atthispoint,thePLLinputfrequency,asindicatedbytheinclk0signal,is200MHz.
2.
Thec0,c1,andc2portsgeneratea333.
333-MHzclockoutputwhilethec3portgeneratesa166.
666-MHzclockoutput.
1Thisdesignexampleusesthehalf-rateoption,whichmeansthattheFPGAcoresendsandreceivesdatafromtheexternalmemoryinterfaceatahalf-rateof166.
666MHz.
Thepinthatinterfaceswiththememorytogglesat333.
333MHz.
However,becausethispinisalsotoggledbyaDDIO_OUTsignal,thedatathroughputis666.
666Mbps.
3.
TheoutputpathfromtheFPGAcoretothebidirectionalDQpinisrepresentedbya32-bitinput,bidir_dq_hr_output_data_in[31:0].
TheinputpathfromthebidirectionalpintotheFPGAcoreisrepresentedbya32-bitoutput,bidir_dq_hr_input_data_out[31:0].
TheOEpathfromtheFPGAcoretothebidirectionalbuffer,bidir_dq_hr_oe_in[15:0],is16bitswideandisactive-low.
4.
FortheDQoutputpin,theoutputpathintheFPGAcoretothebidirectionalDQpinisrepresentedbya4-bitinput,output_dq_hr_output_data_in[3:0].
TheOEpathis2bitswidefromtheFPGAcoretothebidirectionalbuffer,output_dq_hr_oe_in[1:0].
1Inthefirstpartofthesimulation,onlyoutputpathsareused;therefore,bidir_dq_hr_oe_in[15:0]=16'b0anddqs_hr_oe_in[1:0]=2'b0.
5.
Forbidir_dq_hr_output_data_in[31:0],eachbitistoggledwitha10-MHzdatasignalfrom100nsto300ns.
Thetogglingbehaviorofbidir_dq_hr_output_data_in[31:0]isrepresentedinthewaveformingroupsof4-bitsignals(forexample,bidir_dq_hr_output_data_in[3:0]),asthefourinputpathsareconnectedtothebidir_dq_io[0]pin.
6.
Thebidir_dq_hr_output_data_in[3]andbidir_dq_hr_output_data_in[2]signalsgothroughtheDDIO_OUTport,whichisclockedat166.
666MHzbythec3PLLclockoutput.
Atthesametime,thebidir_dq_hr_output_data_in[1]andbidir_dq_hr_output_data_in[0]signalsgothroughanotherDDIO_OUTport,whichisclockedat166.
666MHzbythec3PLLclockoutput.
4–61Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporation7.
Bothoutputs(bidir_dq_0_output_hr_ddio_out_high_inst/dataoutandbidir_dq_0_output_hr_ddio_out_low_inst/dataout)ofthepreviousDDIO_OUTportsarechanneledintoanotherDDIO_OUTport,whichisclockedat333.
333MHzbythec1PLLclockoutput.
8.
Theoutputbidir_dq_0_output_ddio_out_inst/dataoutisthenconnectedtothebidirectionalDQoutputdelaychain1.
9.
Theoutputbidir_dq_0_output_delay_chain1_inst/dataoutisconnectedtothebidirectionalDQoutputdelaychain2,andtheoutputbidir_dq_0_output_delay_chain2_inst/dataoutisconnectedtothebidir_dq_io[0]pin.
10.
Thesamedataispropagatedthroughtheotherinputsofbidir_dq_hr_output_data_in[31:4],whichcausesthebidir_dq_io[7:1]pinstotoggleinthesamemanner.
11.
Thethroughputofdatagoingoutoneachpintotheexternalmemoryis666.
666Mbps.
12.
Theoutputdelaychainsaredisabled.
Thebidir_dq_0_output_delay_chain1_inst/datain,bidir_dq_0_output_delay_chain2_inst/datain,bidir_dq_0_output_delay_chain1_inst/dataout,andbidir_dq_0_output_delay_chain2_inst/dataoutsignalsarealigned,whichindicatesthatthere'snodelaysettingsonthetwooutputdelaychains.
Thesamewritesequenceappliestowritingdatawithdifferentdelaychainvaluesactivatedonthetwooutputdelaychains.
Youcanobtainthedifferenceinthedelaychainvaluesbyanalyzingthetimingpathsofthefollowingsignals:bidir_dq_0_output_delay_chain1_inst/datainbidir_dq_0_output_delay_chain2_inst/datainbidir_dq_0_output_delay_chain1_inst/dataoutbidir_dq_0_output_delay_chain2_inst/dataoutbidir_dq_0_output_hr_ddio_out_high_inst/dataoutbidir_dq_0_output_hr_ddio_out_low_inst/dataoutbidir_dq_0_output_ddio_out_inst/dataoutbidir_dq_io[0]1Formoreinformationabouthowtoanalyzethetimingpathstoobtainthedelaychainvalues,refertothetimingdiagramsin"DQS_CONFIG/IO_CONFIGBlock"onpage4–22.
13.
TheoutputpathfromtheFPGAcoretothebidirectionalDQSpinisrepresentedbya4-bitinput,dqs_hr_output_data_in[3:0].
TheOEpathis2bitswidefromtheFPGAcoretothebidirectionalbuffer,dqs_hr_oe_in[1:0].
TheinputpathoftheDQSpingoesthroughaspecializedcircuitrytoclockthe8-bitbidirectionalDQpininputpaths.
Chapter4:FunctionalDescription4–62DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuide14.
Thedqs_hr_output_data_in[3:0],dqs_hr_output_data_in[3]anddqs_hr_output_data_in[2]signalsaretoggledwithaconstantvalueof1'b1.
Afterthat,thedqs_hr_output_data_in[1]anddqs_hr_output_data_in[0]signalsaretoggledwithaconstantvalueof1'b0.
ThesignalsaretoggledataconstantratetogeneratethenecessaryDQSwritestrobe/clocksignals,whicharesenttogetherwiththeDQwritedatatotheexternalmemory.
15.
Asthethroughputofthedataissentat666.
666Mbps,theDQSwritestrobe/clocksignalisa333.
333-MHzDDRclocksignal.
Toobtainsuchasignal,thedqs_hr_output_data_in[3]anddqs_hr_output_data_in[2]signalsgothroughaDDIO_OUTport,whichisclockedat166.
666MHzbythec3PLLclockoutput.
Atthesametime,thedqs_hr_output_data_in[1]anddqs_hr_output_data_in[0]signalsgothroughanotherDDIO_OUTport,whichisclockedat166.
666MHzbythec3PLLclockoutput.
16.
Bothoutputs(dqs_output_hr_ddio_out_high_inst/dataoutanddqs_output_hr_ddio_out_low_inst/dataout)ofthepreviousDDIO_OUTportsarechanneledintoanotherDDIO_OUTport,whichisclockedat333.
333MHzbythec1PLLclockoutput.
17.
Theoutputdqs_output_ddio_out_inst/dataoutisthenconnectedtooutput_delay_chain_1.
Theoutputdqs_output_delay_chain1_inst/dataoutisconnectedtooutput_delay_chain_2.
18.
Theoutputdqs_output_delay_chain2_inst/dataoutisconnectedtothedqs_iopin,whichactsasa333.
333-MHzDQSwritestrobe/clocksignal.
fFordetailsaboutchangingthedelaychainvaluesdynamically,refertotheI/OBuffer(ALTIOBUF)MegafunctionUserGuide.
4–63Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFigure4–25.
DataTransferFromtheFPGACoretotheBidirectionalDQPinwithNoDelayChainsActivatedbidir_dq_0_output_delay_chain1_inst.
dataoutbidir_dq_0_output_delay_chain2_inst.
dataoutbidir_dq_io[7:0]dqs_hr_oe_in[1:0]dqs_hr_output_data_in[3:0]dqs_output_hr_ddio_out_low_inst.
dataoutdqs_output_hr_ddio_out_high_inst.
dataoutdqs_output_delay_chain1_inst.
dataoutdqs_output_delay_chain2_inst.
dataoutdqs_output_ddio_out_inst.
dataoutdqs_io00FF00FFinclk0lockedaresetconfig_clkconfig_datainconfig_updatec2bidir_dq_io_config_ena[7:0]bidir_dq_hr_oe_in[15:0]bidir_dq_0_oe_ddio_oe_inst.
dataoutbidir_dq_0_oe_hr_ddio_out_inst.
dataoutbidir_dq_0_oe_delay_chain1_inst.
dataoutbidir_dq_0_oe_delay_chain2_inst.
dataoutc3bidir_dq_hr_output_data_in[31:0]c1bidir_dq_0_output_hr_ddio_out_high_inst.
dataoutbidir_dq_0_output_hr_ddio_out_low_inst.
dataoutbidir_dq_0_output_ddio_out_inst.
dataoutoutput_dq_0_output_delay_chain1_inst.
dataoutoutput_dq_0_output_delay_chain2_inst.
dataout0000000000FFFFFFFF00000000FFFFFFFF0ns20ns40ns60ns80ns100ns120ns140ns160ns180ns200ns220ns240ns260ns280ns300ns[1]bidir_dq_0_output_delay_chain1_inst.
datainbidir_dq_0_output_delay_chain2_inst.
datain[2][3][5][7][8,9,10][12][13,14,15][16][17,18]Chapter4:FunctionalDescription4–64DesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIDevicesFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideReadingDatafromtheExternalMemoryThefollowingsequencedescribesthetransferringofdatafromthebidirectionalDQpinstotheFPGAcorewithvariousdelaychainsettings(refertoFigure4–26onpage4–65):1Theinterfacetotheexternalmemoryhasathroughputof666.
666Mbpsduringthereadprocess.
1InFigure4–26,onlytheinputpathsareused;therefore,bidir_dq_hr_oe_in[15:0]=16'b1anddqs_hr_oe_in[1:0]=2'b1from5sonwards.
1.
Eachbitinthebidir_dq_io[7:0]pinistoggledwitha10-MHzdatasignalfrom5.
25sto5.
45s.
Thepinbehaviorisrepresentedinthewaveformingroupsof4-bitsignalsbecausethebidir_dq_io[0]inputisconnectedtothebidir_dq_hr_input_data_out[3:0]outputs.
2.
Thebidir_dq_io[0]pinisconnectedtotheinputdelaychain.
3.
Theoutputbidir_dq_0_input_delay_chain_inst/dataoutofthedelaychainisconnectedtotheinputoftheDDIO_INport,whichisclockedbyaspecializedDQScircuitrythatusestheDLL.
4.
Theoutputs(bidir_dq_0_ddio_in_inst/regouthiandbidir_dq_0_ddio_in_inst/regoutlo)ofthepreviousDDIO_INportsarechanneledtotwoinputphasealignmentblocks,respectively.
Theseinputphasealignmentblocksareclockedat333.
333MHzbythec2clockoutputofthePLL.
5.
TheoutputsofthetwoIPAs,bidir_dq_0_ipa_high_inst/dataoutandbidir_dq_0_ipa_low_inst/dataout,arechanneledtoahalf-rateinputblock,whichisclockedbytheIO_CLOCK_DIVIDERblocks.
6.
Theoutputbidir_dq_0_half_rate_input_inst/dataout[3:0]ofthisblockisthenconnectedtothebidir_dq_hr_input_data_out[3:0]outputs.
7.
Thesamedataispropagatedthroughtheotherbidirectionalpinsofbidir_dq_io[7:1],whichcausesthebidir_dq_hr_input_data_out[31:4]outputstotoggleinthesamemanner.
8.
Thethroughputofthedataintheoutputportsareatahalf-rateof166.
666MHz.
9.
Theinputdelaychainisenabled.
Thebidir_dq_0_input_delay_chain_inst/datainandbidir_dq_0_input_delay_chain_inst/dataoutsignalsarenotaligned,whichindicatesthatthereisadelayontheinputdelaychain.
Thesamereadsequenceappliestoreadingdatawithdifferentchainvaluesactivatedontheinputdelaychain.
Youcanobtainthedifferenceinthedelaychainvaluesbyanalyzingthetimingpathsofthefollowingsignals:bidir_dq_io[0]bidir_dq_0_input_delay_chain_inst/datainbidir_dq_0_input_delay_chain_inst/dataoutbidir_dq_0_ddio_in_inst/regouthibidir_dq_0_ddio_in_inst/regoutlo4–65Chapter4:FunctionalDescriptionDesignExample:ImplementingHalf-RateDDR2InterfaceinStratixIIIALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationFigure4–26.
DataTransferfromtheBidirectionalDQPintotheFPGACorewith50-psDelayChainActivatedbidir_dq_0_input_delay_chain_inst.
dataoutbidir_dq_0_ddio_in_inst.
regouthibidir_dq_0_ddio_in_inst.
regoutlobidir_dq_0_ipa_low_inst.
dataoutbidir_dq_0_ipa_high_inst.
dataoutbidir_dq_0_half_rate_input_inst.
dataout[3:0]bidir_dq_hr_input_data_out[31:0]dqs_config_enac0dqsn_io_config_enadqsn_hr_oe_in[1:0]dqsn_iodqs_io_config_enaoutput_dq_io_config_enaoutput_dq_hr_oe_in[1:0]output_dq_0_oe_hr_ddio_out_inst.
dataoutoutput_dq_0_oe_ddio_oe_inst.
dataoutoutput_dq_0_oe_delay_chain1_inst.
dataoutoutput_dq_0_oe_delay_chain2_inst.
dataoutoutput_dq_hr_output_data_in[3:0]output_dq_0_output_hr_ddio_out_high_inst.
dataout5.
10us5.
12us5.
14us5.
16us5.
18us5.
20us5.
22us5.
24us5.
26us5.
28us5.
30us5.
32us5.
34us5.
36us5.
38us5.
40us5.
42us5.
44us5.
46usbidir_dq_io[7:0]dqs_hr_oe_in[1:0]dqs_hr_output_data_in[3:0]dqs_output_hr_ddio_out_low_inst.
dataoutdqs_output_hr_ddio_out_high_inst.
dataoutdqs_output_delay_chain1_inst.
dataoutdqs_output_delay_chain2_inst.
dataoutdqs_output_ddio_out_inst.
dataoutdqs_ioFF00FFF308FFFFFFFFF00000000FFFFFFFFF0Foutput_dq_0_output_ddio_out_inst.
dataoutoutput_dq_0_output_hr_ddio_out_low_inst.
dataoutbidir_dq_0_input_delay_chain_inst.
datain[1][9][10]February2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideA.
ClearBoxGeneratorUsingClearBoxGeneratorYoucanusetheclearboxgenerator,acommand-lineexecutable,toconfigureparametersthatarenotavailableintheALTDQ_DQSparametereditor.
Theclearboxgeneratorcreatesormodifiesdesignfilesthatcontaincustommegafunctionvariations,whichcanthenbeinstantiatedinadesignfile.
Toruntheclearboxgenerator,performthefollowingsteps:1.
Typethefollowingcommandatthecommandpromptofyouroperatingsystem:\quartus\bin\2.
Theexecutablenameisclearbox.
exe.
Tousetheexecutable,typethefollowingcommand:clearboxaltdq_dqs.
dll-f*.
txtwhere*.
txtrepresentsoneormoretextfilescontainingtheportsandparametersthatyouwanttogenerate,refertoFigureA–1.
FigureA–1.
AccessingtheClearBoxGeneratorA–2AppendixA:ClearBoxGeneratorClearBoxGeneratorOptionsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationClearBoxGeneratorOptionsThissectiondescribestheoptionsavailablewhenyougeneratetheALTDQ_DQSmegafunctionwiththeclearboxgenerator.
Tofindouttheavailableportsandparametersforthismegafunction,typethefollowingcommandatthecommandpromptofyouroperatingsystem:clearboxaltdq_dqs.
dll-hFigureA–2showsasamplelistingoftheavailableportsandparametersfortheALTDQ_DQSmegafunction.
ToefficientlygenerateoutputfilesfortheALTDQ_DQSmegafunction,Alterarecommendsthatyouuseatextfiletopasstherequiredportsandparameterstotheclearboxgenerator.
Thismethodpromotesreusabilityandprovidesaneasierwaytocustomizethemegafunction.
FigureA–2.
AvailablePortsandParametersfortheALTDQ_DQSMegafunctionA–3ClearBoxGeneratorOptionsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideFigureA–3showsasampletextfileusedfortheclearboxgenerator.
Withthetextfile,youcangenerateoutputfilesusingthefollowingcommand:clearboxaltdq_dqs.
dll–fsample_param_test.
txtAftertheoutputfilesaregenerated,youcaninstantiatethemegafunctionmoduleintoeitheraHDLfileorablockdiagramfileintheQuartusIIsoftware.
TodeterminetheresourceusageforaparticularconfigurationintheALTDQ_DQSmegafunction,typethefollowingcommand:clearboxaltdq_dqs.
dll-fsample_param_test.
txt-resc_countClearBoxParametersTableA–1liststheClearBoxparametersfortheALTDLLmegafunction.
FigureA–3.
SampleTextFileforClearBoxGeneratorTableA–1.
ALTDLLMegafunctionParameters(Part1of3)ParameterNameTypeRequiredDescriptionDELAY_BUFFER_MODEStringNoDetermineswhethertheDLLdelaybuffersareworkinginlow-frequencymodeorhigh-frequencymode.
AvailablevaluesareLOWandHIGH.
ThedefaultvalueisLOW.
DELAY_CHAIN_LENGTHIntegerNoThisparameterrepresentsthenumberofdelaybuffersinthedelayloop.
Theavailablevaluesare6,8,10,12,and16.
Thisparameterdefaultsto12.
DLL_OFFSET_CTRL_A_STATIC_OFFSETStringNoThisisaGray-codedsignedintegerexpressedasastringwitharangefrom–63to63.
IftheDLL_OFFSET_CTRL_A_USE_OFFSETparameterissettoFALSE,thevalueisaddedtotheDLLdelay-settingvalueandappearsasoutputonthedll_offset_ctrl_a_offsetctrlout[5.
.
0]outputbus.
IftheDLL_OFFSET_CTRL_A_USE_OFFSETparameterissettoTRUE,ignorethisvalue.
Thedefaultvalueis0.
A–4AppendixA:ClearBoxGeneratorClearBoxGeneratorOptionsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDLL_OFFSET_CTRL_A_USE_OFFSETStringNoAvailablevaluesareTRUEandFALSE.
Itdeterminestheoutputofthedll_offset_ctrl_a_offsetctrlout[5.
.
0]outputbus.
IfsettoTRUE,thendependingonwhetherthedll_offset_ctrl_a_addnsubinputisassertedornot,thephaseoffsetspecifiedonthedll_offset_ctrl_a_offset[5.
.
0]inputbusisaddedorsubtractedfromtheDLLdelaysettingoutputtogetthedll_offset_ctrl_a_offsetctrlout[5.
.
0]output.
IfsettoFALSE,thephaseoffsetspecifiedbytheDLLdelaysettingtogetthedll_offset_ctrl_a_offsetctrlout[5.
.
0]output.
Ifomitted,thedefaultisFALSE.
DLL_OFFSET_CTRL_B_STATIC_OFFSETStringNoThisisaGray-codedsignedintegerexpressedasastringwitharangefrom–63to63.
IftheDLL_OFFSET_CTRL_B_USE_OFFSETparameterissettoFALSE,thevalueisaddedtotheDLLdelay-settingvalueandappearsasoutputonthedll_offset_ctrl_a_offsetctrlout[5.
.
0]outputbus.
IftheDLL_OFFSET_CTRL_B_USE_OFFSETparameterissettoTRUE,ignorethisvalue.
Thedefaultvalueis0.
DLL_OFFSET_CTRL_B_USE_OFFSETStringNoAvailablevaluesareTRUEandFALSE.
Itdeterminestheoutputofthedll_offset_ctrl_b_offsetctrlout[5.
.
0]outputbus.
IfsettoTRUE,thendependingonwhetherthedll_offset_ctrl_b_addnsubinputisassertedornot,thephaseoffsetspecifiedonthedll_offset_ctrl_b_offset[5.
.
0]inputbusisaddedorsubtractedfromtheDLLdelaysettingoutputtogetthedll_offset_ctrl_b_offsetctrlout[5.
.
0]output.
IfsettoFALSE,thephaseoffsetspecifiedbytheDLLdelaysettingtogetthedll_offset_ctrl_b_offsetctrlout[5.
.
0]output.
Ifomitted,thedefaultisFALSEINPUT_FREQUENCYStringYesThisisthefrequencyoftheclockconnectedtotheclkinputport.
Checkthisparametervaluetoensurethatitfallswithinavalidrange.
Thisfieldisrequiredanddefaultsto0.
Youcanspecifyadurationbyplacingatimeunitafterthevalue(forexample,2.
5ns).
Thevalueisinfloating-pointformatwithnodecimalpointlimit.
JITTER_REDUCTIONStringNoAvailablevaluesareTRUEandFALSE.
IfsettoTRUE,thejitterreductioncircuitisenabledonthedll_delayctrlout[5.
.
0],anddll_offset_ctrl_a_offsetctrlout[5.
.
0]ordll_offset_ctrl_b_offsetctrlout[5.
.
0]outputsandtheDLLmayrequireupto1,024clockcyclestolock.
IfsettoFALSE,thejitterreductioncircuitisdisabledandtheDLLonlyrequiresupto256clockcyclestolock.
Ifomitted,thedefaultisFALSE.
TableA–1.
ALTDLLMegafunctionParameters(Part2of3)ParameterNameTypeRequiredDescriptionA–5ClearBoxGeneratorOptionsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTableA–2liststhehigh-levelClearBoxparametersfortheALTDQ_DQSmegafunction.
USE_DLL_OFFSET_CTRL_AStringNoSpecifieswhethertoinstantiateDLL_OFFSET_CTRL_Ablock.
ValuesareTRUEandFALSE.
Ifomitted,thedefaultisFALSE.
USE_DLL_OFFSET_CTRL_BStringNoSpecifieswhethertoinstantiateDLL_OFFSET_CTRL_Bblock.
ValuesareTRUEandFALSE.
Ifomitted,thedefaultisFALSE.
TableA–1.
ALTDLLMegafunctionParameters(Part3of3)ParameterNameTypeRequiredDescriptionTableA–2.
ALTDQ_DQSMegafunctionHigh-LevelConfigurationsParameterNameOptional/RequiredDefaultLegalValuesDescriptionUSE_DQSOptionalFALSEFALSE,TRUEInstantiatesDQSIOifTRUEUSE_DQS_INPUT_PATHOptionalFALSEFALSE,TRUEInstantiatesDQSinputpathifTRUEUSE_DQS_OUTPUT_PATHOptionalFALSEFALSE,TRUEInstantiatesDQSoutputpathifTRUEUSE_DQS_OE_PATHOptionalFALSEFALSE,TRUEInstantiatesDQSOEpathifTRUEDQS_DQSN_MODEOptionalNONENONE,DIFFERENTIAL,COMPLEMENTARYInstantiatesDQSandDQSnI/OsasadifferentialpairifDIFFERENTIAL,InstantiateDQSandDQSnI/OsasacomplementarypairifCOMPLEMENTARY,InstantiateonlyaDQSIOifNONENUMBER_OF_BIDIR_DQOptional00,1,2.
.
48ReferredasnbNUMBER_OF_OUTPUT_DQOptional00,1,2.
.
48ReferredasnoNUMBER_OF_INPUT_DQOptional00,1,2.
.
48ReferredasniUSE_DQ_OE_PATHOptionalFALSEFALSE,TRUEInstantiatesOEpathforOUTPUT_DQIOsUSE_HALF_RATEOptionalFALSEFALSE,TRUEInstantiateshalf-ratecomponentsUSE_DYNAMIC_OCTOptionalFALSEFALSE,TRUEInstantiatesdynamicOCTcomponentsNUMBER_OF_CLK_DIVIDEROptional00,1,2.
.
8ReferredasncA–6AppendixA:ClearBoxGeneratorClearBoxGeneratorOptionsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTableA–3summarizestheClearBoxparametersfortheALTDQ_DQSmegafunctiontoconfiguretheDQSinputpath.
TableA–3.
MegafunctionParameterstoConfigureDQSInputPath(Part1of4)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionUSE_DQS_INPUT_DELAY_CHAINOptionalFALSEFALSE,TRUEInstantiatesDQS_INPUT_DELAY_CHAINifTRUE.
USE_DQS_DELAY_CHAINOptionalFALSEFALSE,TRUEInstantiatesDQS_DELAY_CHAINifTRUE.
USE_DQS_ENABLEOptionalFALSEFALSE,TRUEInstantiatesDQS_ENABLEifTRUE.
USE_DQS_ENABLE_CTRLOptionalFALSEFALSE,TRUEInstantiatesDQS_ENABLE_CTRLifTRUE.
USE_DQSBUSOUT_DELAY_CHAINOptionalFALSEFALSE,TRUEInstantiatesDQSBUSOUT_DELAY_CHAINifTRUE.
USE_DQSENABLE_DELAY_CHAINOptionalFALSEFALSE,TRUEInstantiatesDQSENABLE_DELAY_CHAINifTRUE.
DQS_INPUT_FREQUENCYOptionalUNUSED—ThisparameterissettothefrequencyoftheDQSstrobe/clockinputexpressedasastringand,ifisnotsetto0,andisnotsettoFALSE,thisneedstomatchtheinput_frequencyparameteroftheDLLfeedingthedelayctrlin[5.
.
0]input.
ThisisanoptionalfieldanddefaultstoUNUSED.
DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCEOptionalCore,DLLDLLThisparameteristheGray-codeddelaychainsettingfortheDQSreadpath.
ThisisanoptionalinputanddefaultstoGND.
YoucanignorethisinputiftheparameterissettoFALSEandissetto0.
YoucanfeedthisinputbythedelayctrloutoutputofaDLLorthecore.
Thisinputdoesnotneedtomatchthepolarityofitssourceandcanbeinverted(unlessfedbythedelayctrloutoutputofaDLL).
A–7ClearBoxGeneratorOptionsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideUSE_DQS_DELAY_CHAIN_PHASECTRLINOptionalOFALSEFALSE,TRUEThisparameteristhesignalusedtochoosethephaseappliedtothedqsbusoutoutputwhenissettoTRUE;otherwise,thephasesettingisdeterminedbytheparameter.
OnlyfeedthisportbythedqsinputphasesettingoutputportoftheDQSconfig.
YoumustconnectthisportifissettoTRUE;otherwise,thisportisoptionalanddefaultstoGND.
Thisinputmustmatchthepolarityofitssourceandcannotbeinverted.
DQS_DELAY_CHAIN_PHASE_SETTINGOptional00,1,2,3,4Thisparameterisadelaychainsetting.
IfissettoFALSE,thisparametersetsthenumberofDQSdelaybuffersthatthedqsinsignalshouldtravelthroughtothedqsbusoutport;otherwise,youcanignorethissetting.
Whenitissetto0,thedqsbusoutsignalbypassestheDQSdelaychain.
Whenitissetto1,2,3,or4,thedqsbusoutsignalgoesthrough1,2,3,or4delaybuffers,respectively,thatarecontrolledbydelayctrlin[5.
.
0].
Thephase-shiftimplementedisdeterminedbytheratiooftheDQSdelaybufferstoDLLdelaybuffers:phase_shift=phase_setting/DLLdelay_chain_length*360DELAY_BUFFER_MODEOptionalLOWLOW,HIGHThisparameterdetermineswhetherthevariabledelaybuffersareworkinginlow-frequencymodeorhigh-frequencymode.
DQS_PHASE_SHIFTOptional00.
.
36,000ThisparameterindicatesthephaseshiftbetweenthedelayedDQSsignalandtheinputDQSsignalinunitsofhundredsofdegrees(forexample,a90°phaseshiftisrepresentedas9,000).
Thisparameterisapplicableonlyforstatictiminganalysisbecausethephaseshiftthroughthedelayctrlin[5.
.
0],phasectrlin[2.
.
0],andoffsetctrlin[5.
.
0]portscannotbedetermined.
DQS_OFFSETCTRL_ENABLEOptionalFALSEFALSE,TRUEThisparameterdescribeswhethertheoffsetctrlin[5.
.
0]inputsareused.
TableA–3.
MegafunctionParameterstoConfigureDQSInputPath(Part2of4)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionA–8AppendixA:ClearBoxGeneratorClearBoxGeneratorOptionsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDQS_CTRL_LATCHES_ENABLEOptionalFALSEFALSE,TRUEThisparameterdescribeswhetherthedelayctrlin[5.
.
0]andoffsetctrlin[5.
.
0]inputsarelatchedornot.
IfsettoTRUE,onlyaDLLfeedsthedelayctrlin[5.
.
0]inputbus.
USE_DQS_ENABLE_CTRL_PHASE_CTRLINOptionalTRUEFALSE,TRUEIfsettoTRUE,thephasesettingisdeterminedbythephasectrlininput.
IfsettoFALSE,thephasesettingisdeterminedbytheparameter.
DQS_ENABLE_CTRL_PHASE_SETTINGOptional00.
.
7ThisparameterdeterminesthephaseshiftimplementedbythedelaychainifissettoFALSE;otherwise,youcanignorethissetting.
LEVEL_DQS_ENABLEOptionalOFALSEFALSE,TRUEThisisanoptionalfieldanddefaultstoFALSE.
DELAY_DQS_ENABLE_BY_HALF_CYCLEOptionalFALSEFALSE,TRUEThisisanoptionalfieldanddefaultstoFALSE.
DQS_ENABLE_CTRL_ADD_PHASE_TRANSFER_REGOptionalFALSEFALSE,TRUE,DYNAMICIfsettoTRUE,anegativeedge-triggeredregisterisaddedindatapathfortheclockphasetransfer.
IfsettoFALSE,noregisterisadded.
IfitissettoDYNAMIC,theenaphasetransferreginputdetermineswhethertheregisterisaddedornot.
Youcanusethenegative-edgeregistertoguaranteethesetupandholdtimeforaphasetransfer.
DQS_ENABLE_CTRL_INVERT_PHASEOptionalFALSEFALSE,TRUE,DYNAMICIfsettoTRUE,thephaseoutputisinverted.
IfsettoFALSE,thephaseoutputisnotinverted.
IfitissettoDYNAMIC,thephaseinvertctrlinputdetermineswhethertheinverterisusedornot.
Usetheinvertertoincreasethenumberofavailablephases.
USE_IO_CLOCK_DIVIDER_PHASECTRLINOptionalTRUEFALSE,TRUEIfsettoTRUE,thephasesettingisdeterminedbythephasectrlininput.
IfsettoFALSE,thephasesettingisdeterminedbytheparameter.
IO_CLOCK_DIVIDER_PHASE_SETTINGOptional00.
.
7ThisparameterdeterminesthephaseshiftimplementedbythedelaychainifissettoFALSE;otherwise,ignorethissetting.
TableA–3.
MegafunctionParameterstoConfigureDQSInputPath(Part3of4)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionA–9ClearBoxGeneratorOptionsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTableA–4summarizestheClearBoxparametersfortheALTDQ_DQSmegafunctiontoconfiguretheDQSoutputpath.
IO_CLOCK_DIVIDER_INVERT_PHASEOptionalFALSEFALSE,TRUE,DYNAMICIfsettoTRUE,thephaseoutputisinverted.
IfsettoFALSE,thephaseoutputisnotinverted.
IfitissettoDYNAMIC,thephaseinvertctrlinputdetermineswhethertheinverterisusedornot.
Usetheinvertertoincreasethenumberofavailablephases.
USE_IO_CLOCK_DIVIDER_MASTERINOptionalFALSEFALSE,TRUEIfsettoTRUE,thenthemasterininputisusedtosynchronizethisdividerwithanotherIO_CLOCK_DIVIDER.
IfsettoFALSE,thisdivideroperatesindependently(thismodeismeantforthemasterdividerforagroupofdividers).
IO_CLOCK_DIVIDER_CLK_SOURCEOptionalCoreCore,dqs_bus,inverted_dqs_busIfCore,IO_CLOCK_DIVIDER:clkportontheprimitiveisfedbyio_clock_divider_clkportonthemegafunction.
Ifdqs_bus,IO_CLOCK_DIVIDER:clkportontheprimitiveisfedbydqs_bus_outportonthemegafunction.
Ifinverted_dqs_bus,IO_CLOCK_DIVIDER:clkportontheprimitiveisfedby!
dqs_bus_outportonthemegafunction.
TableA–3.
MegafunctionParameterstoConfigureDQSInputPath(Part4of4)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionTableA–4.
MegafunctionParameterstoConfigureDQSOutputPath(Part1of2)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionUSE_DQS_OUTPUT_DELAY_CHAIN1OptionalFALSEFALSE,TRUEInstantiatesDQS_OUTPUT_DELAY_CHAIN1ifTRUE.
USE_DQS_OUTPUT_DELAY_CHAIN2OptionalFALSEFALSE,TRUEInstantiatesDQS_OUTPUT_DELAY_CHAIN2ifTRUE.
DQS_OUTPUT_REG_MODEOptionalNONENONE,FF,DDIOInstantiatesDQS_OUTPUT_FFifFF.
InstantiatesDQS_OUTPUT_DDIO_OUTifDDIO.
DQS_OUTPUT_REG_POWER_UPOptionalLOWLOW,HIGHThisparameterdescribesthepower-upconditionofallregistersintheprimitive.
A–10AppendixA:ClearBoxGeneratorClearBoxGeneratorOptionsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTableA–5summarizestheClearBoxparametersfortheALTDQ_DQSmegafunctiontoconfiguretheDQSOEpath.
DQS_OUTPUT_REG_ASYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthearesetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThearesetportisrequiredifthisparameterissettoCLEARorPRESET.
DQS_OUTPUT_REG_SYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthesresetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThesresetportisrequiredifthisparameterissettoCLEARorPRESET.
TableA–4.
MegafunctionParameterstoConfigureDQSOutputPath(Part2of2)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionTableA–5.
MegafunctionParameterstoConfigureDQSOEPathParameterNameOptional/RequiredDefaultLegalValuesDescriptionUSE_DQS_OE_DELAY_CHAIN1OptionalFALSEFALSE,TRUEInstantiatesDQS_OE_DELAY_CHAIN1ifTRUEUSE_DQS_OE_DELAY_CHAIN2OptionalFALSEFALSE,TRUEInstantiatesDQS_OE_DELAY_CHAIN2ifTRUEDQS_OE_REG_MODEOptionalNONENONE,FF,DDIOInstantiatesDQS_OE_FFifFFInstantiatesDQS_OE_DDIO_OEifDDIODQS_OE_REG_POWER_UPOptionalLOWLOW,HIGHThisparameterdescribesthepower-upconditionofallregistersintheprimitive.
DQS_OE_REG_ASYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthearesetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThearesetportisrequiredifthisparameterissettoCLEARorPRESET.
DQS_OE_REG_SYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthesresetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThesresetportisrequiredifthisparameterissettoCLEARorPRESET.
A–11ClearBoxGeneratorOptionsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTableA–6summarizestheClearBoxparametersfortheALTDQ_DQSmegafunctiontoconfiguretheOCTpath.
ThepossiblevaluesforareDQS,DQSn,BIDIR_DQandOUTPUT_DQ.
TableA–7summarizestheClearBoxparametersfortheALTDQ_DQSmegafunctiontoconfiguretheDQinputpath.
ThepossiblevaluesforareBIDIR_DQandINPUT_DQ.
TableA–6.
MegafunctionParameterstoConfigureOCTPathParameterNamerOptional/RequiredDefaultLegalValuesMappingtoSub-BlocksUSE_OCT_DELAY_CHAIN1OptionalFALSEFALSE,TRUEInstantiates_OCT_DELAY_CHAIN1ifTRUEUSE_OCT_DELAY_CHAIN2OptionalFALSEFALSE,TRUEInstantiates_OCT_DELAY_CHAIN2ifTRUEOCT_REG_MODEOptionalNONENONE,FF,DDIOInstantiates_OCT_FFifFFInstantiates_OCT_DDIO_OEifDDIOTableA–7.
MegafunctionParameterstoConfigureDQInputPath(Part1of3)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionUSE_DQ_INPUT_DELAY_CHAINOptionalFALSEFALSE,TRUEInstantiates_INPUT_DELAY_CHAINifTRUEDQ_INPUT_REG_MODEOptionalNONENONE,FF,DDIOInstantiates_INPUT_FFifFFInstantiates_DDIO_INifDDIODQ_INPUT_REG_POWER_UPOptionalLOWLOW,HIGHThisparameterdescribesthepower-upconditionofallregistersintheprimitive.
DQ_INPUT_REG_ASYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthearesetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThearesetportisrequiredifthisparameterissettoCLEARorPRESET.
DQ_INPUT_REG_SYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthesresetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThesresetportisrequiredifthisparameterissettoCLEARorPRESET.
A–12AppendixA:ClearBoxGeneratorClearBoxGeneratorOptionsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationDQ_INPUT_REG_CLK_SOURCEOptionaldqs_busdqs_bus,CoreIfCore,_INPUT_FF:clk/_DDIO_IN:clkportontheprimitiveisfedbydq_input_reg_clkportonthemegafunctionIfdqs_bus,_INPUT_FF:clk/_DDIO_IN:clkportontheprimitiveisfedbydqs_bus_outportonthemegafunctionDQ_INPUT_REG_CLK_USE_CLKNOptionalFALSEFALSE,TRUEIfTRUE,_DDIO_IN:clkportontheprimitiveisfedbydqs_bus_outportonthemegafunctionand_DDIO_IN:clknportontheprimitiveisfedbydqsn_bus_outportonthemegafunctionUSE_DQ_IPAOptionalFALSEFALSE,TRUEInstantiates_IPA_HIGH/_IPA_LOWifTRUEUSE_DQ_IPA_PHASECTRLINOptionalFALSEFALSE,TRUE_IPA_HIGH.
use_phasectrlinportontheprimitive_IPA_LOW.
use_phasectrlinportontheprimitiveDQ_IPA_PHASE_SETTINGOptional00.
.
7_IPA_HIGH.
phase_settingportontheprimitive_IPA_LOW.
phase_settingportontheprimitiveDQ_IPA_ADD_INPUT_CYCLE_DELAYOptionalFALSEFALSE,TRUE,DYNAMIC_IPA_HIGH.
add_input_cycle_delayportontheprimitive_IPA_LOW.
add_input_cycle_delayportontheprimitiveDQ_IPA_BYPASS_OUTPUT_REGISTEROptionalFALSEFALSE,TRUE_IPA_HIGH.
bypass_output_registerportontheprimitive_IPA_LOW.
bypass_output_registerportontheprimitiveDQ_IPA_ADD_PHASE_TRANSFER_REGOptionalFALSEFALSE,TRUE,DYNAMIC_IPA_HIGH.
add_phase_transfer_regportontheprimitive_IPA_LOW.
add_phase_transfer_regportontheprimitiveTableA–7.
MegafunctionParameterstoConfigureDQInputPath(Part2of3)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionA–13ClearBoxGeneratorOptionsFebruary2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideTableA–8summarizestheClearBoxparametersfortheALTDQ_DQSmegafunctiontoconfiguretheDQoutputpath.
ThepossiblevaluesforareBIDIR_DQandOUTPUT_DQ.
DQ_IPA_INVERT_PHASEOptionalOFALSEFALSE,TRUE,DYNAMIC_IPA_HIGH.
invert_phaseportontheprimitive_IPA_LOW.
invert_phaseportontheprimitiveDQ_HALF_RATE_USE_DATAOUTBYPASSOptionalFALSEFALSE,TRUE_HALF_RATE_INPUT.
use_dataoutbypassportontheprimitiveTableA–7.
MegafunctionParameterstoConfigureDQInputPath(Part3of3)ParameterNameOptional/RequiredDefaultLegalValuesDescriptionTableA–8.
MegafunctionParameterstoConfigureDQOutputPathParameterNameOptional/RequiredDefaultLegalValuesDescriptionUSE_DQ_OUTPUT_DELAY_CHAIN1OptionalFALSEFALSE,TRUEInstantiates_OUTPUT_DELAY_CHAIN1ifTRUEUSE_DQ_OUTPUT_DELAY_CHAIN2OptionalFALSEFALSE,TRUEInstantiates_OUTPUT_DELAY_CHAIN2ifTRUEDQ_OUTPUT_REG_MODEOptionalNONENONE,FF,DDIOInstantiatesportontheprimitiveifFFInstantiates_OUTPUT_DDIO_OUTifDDIODQ_OUTPUT_REG_POWER_UPOptionalLOWLOW,HIGHThisparameterdescribesthepower-upconditionofallregistersintheprimitive.
DQ_OUTPUT_REG_ASYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthearesetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThearesetportisrequiredifthisparameterissettoCLEARorPRESET.
DQ_OUTPUT_REG_SYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthesresetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThesresetportisrequiredifthisparameterissettoCLEARorPRESET.
A–14AppendixA:ClearBoxGeneratorClearBoxGeneratorOptionsALTDLLandALTDQ_DQSMegafunctionsUserGuideFebruary2012AlteraCorporationTableA–9summarizestheClearBoxparametersfortheALTDQ_DQSmegafunctiontoconfiguretheDQOEpath.
ThepossiblevaluesforareBIDIR_DQandOUTPUT_DQ.
TableA–9.
MegafunctionParameterstoConfigureDQOEPathParameterNameOptional/RequiredDefaultLegalValuesDescriptionUSE_DQ_OE_DELAY_CHAIN1OptionalFALSEFALSE,TRUEInstantiates_OE_DELAY_CHAIN1ifTRUEUSE_DQ_OE_DELAY_CHAIN2OptionalFALSEFALSE,TRUEInstantiates_OE_DELAY_CHAIN2ifTRUEDQ_OE_REG_MODEOptionalNONENONE,FF,DDIOInstantiates_OE_FFifFFInstantiates_OE_DDIO_OEifDDIODQ_OE_REG_POWER_UPOptionalLOWLOW,HIGHThisparameterdescribesthepower-upconditionofallregistersintheprimitive.
DQ_OE_REG_ASYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthearesetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThearesetportisrequiredifthisparameterissettoCLEARorPRESET.
DQ_OE_REG_SYNC_MODEOptionalNONECLEAR,PRESET,NONEThisparameterdeterminesifthesresetportclears,presets,orhasnoeffectontheDDIOregister(s).
ThesresetportisrequiredifthisparameterissettoCLEARorPRESET.
February2012AlteraCorporationALTDLLandALTDQ_DQSMegafunctionsUserGuideAdditionalInformationRevisionHistoryThefollowingtableliststherevisionhistoryforthisuserguide.
HowtoContactAlteraForthemostup-to-dateinformationaboutAlteraproducts,refertothefollowingtable.
DateVersionChangesMadeFebruary2012v.
5.
0Updateinputfrequency.
May2010v4.
0UpdatedtheALTDLLandALTDQ_DQSMegafunctionsUserGuide.
AddedthenewALTDLLandALTDQ_DQSparametereditoroptions.
AddedAppendixforclearboxGenerator.
Addednewdesignexample.
Removedrepetitiveandredundantinformation.
September2009v3.
0UpdatedandreorganisedChapter1andChapter2.
December2008v2.
0Added:HardCopyIIIin"Features"onpage1–2Addedfull-ratemodeandhalf-ratemodetermsanddescriptionsinFigure1–3onpage1–9Lastsentencein"Step1:UnderstandtheAvailableExternalMemoryDedicatedCircuitryinDevices"onpage1–5"ALTDLLFeatures"onpage1–9Note(2),(3),(4)inFigure1–3onpage1–6AddedMegafunctionPortsandParameterstablesin"AbouttheseMegafunctions"AddedSub-BlocksParametersandPortsin"AbouttheseMegafunctions"AddedAdvancedOptionstablesin"GettingStarted"Removedfiguresin"GettingStarted"Addednewtablesin"Specifications"Added"Primitives"onpage1–51July2008v1.
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