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cnZHCSBO5–SEPTEMBER2013低低偏偏移移,,1至至5差差分分3.
3V低低电电压压正正射射极极耦耦合合逻逻辑辑(LVPECL)扇扇出出缓缓冲冲器器查查询询样样品品:LMK007251特特性性应应用用范范围围5个个3.
3V差差分分LVPECL输输出出无无线线和和有有线线基基础础设设施施–附附加加抖抖动动::312.
5MHz时时为为43fsRMS((典典型型网网络络和和数数据据通通信信值值))服服务务器器和和计计算算–噪噪声声基基底底((≥1MHz偏偏移移))::312.
5MHz时时为为-医医疗疗成成像像158dBc/Hz((典典型型值值))便便携携式式测测试试和和测测量量–输输出出频频率率::650MHz((最最大大值值))高高端端A/V–输输出出偏偏移移::35ps((最最大大值值))–部部件件间间偏偏移移::100ps((最最大大值值))说说明明–传传播播延延迟迟::0.
37ns((最最大大值值))LMK00725是一款低偏移、高性能时钟扇出缓冲器,两两个个差差分分输输入入对对((可可由由引引脚脚选选择择))此缓冲器能够从可接受差分或单端输入的两个输入中的–CLKx,,nCLK输输入入对对接接受受LVPECL,,低低压压差差分分一个分发多达5个3.
3VLVPECL输出.
时钟使能输信信号号(LVDS),,主主机机时时钟钟信信号号电电平平(HCSL),,短短入在内部同步,以便在时钟使能引脚被置为有效或置为截截线线串串联联端端接接逻逻辑辑(SSTL),,低低压压高高速速收收发发器器逻逻无效时消除输出上的欠幅脉冲或毛刺脉冲.
低附加抖辑辑(LVHSTL)或或单单端端信信号号动和相位噪底,以及可靠输出和部件间偏移特性使得同同步步时时钟钟启启用用LMK00725成为对高性能和可重复性有严格要求的应电电源源::3.
3V±5%用的理想选择.
封封装装::20引引线线薄薄型型小小尺尺寸寸封封装装(TSSOP)工工业业温温度度范范围围::-40C至至85C与与ICS85304-01引引脚脚兼兼容容,,具具有有更更低低附附加加抖抖动动和和更更宽宽温温度度范范围围FUNCTIONALBLOCKDIAGRAM(1)RPU=51kΩpullup,RPD=51kΩpulldownFigure1.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
ProductionprocessingdoesnotEnglishDataSheet:SNAS625necessarilyincludetestingofallparameters.
LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
PINOUTDIAGRAMFigure2.
Table1.
PINDESCRIPTIONS(1)(2)NO.
NAMETYPE(1)DESCRIPTION1,2Q0,nQ0OLVPECLoutputpair03,4Q1,nQ1OLVPECLoutputpair15,6Q2,nQ2OLVPECLoutputpair27,8Q3,nQ3OLVPECLoutputpair39,10Q4,nQ4OLVPECLoutputpair411,18,20VCCPWRPowersupplypinsClockselectinput.
LVCMOS/TTLcompatible.
12CLK_SELI,RPD0=SelectCLK0,nCLK01=SelectCLK1,nCLK113CLK0I,RPDNon-invertingdifferentialclockinput0.
14nCLK0I,RPUInvertingdifferentialclockinput0.
15VEEPWRNegativesupplypin16CLK1I,RPDNon-invertingdifferentialclockinput1.
17nCLK1I,RPUInvertingdifferentialclockinput1.
Synchronousclockenableinput.
LVCMOS/TTLcompatible.
19CLK_ENI,RPU0=Qxoutputsareforcedlow,nQxoutputsareforcedhigh.
1=Clockoutputsareenabledandfollowclockinput.
(1)G=Ground,I=Input,O=Output,P=Power,RPU=51kΩpullup,RPD=51kΩpulldown(2)PleaserefertoRecommendationsforUnusedInputandOutputPins,ifapplicable.
2Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013ABSOLUTEMAXIMUMRATINGS(1)(2)Overoperatingfree-airtemperaturerange(unlessotherwisenoted)SYMBOLPARAMETERMINTYPMAXUNITVCCSupplyVoltage-0.
33.
6VVINInputVoltageRange-0.
3VCC+0.
3VTSTGStorageTemperatureRange-65150°CTJJunctionTemperature150°CHumanBodyModel(HBM)2000ElectrostaticESDMachineModel(MM)150VDischargeChargedDeviceModel(CDM)750(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditionsisnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
THERMALCHARACTERISTICSOveroperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERθJAUNITPackageThermalImpedance,JunctiontoAir(0LFPM)107.
2°C/WRECOMMENDEDOPERATINGCONDITIONSOveroperatingfree-airtemperaturerange(unlessotherwisenoted)SYMBOLPARAMETERTESTCONDITIONSMINTYPMAXUNITVCCSupplyVoltageVEE=GND3.
1353.
33.
465IOUTOutputCurrent30mATAAmbientTemperature-4085°CTJJunctionTemperature125°CPOWERSUPPLYCHARACTERISTICSOveroperatingfree-airtemperaturerange(unlessotherwisenoted)SYMBOLPARAMETERTESTCONDITIONSMINTYPMAXUNITPowerSupplyCurrentIEE5260mAthroughVEELVCMOS/TTLDCCHARACTERISTICSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)SYMBOLPARAMETERTESTCONDITIONSMINTYPMAXUNITVIHInputHighVoltage2VCC+0.
3VVILInputLowVoltageVEE–0.
30.
4VVCC=VIN=3.
465VIIHInputHighCurrentCLK_EN5ACLK_SEL150VCC=3.
465V,VIN=0VIILInputLowCurrentCLK_EN-150ACLK_SEL-5CINInputCapacitance1pFInputPulluporPulldown51RINkΩResistanceCopyright2013,TexasInstrumentsIncorporated3LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnDIFFERENTIALINPUTDCCHARACTERISTICSOveroperatingfree-airtemperaturerange(unlessotherwisenoted)SYMBOLPARAMETERTESTCONDITIONSMINTYPMAXUNITDifferentialInputVoltageVID0.
151.
3VSwing(VIH-VIL)(1)(2)InputCommonModeVICM0.
5VCC–0.
85VVoltage(1)(2)(3)VCC=VIN=3.
465VIIHInputHighCurrent(4)nCLKx5ACLKx150VCC=3.
465V,VIN=0VIILInputLowCurrent(4)nCLKx-150ACLKx-5(1)VILshouldnotbelessthan-0.
3V(2)SeeFigure22(3)InputcommonmodevoltageisdefinedasVIH(4)ForIIHandIILmeasurementsonCLKx(ornCLKx),caremustbetakentocomplywithVIDandVICMspecificationsusingtheappropriatebiasonnCLKx(orCLKx)LVPECLOUTPUTCHARACTERISTICSOverrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted),outputsterminatedwith50ΩtoVCC–2V.
AllACparametersmeasuredat500MHzunlessotherwisenoted.
SYMBOLPARAMETERTESTCONDITIONSMINTYPMAXUNITVOHOutputHighVoltageDCmeasurementVCC–1.
4VCC–0.
9VVOLOutputLowVoltageDCmeasurementVCC–2.
0VCC–1.
6VOutputVoltageSwingVODDCmeasurement0.
5750.
85V(VOH-VOL)fOUTOutputFrequency(1)650MHztPDPropagationDelay(1)(2)f≤650MHz0.
170.
250.
37nstSK(O)OutputSkew(1)(3)(4)35pstSK(PP)Part-to-PartSkew(1)(4)(5)100pstR/tFOutputRise/FallTime(1)20%to80%,f=50MHz100200psf=156.
25MHz,Inputslewrate≥3V/ns,10KHz75to20MHzintegrationbandJADDAdditiveJitter(6)fsRMSf=312.
5MHz,Inputslewrate≥3V/ns,10kHz43to20MHzintegrationband(1)Parameterisspecifiedbycharacterization.
Nottestedinproduction.
(2)Measuredfromthedifferentialinputcrossingpointtothedifferentialoutputcrossingpoint.
(3)Definedasskewbetweenoutputsatthesamesupplyvoltageandwithequalloadingconditions.
Measuredattheoutputdifferentialcrossingpoints.
(4)ParameterisdefinedinaccordancewithJEDECStandard65.
(5)Calculationforpart-to-partskewisthedifferencebetweenthefastestandslowesttPDacrossmultipledevices,operatingatthesamesupplyvoltage,samefrequency,sametemperature,withequalloadconditions,andusingthesametypeofinputsoneachdevice.
Measuredattheoutputdifferentialcrossingpoints.
(6)BufferAdditiveJitter:JADD=SQRT(JSYSTEM-JSOURCE),whereJSYSTEMistheRMSjitterofthesystemoutput(source+buffer)andJSOURCEistheRMSjitteroftheinputsource,andsystemoutputnoiseisnotcorrelatedtotheinputsourcenoise.
Additivejittershouldbeconsideredonlywhentheinputsourcenoiseflooris3dBorbetterthanthebuffernoisefloor(NF).
Thisisusuallythecaseforhigh-qualityultra-low-noiseoscillators.
PleaserefertoSystem-LevelPhaseNoiseandAdditiveJitterMeasurementforinputsourceandmeasurementdetails.
4Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013LVPECLOUTPUTCHARACTERISTICS(continued)Overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted),outputsterminatedwith50ΩtoVCC–2V.
AllACparametersmeasuredat500MHzunlessotherwisenoted.
SYMBOLPARAMETERTESTCONDITIONSMINTYPMAXUNITf=156.
25MHz,Inputslewrate≥3V/ns,10kHzto20MHzintegrationband10kHzoffset-145dBc/Hz100kHzoffset-1531MHzoffset-15810MHzoffset-15920MHzoffset-159PNFLOORPhaseNoiseFloor(7)f=312.
5MHz,Inputslewrate≥3V/ns,10kHzto20MHzintegrationband10kHzoffset-149dBc/Hz100kHzoffset-1541MHzoffset-15610MHzoffset-15820MHzoffset-158ODCOutputDutyCycle(8)50%InputDutyCycle485052%PowerSupplyf=100MHz,VCCripple=PSRR-80dBcRippleRejection(9)100mVp-p@1MHz(7)BufferPhaseNoiseFloor:PNFLOOR(dBc/Hz)=10*log10[10^(PNTOTAL/10)–10^(PNSOURCE/10)],wherePNTOTAListhephasenoisefloorofthesystemoutput(source+buffer)andPNSOURCEisthephasenoiseflooroftheinputsource.
BufferPhaseNoiseFloorshouldbeconsideredonlywhentheinputsourcenoiseflooris3dBorbetterthanthebuffernoisefloor(PNFLOOR).
Thisisusuallythecaseforhigh-qualityultra-low-noiseoscillators.
PleaserefertoSystem-LevelPhaseNoiseandAdditiveJitterMeasurementforinputsourceandmeasurementdetails.
(8)Parameterisspecifiedbycharacterization.
Nottestedinproduction.
(9)Powersupplyripplerejection,orPSRR,isdefinedasthesingle-sidebandphasespurlevel(indBc)modulatedontotheclockoutputwhenasingle-tonesinusoidalsignal(ripple)isinjectedontotheVCCsupply.
Assumingnoamplitudemodulationeffectsandsmallindexmodulation,thepeak-to-peakdeterministicjitter(DJ)canbecalculatedusingthemeasuredsingle-sidebandphasespurlevel(PSRR)asfollows:DJ(psp-p)=[(2x10(PSRR/20))/(πxfCLK)]x1E12.
Copyright2013,TexasInstrumentsIncorporated5LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnTYPICALCHARACTERISTICSUnlessotherwisenoted:TA=25C,VCC=3.
3V,Inputslewrate≥3V/ns,10kHzto20MHzintegrationbandFigure3.
OutputSwing,VOD(V)Figure4.
AdditiveJittervsvsFrequency(MHz)InputSlewRateFigure5.
AdditiveJitterFigure6.
PhaseNoiseFloor@10MHzoffsetvsvsInputSlewRate,fCLK=156.
25MHzInputSlewRateFigure7.
PhaseNoiseFloor@10MHzoffsetvsInputSlewRate,fCLK=156.
25MHz6Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013FUNCTIONALDESCRIPTIONSCONTROLINPUTFUNCTIONOveroperatingfree-airtemperaturerange(unlessotherwisenoted)Table2.
InputsOutputsCLK_ENCLK_SELSelectedSourceQxnQx00CLK0,nCLK0Disabled;LOWDisabled;HIGH01CLK1,nCLK1Disabled;LOWDisabled;HIGH10CLK0,nCLK0EnabledEnabled11CLK1,nCLK1EnabledEnabledCLOCKENABLETIMINGAfterCLK_ENswitches,theclockoutputsaredisabledorenabledfollowingarisingandfallinginputclockedgeasshowninFigure8.
Intheactivemode,theoutputstatesareafunctionoftheCLKx,nCLKxinputsasdescribedinCLOCKINPUTFUNCTION.
Figure8.
ClockEnableTimingDiagramCLOCKINPUTFUNCTIONOveroperatingfree-airtemperaturerange(unlessotherwisenoted)Table3.
InputsOutputsInputtoOutputPolarityModeCLK0orCLK1nCLK0ornCLK1QxnQxDifferentialto01LOWHIGHNon-invertingDifferentialDifferentialto10HIGHLOWNon-invertingDifferentialSingle-Endedto0Biased(1)LOWHIGHNon-invertingDifferentialSingle-Endedto1Biased(1)HIGHLOWNon-invertingDifferentialSingle-EndedtoBiased(1)0HIGHLOWInvertingDifferentialSingle-EndedtoBiased(1)1LOWHIGHInvertingDifferential(1)RefertoInputDCConfigurationDuringDeviceTestCopyright2013,TexasInstrumentsIncorporated7LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnTESTLOADCONFIGURATIONFigure9.
OutputDCConfiguration;TestLoadCircuit8Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013INPUTCLOCKINTERFACECIRCUITSFigure10.
Single-Ended/LVCMOSInputDCConfigurationDuringDeviceTestFigure11.
LVPECLInputConfigurationDuringDeviceTestFigure12.
LVPECLInputConfigurationDuringDeviceTestCopyright2013,TexasInstrumentsIncorporated9LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnFigure13.
HCSLInputConfigurationDuringDeviceTestFigure14.
LVDSInputConfigurationDuringDeviceTestFigure15.
SSTLInputConfigurationDuringDeviceTest10Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013OUTPUTCLOCKINTERFACECIRCUITSFigure16.
LVPECLOutputDCConfiguration:TypicalApplicationLoadFigure17.
LVPECLOutputDCConfiguration:TypicalApplicationLoad(1)R-biascanrangefrom120Ωto240Ω,but180Ωisequivalenttoloadingoutputswith50ΩtoVCC-2V.
Figure18.
LVPECLOutputACConfiguration:TypicalApplicationLoadCopyright2013,TexasInstrumentsIncorporated11LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnAPPLICATIONINFORMATIONApplicationBlockDiagramExamplesFigure19.
10-GigabitEthernetPHYClockFanoutwithLVPECLOutputACConfigurationFigure20.
InterfacingLVPECLOutputstoHCSLReceiverInputs12Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013InputDetailFigure21.
ClockInputComponentsParameterMeasurementInformationNOTE:VCM=VICM–VID/2=(VIH+VIL)/2Figure22.
DifferentialInputLevelFigure23.
OutputVoltage,andRiseandFallTimesFigure24.
DifferentialandSingle-EndedOutputSkewandPropagationDelayCopyright2013,TexasInstrumentsIncorporated13LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnRecommendationsforUnusedInputandOutputPinsCLK_SELandCLK_EN:Theseinputshaveinternalpull-up(RPU)orpull-down(RPD)accordingtoFigure1andcanbeleftfloatingifunused.
ThefloatingstateforCLK_SELischannel0selected,andthedefaultforCLK-ENisnormaloutput.
CLK/nCLKinputs:SeeFigure21fortheinternalconnections.
Whenusingsingleendedinput,takenoteoftheinternalpull-upandpull-downtomakesuretheunusedinputisproperlybiased.
Forsingleendedinput,theFigure10arrangementisrecommended.
Outputs:Unusedoutputscanbeleftfloatingorterminated.
Ifleftfloating,itisrecommendedtonotattachanytracestotheoutputpins.
InputSlewRateConsiderationsLMK00725employshigh-speedandlow-latencycircuittopology,allowingthedevicetoachieveultra-lowadditivejitter/phasenoiseandhigh-frequencyoperation.
Totakeadvantageofthesebenefitsinthesystemapplication,itisoptimalfortheinputsignaltohaveahighslewrateof3V/nsorgreater.
Drivingtheinputwithaslowerslewratecandegradetheadditivejitterandnoisefloorperformance.
Forthisreason,adifferentialsignalinputisrecommendedoversingle-endedbecauseittypicallyprovideshigherslewrateandcommon-mode-rejection.
Refertothe"AdditiveRMSJittervs.
InputSlewRate"plotsintheTYPICALCHARACTERISTICSsection.
Also,usinganinputsignalwithveryslowinputslewrate,suchaslessthan0.
05V/ns,hasthetendencytocauseoutputswitchingnoisetofeed-backtotheinputstageandcausetheoutputtochatter.
Thisisespeciallytruewhendrivingeitherinputinsingle-endedfashionwithaveryslowslewrate,suchasasine-waveinputsignal.
System-LevelPhaseNoiseandAdditiveJitterMeasurementForhigh-performancedevices,limitationsoftheequipmentinfluencephase-noisemeasurements.
Thenoiseflooroftheequipmentisoftenhigherthanthenoisefloorofthedevice.
Therealnoisefloorofthedeviceisprobablylower.
Itisimportanttounderstandthatsystem-levelphasenoisemeasuredattheDUToutputisinfluencedbytheinputsourceandthemeasurementequipment.
ForFigure25andFigure26system-levelphasenoiseplots,aRohde&SchwarzSMA100Alow-noisesignalgeneratorwascascadedwithanAgilent70429AK95single-endedtodifferentialconverterblockwithultra-lowphasenoiseandfastedgeslewrate(>3V/ns)toprovideaverylow-noiseclockinputsourcetotheLMK00725.
AnAgilentE5052sourcesignalanalyzerwithultra-lowmeasurementnoisefloorwasusedtomeasurethephasenoiseoftheinputsource(SMA100A+70429AK95)andsystemoutput(inputsource+LMK00725).
Theinputsourcephasenoiseisshownbythelightyellowtrace,andthesystemoutputphasenoiseisshownbythedarkyellowtrace.
Theadditivephasenoiseornoisefloorofthebuffer(PNFLOOR)canbecomputedasfollows:PNFLOOR(dBc/Hz)=10*log10[10^(PNSYSTEM/10)–10^(PNSOURCE/10)]wherePNSYSTEMisthephasenoiseofthesystemoutput(source+buffer)PNSOURCEisthephasenoiseoftheinputsource(1)spaceTheadditivejitterofthebuffer(JADD)canbecomputedasfollows:JADD=SQRT(JSYSTEM2–JSOURCE2),whereJSYSTEMistheRMSjitterofthesystemoutput(source+buffer),integratedfrom10kHzto20MHzJSOURCEistheRMSjitteroftheinputsource,integratedfrom10kHzto20MHz(2)14Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013Figure25.
156.
25MHzInputPhaseNoise(66fsrms,LightYellow)andOutputPhaseNoise(92.
1fsrms,DarkYellow).
AdditiveJitter=65fsrms(10kHzto20MHz)@4V/nsInputSlewRateFigure26.
312.
5MHzInputPhaseNoise(43fsrms,LightYellow)andOutputPhaseNoise(55.
7fsrms,DarkYellow).
AdditiveJitter=36fsrms(10kHzto20MHz)@6V/nsInputSlewRateCopyright2013,TexasInstrumentsIncorporated15LMK00725ZHCSBO5–SEPTEMBER2013www.
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cnPowerConsiderationsThepowerdissipationoftheLMK00725consistsofthequiescentpowerandloadrelatedpower.
Hereistheexpressionforthetotalpowerwhichusesthevaluesderivedfor"QuiescentPower"and"LoadPower"furtherbelow:PTotal=PQ(worstcase)+PL=208mW+30.
2mWx(#ofterminatedoutputs)(3)Forall5outputsterminated:PTotal=208mW+27mWx5=343mW(4)QuiescentPower:PQ=VCCxIEE=3.
3Vx60mA=198mW(5)Consideringa5%toleranceonVcc:PQ(worstcase)=198mWx1.
05=208mW(6)LoadPower:Assuming50%outputdutycycleand50Ωloadfromeachoutput(QandnQ)toVcc-2V(or1.
3V)andoutputvoltagelevelsof1.
1Vand1.
8VbelowVccforVOHandVOLrespectively:PL/output_pair=P_high+P_low={1.
1Vx[Vcc-1.
1V-(Vcc-2V)]/50Ω)}+{1.
8Vx[Vcc-1.
8V-(Vcc-2V)]/50Ω)}=20mW+7mW=27mW(7)NOTEFordimensioningthepowersupply,considerthetotalpowerconsumption.
Thetotalpowerconsumptionisthesumofdevicepowerconsumptionandthepowerconsumptionoftheload.
ThermalManagementPowerconsumptionoftheLMK00725canbehighenoughtorequireattentiontothermalmanagement.
Forreliabilityandperformancereasons,limitthedietemperaturetoamaximumof125°C.
Thatis,asanestimate,TA(ambienttemperature)plusdevicepowerconsumptiontimesθJAshouldnotexceed125°C.
AssumingtheconditionsinthePowerConsiderationssectionandoperatingatanambienttemperatureof70°Cwithalloutputsloaded,hereisanestimateoftheLMK00725junctiontemperature:TJ=TA+PTotalxθJA=70°C+343mWx107.
2°C/W=70°C+37°C=107°C(8)Herearesomerecommendationsforimprovingheatflowawayfromthedie:Usemulti-layerboardsSpecifyahighercopperthicknessfortheboardIncreasethenumberofviasfromthetoplevelgroundplaneunderandaroundthedevicetointernallayersandtothebottomlayerwithasmuchcopperareaflowoneachlevelaspossibleApplyairflowLeaveunusedoutputsfloating16Copyright2013,TexasInstrumentsIncorporatedLMK00725www.
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cnZHCSBO5–SEPTEMBER2013Power-SupplyFilteringHigh-performanceclockbuffersaresensitivetonoiseonthepowersupply,whichcandramaticallyincreasetheadditivejitterofthebuffer.
Thus,itisessentialtoreducenoisefromthesystempowersupply,especiallywhenjitterorphasenoiseiscriticaltoapplications.
Useoffiltercapacitorseliminatesthelow-frequencynoisefrompowersupply,wherethebypasscapacitorsprovidetheverylow-impedancepathforhigh-frequencynoiseandguardthepower-supplysystemagainstinducedfluctuations.
Thebypasscapacitorsalsoprovideinstantaneouscurrentsurgesasrequiredbythedevice,andshouldhavelowESR.
Tousethebypasscapacitorsproperly,placethemveryclosetothepowersupplypinsandlayouttraceswithshortloopstominimizeinductance.
TIrecommendsaddingasmanyhigh-frequencybypasscapacitors(suchas0.
1-F,forexample)astherearesupplypinsinthepackage.
Itisrecommended,butnotrequired,toinsertaferritebeadbetweentheboardpowersupplyandthechippowersupplytoisolatethehigh-frequencyswitchingnoisesgeneratedbytheclockdriver,therebypreventingthemfromleakingintotheboardsupply.
ChoosinganappropriateferritebeadwithverylowDCresistanceisimportant,becauseitisimperativetoprovideadequateisolationbetweentheboardsupplyandthechipsupply.
Itisalsoimperativetomaintainavoltageatthesupplypinsthatisgreaterthantheminimumvoltagerequiredforproperoperation.
Figure27.
Power-SupplyDecouplingCopyright2013,TexasInstrumentsIncorporated17PACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesLMK00725PWACTIVETSSOPPW2073RoHS&GreenSNLevel-1-260C-UNLIM-40to85LMK00725LMK00725PWRACTIVETSSOPPW202500RoHS&GreenSNLevel-1-260C-UNLIM-40to85LMK00725(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
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