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CustomSiliconSolutions,Inc.
20091Version1.
1,May2009cssCustomSiliconSolutions,Inc.
CSS555CMicropowerTimer(withInternalTimingCapacitor)GENERALPARTDESCRIPTIONTheCSS555Cisamicropowerversionofthepopular555timerIC.
Itfeaturesanoperatingcurrentunder5Aandaminimumsupplyvoltageof1.
2V,makingitidealforbattery-operatedapplications.
Asix-decadeprogrammablecounterisincludedtoallowgenerationoflongtimingdelays.
ConfigurationdataforthecounterisheldinEEPROMtomaintainthestandardpincountofeight.
Theanalogcircuitsaretemperaturecompensatedtoprovideexcellentstabilityoverawideambienttemperaturerange.
Asimplefour-wireinterfaceprovidesRead/WriteaccesstotheEEPROM.
TheCSS555Cdeviceincludesaninternalprecisiontimingcapacitor(CTI).
Itsvalueistrimmedto100pF±1%.
KeyFeaturesPinConfigurationLowestpower555timer(by>10X)!
ActivemodecurrentCSS555C-ID8pinplasticDIPPulseWidthModulationCSS555C-IS8pinplasticSOICLowCost,HighReliabilityApplicationsSeepage9formoredetailsandoptions.
CustomSiliconSolutionsInc.
17951SkyParkCircle,SuiteFIrvine,CA92614(949)797-9220FAX:(949)797-9225www.
CustomSiliconSolutions.
comGNDTRIGGEROUTPUTRESETV+DISCHARGETHRESHOLDCONTROLV87651234PDIPorSOICCSS555CLongPeriodDelayGeneratorVDDRARBTriggerOutputResetOperatingconditions:RA=RB=4.
7M,Internalcounter=106(maximum)CINT=100pF,Delay=16.
3minutesAveragepower=7.
5WatVDD=3.
0V12348765CSS555CCustomSiliconSolutions,Inc.
20092Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)BlockDiagramsStandard555TimerConfiguration(Std.
Mode)(Programmablecounterbypassed,Dividersetting=1)Figure3ExtendedPeriodConfiguration(EPMode)(Programmablecounterenabled,Dividersetting≥10)Figure4EEPROMBitAssignmentsCounterConfigurationDividerSetting(Mult)ModeControlBitsFunctionxxxxx0001(Std.
555)xxxx0xxxAstableMode("Don'tCare"ifStd.
555)xxxxx00110xxxx1xxxMonostableMode("Don'tCare"ifStd.
555)xxxxx010100xxx0xxxxMicroPowerxxxxx0111Kxxx1xxxxLowPowerxxxxx10010Kxx0xxxxxStandardVoltage(Triplevels=&VDD)xxxxx101100Kxx1xxxxxLowVoltage(Triplevels=10%&90%VDD)xxxxx1101MBit6Unusedxxxxx1111(Std.
555)Bit71(ReadOnly)Table1ATable1BNote:Fordetailedprogramminginformation,seeApplicationNoteAN555-1(CSS555_App_Note1_Serial_Interface)_+Comp_+CompRSQQResetFlipFlopVDDTriggerOutputControlVoltageThresholdVHVLR1R2R3ResetVSS156482Discharge37R1+R2+R3~6MForVDD>1.
8V,VH=2/3xVDD,VL=1/3xVDDForVDDCSS555CMicropowerTimer(withInternalTimingCapacitor)ELECTRICALSPECIFICATIONSAbsoluteMaximumRatingsSupplyVoltage(VDD)6VVoltageatanyPin-0.
3toVDD+0.
3VTotalCurrentintoVDDPin(Source)50mATotalCurrentoutofGNDPin(Sink)60mAStorageTemperatureRange-65°Cto+140°CNote:Absolutemaximumratingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
DCandACelectricalspecificationsarenotensuredwhenoperatingthedeviceatabsolutemaximumratings.
ElectricalCharacteristicsTemperature=25°C,TestCircuit#1,unlessotherwisespecified(IfVDDCSS555CMicropowerTimer(withInternalTimingCapacitor)ElectricalCharacteristics(cont)Temperature=-40°Cto+85°C,TestCircuit#1,unlessotherwisespecified(IfVDDCSS555CVSSTriggerOutputResetRBNote:CT≡ExternalTimingCapacitorCTI≡InternalTimingCapacitorCTOTAL≡CT+CTICustomSiliconSolutions,Inc.
20095Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)PinDescriptionsPinNumberPinNamePrimaryFunction(NormalMode)SecondaryFunction(EEProgramming)1VSSGround2TRIGGERInitiatestimingcycles(Activelow)SerialClock3OUTPUTTimerOutput(CMOSLevels)SerialDataOut4RESETAsynchronoustimerreset(Activelow)SerialDataIn5CONTROLVUppercomparatorswitchlevelR/Wenable(ActiveifVCTRLCSS555CICmaybeusedinmanyapplicationsasadirectreplacementforthepopular555timer.
Itfeaturesthelowest555operatingcurrentandaminimumsupplyvoltageof1.
2V.
Italsofeaturesaprogrammabledecadecounterforgeneratinglongtimedelays.
AninternalEEPROMstoresthecounterconfiguration:Divideby1(standard555)ordivideby10,100,103,104,105or106.
Theinternalcounterallowslongtimedelaystobegeneratedwithsmallvaluecapacitors.
MonostableOperation(Standard555Mode)ThecircuitinFigure6showsamonostableor"oneshot"configuration.
Asingle,positiveoutputpulseisgeneratedonthefallingedgeoftheTRIGGERinput.
WhenTRIGGERgoeslow,aflip-flopisset,theOUTPUTpinissethighandDISCHARGEallowsthetimingcapacitortochargetowardsVDDviaRA.
WhenVTHreachestheuppercomparatortriplevel,theflip-flopisreset,OUTPUTisforcedlowandDISCHARGEpullsVTHtoGND.
AfterVTHhasdischarged,thecircuitisreadyforthenexttriggerpulse.
TypicalsignalwaveformsareshowninFigure7.
TheRESETinputmustbeheldhigh(inactive)duringthetimingcycle.
IfRESETisbroughtlow,theOUTPUTpinisimmediatelyforcedlowandthecycleisterminated.
Figure6–MonostableCircuit(Std.
Mode)Inthemonostableconfiguration,thedurationofthetimingcycleissimplythetimerequiredtochargethetimingcapacitorfromGNDtotheuppercomparatortriplevel.
ThetriplevelisnominallyVDD.
Atlowsupplyvoltagesitisincreasedto0.
9VDD.
(AnEEPROMbitcontrolsthisselection.
)Thedelaytimeequationsforbothconditionsareprovidedinthefollowingparagraph.
DelayTimeEquations:Forstandardsupplyvoltages(VLOWBit=0)Chargetime(VTH=0VtoVDD)=1.
1xRAxCTotalForlowvoltagemode(VLOWBit=1)Chargetime(VTH=0Vto0.
9VDD)=2.
3xRAxCTotalwhereCTotal=(CInternal+CExternal)or(CTI+CT)Figure7–MonostableWaveforms(Std.
Mode)Figure8providesalog-logselectionchart.
ItshowsthetimedelayforvariouscombinationsofRAandCTotal.
Withthecounterbypassed(Mult=1),timedelaysfrom1usecto1secondareeasilygeneratedwithcapacitorvaluesfrom100pFto1uF.
Forlongtimedelays(ormediumdelaytimesusingsmallcapacitorvalues)the"ExtendedPeriod"configurationshouldbeused.
(Seethenextsection.
)0.
00010.
00100.
01000.
10001.
00000.
010.
101.
0010.
00100.
001000.
00DelayTime(ms)Ctotal=Ct+Cti(uF)Figure8–TimeDelayChartRA=1K10K100KGreen:LowVDDBlue:Std.
VDD10M1MVDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetTriggerOutputResetVTHOptionalTRIGGEROUTPUTVCAP0VVDDRESETMult=1CustomSiliconSolutions,Inc.
20096Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)MonostableOperation(ExtendedPeriodor"EP"Mode)Forlongertimedelays,thecircuitinFigure9usestheinternaldecadecountertoeffectivelymultiplythevalueofthetimingcapacitor.
ThreebitsintheEEPROMselectamultipliervaluefrom10to106.
The555analogblockisconfiguredasafreerunningoscillator,whichistheinputclocktothecounter.
OnthefallingedgeofTRIGGER,the555oscillatorisenabled,OUTPUTissethigh,thedecadecounterisenabledandanewtimingcyclebegins.
Thetimingcycleendswhenthecounterreachestheselectedterminalcount.
WaveformsforanextendeddelaycycleareshowninFigure10.
Figure9–ExtendedPeriodDelayCircuitFigure10–ExtendedPeriodWaveformsIntheExtendedPeriodmonostableconfiguration,thedurationofthetimingcycleistheoscillatorperiodmultipliedbythecountersetting.
The555oscillatorisconfiguredforastableoperation.
(TheinternalTRIGGERsignaltotheoscillatorisinternallytiedtoTHRESHOLD.
SeeFigure4.
)VCAPoscillatesbetween&VDD(or10%&90%iflowvoltagemodeisselected).
Thedelaytimeequationsforbothsupplyconditionsareprovidedinthefollowingparagraph.
ExtendedDelayTimeEquations:Forstandardsupplyvoltages(VLOWBit=0)OscillatorPeriod(tOSC)=0.
695x(RA+2RB)xCTotalTotalDelayTime=CounterSetting(orMult)xtOSCTotalDelayTime=Multx0.
695x(RA+2RB)xCTotalwhereCTotal=CT+CTICT=ExternaltimingcapacitorCTI=Internal100pFtimingcapacitorForlowvoltagemode(VLOWBit=1)OscillatorPeriod(tOSC)=2.
197x(RA+2RB)xCTotalTotalDelayTime=CounterSetting(orMult)xtOSCTotalDelayTime=Multx2.
197x(RA+2RB)xCTotalThechartinFigure11showsnominaldelaytimesformultipliersettingsfrom1to106andresistorvalues(RA+2RB)from1Kto10M.
(Theinternaltimingcapacitor,CTI,equals100pF.
Noexternalcapacitor.
)Theresultingdelaytimescoveraneight-decaderange!
11010010001000010000010000001.
E-021.
E-011.
E+001.
E+011.
E+021.
E+031.
E+041.
E+051.
E+06DelayTime(sec)CounterValueFigure11–ExtendedPeriodDelayChartThecomponentvaluesrequiredforsomecommondelaytimesarelistedinTable5.
Forthiscalculation,thevalueofRAandRBareequal.
Tokeeptheoverallpowerlow,valuesabove1Mwereselected.
DelayMultiplierCTotalValueRA&RB1msec1100pF2.
35M1sec.
1K100pF4.
8M1min.
100K100pF2.
9M1hour1M500pF3.
5M1day1M0.
01uF4.
1M1week1M0.
1uF2.
9MTable5–ExtendedPeriodDelayTableNote:CTotal=CT+CTICT=Externaltimingcapacitor(maybezero)CTI=Internal100pFtimingcapacitorTRIGGEROUTPUTVCAP0VVDDVDDRESETMult=10CTI=100pFRA+2RB=1K10K100K1M10MGreen:LowVDDBlue:Std.
VDDVDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetTriggerOutputResetRBVTHOptionalCustomSiliconSolutions,Inc.
20097Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)AstableOperation(Standard555Mode)ThecircuitinFigure12showstheastableor"freerunningoscillator"configuration.
Ifthecountersettingequalsone,thecounterisbypassedandthedeviceoperateslikeastandard555timer.
WiththeTRIGGERinputtiedtoTHRESHOLD,anewtimingcycleisstartedeachtimeVTHdropsbelowthelowercomparatortriplevel.
Figure12–AstableCircuit(Std.
Mode)ThecapacitorchargestoVDDthrough(RA+RB)anddischargestoVDDthroughRB.
(Asinthemonostablemode,thetriplevelsarechangedto10%&90%forlowsupplyvoltages.
ThisselectionismadeviatheEEPROM.
)ThedutycycleisdeterminedbytheratioofRAandRB.
TypicalsignalwaveformsareshowninFigure13.
TheRESETinputmustbeheldhighfortheoscillatortobeactive.
IfRESETisbroughtlow,theOUTPUTpinisimmediatelyforcedlowandoscillationhalts.
Equationsforthefreerunningoscillatorareprovidedinthefollowingparagraph.
Figure13–AstableWaveforms(Std.
Mode)Note:TheTRIGGERsignalisconnectedtoVTHFreeRunningOscillatorEquations:Forstandardsupplyvoltages(VLOWBit=0)OscillatorPeriod(tOSC)=0.
695x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=1.
44/[(RA+2RB)xCTotal]whereCTotal=CT+CTICT=ExternaltimingcapacitorCTI=Internal100pFtimingcapacitorForlowvoltagemode(VLOWBit=1)OscillatorPeriod(tOSC)=2.
197x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=0.
455/[(RA+2RB)xCTotal]DutyCycle=RB/(RA+2RB)ThechartinFigure14showsnominaloscillatorfrequenciesforresistorvalues(RA+2RB)from1Kto10Mandcapacitorvaluesfrom100pFto1uF.
Theresultingfrequencyrangeextendsfrom1Hzto1MHz.
(Forthischart,thecounterisbypassed;Mult=1.
)0.
00010.
00100.
01000.
10001.
00001101001000100001000001000000Frequency(Hz)Ctotal=Ct+Cti(uF)Figure14–AstableFrequencyChart(Std.
Mode)AstableOperation(ExtendedPeriodor"EP"Mode)ThecircuitinFigure15employstheinternaldecadecountertodividethe555oscillatorfrequencybythemultipliersetting.
Themultipliervalue,10to106,isselectedbytheEEPROM.
The555analogblockisconfiguredasafreerunningoscillator,whichsuppliestheinputclocktothecounter.
TheoscillatorrunswhenRESETishigh(logicone)andTRIGGERislow.
Eachdivideby10stageofthedecadecounterconsistsofadivideby5followedbyadivideby2.
Thisconfigurationprovidesa50%outputdutycyclenomatterwhichmultipliersettingisselected.
WaveformsforthismodeareshowninFigure16.
RA+2RB=10M1M100K10K1KGreen:LowVDDBlue:Std.
VDDOUTPUTVCAP0VVDDVDDRESETMult=1VDDRAOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetOutputResetRBOptionalVTHCustomSiliconSolutions,Inc.
20098Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)Figure15–AstableCircuit(EPMode)Figure16–AstableWaveforms(EPMode)FreeRunningOscillatorEquations:Forstandardsupplyvoltages(VLOWBit=0)OscillatorPeriod(tOSC)=0.
695x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=1.
44/[(RA+2RB)xCTotal]OutputFrequency=fOSC/MultwhereCTotal=CT+CTICT=ExternaltimingcapacitorCTI=Internal100pFtimingcapacitorForlowvoltagemode(VLOWBit=1)OscillatorPeriod(tOSC)=2.
197x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=0.
455/[(RA+2RB)xCTotal]OutputFrequency=fOSC/MultDutyCycle=50%ThechartinFigure17showsnominaloscillatorfrequenciesformultipliersettingsfrom1to106andresistorvalues(RA+2RB)from1Kto10M.
(Theinternaltimingcapacitor,CTI,equals100pF.
Noexternaltimingcapacitor.
)Theresultingfrequenciesrangefromlessthan1Hzto1MHz.
11010010001000010000010000001101001000100001000001000000Frequency(Hz)CounterValueFigure17–AstableFrequencyChart(EPMode)EEPROM(ConfigurationMemory)AninternalEEPROMprovidestwobytesofnonvolatilememorythatstorestheconfigurationinformationandthe100pFcapacitortrimsetting.
Theconfigurationbitscontrolthemultipliersetting(1to106),thepowersetting(microorlow)andthecomparatortriplevels(standardorlowvoltage).
(SeeTables1A&1Bformoredetails.
)ByemployinganinternalEEPROMforconfigurationcontrol,thepincountandpinfunctionsremaincompatiblewithexisting555IC's.
TheEEPROMincludesahighvoltagegenerator.
NospecialsignallevelsarerequiredtoReadorWritetoit.
AccesstotheEEPROMisenabledbyforcingtheCONTROLpintoGND.
(ThispinisnormallyleftopenandaninternalvoltagedividerholdsitatVDD.
)WithCONTROLheldatGND,theTRIGGERandRESETpinsareredefinedtobeSCLK(SerialClock)andSDIN(SerialDataIn).
DatafromtheEEPROMcanbereadattheOUTPUTpin.
Theinterfaceissimpleandstraightforward.
Itcansupportprogrammingindividualunitsordevicesinstalledintheirapplicationcircuit.
AdetaileddescriptionoftheserialinterfaceisprovidedinApplicationNoteAN555-1("CSS555CEEPROMSerialInterface").
Adevelopmentkitisavailableandprovidesbothprogrammingandevaluationcapabilities.
ItusesastandardPCandoneUSBport.
PleasecontactCustomSiliconSolutionsformoreinformation.
ThecoreEEPROMcellisadifferential,floatinggatecircuit.
LikeanSRAM,itfeatureszerostaticcurrent.
Itsoutputdataisvalidwheneverthesupplyvoltageisabove1.
0V.
Ithasexcellentdataretentionandendurancecharacteristics.
Dataretentionisgreaterthan10yearsat85°Canditsendurance(maximumnumberofStorecycles)isgreaterthan100,000cycles.
AtypicalStoreoperationcanbeperformedinlessthan25msec.
TRIGGEROUTPUTVCAP0VVDDVDDRESETMult=10RA+2RB=10M1M100K10K1KCT=100pFGreen:LowVDDBlue:Std.
VDDVDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetTriggerOutputResetRBVTHOptionalCustomSiliconSolutions,Inc.
20099Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)SupplyCurrentConsiderationsTheinternalsupplycurrentusedbytheCSS555Ccanbedividedintothreemaincomponents:1)~1.
8uAconstantcurrent(independentofVDD)2)~6MfromVDDtoGND(0.
5uAatVDD=3V)3)~0.
5uAswitchingcurrentatVDD=3V,FOSC=100KHz(~linearlyproportionaltoVDD&FOSC)Tominimizethesecondcomponent,keepVDDaslowaspossible.
Tominimizetheswitchingcurrent,keepVDD&FOSClow.
(Choosealowermultipliervaluesotheoscillatorfrequencyiswellbelow100KHz.
)TheexternalcurrentisdeterminedbythevaluesofRAandRB.
Theyshouldbeashighaspractical.
(PCBsurfaceleakagetypicallylimitsthevalueto≤10M.
)TheCSS555Chasa"Break-Before-Make"driverfortheOUTPUTsignal.
Thiscircuiteliminatesthelarge"throughcurrent"thatflowsdirectlyfromVDDtoGNDduringeachoutputtransition.
Thissignificantlyreducesthenoiseinjectedintothepowersupply.
Thedischargepathinthemonostableconfigurationisanothersourceoftransientcurrent.
(WhenVTHreachestheuppertrippoint,thecapacitorisveryquicklydischargedtoGND.
)Tominimizethistransientcurrent,simplyaddaresistor(RLIM)inserieswiththeDISCHARGEpin.
(seeFigure18)ThevalueofRLIMmustbelowenoughtoallowthetimingcapacitortocompletelydischargebeforethenexttimingcycle.
AtypicalvalueforRLIMis1Kto10K.
Figure18–MonostablewithRLIMESDProtectionAllinputandoutputpinsincludeprotectiondevicestoguardagainstESDdamage.
AsimplifiedschematicoftheinputprotectioncircuitisshowninFigure19.
Thevoltagelevelsatallpinsshouldbekeptbetween(VSS–0.
3V)and(VDD+0.
3V)topreventforwardbiasingthediodes.
Figure19–InputProtectionCircuitInternalTimingCapacitorTheinternaltimingcapacitorisaPoly/Polystructurewhichhasexcellentstabilityovertemperature(TC~25ppm/°C)andvoltage(VC~250ppm/V).
Itconsistsofafixed75pFcapacitor(CTIB)anda0pFto40pFtrimcapacitor(CTIA).
EightEEPROMbitsstorethetrimsettingwithastepsizeof~0.
16pF.
Thevalueissetatfinalpackagetest,butmaybere-adjustedbytheuser.
(SeeapplicationnoteAN555-1formoredetails.
)Thethirdcapacitor,CS,isthestraycapacitanceduetothepadcell,bondwireandpackageleadframe.
Itistypically5pF.
Figure20–Internal100pFTimingCapacitorOrderingInformationPartNumberPackageDescriptionShippingOptionsCSS555C-ID8pinplasticDIP50units/RailCSS555C-IS8pinplasticSOIC98units/RailCSS555C-ISTR8pinplasticSOIC2500units/Tape&ReelCSS555C_IWDieorTestedWafersContactCSSforoptionsCSS555C_DVKDevelopmentKitN.
A.
Table6–OrderingOptionsAllpackagingoptionsuseleadfreematerials.
Allparttypesareratedforoperationfrom-40°Cto+85°C.
ThedefaultconfigurationstoredinEEPROMis:ConfigurationData=80HEXOperatingMode=Standard555PowerSetting=MicroVoltageSetting=StandardTimingCapacitor=Trimmedto100pFPackagedpartsmaybeorderedwithalternateconfigurationsettings.
Aminimumpurchaseand/orservicechargemayapply.
PleasecontactCSSfordetails.
DevelopmentKitThe"CSS555CDevelopmentKit"isaPCbasedsystemthatallowstheusertoReadandProgramtheinternalEEPROM.
Itincludesaneasytousedialogboxandserialinterface(USBportrequired).
Thecircuitcardincludesplentyofextraterminalssothatmostapplicationscanbebuiltandevaluatedquicklyandeasily.
Formoreinformation,pleaserefertothedevelopmentkit'sinstructionmanual.
VDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetRLIMOptionalVTHVDDInput/OutputPinInputProtectionDiodesToInternalCircuitsCTIA0pF-40pFPoly/PolyCapacitor8EETRIMCTIB75pFCS5pFTHRESHOLDPINCustomSiliconSolutions,Inc.
200910Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)TypicalPerformanceCharacteristicsFigure21SupplyCurrent(MicroPower)Figure22SupplyCurrent(LowPower)Figure23FrequencyDriftvs.
VDDFigure24FrequencyDriftvs.
TemperatureFigure25PropagationDelay(StandardVDD)Figure26PropagationDelay(LowVDD)NormalizedFrequencyDriftvs.
VDD-2.
0-1.
5-1.
0-0.
50.
00.
51.
01.
52.
00.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
05.
56.
0VDD(V)DeltaFreq.
(%)Std.
VDDLowVDDAstableModeCT=1nF;RA,RB=1MegTemperature=25CNormalizedFrequencyDriftvs.
Temperature-2.
0-1.
5-1.
0-0.
50.
00.
51.
01.
52.
0-50-250255075100Temperature(deg.
C)DeltaFreq.
(%)VDD=5.
0VVDD=3.
0VVDD=2.
0VAstableModeCT=10nF;RA,RB=100KPropagationDelayvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
005101520253035TriggerLowLevel(%VDD)PropagationDelay(usec)VDD5V3V2VPowerSettingMicroLowStandardTripLevels(1/3&2/3VDD)PropagationDelayvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
0012345678910TriggerLowLevel(%VDD)PropagationDelay(usec)LowVDDTripLevels(10%&90%)PowerSettingMicroLowVDD3.
0V2.
0V1.
5VIDDvs.
VDD&Temperature02468100.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
05.
56.
0VDD(V)IDD(uA)+125C+85C+25C-40CPowerSetting=MicroIDDvs.
VDD&Temperature0510152025300.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
05.
56.
0VDD(V)IDD(uA)+125C+85C+25C-40CPowerSetting=LowCustomSiliconSolutions,Inc.
200911Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)TypicalPerformanceCharacteristics(continued)Figure27TriggerPulseWidth(Std.
VDD)Figure28TriggerPulseWidth(LowVDD)Figure29OUTPUTVOHvs.
IOHFigure30OUTPUTIOHvs.
TemperatureFigure31OUTPUTVOLvs.
IOLFigure32OUTPUTIOLvs.
TemperatureMinimumTriggerPulseWidthvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
005101520253035TriggerLowLevel(%VDD)PulseWidth(usec)PowerSettingMicroLowStandardTripLevels(1/3&2/3VDD)VDD5.
0V3.
0V2.
0VMinimumTriggerPulseWidthvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
0012345678910TriggerLowLevel(%VDD)PulseWidth(usec)LowVDDTripLevels(10%&90%VDD)PowerSettingMicroLowVDD3.
0V2.
0V1.
5VTimerOUTPUTLowVoltagevs.
SinkCurrent0.
00.
51.
01.
52.
00.
11.
010.
0100.
0OutputSinkCurrent(mA)OutputLowVoltage(V)VDD3.
0VVDD1.
5VVDD5.
0VTimerOUTPUTDriveLowvs.
Temperature012345678910-50-250255075100125Temperature(degreesC)OutputSinkCurrent(mA)VDD=5.
0VVDD=1.
5VVDD=3.
0VIOLmeasuredatVOL=0.
2VTimerOUTPUTDriveHighvs.
Temperature012345678910-50-250255075100125Temperature(degreesC)OutputSourceCurrent(mA)VDD=5.
0VVDD=3.
0VVDD=1.
5VIOHmeasuredatVOH=VDD-0.
2VTimerOUTPUTHighVoltagevs.
SourceCurrent0.
00.
51.
01.
52.
00.
11.
010.
0100.
0OutputSourceCurrent(mA)OutputHighVoltage(VDD-Vout)(V)VDD5.
0VVDD3.
0VVDD1.
5VCustomSiliconSolutions,Inc.
200912Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)TypicalPerformanceCharacteristics(continued)Figure33DISCHARGEVOLvs.
IOLFigure34DISCHARGEIOLvs.
TemperatureDISCHARGELowVoltagevs.
SinkCurrent0.
00.
51.
01.
52.
00.
11.
010.
0100.
0OutputSinkCurrent(mA)OutputLowVoltage(V)VDD5.
0VVDD3.
0VVDD1.
5VDISCHARGEOutputDriveLowvs.
Temperature02468101214161820-50-250255075100125Temperature(degreesC)OutputSinkCurrent(mA)VDD=5.
0VVDD=3.
0VVDD=1.
5VIOLmeasuredatVOL=0.
2VCustomSiliconSolutions,Inc.
200913Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)PACKAGEDRAWINGSPinoutDiagramSOICMechanicalDrawingFigure35Table7PDIPMechanicalDrawingTable8SOICDimensionsInchesMillimetersSymbolMINMAXMINMAXA0.
0530.
0691.
351.
75A10.
0040.
0100.
100.
25B0.
0140.
0190.
350.
49C0.
0070.
0100.
190.
25D0.
1890.
1974.
805.
00E0.
1500.
1573.
804.
00e0.
0501.
27H0.
2280.
2445.
806.
20h0.
0100.
0200.
250.
50L0.
0160.
0500.
401.
27α0°8°0°8°PDIPDimensionsInchesMillimetersSymbolMINMAXMINMAXA10.
015-0.
38-A20.
1280.
1323.
253.
35b0.
0140.
0220.
360.
56b20.
0570.
0681.
451.
73b30.
0320.
0460.
811.
17C0.
0100.
0120.
250.
30D0.
3750.
3859.
539.
78E0.
3000.
3207.
628.
13E10.
2450.
2556.
226.
48e0.
1002.
54eB0.
3300.
3708.
389.
40Q10.
0550.
0801.
402.
03S0.
0250.
0800.
062.
03α3°8°3°8°CSSCSS555C-ISYYWWGEHPin1IndicatoreBAA1DhCα7°TypL0°minCSSCSS555C-IDYYWWGE1eA2bA1Db2b3SQ1CαeBEGNDTRIGGEROUTPUTRESETVDDDISCHARGETHRESHOLDCONTROLV87651234Figure36Figure37
20091Version1.
1,May2009cssCustomSiliconSolutions,Inc.
CSS555CMicropowerTimer(withInternalTimingCapacitor)GENERALPARTDESCRIPTIONTheCSS555Cisamicropowerversionofthepopular555timerIC.
Itfeaturesanoperatingcurrentunder5Aandaminimumsupplyvoltageof1.
2V,makingitidealforbattery-operatedapplications.
Asix-decadeprogrammablecounterisincludedtoallowgenerationoflongtimingdelays.
ConfigurationdataforthecounterisheldinEEPROMtomaintainthestandardpincountofeight.
Theanalogcircuitsaretemperaturecompensatedtoprovideexcellentstabilityoverawideambienttemperaturerange.
Asimplefour-wireinterfaceprovidesRead/WriteaccesstotheEEPROM.
TheCSS555Cdeviceincludesaninternalprecisiontimingcapacitor(CTI).
Itsvalueistrimmedto100pF±1%.
KeyFeaturesPinConfigurationLowestpower555timer(by>10X)!
ActivemodecurrentCSS555C-ID8pinplasticDIPPulseWidthModulationCSS555C-IS8pinplasticSOICLowCost,HighReliabilityApplicationsSeepage9formoredetailsandoptions.
CustomSiliconSolutionsInc.
17951SkyParkCircle,SuiteFIrvine,CA92614(949)797-9220FAX:(949)797-9225www.
CustomSiliconSolutions.
comGNDTRIGGEROUTPUTRESETV+DISCHARGETHRESHOLDCONTROLV87651234PDIPorSOICCSS555CLongPeriodDelayGeneratorVDDRARBTriggerOutputResetOperatingconditions:RA=RB=4.
7M,Internalcounter=106(maximum)CINT=100pF,Delay=16.
3minutesAveragepower=7.
5WatVDD=3.
0V12348765CSS555CCustomSiliconSolutions,Inc.
20092Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)BlockDiagramsStandard555TimerConfiguration(Std.
Mode)(Programmablecounterbypassed,Dividersetting=1)Figure3ExtendedPeriodConfiguration(EPMode)(Programmablecounterenabled,Dividersetting≥10)Figure4EEPROMBitAssignmentsCounterConfigurationDividerSetting(Mult)ModeControlBitsFunctionxxxxx0001(Std.
555)xxxx0xxxAstableMode("Don'tCare"ifStd.
555)xxxxx00110xxxx1xxxMonostableMode("Don'tCare"ifStd.
555)xxxxx010100xxx0xxxxMicroPowerxxxxx0111Kxxx1xxxxLowPowerxxxxx10010Kxx0xxxxxStandardVoltage(Triplevels=&VDD)xxxxx101100Kxx1xxxxxLowVoltage(Triplevels=10%&90%VDD)xxxxx1101MBit6Unusedxxxxx1111(Std.
555)Bit71(ReadOnly)Table1ATable1BNote:Fordetailedprogramminginformation,seeApplicationNoteAN555-1(CSS555_App_Note1_Serial_Interface)_+Comp_+CompRSQQResetFlipFlopVDDTriggerOutputControlVoltageThresholdVHVLR1R2R3ResetVSS156482Discharge37R1+R2+R3~6MForVDD>1.
8V,VH=2/3xVDD,VL=1/3xVDDForVDDCSS555CMicropowerTimer(withInternalTimingCapacitor)ELECTRICALSPECIFICATIONSAbsoluteMaximumRatingsSupplyVoltage(VDD)6VVoltageatanyPin-0.
3toVDD+0.
3VTotalCurrentintoVDDPin(Source)50mATotalCurrentoutofGNDPin(Sink)60mAStorageTemperatureRange-65°Cto+140°CNote:Absolutemaximumratingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
DCandACelectricalspecificationsarenotensuredwhenoperatingthedeviceatabsolutemaximumratings.
ElectricalCharacteristicsTemperature=25°C,TestCircuit#1,unlessotherwisespecified(IfVDDCSS555CMicropowerTimer(withInternalTimingCapacitor)ElectricalCharacteristics(cont)Temperature=-40°Cto+85°C,TestCircuit#1,unlessotherwisespecified(IfVDDCSS555CVSSTriggerOutputResetRBNote:CT≡ExternalTimingCapacitorCTI≡InternalTimingCapacitorCTOTAL≡CT+CTICustomSiliconSolutions,Inc.
20095Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)PinDescriptionsPinNumberPinNamePrimaryFunction(NormalMode)SecondaryFunction(EEProgramming)1VSSGround2TRIGGERInitiatestimingcycles(Activelow)SerialClock3OUTPUTTimerOutput(CMOSLevels)SerialDataOut4RESETAsynchronoustimerreset(Activelow)SerialDataIn5CONTROLVUppercomparatorswitchlevelR/Wenable(ActiveifVCTRLCSS555CICmaybeusedinmanyapplicationsasadirectreplacementforthepopular555timer.
Itfeaturesthelowest555operatingcurrentandaminimumsupplyvoltageof1.
2V.
Italsofeaturesaprogrammabledecadecounterforgeneratinglongtimedelays.
AninternalEEPROMstoresthecounterconfiguration:Divideby1(standard555)ordivideby10,100,103,104,105or106.
Theinternalcounterallowslongtimedelaystobegeneratedwithsmallvaluecapacitors.
MonostableOperation(Standard555Mode)ThecircuitinFigure6showsamonostableor"oneshot"configuration.
Asingle,positiveoutputpulseisgeneratedonthefallingedgeoftheTRIGGERinput.
WhenTRIGGERgoeslow,aflip-flopisset,theOUTPUTpinissethighandDISCHARGEallowsthetimingcapacitortochargetowardsVDDviaRA.
WhenVTHreachestheuppercomparatortriplevel,theflip-flopisreset,OUTPUTisforcedlowandDISCHARGEpullsVTHtoGND.
AfterVTHhasdischarged,thecircuitisreadyforthenexttriggerpulse.
TypicalsignalwaveformsareshowninFigure7.
TheRESETinputmustbeheldhigh(inactive)duringthetimingcycle.
IfRESETisbroughtlow,theOUTPUTpinisimmediatelyforcedlowandthecycleisterminated.
Figure6–MonostableCircuit(Std.
Mode)Inthemonostableconfiguration,thedurationofthetimingcycleissimplythetimerequiredtochargethetimingcapacitorfromGNDtotheuppercomparatortriplevel.
ThetriplevelisnominallyVDD.
Atlowsupplyvoltagesitisincreasedto0.
9VDD.
(AnEEPROMbitcontrolsthisselection.
)Thedelaytimeequationsforbothconditionsareprovidedinthefollowingparagraph.
DelayTimeEquations:Forstandardsupplyvoltages(VLOWBit=0)Chargetime(VTH=0VtoVDD)=1.
1xRAxCTotalForlowvoltagemode(VLOWBit=1)Chargetime(VTH=0Vto0.
9VDD)=2.
3xRAxCTotalwhereCTotal=(CInternal+CExternal)or(CTI+CT)Figure7–MonostableWaveforms(Std.
Mode)Figure8providesalog-logselectionchart.
ItshowsthetimedelayforvariouscombinationsofRAandCTotal.
Withthecounterbypassed(Mult=1),timedelaysfrom1usecto1secondareeasilygeneratedwithcapacitorvaluesfrom100pFto1uF.
Forlongtimedelays(ormediumdelaytimesusingsmallcapacitorvalues)the"ExtendedPeriod"configurationshouldbeused.
(Seethenextsection.
)0.
00010.
00100.
01000.
10001.
00000.
010.
101.
0010.
00100.
001000.
00DelayTime(ms)Ctotal=Ct+Cti(uF)Figure8–TimeDelayChartRA=1K10K100KGreen:LowVDDBlue:Std.
VDD10M1MVDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetTriggerOutputResetVTHOptionalTRIGGEROUTPUTVCAP0VVDDRESETMult=1CustomSiliconSolutions,Inc.
20096Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)MonostableOperation(ExtendedPeriodor"EP"Mode)Forlongertimedelays,thecircuitinFigure9usestheinternaldecadecountertoeffectivelymultiplythevalueofthetimingcapacitor.
ThreebitsintheEEPROMselectamultipliervaluefrom10to106.
The555analogblockisconfiguredasafreerunningoscillator,whichistheinputclocktothecounter.
OnthefallingedgeofTRIGGER,the555oscillatorisenabled,OUTPUTissethigh,thedecadecounterisenabledandanewtimingcyclebegins.
Thetimingcycleendswhenthecounterreachestheselectedterminalcount.
WaveformsforanextendeddelaycycleareshowninFigure10.
Figure9–ExtendedPeriodDelayCircuitFigure10–ExtendedPeriodWaveformsIntheExtendedPeriodmonostableconfiguration,thedurationofthetimingcycleistheoscillatorperiodmultipliedbythecountersetting.
The555oscillatorisconfiguredforastableoperation.
(TheinternalTRIGGERsignaltotheoscillatorisinternallytiedtoTHRESHOLD.
SeeFigure4.
)VCAPoscillatesbetween&VDD(or10%&90%iflowvoltagemodeisselected).
Thedelaytimeequationsforbothsupplyconditionsareprovidedinthefollowingparagraph.
ExtendedDelayTimeEquations:Forstandardsupplyvoltages(VLOWBit=0)OscillatorPeriod(tOSC)=0.
695x(RA+2RB)xCTotalTotalDelayTime=CounterSetting(orMult)xtOSCTotalDelayTime=Multx0.
695x(RA+2RB)xCTotalwhereCTotal=CT+CTICT=ExternaltimingcapacitorCTI=Internal100pFtimingcapacitorForlowvoltagemode(VLOWBit=1)OscillatorPeriod(tOSC)=2.
197x(RA+2RB)xCTotalTotalDelayTime=CounterSetting(orMult)xtOSCTotalDelayTime=Multx2.
197x(RA+2RB)xCTotalThechartinFigure11showsnominaldelaytimesformultipliersettingsfrom1to106andresistorvalues(RA+2RB)from1Kto10M.
(Theinternaltimingcapacitor,CTI,equals100pF.
Noexternalcapacitor.
)Theresultingdelaytimescoveraneight-decaderange!
11010010001000010000010000001.
E-021.
E-011.
E+001.
E+011.
E+021.
E+031.
E+041.
E+051.
E+06DelayTime(sec)CounterValueFigure11–ExtendedPeriodDelayChartThecomponentvaluesrequiredforsomecommondelaytimesarelistedinTable5.
Forthiscalculation,thevalueofRAandRBareequal.
Tokeeptheoverallpowerlow,valuesabove1Mwereselected.
DelayMultiplierCTotalValueRA&RB1msec1100pF2.
35M1sec.
1K100pF4.
8M1min.
100K100pF2.
9M1hour1M500pF3.
5M1day1M0.
01uF4.
1M1week1M0.
1uF2.
9MTable5–ExtendedPeriodDelayTableNote:CTotal=CT+CTICT=Externaltimingcapacitor(maybezero)CTI=Internal100pFtimingcapacitorTRIGGEROUTPUTVCAP0VVDDVDDRESETMult=10CTI=100pFRA+2RB=1K10K100K1M10MGreen:LowVDDBlue:Std.
VDDVDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetTriggerOutputResetRBVTHOptionalCustomSiliconSolutions,Inc.
20097Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)AstableOperation(Standard555Mode)ThecircuitinFigure12showstheastableor"freerunningoscillator"configuration.
Ifthecountersettingequalsone,thecounterisbypassedandthedeviceoperateslikeastandard555timer.
WiththeTRIGGERinputtiedtoTHRESHOLD,anewtimingcycleisstartedeachtimeVTHdropsbelowthelowercomparatortriplevel.
Figure12–AstableCircuit(Std.
Mode)ThecapacitorchargestoVDDthrough(RA+RB)anddischargestoVDDthroughRB.
(Asinthemonostablemode,thetriplevelsarechangedto10%&90%forlowsupplyvoltages.
ThisselectionismadeviatheEEPROM.
)ThedutycycleisdeterminedbytheratioofRAandRB.
TypicalsignalwaveformsareshowninFigure13.
TheRESETinputmustbeheldhighfortheoscillatortobeactive.
IfRESETisbroughtlow,theOUTPUTpinisimmediatelyforcedlowandoscillationhalts.
Equationsforthefreerunningoscillatorareprovidedinthefollowingparagraph.
Figure13–AstableWaveforms(Std.
Mode)Note:TheTRIGGERsignalisconnectedtoVTHFreeRunningOscillatorEquations:Forstandardsupplyvoltages(VLOWBit=0)OscillatorPeriod(tOSC)=0.
695x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=1.
44/[(RA+2RB)xCTotal]whereCTotal=CT+CTICT=ExternaltimingcapacitorCTI=Internal100pFtimingcapacitorForlowvoltagemode(VLOWBit=1)OscillatorPeriod(tOSC)=2.
197x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=0.
455/[(RA+2RB)xCTotal]DutyCycle=RB/(RA+2RB)ThechartinFigure14showsnominaloscillatorfrequenciesforresistorvalues(RA+2RB)from1Kto10Mandcapacitorvaluesfrom100pFto1uF.
Theresultingfrequencyrangeextendsfrom1Hzto1MHz.
(Forthischart,thecounterisbypassed;Mult=1.
)0.
00010.
00100.
01000.
10001.
00001101001000100001000001000000Frequency(Hz)Ctotal=Ct+Cti(uF)Figure14–AstableFrequencyChart(Std.
Mode)AstableOperation(ExtendedPeriodor"EP"Mode)ThecircuitinFigure15employstheinternaldecadecountertodividethe555oscillatorfrequencybythemultipliersetting.
Themultipliervalue,10to106,isselectedbytheEEPROM.
The555analogblockisconfiguredasafreerunningoscillator,whichsuppliestheinputclocktothecounter.
TheoscillatorrunswhenRESETishigh(logicone)andTRIGGERislow.
Eachdivideby10stageofthedecadecounterconsistsofadivideby5followedbyadivideby2.
Thisconfigurationprovidesa50%outputdutycyclenomatterwhichmultipliersettingisselected.
WaveformsforthismodeareshowninFigure16.
RA+2RB=10M1M100K10K1KGreen:LowVDDBlue:Std.
VDDOUTPUTVCAP0VVDDVDDRESETMult=1VDDRAOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetOutputResetRBOptionalVTHCustomSiliconSolutions,Inc.
20098Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)Figure15–AstableCircuit(EPMode)Figure16–AstableWaveforms(EPMode)FreeRunningOscillatorEquations:Forstandardsupplyvoltages(VLOWBit=0)OscillatorPeriod(tOSC)=0.
695x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=1.
44/[(RA+2RB)xCTotal]OutputFrequency=fOSC/MultwhereCTotal=CT+CTICT=ExternaltimingcapacitorCTI=Internal100pFtimingcapacitorForlowvoltagemode(VLOWBit=1)OscillatorPeriod(tOSC)=2.
197x(RA+2RB)xCTotalOsc.
Freq.
(fOSC)=1/tOSC=0.
455/[(RA+2RB)xCTotal]OutputFrequency=fOSC/MultDutyCycle=50%ThechartinFigure17showsnominaloscillatorfrequenciesformultipliersettingsfrom1to106andresistorvalues(RA+2RB)from1Kto10M.
(Theinternaltimingcapacitor,CTI,equals100pF.
Noexternaltimingcapacitor.
)Theresultingfrequenciesrangefromlessthan1Hzto1MHz.
11010010001000010000010000001101001000100001000001000000Frequency(Hz)CounterValueFigure17–AstableFrequencyChart(EPMode)EEPROM(ConfigurationMemory)AninternalEEPROMprovidestwobytesofnonvolatilememorythatstorestheconfigurationinformationandthe100pFcapacitortrimsetting.
Theconfigurationbitscontrolthemultipliersetting(1to106),thepowersetting(microorlow)andthecomparatortriplevels(standardorlowvoltage).
(SeeTables1A&1Bformoredetails.
)ByemployinganinternalEEPROMforconfigurationcontrol,thepincountandpinfunctionsremaincompatiblewithexisting555IC's.
TheEEPROMincludesahighvoltagegenerator.
NospecialsignallevelsarerequiredtoReadorWritetoit.
AccesstotheEEPROMisenabledbyforcingtheCONTROLpintoGND.
(ThispinisnormallyleftopenandaninternalvoltagedividerholdsitatVDD.
)WithCONTROLheldatGND,theTRIGGERandRESETpinsareredefinedtobeSCLK(SerialClock)andSDIN(SerialDataIn).
DatafromtheEEPROMcanbereadattheOUTPUTpin.
Theinterfaceissimpleandstraightforward.
Itcansupportprogrammingindividualunitsordevicesinstalledintheirapplicationcircuit.
AdetaileddescriptionoftheserialinterfaceisprovidedinApplicationNoteAN555-1("CSS555CEEPROMSerialInterface").
Adevelopmentkitisavailableandprovidesbothprogrammingandevaluationcapabilities.
ItusesastandardPCandoneUSBport.
PleasecontactCustomSiliconSolutionsformoreinformation.
ThecoreEEPROMcellisadifferential,floatinggatecircuit.
LikeanSRAM,itfeatureszerostaticcurrent.
Itsoutputdataisvalidwheneverthesupplyvoltageisabove1.
0V.
Ithasexcellentdataretentionandendurancecharacteristics.
Dataretentionisgreaterthan10yearsat85°Canditsendurance(maximumnumberofStorecycles)isgreaterthan100,000cycles.
AtypicalStoreoperationcanbeperformedinlessthan25msec.
TRIGGEROUTPUTVCAP0VVDDVDDRESETMult=10RA+2RB=10M1M100K10K1KCT=100pFGreen:LowVDDBlue:Std.
VDDVDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetTriggerOutputResetRBVTHOptionalCustomSiliconSolutions,Inc.
20099Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)SupplyCurrentConsiderationsTheinternalsupplycurrentusedbytheCSS555Ccanbedividedintothreemaincomponents:1)~1.
8uAconstantcurrent(independentofVDD)2)~6MfromVDDtoGND(0.
5uAatVDD=3V)3)~0.
5uAswitchingcurrentatVDD=3V,FOSC=100KHz(~linearlyproportionaltoVDD&FOSC)Tominimizethesecondcomponent,keepVDDaslowaspossible.
Tominimizetheswitchingcurrent,keepVDD&FOSClow.
(Choosealowermultipliervaluesotheoscillatorfrequencyiswellbelow100KHz.
)TheexternalcurrentisdeterminedbythevaluesofRAandRB.
Theyshouldbeashighaspractical.
(PCBsurfaceleakagetypicallylimitsthevalueto≤10M.
)TheCSS555Chasa"Break-Before-Make"driverfortheOUTPUTsignal.
Thiscircuiteliminatesthelarge"throughcurrent"thatflowsdirectlyfromVDDtoGNDduringeachoutputtransition.
Thissignificantlyreducesthenoiseinjectedintothepowersupply.
Thedischargepathinthemonostableconfigurationisanothersourceoftransientcurrent.
(WhenVTHreachestheuppertrippoint,thecapacitorisveryquicklydischargedtoGND.
)Tominimizethistransientcurrent,simplyaddaresistor(RLIM)inserieswiththeDISCHARGEpin.
(seeFigure18)ThevalueofRLIMmustbelowenoughtoallowthetimingcapacitortocompletelydischargebeforethenexttimingcycle.
AtypicalvalueforRLIMis1Kto10K.
Figure18–MonostablewithRLIMESDProtectionAllinputandoutputpinsincludeprotectiondevicestoguardagainstESDdamage.
AsimplifiedschematicoftheinputprotectioncircuitisshowninFigure19.
Thevoltagelevelsatallpinsshouldbekeptbetween(VSS–0.
3V)and(VDD+0.
3V)topreventforwardbiasingthediodes.
Figure19–InputProtectionCircuitInternalTimingCapacitorTheinternaltimingcapacitorisaPoly/Polystructurewhichhasexcellentstabilityovertemperature(TC~25ppm/°C)andvoltage(VC~250ppm/V).
Itconsistsofafixed75pFcapacitor(CTIB)anda0pFto40pFtrimcapacitor(CTIA).
EightEEPROMbitsstorethetrimsettingwithastepsizeof~0.
16pF.
Thevalueissetatfinalpackagetest,butmaybere-adjustedbytheuser.
(SeeapplicationnoteAN555-1formoredetails.
)Thethirdcapacitor,CS,isthestraycapacitanceduetothepadcell,bondwireandpackageleadframe.
Itistypically5pF.
Figure20–Internal100pFTimingCapacitorOrderingInformationPartNumberPackageDescriptionShippingOptionsCSS555C-ID8pinplasticDIP50units/RailCSS555C-IS8pinplasticSOIC98units/RailCSS555C-ISTR8pinplasticSOIC2500units/Tape&ReelCSS555C_IWDieorTestedWafersContactCSSforoptionsCSS555C_DVKDevelopmentKitN.
A.
Table6–OrderingOptionsAllpackagingoptionsuseleadfreematerials.
Allparttypesareratedforoperationfrom-40°Cto+85°C.
ThedefaultconfigurationstoredinEEPROMis:ConfigurationData=80HEXOperatingMode=Standard555PowerSetting=MicroVoltageSetting=StandardTimingCapacitor=Trimmedto100pFPackagedpartsmaybeorderedwithalternateconfigurationsettings.
Aminimumpurchaseand/orservicechargemayapply.
PleasecontactCSSfordetails.
DevelopmentKitThe"CSS555CDevelopmentKit"isaPCbasedsystemthatallowstheusertoReadandProgramtheinternalEEPROM.
Itincludesaneasytousedialogboxandserialinterface(USBportrequired).
Thecircuitcardincludesplentyofextraterminalssothatmostapplicationscanbebuiltandevaluatedquicklyandeasily.
Formoreinformation,pleaserefertothedevelopmentkit'sinstructionmanual.
VDDRATriggerOutputResetCTVDDDischgThreshControlCSS555CVSSTriggerOutputResetRLIMOptionalVTHVDDInput/OutputPinInputProtectionDiodesToInternalCircuitsCTIA0pF-40pFPoly/PolyCapacitor8EETRIMCTIB75pFCS5pFTHRESHOLDPINCustomSiliconSolutions,Inc.
200910Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)TypicalPerformanceCharacteristicsFigure21SupplyCurrent(MicroPower)Figure22SupplyCurrent(LowPower)Figure23FrequencyDriftvs.
VDDFigure24FrequencyDriftvs.
TemperatureFigure25PropagationDelay(StandardVDD)Figure26PropagationDelay(LowVDD)NormalizedFrequencyDriftvs.
VDD-2.
0-1.
5-1.
0-0.
50.
00.
51.
01.
52.
00.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
05.
56.
0VDD(V)DeltaFreq.
(%)Std.
VDDLowVDDAstableModeCT=1nF;RA,RB=1MegTemperature=25CNormalizedFrequencyDriftvs.
Temperature-2.
0-1.
5-1.
0-0.
50.
00.
51.
01.
52.
0-50-250255075100Temperature(deg.
C)DeltaFreq.
(%)VDD=5.
0VVDD=3.
0VVDD=2.
0VAstableModeCT=10nF;RA,RB=100KPropagationDelayvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
005101520253035TriggerLowLevel(%VDD)PropagationDelay(usec)VDD5V3V2VPowerSettingMicroLowStandardTripLevels(1/3&2/3VDD)PropagationDelayvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
0012345678910TriggerLowLevel(%VDD)PropagationDelay(usec)LowVDDTripLevels(10%&90%)PowerSettingMicroLowVDD3.
0V2.
0V1.
5VIDDvs.
VDD&Temperature02468100.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
05.
56.
0VDD(V)IDD(uA)+125C+85C+25C-40CPowerSetting=MicroIDDvs.
VDD&Temperature0510152025300.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
05.
56.
0VDD(V)IDD(uA)+125C+85C+25C-40CPowerSetting=LowCustomSiliconSolutions,Inc.
200911Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)TypicalPerformanceCharacteristics(continued)Figure27TriggerPulseWidth(Std.
VDD)Figure28TriggerPulseWidth(LowVDD)Figure29OUTPUTVOHvs.
IOHFigure30OUTPUTIOHvs.
TemperatureFigure31OUTPUTVOLvs.
IOLFigure32OUTPUTIOLvs.
TemperatureMinimumTriggerPulseWidthvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
005101520253035TriggerLowLevel(%VDD)PulseWidth(usec)PowerSettingMicroLowStandardTripLevels(1/3&2/3VDD)VDD5.
0V3.
0V2.
0VMinimumTriggerPulseWidthvs.
TriggerLevel0.
00.
51.
01.
52.
02.
53.
03.
54.
04.
55.
0012345678910TriggerLowLevel(%VDD)PulseWidth(usec)LowVDDTripLevels(10%&90%VDD)PowerSettingMicroLowVDD3.
0V2.
0V1.
5VTimerOUTPUTLowVoltagevs.
SinkCurrent0.
00.
51.
01.
52.
00.
11.
010.
0100.
0OutputSinkCurrent(mA)OutputLowVoltage(V)VDD3.
0VVDD1.
5VVDD5.
0VTimerOUTPUTDriveLowvs.
Temperature012345678910-50-250255075100125Temperature(degreesC)OutputSinkCurrent(mA)VDD=5.
0VVDD=1.
5VVDD=3.
0VIOLmeasuredatVOL=0.
2VTimerOUTPUTDriveHighvs.
Temperature012345678910-50-250255075100125Temperature(degreesC)OutputSourceCurrent(mA)VDD=5.
0VVDD=3.
0VVDD=1.
5VIOHmeasuredatVOH=VDD-0.
2VTimerOUTPUTHighVoltagevs.
SourceCurrent0.
00.
51.
01.
52.
00.
11.
010.
0100.
0OutputSourceCurrent(mA)OutputHighVoltage(VDD-Vout)(V)VDD5.
0VVDD3.
0VVDD1.
5VCustomSiliconSolutions,Inc.
200912Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)TypicalPerformanceCharacteristics(continued)Figure33DISCHARGEVOLvs.
IOLFigure34DISCHARGEIOLvs.
TemperatureDISCHARGELowVoltagevs.
SinkCurrent0.
00.
51.
01.
52.
00.
11.
010.
0100.
0OutputSinkCurrent(mA)OutputLowVoltage(V)VDD5.
0VVDD3.
0VVDD1.
5VDISCHARGEOutputDriveLowvs.
Temperature02468101214161820-50-250255075100125Temperature(degreesC)OutputSinkCurrent(mA)VDD=5.
0VVDD=3.
0VVDD=1.
5VIOLmeasuredatVOL=0.
2VCustomSiliconSolutions,Inc.
200913Version1.
1,May2009CSS555CMicropowerTimer(withInternalTimingCapacitor)PACKAGEDRAWINGSPinoutDiagramSOICMechanicalDrawingFigure35Table7PDIPMechanicalDrawingTable8SOICDimensionsInchesMillimetersSymbolMINMAXMINMAXA0.
0530.
0691.
351.
75A10.
0040.
0100.
100.
25B0.
0140.
0190.
350.
49C0.
0070.
0100.
190.
25D0.
1890.
1974.
805.
00E0.
1500.
1573.
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