波形Verilog代码(计数器、交通灯、串并转换)

1、通用二进制计数器

设计一个二进制计数器默认为8位计数器具有加/减计数功能、异步复位、预制数功能。

代码如下

`defin eWIDTH 8modul eBinar yCoun ter(count er,clk,up_do wn,load,reset ,din);outpu treg[`WIDTH-1:0]count er;input clk;input up_do wn; //1为加计数 0为减计数input reset ;input load; //预置数 1有效 din输出到coun terinp ut [`WIDTH-1:0]din;alway s@(posed ge clk or posed ge reset )beginif(reset )count er<=0;else if(load)count er<=din;else if(up_do wn==1)count er<=count er+1;else if(up_do wn==0)begincount er<=count er-1;if(count er<1)count er<=0;endendendmo dule

测试程序如下

`defin eWIDTH 8modul eBinar yCoun ter_t b;reg clk,up_do wn,reset ,load;reg[`W ID TH-1:0]din;wire [`WIDTH-1:0]count er;integ er i;initi albeginclk=0;reset=1;

#5 reset=0;

#3000$s to p;end

alway s#5 clk=~clk;

/*alway s@(posed ge clk)beginup_do wn={$rando m}%2;lo ad={$rando m}%2;din={$rando m}%256;end

*/initi albegin

#5;for(i=0;i<256;i=i+3)begindin=i;

#10;endendiniti albeginup_do wn=1;lo ad=1;

#20 load=0;

#30 load=1;

#30 load=0;endalway s#200 up_do wn=~up_do wn;

Binar yCoun ter bcoun ter(.count er(count er),

.clk(clk),.up_do wn(up_do wn),.load(load),.reset (reset ),.din(din));endmo dule

波形图如下

图1二进制计数器波形图

图2二进制计数器波形图

从图像可看出 20s-50s为加计数 50s-80s时l oad=1执行置数功能 80s-200s时up_do wn=1,为加计数 200s-280s时up_do wn=0为减计数。

2、格雷码计数器

代码如下

`defin eWIDTH 4modul eGrayC ounte r(gray,clk,rst_n);outpu t[`WIDTH-1:0]gray;input clk;input rst_n;reg[`WIDTH-1:0]binar y;alway s@(posed ge clk or neged ge rst_n)beginif(!rst_n)binar y<=0;else if(binar y<16)beginbinar y<=binar y+1;

//binar y<=(binar y<16)?binar y:0;endelsebinar y<=0;endassig ngray[0]=binar y[0]^binar y[1];assig ngray[1]=binar y[1]^binar y[2];assig ngray[2]=binar y[2]^binar y[3];assig ngray[3]=binar y[3];endmo dule

测试程序如下

`defin eWIDTH 4modul eGrayC ounte r_tb;w ire [`W ID TH-1:0]gra y;reg clk;reg rst_n;initi albeginclk=0;rst_n=0;

#10 rst_n=1;

#1000$s to p;endalway s#5 clk=~clk;

/*alway s@(posed ge clk)beginend

*/

GrayC ounte rgc(.gray(gray),.clk(clk),.rst_n(rst_n));endmo dule

波形图如下

图3格雷码计数器波形图二进制数值

图3格雷码计数器波形图十进制数值

3、完成一个串并转换电路(8位)的Veri log代码设计。代码如下modul etrans form_cb(sclk,pclk,rst,ser_d in,enabl e,p_dou t);input sclk;input pclk;input rst;input enabl e;input ser_din;outpu t[7:0]p_dou t;reg[7:0] te mp,po ut_buf;re g[2:0]c o unt ;

//integ er i;alway s@(posed ge sclk or neged ge rst)beginif(!rst)beginc o unt<=0;te mp<=0;endelse if(count<=3'b111)beginc o unt<=co unt+1;temp[0]<=ser_d in;te mp<=te mp<<1;temp[7:0]<={temp[6:0],ser_d in};endend

alway s@(posed ge pclk or neged ge rst)beginif(!rst)pout_buf<=0;elsepout_buf<=temp;endassig np_dou t=(enabl e)?pout_buf:8'bz;endmo dule

测试程序如下modul etrans form_cb_tb;reg sclk;reg p c lk;reg rst;reg enabl e;reg ser_d in;wire [7:0]p_dou t;initi albeginsclk=0;pclk=0;rst=0;enabl e=0;

#15 rst=1;enabl e=1;

#15 enabl e=0;

#20 enabl e=1;

#50 enabl e=0;

#50 enabl e=1;

#1000$s to p;endalway s#5 sclk=~sclk;alway s#40 pclk=~pclk;alway s@(posed ge sclk)ser_d in={$rando m}%2;trans form_ cb ps(.sclk(sclk),.pclk(pclk),.rst(rst),.ser_d in(ser_d in),.enabl e(enable),.p_dou t(p_dou t));endmo dule

波形图如下

图5 8位串并转换电路波形图

图6 8位串并转换电路波形图

图7 8位串并转换电路波形图

图8 8位串并转换电路波形图

从图中可以看出 0-15s、 30s-50s时e nable无效输出为三态 15s-30s、 50s-100s时enabl e有效输出8位并行数据在200s 、280s、 360s可以看出每到pcl k上升沿 同步输出一个并行8位数据。

4、设计交通灯控制器有限状态机问题。

主干道上车很多有最高优先级默认主干道是绿灯亮支路偶尔有车有车时必须变绿灯只要维持足够的时间能让车通过即可支路上只要不再有车则支路绿灯变黄灯然后变红灯 同时主干道亮绿灯有一个传感器监视支路上是否有车 向控制器输入信号X X=1表示有车否则X=0

代码如下modul etraff ic_li ght(clock,clear,x,hwy,cntry);input clock;input clear;input x;outpu t reg[1:0] hwy; //主绿hwy=2'b00,主黄hwy=2'b01,主红hwy=2'b10;outpu t reg[1 :0] cntry; //支绿cnt ry=2'b00,支黄cnt ry=2'b01,支红cntry=2'b10;

//re g[5:0] c o unt ; //计数器reg[1 :0] state ,nexts tate;param eter hwy_g reen=2'b00,hwy_y ellow=2'b01,cntry_gree n=2'b 10,cntry_yellow=2'b 11;alway s@(posed ge clock or neged ge clear )beginif(!clear )begin

//c o unt<=0;state<=hwy_g reen;end

elsebegin

// co unt<=count+1;state<=nexts tate;endendalway s@(x or state )

//nexts tate<=hwy_g reen;case(s tate )hwy_g reen:beginhwy<=2'b00;cntry<=2'b 10;if(x)nexts tate<=hwy_y ellow;elsenexts tate<=hwy_g reen;endhwy_y ellow:beginhwy<=2'b01;cntry<=2'b 10;if(x)nexts tate<=cntry_gree n;elsenexts tate<=hwy_g reen;endcntry_gree n:beginhwy<=2'b 10;cntry<=2'b00;if(x)nexts tate<=cntry_gree n;elsenexts tate<=cntry_yell ow;endcntry_yell ow:beginhwy<=2'b 10;cntry<=2'b01;if(x)nexts tate<=cntry_gree n;elsenexts tate<=hwy_g reen;endendca seendmo dule