CIN1www.pu811.com

DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013DP83640PrecisionPHYTER-IEEE1588PrecisionTimeProtocolTransceiverCheckforSamples:DP836401Introduction1.
1Features123IEEE1588V1andV2SupportedError-freeOperationupto150MetersCAT5CableUDP/IPv4,UDP/IPv6,andLayer2EthernetPacketsSupportedESDProtection-8kVHumanBodyModelIEEE1588ClockSynchronization2.
5Vand3.
3VI/OsandMACInterfaceTimestampResolutionof8nsAuto-MDIXfor10/100MbpsAllowsSub10nsSynchronizationtoMasterRMIIRev.
1.
2andMIIMACInterfaceReference25MHzMDCandMDIOSerialManagement12IEEE1588GPIOsforTriggerorCaptureInterfaceDeterministic,LowTransmitandReceiveIEEE802.
3u100BASE-FXFiberInterfaceLatencyIEEE1149.
1JTAGSelectableFrequencySynchronizedClockProgrammableLEDSupportforLink,10/100OutputMb/sMode,Duplex,Activity,andCollisionDynamicLinkQualityMonitoringDetectTDRBasedCableDiagnosticandCableLengthOptional100BASE-TXFastLink-lossDetectionDetectionIndustrialTemperatureRange10/100Mb/sPacketBIST(BuiltinSelfTest)48pinLQFPPackage(7mm)x(7mm)1.
2ApplicationsFactoryAutomation–Ethernet/IP–CIPSyncTestandMeasurement–LXIStandardTelecom–BasestationRealTimeNetworking1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2PHYTERisatrademarkofTexasInstruments.
3Allothertrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
ProductsconformtoCopyright2007–2013,TexasInstrumentsIncorporatedspecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com1.
3DescriptionTheDP83640PrecisionPHYTERdevicedeliversthehighestlevelofprecisionclocksynchronizationforrealtimeindustrialconnectivitybasedontheIEEE1588standard.
TheDP83640hasdeterministic,lowlatencyandallowschoiceofmicrocontrollerwithnohardwarecustomizationrequired.
Theintegrated1588functionalityallowssystemdesignerstheflexibilityandprecisionofaclosetothewiretimestamp.
Thethreekey1588featuressupportedbythedeviceare:PackettimestampsforclocksynchronizationIntegratedIEEE1588synchronizedclockgenerationSynchronizedeventtriggeringandtimestampingthroughGPIODP83640offersinnovativediagnosticfeaturesuniquetoTexasInstruments,includingdynamicmonitoringoflinkqualityduringstandardoperationforfaultprediction.
Theseadvancedfeaturesallowthesystemdesignertoimplementafaultpredictionmechanismtodetectandwarnofdeterioratingandchanginglinkconditions.
ThissingleportfastEthernettransceivercansupportbothcopperandfibermedia.
Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
2IntroductionCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20131Introduction1Timing304.
24ACSpecifications—Auto-NegotiationFastLink1.
1Features1Pulse(FLP)Timing311.
2Applications14.
25ACSpecifications—100BASE-TXSignalDetect1.
3Description2Timing312DeviceInformation54.
26ACSpecifications—100Mb/sInternalLoopback2.
1SystemDiagram5Timing322.
2BlockDiagram64.
27ACSpecifications—10Mb/sInternalLoopbackTiming332.
3KeyIEEE1588Features74.
28ACSpecifications—RMIITransmitTiming(Slave3PinDescriptions11Mode)343.
1PinLayout124.
29ACSpecifications—RMIITransmitTiming(Master3.
2PackagePinAssignments13Mode)353.
3SerialManagementInterface(SMI)144.
30ACSpecifications—RMIIReceiveTiming(Slave3.
4MACDataInterface14Mode)363.
5ClockInterface154.
31ACSpecifications—RMIIReceiveTiming(MasterMode)373.
6LEDInterface154.
32ACSpecifications—RX_CLKTiming(RMIIMaster3.
7IEEE1588Event/Trigger/ClockInterface16Mode)373.
8JTAGInterface164.
33ACSpecifications—CLK_OUTTiming(RMIISlave3.
9ResetandPowerDown16Mode)383.
10StrapOptions174.
34ACSpecifications—SingleClockMII(SCMII)TransmitTiming383.
1110Mb/sand100Mb/sPMDInterface184.
35ACSpecifications—SingleClockMII(SCMII)3.
12PowerSupplyPins18ReceiveTiming394ElectricalSpecifications194.
36ACSpecifications—100Mb/sX1toTX_CLK4.
1AbsoluteMaximumRatings19Timing394.
2RecommendedOperatingConditions195Configuration404.
3ACandDCSpecifications195.
1MediaConfiguration404.
4DCSPECIFICATIONS205.
2Auto-Negotiation404.
5ACSpecifications—PowerUpTiming215.
3Auto-MDIX424.
6ACSpecifications—ResetTiming225.
4PHYAddress434.
7ACSpecifications—MIISerialManagementTiming5.
5LEDInterface44235.
6HalfDuplexvs.
fullDuplex464.
8ACSpecifications—100Mb/sMIITransmitTiming5.
7InternalLoopback46235.
8PowerDown/Interrupt464.
9ACSpecifications—100Mb/sMIIReceiveTiming244.
10ACSpecifications—100BASE-TXand100BASE-5.
9EnergyDetectMode47FXMIITransmitPacketLatencyTiming245.
10LinkDiagnosticCapabilities474.
11ACSpecifications—100BASE-TXand100BASE-5.
11BIST51FXMIITransmitPacketDeassertionTiming.
.
.
.
.
.
.
256MACInterface524.
12ACSpecifications—100BASE-TXTransmitTiming6.
1MIIInterface52(tR/F&Jitter)256.
2ReducedMIIInterface534.
13ACSpecifications—100BASE-TXand100BASE-FXMIIReceivePacketLatencyTiming266.
3SingleClockMIIMode544.
14ACSpecifications—100BASE-TXand100BASE-6.
4IEEE802.
3uMIISerialManagementInterface.
.
.
.
55FXMIIReceivePacketDeassertionTiming.
.
.
.
.
.
.
266.
5PHYControlFrames574.
15ACSpecifications—10Mb/sMIITransmitTiming276.
6PHYStatusFrames574.
16ACSpecifications—10Mb/sMIIReceiveTiming.
277Architecture594.
17ACSpecifications—10BASE-TMIITransmit7.
1100BASE-TXTransmitter59Timing(StartofPacket)287.
2100BASE-TXReceiver614.
18ACSpecifications—10BASE-TMIITransmit7.
3100BASE-FXOperation65Timing(EndofPacket)287.
410BASE-TTransceiverModule664.
19ACSpecifications—10BASE-TMIIReceiveTiming(StartofPacket)298ResetOperation704.
20ACSpecifications—10BASE-TMIIReceiveTiming8.
1HardwareReset70(EndofPacket)298.
2FullSoftwareReset704.
21ACSpecifications—10Mb/sHeartbeatTiming.
.
.
308.
3SoftReset704.
22ACSpecifications—10Mb/sJabberTiming.
.
.
.
.
.
308.
4PTPReset704.
23ACSpecifications—10BASE-TNormalLinkPulseCopyright2007–2013,TexasInstrumentsIncorporatedContents3SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com9DesignGuidelines7110.
2ExtendedRegisters-Page0949.
1TPINetworkCircuit7110.
3TestRegisters-Page11049.
2FiberNetworkCircuit7210.
4LinkDiagnosticsRegisters-Page21059.
3ESDProtection7210.
5PTP1588BaseRegisters-Page41129.
4ClockIn(X1)Recommendations7210.
6PTP1588ConfigurationRegisters-Page5.
.
.
.
.
.
12010RegisterBlock7510.
7PTP1588ConfigurationRegisters-Page6.
.
.
.
.
.
12710.
1RegisterDefinition83RevisionHistory1314ContentsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20132DeviceInformation2.
1SystemDiagramFigure2-1.
SystemDiagramCopyright2007–2013,TexasInstrumentsIncorporatedDeviceInformation5SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com2.
2BlockDiagramFigure2-2.
DP83640FunctionalBlockDiagarm6DeviceInformationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20132.
3KeyIEEE1588FeaturesIEEE1588providesatimesynchronizationprotocol,oftenreferredtoasthePrecisionTimeProtocol(PTP),whichsynchronizestimeacrossanEthernetnetwork.
DP83640supportsIEEE1588RealTimeEthernetapplicationsbyprovidinghardwaresupportforthreetimecriticalelements.
IEEE1588synchronizedclockgenerationPackettimestampsforclocksynchronizationEventtriggeringandtimestampingthroughGPIOBycombiningtheabovecapabilities,theDP83640providesadvancedandflexiblesupportforIEEE1588foruseinahighlyaccurateIEEE1588system.
TheDP83640providesfeaturesforcontrollingtheclockoperationinSlavemode.
TheclockvaluecanbeupdatedtomatchtheMasterclockinseveralways.
Inaddition,theclockcanbeprogrammedtoadjustitsfrequencytocompensatefordrift.
TheDP83640supportsrealtimetriggeringactivitiesandcapturesrealtimeeventstoreporttothemicrocontroller.
ControlleddevicescanbeconnectedtotheDP83640throughtheavailableGPIO.
TheIEEE1588featuresarebrieflypresentedbelow.
ForamoredetaileddiscussiononconfiguringtheIEEE1588features,refertotheSoftwareDevelopmentGuidefortheDP83640.
Figure2-3.
DP83640ExampleSystemApplicationCopyright2007–2013,TexasInstrumentsIncorporatedDeviceInformation7SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com2.
3.
1IEEE1588SYNCHRONIZEDCLOCKTheDP83640providesseveralmechanismsforupdatingtheIEEE1588clockbasedonthesynchronizationprotocolrequired.
Thesemethodsarelistedbelow.
DirectlyRead/WritableAdjustablebyAdd/SubtractFrequencyScalableTemporaryFrequencyControlTheclockconsistsofthefollowingfields:Seconds(32–bitfield),Nanoseconds(30–bitfield),andFractionalNanoseconds(unitsof2-32ns).
Adirectsetofthetimevaluecanbedonebysettinganewtimevalue.
Astepadjustmentvalueinnanosecondsmaybeaddedtothecurrentvalue.
Notethattheadjustmentvaluecanbepositiveornegative.
Theclockcanbeprogrammedtooperateatanadjustedfrequencyvaluebyprogrammingarateadjustmentvalue.
Theclockcanalsobeprogrammedtoperformatemporaryadjustedfrequencyvaluebyincludingarateadjustmentduration.
Therateadjustmentallowsforcorrectionontheorderof2-32nsperreferenceclockcycle.
Thefrequencyadjustmentwillallowtheclocktocorrecttheoffsetovertime,avoidinganypotentialside-effectscausedbyastepadjustmentinthetimevalue.
Themethodusedtoupdatetheclockvaluemaydependonthedifferenceinthevalues.
Forexample,attheinitialsynchronizationattempt,theclocksmaybeveryfarapart,andthereforerequireastepadjustmentoradirecttimeset.
Later,whenclocksareverycloseinvalue,thetemporaryrateadjustmentmethodmaybethebestoption.
Theclockdoesnotsupportnegativetimevalues.
Ifnegativetimeisrequiredinthesystem,softwarewillhavetomakeconversionsfromthePHYclocktimetoactualtime.
Theclockalsodoesnotsupporttheupper16-bitsofthesecondsfieldasdefinedbythespecification(Version2specifiesa48-bitsecondsfield).
Ifthisvalueisrequiredtobegreaterthan0,itwillhavetobehandledbysoftware.
Sincearolloverofthesecondsfieldonlyoccursevery136years,itshouldnotbeasignificantburdentosoftware.
2.
3.
1.
1IEEE1588ClockOutputTheDP83640providesforasynchronizedclocksignalforusebyexternaldevices.
Theoutputclocksignalcanbeanyfrequencygeneratedfrom250MHzdividedbyn,wherenisanintegerintherangeof2to255.
Thisprovidesnominalfrequenciesfrom125MHzdownto980.
4kHz.
TheclockoutputsignaliscontrolledbythePTP_COCregister.
TheoutputclocksignalisgeneratedusingtherateinformationinthePTP_RATEregistersandisthereforefrequencyaccuratetothe1588clocktimeofthedevice.
Inaddition,ifclocktimeadjustmentsaremadeusingtheTemporaryRatecapabilities,thenalltimeadjustmentswillbetrackedbytheoutputclocksignalaswell.
Notethatanystepadjustmentinthe1588clocktimewillnotbeaccuratelyrepresentedonthe1588clockoutputsignal.
2.
3.
1.
2IEEE1588ClockInputTheIEEE1588PTPlogicoperatesonanominal125MHzreferenceclockgeneratedbyaninternalPhaseGenerationModule(PGM).
However,optionsareavailabletouseadivided-downversionofthePGMclocktoreducepowerconsumptionattheexpenseofprecision,ortouseanexternalreferenceclockofupto125MHzintheeventthe1588clockistrackedexternally.
8DeviceInformationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20132.
3.
2PACKETTIMESTAMPS2.
3.
2.
1IEEE1588TransmitPacketParserandTimestampTheIEEE1588transmitparsermonitorstransmitpacketdatatodetectIEEE1588Version1andVersion2Eventmessages.
ThetransmitparsercandetectPTPEventmessagestransporteddirectlyinLayer2EthernetpacketsaswellasinUDP/IPv4andUDP/IPv6packets.
UpondetectionofaPTPEventMessage,thedevicewillcapturethetransmittimestampandprovideittosoftware.
Sincesoftwareknowstheorderofpackettransmission,onlythetimestampisrecorded(thereisnoneedtorecordsequencenumberorotherinformation).
Thedevicecanbufferfourtimestamps.
Ifenabled,aninterruptmaybegenerateduponaTransmitTimestampReady.
2.
3.
2.
1.
1One-StepOperationInsomecases,thetransmittercanbesettooperateinaOne-Stepmode.
ForSyncMessages,aOne-Stepdevicecanautomaticallyinserttimestampinformationintheoutgoingpacket.
Thiseliminatestheneedforsoftwaretoreadthetimestampandsendafollowupmessage.
2.
3.
2.
2IEEE1588ReceivePacketParserandTimestampTheIEEE1588receiveparsermonitorsreceivepacketdatatodetectIEEE1588Version1andVersion2Eventmessages.
ThereceiveparsercandetectPTPEventmessagestransporteddirectlyinEthernetpacketsaswellasinUDP/IPv4andUDP/IPv6packets.
UpondetectionofaPTPEventmessage,thedevicewillcapturethereceivetimestampandprovidethetimestampvaluetosoftware.
Inadditiontothetimestamp,thedevicewillrecordthe16-bitSequenceId,the4-bitmessageTypefield,andgeneratea12-bithashvalueforoctets20-29ofthePTPeventmessage.
Thedevicecanbufferfourtimestamps.
Aninterruptwillbegenerated,ifenabled,uponaReceiveTimestampReady.
2.
3.
2.
2.
1ReceiveTimestampInsertionTheDP83640candeliverthetimestamptosoftwarebyinsertingthetimestampinthereceivedpacket.
Thisallowsforasimplemethodtodeliverthepackettosoftwarewithouthavingtomatchthetimestamptothecorrectpacket.
ThisalsoeliminatestheneedtoreadthereceivetimestampthroughtheSerialManagementInterface.
2.
3.
2.
3NTPPacketTimestampTheDP83640maybeprogrammedtotimestampNTPpacketsinsteadofPTPpackets.
ThisoperationisenabledbysettingtheNTP_TS_ENcontrolinthePTP_TXCFG0register.
WhenconfiguredforNTPtimestamps,theDP83640willtimestamppacketswiththeNTPUDPportnumberratherthanthePTPportnumber(notethatthedevicecannotbeconfiguredtotimestampbothPTPandNTPpackets).
One-StepoperationisnotsupportedforNTPtimestamps,sotransmittimestampscannotbeinserteddirectlyintooutgoingNTPpackets.
Timestampinsertionisavailableforreceivetimestampsbutmustuseasingle,fixedlocation.
2.
3.
3EVENTTRIGGERINGANDTIMESTAMPING2.
3.
3.
1IEEE1588EventTriggeringTheDP83640iscapableofbeingprogrammedtogenerateatriggersignalonanoutputpinbasedontheIEEE1588timevalue.
Eachtriggercanbeprogrammedtogenerateaone-timerisingorfallingedge,asinglepulseofprogrammablewidth,oraperiodicsignal.
Foreachtrigger,themicrocontrollerspecifiesthedesiredGPIOandtimethattheactivityistooccur.
ThetriggerisgeneratedwhentheinternalIEEE1588clockmatchesthedesiredactivationtime.
Copyright2007–2013,TexasInstrumentsIncorporatedDeviceInformation9SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comThedevicesupportsupto8triggersignalswhichcanbeoutputonanyoftheGPIOsignalpins.
MultipletriggersmaybeassignedtoasingleGPIO,allowinggenerationofmorecomplexwaveforms(i.
e.
asequenceofvaryingwidthpulses).
ThetriggersignalsareOR'edtogethertoformacombinedsignal.
ThetriggersareconfiguredthroughthePTPTriggerConfigurationRegisters.
ThetriggertimeandwidthsettingsarecontrolledthroughthePTPControlandTimeDataregisters.
TheDP83640canbeprogrammedtooutputaPulse-Per-Second(PPS)signalusingthetriggerfunctions.
2.
3.
3.
2IEEE1588EventTimestampingTheDP83640canbeprogrammedtotimestampaneventbymonitoringaninputsignal.
Theeventcanbemonitoredforrisingedge,fallingedge,oreither.
TheEventTimestampUnitcanmonitoruptoeighteventswhichcanbesettoanyoftheGPIOsignalpins.
PTPeventtimestampsarestoredinaqueuewhichallowsstorageofuptoeighttimestamps.
Whenaneventtimestampisavailable,thedevicewillsettheEVENT_RDYbitinthePTPStatusRegister.
ThePTPEventStatusRegister(PTP_ESTS)providesdetailedinformationonthenextavailableeventtimestamp,includinginformationontheeventnumber,rise/falldirection,andindicationofeventsmissedduetooverflowofthedevicesEventqueue.
Eventtimestampvaluesshouldbeadjustedby35ns(3timesperiodoftheIEEE1588referenceclockfrequencyof125MHz+11ns)tocompensateforinputpathandsynchronizationdelays.
TheEventTimestampUnitisconfiguredthroughthePTPEventConfigurationRegister(PTP_EVNT).
2.
3.
4PTPINTERRUPTSThePTPmodulemayinterruptthesystemusingthePWRDOWN/INTNpinonthedevice,sharedwithotherinterruptsfromthePHY.
Asanalternative,thedevicemaybeprogrammedtouseaGPIOpintogeneratePTPinterruptsseparatefromotherPHYinterrupts.
2.
3.
5GPIOTheDP83640features12IEEE1588GPIOpins.
TheseGPIOpinsallowforeventmonitoring,triggering,interrupts,andaclockoutput.
TheLEDpinscomprise3ofthe12GPIOpins.
IfanLEDpinistobeusedasaGPIO,itsLEDfunctionmustbedisabledpriortoconfiguringtheGPIOfunction.
10DeviceInformationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20133PinDescriptionsTheDP83640pinsareclassifiedintothefollowinginterfacecategories(eachinterfaceisdescribedinthesectionsthatfollow):SerialManagementInterfaceMACDataInterfaceClockInterfaceLEDInterfaceGPIOInterfaceJTAGInterfaceResetandPowerDownStrapOptions10/100Mb/sPMDInterfacePowerandGroundpinsNote:Strappingpinoption.
PleaseseeSection3.
10forstrapdefinitions.
AllDP83640signalpinsareI/Ocellsregardlessoftheparticularuse.
ThedefinitionsbelowdefinethefunctionalityoftheI/Ocellsforeachpin.
TypeI:InputTypeO:OutputTypeI/O:Input/OutputTypeOD:OpenDrainTypePD:InternalPulldownTypePU:InternalPullupTypeS:StrappingPin(Allstrappinshaveweakinternalpull-upsorpull-downs.
Ifthedefaultstrapvalueistobechangedthenanexternal2.
2kΩresistorshouldbeused.
PleaseseeSection3.
10fordetails.
Copyright2007–2013,TexasInstrumentsIncorporatedPinDescriptions11SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com3.
1PinLayoutFigure3-1.
TopView12PinDescriptionsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20133.
2PackagePinAssignmentsPT0048APin#PinNamePT0048APin#PinName1TX_CLK25GPIO42TX_EN26LED_ACT3TXD_027LED_SPEED/FX_SD4TXD_128LED_LINK5TXD_229RESET_N6TXD_330MDIO7PWRDOWN/INTN31MDC8TCK32IO_VDD9TDO33X210TMS34X111TRST#35IO_CORE_VSS12TDI36GPIO813RD-37GPIO914RD+38RX_CLK15CD_VSS39RX_DV16TD-40CRS/CRS_DV17TD+41RX_ER18ANAVSS42COL19ANA33VDD43RXD_320VREF44RXD_221GPIO145RXD_122GPIO246RXD_023GPIO347IO_VSS24CLK_OUT48IO_VDDCopyright2007–2013,TexasInstrumentsIncorporatedPinDescriptions13SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com3.
3SerialManagementInterface(SMI)SignalNamePinNameTypePin#DescriptionMDCMDCI31MANAGEMENTDATACLOCK:SynchronousclocktotheMDIOmanagementdatainput/outputserialinterfacewhichmaybeasynchronoustotransmitandreceiveclocks.
Themaximumclockrateis25MHzwithnominimumclockrate.
MDIOMDIOI/O30MANAGEMENTDATAI/O:Bi-directionalmanagementinstruction/datasignalthatmaybesourcedbythestationmanagemententityorthePHY.
Thispinrequiresa1.
5kpullupresistor.
Alternately,aninternalpullupmaybeenabledbysettingbit3intheCDCTRL1register.
3.
4MACDataInterfaceSignalNamePinNameTypePin#DescriptionTX_CLKTX_CLKO1MIITRANSMITCLOCK:25MHzTransmitclockoutputin100Mb/smodeor2.
5MHzin10Mb/smodederivedfromthe25MHzreferenceclock.
TheMACshouldsourceTX_ENandTXD[3:0]usingthisclock.
RMIIMODE:UnusedinRMIISlavemode.
ThedeviceusestheX1referenceclockinputasthe50MHzreferenceforbothtransmitandreceive.
ForRMIIMastermode,thedeviceoutputstheinternallygenerated50MHzreferenceclockonthispin.
Thispinprovidesanintegrated50ohmsignaltermination,makingexternalterminationresistorsunnecessary.
TX_ENTX_ENI,PD2MIITRANSMITENABLE:ActivehighinputindicatesthepresenceofvaliddatainputsonTXD[3:0].
RMIITRANSMITENABLE:ActivehighinputindicatesthepresenceofvaliddataonTXD[1:0].
TXD_0TXD_0I3MIITRANSMITDATA:TransmitdataMIIinputpins,TXD[3:0],thatacceptTXD_1TXD_1I4datasynchronoustotheTX_CLK(2.
5MHzin10Mb/smodeor25MHzinTXD_2TXD_2I5100Mb/smode).
TXD_3TXD_3I,PD6RMIITRANSMITDATA:TransmitdataRMIIinputpins,TXD[1:0],thatacceptdatasynchronoustothe50MHzreferenceclock.
RX_CLKRX_CLKO38MIIRECEIVECLOCK:Providesthe25MHzrecoveredreceiveclocksfor100Mb/smodeand2.
5MHzfor10Mb/smode.
RMIIMODE:UnusedinRMIISlavemode.
ThedeviceusestheX1referenceclockinputasthe50MHzreferenceforbothtransmitandreceive.
ForRMIIMastermode,thedeviceoutputstheinternallygenerated50MHzreferenceclockonthispin.
Thispinprovidesanintegrated50ohmsignaltermination,makingexternalterminationresistorsunnecessary.
RX_DVRX_DVO,PD39MIIRECEIVEDATAVALID:AssertedhightoindicatethatvaliddataispresentonthecorrespondingRXD[3:0].
RMIIRECEIVEDATAVALID:ThissignalprovidestheRMIIReceiveDataValidindicationindependentofCarrierSense.
Thispinprovidesanintegrated50ohmsignaltermination,makingexternalterminationresistorsunnecessary.
RX_ERRX_ERS,O,PU41MIIRECEIVEERROR:AssertedhighsynchronouslytoRX_CLKtoindicatethataninvalidsymbolhasbeendetectedwithinareceivedpacketin100Mb/smode.
RMIIRECEIVEERROR:AssertedhighsynchronouslytoX1wheneveramediaerrorisdetected,andRX_DVisassertedin100Mb/smode.
ThispinisnotrequiredtobeusedbyaMACinRMIImode,sincethePHYisrequiredtocorruptdataonareceiveerror.
Thispinprovidesanintegrated50ohmsignaltermination,makingexternalterminationresistorsunnecessary.
RXD_0RXD_0S,O,PD46MIIRECEIVEDATA:NibblewidereceivedatasignalsdrivensynchronouslyRXD_1RXD_145totheRX_CLK(25MHzfor100Mb/smode,2.
5MHzfor10Mb/smode).
RXD_2RXD_244RXD[3:0]signalscontainvaliddatawhenRX_DVisasserted.
RXD_3RXD_343RMIIRECEIVEDATA:2-bitsreceivedatasignals,RXD[1:0],drivensynchronouslytothe50MHzreferenceclock.
Thesepinsprovideintegrated50ohmsignalterminations,makingexternalterminationresistorsunnecessary.
14PinDescriptionsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013SignalNamePinNameTypePin#DescriptionCRS/CRS_DVCRS/CRS_DVS,O,PU40MIICARRIERSENSE:Assertedhightoindicatethereceivemediumisnon-idle.
RMIICARRIERSENSE/RECEIVEDATAVALID:ThissignalcombinestheRMIICarrierandReceiveDataValidindications.
Foradetaileddescriptionofthissignal,seetheRMIISpecification.
Thispinprovidesanintegrated50ohmsignaltermination,makingexternalterminationresistorsunnecessary.
COLCOLS,O,PU42MIICOLLISIONDETECT:Assertedhightoindicatedetectionofacollisioncondition(simultaneoustransmitandreceiveactivity)in10Mb/sand100Mb/sHalfDuplexModes.
Whilein10BASE-THalfDuplexmodewithheartbeatenabledthispinisalsoassertedforadurationofapproximately1sattheendoftransmissiontoindicateheartbeat(SQEtest).
InFullDuplexMode,for10Mb/sor100Mb/soperation,thissignalisalwayslogic0.
Thereisnoheartbeatfunctionduring10Mb/sfullduplexoperation.
RMIICOLLISIONDETECT:PertheRMIISpecification,noCOLsignalisrequired.
TheMACwillrecoverCRSfromtheCRS_DVsignalandusethatalongwithitsTX_ENsignaltodeterminecollision.
Thispinprovidesanintegrated50ohmsignaltermination,makingexternalterminationresistorsunnecessary.
3.
5ClockInterfaceSignalNamePinNameTypePin#DescriptionX1X1I34CRYSTAL/OSCILLATORINPUT:ThispinistheprimaryclockreferenceinputfortheDP83640andmustbeconnectedtoa25MHz0.
005%(±50ppm)clocksource.
TheDP83640supportseitheranexternalcrystalresonatorconnectedacrosspinsX1andX2oranexternalCMOS-leveloscillatorsourceconnectedtopinX1only.
RMIIREFERENCECLOCK:ForRMIISlaveMode,thispinmustbeconnectedtoa50MHz0.
005%(±50ppm)CMOS-leveloscillatorsource.
InRMIIMasterMode,a25MHzreferenceisrequired,eitherfromanexternalcrystalresonatorconnectedacrosspinsX1andX2orfromanexternalCMOS-leveloscillatorsourceconnectedtopinX1only.
X2X2O33CRYSTALOUTPUT:Thispinistheprimaryclockreferenceoutputtoconnecttoanexternal25MHzcrystalresonatordevice.
ThispinmustbeleftunconnectedifanexternalCMOSoscillatorclocksourceisused.
CLK_OUTCLK_OUTI/O,PD24CLOCKOUTPUT:Thispinprovidesahighlyconfigurablesystemclock,whichmayhaveoneoffoursources:1.
RelativetotheinternalPTPclock,withadefaultfrequencyof25MHz(default)2.
50MHzRMIIreferenceclockinRMIIMasterMode3.
25MHzReceiveClock(sameasRX_CLK)in100Mbmode4.
25MHzor50MHzpass-throughofX1referenceclockCLOCKINPUT:ThispinisusedtoinputanexternalIEEE1588referenceclockforusebytheIEEE1588logic.
TheCLK_OUT_ENstrapshouldbedisabledinthesystemtopreventpossiblecontention.
ThePTP_CLKSRCregistermustbeconfiguredpriortoenablingtheIEEE1588functioninordertoallowcorrectoperation.
3.
6LEDInterfaceTheDP83640supportsthreeconfigurableLEDpins.
TheLEDssupporttwooperationalmodeswhichareselectedbytheLEDmodestrapandathirdoperationalmodewhichisregisterconfigurable.
ThedefinitionsfortheLEDsforeachmodearedetailedbelow.
SignalNamePinNameTypePin#DescriptionLED_LINKLED_LINKS,O,PU28LINKLED:InMode1,thispinindicatesthestatusoftheLINK.
TheLEDwillbeONwhenLinkisgood.
LINK/ACTLED:InMode2andMode3,thispinindicatestransmitandreceiveactivityinadditiontothestatusoftheLink.
TheLEDwillbeONwhenLinkisgood.
Itwillblinkwhenthetransmitterorreceiverisactive.
LED_SPEEDLED_SPEED/FX_SS,O,PU27SPEEDLED:TheLEDisONwhendeviceisin100Mb/sandOFFwheninD10Mb/s.
FunctionalityofthisLEDisindependentofmodeselected.
Copyright2007–2013,TexasInstrumentsIncorporatedPinDescriptions15SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comSignalNamePinNameTypePin#DescriptionLED_ACTLED_ACTS,O,PU26ACTIVITYLED:InMode1,thispinistheActivityLEDwhichisONwhenactivityispresentoneitherTransmitorReceive.
COLLISION/DUPLEXLED:InMode2,thispinbydefaultindicatesCollisiondetection.
InMode3,thisLEDoutputindicatesFull-Duplexstatus.
3.
7IEEE1588Event/Trigger/ClockInterfaceSignalNamePinNameTypePin#DescriptionGPIO1GPIO1I/O,PD21GeneralPurposeI/O:Thesepinsmaybeusedtosignalordetectevents.
GPIO2GPIO222GPIO3GPIO323GPIO4GPIO425GPIO5LED_ACTI/O,PU26GeneralPurposeI/O:Thesepinsmaybeusedtosignalordetectevents.
GPIO6LED_SPEED/FX_S27CareshouldbetakenwhendesigningsystemsthatuseLEDsbutusetheseDpinsasGPIOs.
TodisabletheLEDfunctions,refertoSection10.
2.
5.
GPIO7LED_LINK28GPIO8GPIO8I/O,PD36GeneralPurposeI/O:Thesepinsmaybeusedtosignalordetectevents.
GPIO9GPIO937GPIO10TDOI/O,PU9GeneralPurposeI/O:Thesepinsmaybeusedtosignalordetectevents.
GPIO11TDI12CareshouldbetakenwhendesigningsystemsthatusetheJTAGinterfacebutusethesepinsasGPIOs.
GPIO12CLK_OUTI/O,PD24GeneralPurposeI/O:ThispinmaybeusedtosignalordetecteventsormayoutputaprogrammableclocksignalsynchronizedtotheinternalIEEE1588clockormaybeusedasaninputforanexternallygeneratedIEEE1588referenceclock.
IfthesystemdoesnotrequiretheCLK_OUTsignal,theCLK_OUToutputshouldbedisabledviatheCLK_OUT_ENstrap.
3.
8JTAGInterfaceSignalNamePinNameTypePin#DescriptionTCKTCKI,PU8TESTCLOCKThispinhasaweakinternalpullup.
TDOTDOO9TESTOUTPUTTMSTMSI,PU10TESTMODESELECTThispinhasaweakinternalpullup.
TRST#TRST#I,PU11TESTRESET:Activelowtestreset.
Thispinhasaweakinternalpullup.
TDITDII,PU12TESTDATAINPUTThispinhasaweakinternalpullup.
3.
9ResetandPowerDownSignalNamePinNameTypePin#DescriptionRESET_NRESET_NI,PU29RESET:ActiveLowinputthatinitializesorre-initializestheDP83640.
Assertingthispinlowforatleast1swillforcearesetprocesstooccur.
Allinternalregisterswillre-initializetotheirdefaultstatesasspecifiedforeachbitintheRegisterBlocksection.
Allstrapoptionsarere-initializedaswell.
PWRDOWN/INTNPWRDOWN/INTNI,PU7ThedefaultfunctionofthispinisPOWERDOWN.
POWERDOWN:AssertingthissignallowenablestheDP83640PowerDownmodeofoperation.
Inthismode,theDP83640willpowerdownandconsumeminimumpower.
RegisteraccesswillbeavailablethroughtheManagementInterfacetoconfigureandpowerupthedevice.
INTERRUPT:ThispinmaybeprogrammedasaninterruptoutputinsteadofaPowerdowninput.
Inthismode,Interruptswillbeassertedlowusingthispin.
Registeraccessisrequiredforthepintobeusedasaninterruptmechanism.
SeeSection5.
8.
2formoredetailsontheinterruptmechanisms.
16PinDescriptionsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20133.
10StrapOptionsTheDP83640usesmanyofthefunctionalpinsasstrapoptionstoplacethedeviceintospecificmodesofoperation.
Thevaluesofthesepinsaresampledatpoweruporhardreset.
Duringsoftwareresets,thestrapoptionsareinternallyreloadedfromthevaluessampledatpoweruporhardreset.
Thestrapoptionpinassignmentsaredefinedbelow.
Thefunctionalpinnameisindicatedinparentheses.
A2.
2kresistorshouldbeusedforpull-downorpull-uptochangethedefaultstrapoption.
Ifthedefaultoptionisrequired,thenthereisnoneedforexternalpull-uporpulldownresistors.
Sincethesepinsmayhavealternatefunctionsafterresetisdeasserted,theyshouldnotbeconnecteddirectlytoVCCorGND.
SignalNamePinNameTypePin#DescriptionPHYAD0COLS,O,PU42PHYADDRESS[4:0]:TheDP83640providesfivePHYaddresspins,PHYAD1RXD_3S,O,PD43thestateofwhicharelatchedintothePHYCTRLregisteratsystemPHYAD2RXD_2S,O,PD44Hardware-Reset.
PHYAD3RXD_1S,O,PD45TheDP83640supportsPHYAddressstrappingvalues0()PHYAD4RXD_0S,O,PD46through31().
APHYAddressof0putsthepartintotheMIIIsolateMode.
TheMIIisolatemodemustbeselectedbystrappingPHYAddress0;changingtoAddress0byregisterwritewillnotputthePHYintheMIIisolatemode.
PHYAD[0]pinhasweakinternalpull-upresistor.
PHYAD[4:1]pinshaveweakinternalpull-downresistors.
AN_ENLED_LINKS,O,PU28AUTO-NEGOTIATIONENABLE:Whenhigh,thisenablesAuto-AN1LED_SPEED/FX_SS,O,PU27NegotiationwiththecapabilitysetbyAN0andAN1pins.
Whenlow,thisDputsthepartintoForcedModewiththecapabilitysetbyAN0andAN1AN0LED_ACTS,O,PU26pins.
AN0/AN1:TheseinputpinscontroltheforcedoradvertisedoperatingmodeoftheDP83640accordingtothefollowingtable.
ThevalueonthesepinsissetbyconnectingtheinputpinstoGND(0)orVCC(1)through2.
2kresistors.
ThesepinsshouldNEVERbeconnecteddirectlytoGNDorVCC.
ThevaluesetatthisinputislatchedintotheDP83640atHardware-Reset.
Thefloat/pull-downstatusofthesepinsarelatchedintotheBasicModeControlRegisterandtheAuto_NegotiationAdvertisementRegisterduringHardware-Reset.
Thedefaultis111sincethesepinshaveinternalpull-ups.
FIBERMODEDUPLEXSELECTION:IfFibermodeisstrappedusingtheFX_EN_Zpin(FX_EN_Z=0),theAN0strapvalueisusedtoselecthalforfullduplex.
AN_ENandAN1areignoredinFibermodesinceitis100MbonlyanddoesnotsupportAuto-Negotiation.
InFibermode,AN1shouldnotbeconnectedtoanysystemcomponentsexceptthefibertransceiver.
FX_EN_AN_ENAN1AN0ForcedModeZ100010BASE-T,Half-Duplex100110BASE-T,Full-Duplex1010100BASE-TX,Half-Duplex1011100BASE-TX,Full-Duplex0XX0100BASE-FX,Half-Duplex0XX1100BASE-FX,Full-DuplexFX_EN_AN_ENAN1AN0AdvertisedModeZ110010BASE-T,Half/Full-Duplex1101100BASE-TX,Half/Full-Duplex1110100BASE-TX,Full-Duplex111110BASE-T,Half/Full-Duplex,100BASE-TX,Half/Full-DuplexCLK_OUT_ENGPIO1S,I,PD21CLK_OUTOUTPUTENABLE:Whenhigh,enablesclockoutputontheCLK_OUTpinatpower-up.
Copyright2007–2013,TexasInstrumentsIncorporatedPinDescriptions17SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comSignalNamePinNameTypePin#DescriptionFX_EN_ZRX_ERS,O,PU41FXENABLE:Thisstrappingoptionenables100Base-FX(Fiber)mode.
Thismodeisdisabledbydefault.
Anexternalpull-downwillenable100Base-FXmode.
LED_CFGCRS/CRS_DVS,O,PU40LEDCONFIGURATION:ThisstrappingoptiondeterminesthemodeofoperationoftheLEDpins.
DefaultisMode1.
Mode1andMode2canbecontrolledviathestrapoption.
Allmodesareconfigurableviaregisteraccess.
SeeTable5-3forLEDModeSelection.
MII_MODERX_DVS,O,PD39MIIMODESELECT:ThisstrappingoptiondeterminestheoperatingmodeoftheMACDataInterface.
DefaultoperationisMIIModewithavalueof0duetotheinternalpulldown.
StrappingMII_MODEhighwillcausethedevicetobeinRMIImodeofoperation.
MII_MODEMACInterfaceMode0MIIMode1RMIIModePCF_ENGPIO2S,I,PD22PHYCONTROLFRAMEENABLE:Whenhigh,allowstheDP83640torespondtoPHYControlFrames.
RMII_MASTXD_3S,I,PD6RMIIMASTERENABLE:WhenMII_MODEisstrappedhigh,thisstrappingoptionenablesRMIIMastermode,inwhichtheDP83640usesa25MHzcrystalconnectiononX1/X2andgeneratesthe50MHzRMIIreferenceclock.
IfstrappedlowwhenMII_MODEisstrappedhigh,defaultRMIIoperation(RMIISlave)isenabled,inwhichtheDP83640usesa50MHzoscillatorinputonX1astheRMIIreferenceclock.
ThisstrapoptionisignorediftheMII_MODEstrapislow.
3.
1110Mb/sand100Mb/sPMDInterfaceSignalNamePinNameTypePin#DescriptionTD-TD-I/O16Differentialcommondrivertransmitoutput(PMDOutputPair).
TheseTD+TD+17differentialoutputsareautomaticallyconfiguredtoeither10BASE-Tor100BASE-TXsignaling.
InAuto-MDIXmodeofoperation,thispaircanbeusedastheReceiveInputpair.
In100BASE-FXmode,thispairbecomesthe100BASE-FXTransmitpair.
Thesepinsrequire3.
3Vbiasforoperation.
RD-RD-I/O13Differentialreceiveinput(PMDInputPair).
ThesedifferentialinputsareRD+RD+14automaticallyconfiguredtoaccepteither100BASE-TXor10BASE-Tsignaling.
InAuto-MDIXmodeofoperation,thispaircanbeusedastheTransmitOutputpair.
In100BASE-FXmode,thispairbecomesthe100BASE-FXReceivepair.
Thesepinsrequire3.
3Vbiasforoperation.
FX_SDLED_SPEED/FX_SS,I/O,PU27FIBERMODESIGNALDETECT:ThispinprovidestheSignalDetectinputDfor100BASE-FXmode.
3.
12PowerSupplyPinsSignalNamePinNameTypePin#DescriptionANAVSSANAVSSGround18AnalogGroundANA33VDDANA33VDDSupply19AnalogVDDSupplyCD_VSSCD_VSSGround15AnalogGroundIO_CORE_VSSIO_CORE_VSSGround35DigitalGroundIO_VDDIO_VDDSupply32I/OVDDSupply48IO_VSSIO_VSSGround47DigitalGroundVREFVREF20BiasResistorConnection.
A4.
87k1%resistorshouldbeconnectedfromVREFtoGND.
18PinDescriptionsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134ElectricalSpecifications4.
1AbsoluteMaximumRatings(1)(2)SupplyVoltage(VCC)-0.
5Vto4.
2VDCInputVoltage(VIN)-0.
5VtoVCC+0.
5VDCOutputVoltage(VOUT)-0.
5VtoVCC+0.
5VStorageTemperature(TSTG)-65°Cto150°CMaximumCaseTemperatureforTA=85°C95°CMaximumDieTemperature(Tj)150°CLeadTemperature(TL)260°C(Soldering,10s)ESDRating8.
0kV(RZAP=1.
5k,CZAP=120pF)(1)Absolutemaximumratingsarethosevaluesbeyondwhichthesafetyofthedevicecannotbeverified.
Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
4.
2RecommendedOperatingConditionsAnalogSupplyVoltage(VCC)3.
3Volts±0.
3VI/OSupplyVoltage(VI/O)3.
3Volts±10%or2.
5Volts±5%IndustrialTemperature(TI)-40to85°CPowerDissipation(PD)withVI/O=3.
3V290mWPowerDissipation(PD)withVI/O=2.
5V260mW4.
3ACandDCSpecificationsThermalCharacteristicsMaxUnitsThetaJunctiontoCase(Tjc)24.
7°C/WThetaJunctiontoAmbient(Tja)degreesCelsius/Watt-NoAirflow@1.
0W53.
3°C/WCopyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications19SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
4DCSPECIFICATIONSPinSymbolParameterConditionsMinTypMaxUnitsTypesVIHIInputHighVoltage2.
0VI/OVILIInputLowVoltageVI/O=3.
3V0.
8VI/OVI/O=2.
5V0.
7VIIHIInputHighCurrentVIN=VI/O10AI/OIILIInputLowCurrentVIN=GND10AI/OVOLOOutputLowVoltageIOL=4mA0.
4VI/OVOHOOutputHighVoltageIOH=-4mAVI/O-0.
5VI/OIOZOTRI-STATEOutputLeakageCurrentVOUT=VI/OorGND-1010AI/OVTPTD_100PMDOutput100MTransmitVoltage0.
9511.
05VPairVTPTDsymPMDOutput100MTransmitVoltageSymmetry±2%PairVTPTD_10PMDOutput10MTransmitVoltage2.
22.
52.
8VPairVFXTD_100PMDOutputFX100MTransmitVoltage0.
30.
50.
93VPairCIN1ICMOSInputCapacitance8pFCOUT1OCMOSOutputCapacitance8pFSDTHonPMDInput100BASE-TXSignaldetectturn-on1000mVdiffPairthresholdpk-pkSDTHoffPMDInputSignaldetectturn-offthreshold200mVdiffPairpk-pkVTHPMDInput10BASE-TReceiveThreshold300585mVPairIdd100Supply100BASE-TX(FullDuplex)VCC=3.
3V,VI/O=88mA3.
3V,IOUT=0mA(1)VCC=3.
3V,VI/O=84mA2.
5V,IOUT=0mA(1)Idd10Supply10BASE-T(FullDuplex)VCC=3.
3V,VI/O=105mA3.
3V,IOUT=0mA(1)VCC=3.
3V,VI/O=103mA2.
5V,IOUT=0mA(1)IddSupplyPowerDownModeCLK_OUTdisabled10mA(1)ForIddmeasurements,outputsarenotloaded20ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
5ACSpecifications—PowerUpTimingParameterDescriptionNotesMinTypMaxUnitsT2.
1.
1PostPowerUpStabilizationtimeMDIOispulledhighfor32-bitserial167mspriortoMDCpreambleforregistermanagementinitialization.
accesses(1)T2.
1.
2HardwareConfigurationLatch-inHardwareConfigurationPinsare167msTimefrompowerup(1)describedintheSection3.
T2.
1.
3HardwareConfigurationpins50nstransitiontooutputdrivers(1)InRMIISlaveMode,theminimumPostPowerupStabilizationandHardwareConfigurationLatch-intimesare84ms.
Figure4-1.
PowerUpTimingCopyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications21SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
6ACSpecifications—ResetTimingParameterDescriptionNotesMinTypMaxUnitsT2.
2.
1PostRESETStabilizationtimepriortoMDIOispulledhighfor32-bitserial3sMDCpreambleforregisteraccessesmanagementinitializationT2.
2.
2HardwareConfigurationLatch-inTimeHardwareConfigurationPinsare3sfromtheDeassertionofRESET(eitherdescribedintheSection3softorhard)T2.
2.
3HardwareConfigurationpinstransition50nstooutputdrivers(1)T2.
2.
4RESETpulsewidthX1Clockmustbestableforatmin.
1sof1sduringRESETpulselowtime.
(1)Itisimportanttochoosepull-upand/orpull-downresistorsforeachofthehardwareconfigurationpinsthatprovidefastRCtimeconstantsinordertolatch-inthepropervaluepriortothepintransitioningtoanoutputdriver.
Figure4-2.
ResetTiming22ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
7ACSpecifications—MIISerialManagementTimingParameterDescriptionNotesMinTypMaxUnitsT2.
3.
1MDCtoMDIO(Output)DelayTime020nsT2.
3.
2MDIO(Input)toMDCSetupTime10nsT2.
3.
3MDIO(Input)toMDCHoldTime10nsT2.
3.
4MDCFrequency2.
525MHzFigure4-3.
MIISerialManagementTiming4.
8ACSpecifications—100Mb/sMIITransmitTimingParameterDescriptionNotesMinTypMaxUnitsT2.
4.
1TX_CLKHigh/LowTime100Mb/sNormalmode162024nsT2.
4.
2TXD[3:0],TX_ENDataSetupto100Mb/sNormalmode10nsTX_CLKT2.
4.
3TXD[3:0],TX_ENDataHoldfrom100Mb/sNormalmode0nsTX_CLKFigure4-4.
100Mb/sMIITransmitTimingCopyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications23SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
9ACSpecifications—100Mb/sMIIReceiveTimingParameterDescriptionNotesMinTypMaxUnitsT2.
5.
1RX_CLKHigh/LowTime(1)100Mb/sNormalmode162024nsT2.
5.
2RX_CLKtoRXD[3:0],RX_DV,RX_ER100Mb/sNormalmode1030nsDelay(1)RX_CLKmaybeheldloworhighforalongerperiodoftimeduringtransitionbetweenreferenceandrecoveredclocks.
Minimumhighandlowtimeswillnotbeviolated.
Figure4-5.
100Mb/sMIIReceiveTiming4.
10ACSpecifications—100BASE-TXand100BASE-FXMIITransmitPacketLatencyTimingParameterDescription(1)Notes(2)MinTypMaxUnitsT2.
6.
1TX_CLKtoPMDOutputPairLatency100BASE-TXand100BASE-FXmodes5bitsIEEE1588One-StepOperationenabled9bits(1)EnablingPHYControlFrameswilladdlatencyequalto8bitstimesthePCF_BUF_SIZEsetting.
ForexampleifPCF_BUF_SIZEissetto15,thentheadditionaldelaywillbe15*8=120bits.
(2)ForNormalmode,latencyisdeterminedbymeasuringthetimefromthefirstrisingedgeofTX_CLKoccurringaftertheassertionofTX_ENtothefirstbitofthe"J"codegroupasoutputfromthePMDOutputPair.
1bittime=10nsin100Mb/smode.
Figure4-6.
100BASE-TXand100BASE-FXMIITransmitPacketLatencyTiming24ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
11ACSpecifications—100BASE-TXand100BASE-FXMIITransmitPacketDeassertionTimingParameterDescriptionNotesMinTypMaxUnitsT2.
7.
1TX_CLKtoPMDOutputPair100BASE-TXand100BASE-FXmodes5bitsDeassertion(1)(1)DeassertionisdeterminedbymeasuringthetimefromthefirstrisingedgeofTX_CLKoccurringafterthedeassertionofTX_ENtothefirstbitofthe"T"codegroupasoutputfromthePMDOutputPair.
1bittime=10nsin100Mb/modeFigure4-7.
100BASE-TXand100BASE-FXMIITransmitPacketDeassertionTiming4.
12ACSpecifications—100BASE-TXTransmitTiming(tR/F&Jitter)ParameterDescriptionNotesMinTypMaxUnitsT2.
8.
1100Mb/sPMDOutputPairtRandtF(1)345ns100Mb/stRandtFMismatch(2)500psT2.
8.
2100Mb/sPMDOutputPairTransmitJitter1.
4ns(1)Riseandfalltimestakenat10%and90%ofthe+1or-1amplitude(2)NormalMismatchisthedifferencebetweenthemaximumandminimumofallriseandfalltimesFigure4-8.
100BASE-TXTransmitTiming(tR/F&Jitter)Copyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications25SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
13ACSpecifications—100BASE-TXand100BASE-FXMIIReceivePacketLatencyTimingParameterDescriptionNotesMinTypMaxUnits(1)T2.
9.
1CarrierSenseONDelay(2)100BASE-TXmode20bits100BASE-FXmode10T2.
9.
2ReceiveDataLatency(3)(4)100BASE-TXmode24bits100BASE-FXmode14(1)1bittime=10nsin100Mb/smode.
(2)CarrierSenseOnDelayisdeterminedbymeasuringthetimefromthefirstbitofthe"J"codegrouptotheassertionofCarrierSense.
(3)EnablingIEEE1588ReceiveTimestampinsertionwillincreasetheReceiveDataLatencyby40bittimes.
(4)EnablingPHYStatusFrameswillintroducevariabilityinReceiveDataLatencyduetoinsertionofPHYStatusFramesintothereceivedatapath.
Figure4-9.
100BASE-TXand100BASE-FXMIIReceivePacketLatencyTiming4.
14ACSpecifications—100BASE-TXand100BASE-FXMIIReceivePacketDeassertionTimingParameterDescriptionNotesMinTypMaxUnits(1)T2.
10.
1CarrierSenseOFFDelay(2)100BASE-TXmode24bits100BASE-FXmode14(1)1bittime=10nsin100Mb/smode.
(2)CarrierSenseOffDelayisdeterminedbymeasuringthetimefromthefirstbitofthe"T"codegrouptothedeassertionofCarrierSense.
Figure4-10.
100BASE-TXand100BASE-FXMIIReceivePacketDeassertionTiming26ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
15ACSpecifications—10Mb/sMIITransmitTimingParameterDescription(1)NotesMinTypMaxUnitsT2.
11.
1TX_CLKHigh/LowTime10Mb/sMIImode190200210nsT2.
11.
2TXD[3:0],TX_ENDataSetupto10Mb/sMIImode25nsTX_CLKfallingedgeT2.
11.
3TXD[3:0],TX_ENDataHoldfrom10Mb/sMIImode0nsTX_CLKrisingedge(1)AnattachedMacshoulddrivethetransmitsignalsusingthepositiveedgeofTX_CLK.
Asshownabove,theMIIsignalsaresampledonthefallingedgeofTX_CLK.
Figure4-11.
10Mb/sMIITransmitTiming4.
16ACSpecifications—10Mb/sMIIReceiveTimingParameterDescriptionNotesMinTypMaxUnitsT2.
12.
1RX_CLKHigh/LowTime(1)160200240nsT2.
12.
2RXD[3:0],RX_DVtransitiondelayfrom10Mb/sMIImode100nsRX_CLKrisingedgeT2.
12.
3RX_CLKrisingedgedelayfrom10Mb/sMIImode100nsRXD[3:0],RX_DVvaliddata(1)RX_CLKmaybeheldlowforalongerperiodoftimeduringtransitionbetweenreferenceandrecoveredclocks.
Minimumhighandlowtimeswillnotbeviolated.
Figure4-12.
10Mb/sMIIReceiveTimingCopyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications27SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
17ACSpecifications—10BASE-TMIITransmitTiming(StartofPacket)ParameterDescriptionNotesMinTypMaxUnits(1)T2.
13.
1TransmitOutputDelayfromthe10Mb/sMIImode3.
5bitsFallingEdgeofTX_CLK(1)1bittime=100nsin10Mb/s.
Figure4-13.
10BASE-TMIITransmitTiming(StartofPacket)4.
18ACSpecifications—10BASE-TMIITransmitTiming(EndofPacket)ParameterDescriptionNotesMinTypMaxUnitsT2.
14.
1EndofPacketHighTime250300ns(with'0'endingbit)T2.
14.
2EndofPacketHighTime250300ns(with'1'endingbit)Figure4-14.
10BASE-TMIITransmitTiming(EndofPacket)28ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
19ACSpecifications—10BASE-TMIIReceiveTiming(StartofPacket)ParameterDescriptionNotesMinTypMaxUnits(1)T2.
15.
1CarrierSenseTurnOnDelay(PMD6301000nsInputPairtoCRS)T2.
15.
2RX_DVLatency(2)10bitsT2.
15.
3ReceiveDataLatencyMeasurementshownfromSFD8bits(1)1bittime=100nsin10Mb/smode.
(2)10BASE-TRX_DVLatencyismeasuredfromfirstbitofpreambleonthewiretotheassertionofRX_DVFigure4-15.
10BASE-TMIIReceiveTiming(StartofPacket)4.
20ACSpecifications—10BASE-TMIIReceiveTiming(EndofPacket)ParameterDescriptionNotesMinTypMaxUnitsT2.
16.
1CarrierSenseTurnOffDelay1.
0sFigure4-16.
10BASE-TMIIReceiveTiming(EndofPacket)Copyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications29SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
21ACSpecifications—10Mb/sHeartbeatTimingParameterDescriptionNotesMinTypMaxUnitsT2.
17.
1CDHeartbeatDelayAll10Mb/smodes1200nsT2.
17.
2CDHeartbeatDurationAll10Mb/smodes1000nsFigure4-17.
10Mb/sHeartbeatTiming4.
22ACSpecifications—10Mb/sJabberTimingParameterDescriptionNotesMinTypMaxUnitsT2.
18.
1JabberActivationTime85msT2.
18.
2JabberDeactivationTime500msFigure4-18.
10Mb/sJabberTiming4.
23ACSpecifications—10BASE-TNormalLinkPulseTimingParameterDescriptionNotesMinTyp(1)MaxUnitsT2.
19.
1PulseWidth100nsT2.
19.
2PulsePeriod16ms(1)Thesespecificationsrepresenttransmittimings.
Figure4-19.
10BASE-TNormalLinkPulseTiming30ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
24ACSpecifications—Auto-NegotiationFastLinkPulse(FLP)TimingParameterDescriptionNotesMinTyp(1)MaxUnitsT2.
20.
1Clock,DataPulseWidth100nsT2.
20.
2ClockPulsetoClockPulse125sPeriodT2.
20.
3ClockPulsetoDataPulseData=162sPeriodT2.
20.
4BurstWidth2msT2.
20.
5FLPBursttoFLPBurstPeriod16ms(1)ThesespecificationsrepresenttransmittimingsFigure4-20.
Auto-NegotiationFastLinkPulse(FLP)Timing4.
25ACSpecifications—100BASE-TXSignalDetectTimingParameterDescription(1)NotesMinTypMaxUnitsT2.
21.
1SDInternalTurn-onTime1msT2.
21.
2SDInternalTurn-offTimeDefaultoperation250300sFastlink-lossindication1.
3senabled(2)(1)ThesignalamplitudeonPMDInputPairmustbeTP-PMDcompliant.
(2)FastLink-lossdetectisenabledbysettingtheSD_CNFG[8]registerbittoa1.
Figure4-21.
100BASE-TXSignalDetectTimingCopyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications31SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
26ACSpecifications—100Mb/sInternalLoopbackTimingParameterDescriptionNotesMinTypMaxUnitsTX_ENtoRX_DVLoopback(1)100Mb/sinternalloopback240nsT2.
22.
1mode(2)(1)Duetothenatureofthedescramblerfunction,all100BASE-TXLoopbackmodeswillcauseaninitial"dead-time"ofupto550sduringwhichtimenodatawillbepresentatthereceiveMIIoutputs.
The100BASE-TXtimingspecifiedisbasedondevicedelaysaftertheinitial550s"dead-time".
(2)MeasurementismadefromthefirstrisingedgeofTX_CLKafterassertionofTX_EN.
Figure4-22.
100Mb/sInternalLoopbackTiming32ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
27ACSpecifications—10Mb/sInternalLoopbackTimingParameterDescriptionNotesMinTypMaxUnitsT2.
23.
1TX_ENtoRX_DVLoopback10Mb/sinternalloopbackmode(1)2s(1)MeasurementismadefromthefirstfallingedgeofTX_CLKafterassertionofTX_EN.
Figure4-23.
10Mb/sInternalLoopbackTimingCopyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications33SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
28ACSpecifications—RMIITransmitTiming(SlaveMode)ParameterDescriptionNotesMinTypMaxUnitsT2.
24.
1X1ClockPeriod50MHzReferenceClock20nsT2.
24.
2TXD[1:0],TX_EN,DataSetuptoX1risingedge4nsT2.
24.
3TXD[1:0],TX_EN,DataHoldfromX1risingedge2nsT2.
24.
4X1ClocktoPMDOutputPairLatency(100Mb)(1)100BASE-TXor100BASE-FX11bits(1)LatencymeasurementismadefromtheX1risingedgetothefirstbitofsymbol.
Figure4-24.
RMIITransmitTiming(SlaveMode)34ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
29ACSpecifications—RMIITransmitTiming(MasterMode)ParameterDescriptionNotesMinTypMaxUnitsT2.
25.
1RX_CLK,TX_CLK,CLK_OUTPeriod50MHzReferenceClock20nsT2.
25.
2TXD[1:0],TX_ENDataSetuptoRX_CLK,4nsTX_CLK,CLK_OUTrisingedgeT2.
25.
3TXD[1:0],TX_ENDataHoldfromRX_CLK,2nsTX_CLK,CLK_OUTrisingedgeT2.
25.
4RX_CLK,TX_CLK,CLK_OUTtoPMDOutputPairFromRX_CLKrisingedgeto11bitsLatency(1)firstbitofsymbol(1)LatencymeasurementismadefromtheRX_CLKrisingedgetothefirstbitofsymbol.
Figure4-25.
RMIITransmitTiming(MasterMode)Copyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications35SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
30ACSpecifications—RMIIReceiveTiming(SlaveMode)ParameterDescription(1)NotesMinTypMaxUnitsT2.
26.
1X1ClockPeriod50MHzReferenceClock20nsT2.
26.
2RXD[1:0],CRS_DV,andRX_ER214nsoutputdelayfromX1risingedge(2)T2.
26.
3CRSONdelay(3)100BASE-TXmode18.
5bits100BASE-FXmode9T2.
26.
4CRSOFFdelay(4)100BASE-TXmode27bits100BASE-FXmode17T2.
26.
5RXD[1:0]andRX_ER100BASE-TXmode38bitslatency(5)(6)(7)100BASE-FXmode27(1)PertheRMIISpecification,outputdelaysassumea25pFload.
(2)CRS_DVisassertedasynchronouslyinordertominimizelatencyofcontrolsignalsthroughthePHY.
CRS_DVmaytogglesynchronouslyattheendofthepackettoindicateCRSde-assertion.
(3)CRSONdelayismeasuredfromthefirstbitoftheJKsymbolonthePMDInputPairtoinitialassertionofCRS_DV.
(4)CRSOFFdelayismeasuredfromthefirstbitoftheTRsymbolonthePMDInputPairtoinitialde-assertionofCRS_DV.
(5)ReceiveLatencyismeasuredfromthefirstbitofthesymbolpaironthePMDInputPair.
TypicalvaluesarewiththeElasticityBuffersettothedefaultvalue(01).
(6)EnablingIEEE1588ReceiveTimestampinsertionwillincreasetheReceiveDataLatencyby40bittimes.
(7)EnablingPHYStatusFrameswillintroducevariabilityinReceiveDataLatencyduetoinsertionofPHYStatusFramesintothereceivedatapath.
Figure4-26.
RMIIReceiveTiming(SlaveMode)36ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
31ACSpecifications—RMIIReceiveTiming(MasterMode)ParameterDescription(1)NotesMinTypMaxUnitsT2.
27.
1RX_CLK,TX_CLK,CLK_OUT50MHzReferenceClock20nsClockPeriodT2.
27.
2RXD[1:0],CRS_DV,RX_DVand214nsRX_ERoutputdelayfromRX_CLK,TX_CLK,CLK_OUTrisingedge(2)T2.
27.
3CRSONdelay(3)100BASE-TXmode18.
5bits100BASE-FXmode9T2.
27.
4CRSOFFdelay(4)100BASE-TXmode27bits100BASE-FXmode17T2.
27.
5RXD[1:0]andRX_ERlatency(5)100BASE-TXmode38bits100BASE-FXmode27(1)PertheRMIISpecification,outputdelaysassumea25pFload.
(2)CRS_DVisassertedasynchronouslyinordertominimizelatencyofcontrolsignalsthroughthePHY.
CRS_DVmaytogglesynchronouslyattheendofthepackettoindicateCRSde-assertion.
(3)CRSONdelayismeasuredfromthefirstbitoftheJKsymbolonthePMDInputPairtoinitialassertionofCRS_DV.
(4)CRSOFFdelayismeasuredfromthefirstbitoftheTRsymbolonthePMDInputPairtoinitialde-assertionofCRS_DV.
(5)ReceiveLatencyismeasuredfromthefirstbitofthesymbolpaironthePMDInputPair.
TypicalvaluesarewiththeElasticityBuffersettothedefaultvalue(01).
Figure4-27.
RMIIReceiveTiming(MasterMode)4.
32ACSpecifications—RX_CLKTiming(RMIIMasterMode)ParameterDescriptionNotesMinTypMaxUnitsT2.
28.
1RX_CLKHighTime(1)12nsT2.
28.
2RX_CLKLowTime(1)8nsT2.
28.
3RX_CLKPeriod20ns(1)TheHighTimeandLowTmewilladdupto20ns.
Figure4-28.
RX_CLKTiming(RMIIMasterMode)Copyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications37SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com4.
33ACSpecifications—CLK_OUTTiming(RMIISlaveMode)ParameterDescriptionNotesMinTypMaxUnitsT2.
29.
1CLK_OUTHigh/LowTime10nsT2.
29.
2CLK_OUTpropagationdelayRelativetoX18nsFigure4-29.
CLK_OUTTiming(RMIISlaveMode)4.
34ACSpecifications—SingleClockMII(SCMII)TransmitTimingParameterDescriptionNotesMinTypMaxUnitsT2.
30.
1X1ClockPeriod25MHzReferenceClock40nsT2.
30.
2TXD[3:0],TX_ENDataSetupToX1risingedge4nsT2.
30.
3TXD[3:0],TX_ENDataHoldFromX1risingedge2nsT2.
30.
4X1ClocktoPMDOutputPair100BASE-TXor100BASE-FX13bitsLatency(100Mb)(1)(1)LatencymeasurementismadefromtheX1risingedgetothefirstbitofsymbol.
Figure4-30.
SingleClockMII(SCMII)TransmitTiming38ElectricalSpecificationsCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20134.
35ACSpecifications—SingleClockMII(SCMII)ReceiveTimingParameterDescriptionNotesMinTypMaxUnitsT2.
31.
1X1ClockPeriod25MHzReferenceClock(1)40nsT2.
31.
2RXD[3:0],RX_DVandRX_ERoutputFromX1risingedge218nsdelay(2)T2.
31.
3CRSONdelay(3)100BASE-TXmode19bits100BASE-FXmode9T2.
31.
4CRSOFFdelay(4)100BASE-TXmode26bits100BASE-FXmode16T2.
31.
5RXD[3:0]andRX_ERlatency(5)100BASE-TXmode56bits100BASE-FXmode46(1)CRSisassertedandde-assertedasynchronouslyrelativetothereferenceclock.
(2)Outputdelaysassumea25pFload.
(3)CRSONdelayismeasuredfromthefirstbitoftheJKsymbolonthePMDInputPairtoassertionofCRS_DV.
(4)CRSOFFdelayismeasuredfromthefirstbitoftheTRsymbolonthePMDInputPairtode-assertionofCRS_DV.
(5)ReceiveLatencyismeasuredfromthefirstbitofthesymbolpaironthePMDInputPair.
TypicalvaluesarewiththeElasticityBuffersettothedefaultvalue(01).
Figure4-31.
SingleClockMII(SCMII)ReceiveTiming4.
36ACSpecifications—100Mb/sX1toTX_CLKTimingParameterDescriptionNotesMinTypMaxUnitsT2.
32.
1X1toTX_CLKdelay(1)100Mb/sNormalmode05ns(1)X1toTX_CLKtimingisprovidedtosupportdevicesthatuseX1insteadofTX_CLKasthereferencefortransmitMIIdata.
Figure4-32.
100Mb/sX1toTX_CLKTimingCopyright2007–2013,TexasInstrumentsIncorporatedElectricalSpecifications39SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com5ConfigurationThissectionincludesinformationonthevariousconfigurationoptionsavailablewiththeDP83640.
Theconfigurationoptionsdescribedbelowinclude:MediaConfigurationAuto-NegotiationPHYAddressandLEDsHalfDuplexvs.
FullDuplexIsolatemodeLoopbackmodeBIST5.
1MediaConfigurationTheDP83640supportsbothTwisterPair(100BASE-TXand10BASE-T)andFiber(100BASE-FX)media.
TheportmaybeconfiguredforTwistedPair(TP)orFiber(FX)operationbystrapoptionorbyregisteraccess.
Atpower-up/reset,thestateoftheRX_ERpinwillselectthemediafortheport.
Thedefaultselectionistwistedpairmode,whileanexternalpull-downwillselectFXmodeofoperation.
StrappingtheportintoFXmodealsoautomaticallysetstheFar-EndFaultEnable,bit3ofPCSR(16h),theScrambleBypass,bit1ofPCSR(16h)andtheDescramblerBypass,bit0ofPCSR(16h).
Inaddition,themediaselectionmaybecontrolledbywritingtobit6,FX_EN,ofPCSR(16h).
5.
2Auto-NegotiationTheAuto-Negotiationfunctionprovidesamechanismforexchangingconfigurationinformationbetweentwoendsofalinksegmentandautomaticallyselectingthehighestperformancemodeofoperationsupportedbybothdevices.
FastLinkPulse(FLP)BurstsprovidethesignallingusedtocommunicateAuto-Negotiationabilitiesbetweentwodevicesateachendofalinksegment.
ForfurtherdetailregardingAuto-Negotiation,refertoClause28oftheIEEE802.
3uspecification.
TheDP83640supportsfourdifferentEthernetprotocols(10Mb/sHalfDuplex,10Mb/sFullDuplex,100Mb/sHalfDuplex,and100Mb/sFullDuplex),sotheinclusionofAuto-NegotiationensuresthatthehighestperformanceprotocolwillbeselectedbasedontheadvertisedabilityoftheLinkPartner.
TheAuto-NegotiationfunctionwithintheDP83640canbecontrolledeitherbyinternalregisteraccessorbytheuseoftheAN_EN,AN1andAN0pins.
5.
2.
1Auto-NegotiationPinControlThestateofAN_EN,AN0andAN1determineswhethertheDP83640isforcedintoaspecificmodeorAuto-Negotiationwilladvertiseaspecificability(orsetofabilities)asgiveninTable5-1.
Thesepinsallowconfigurationoptionstobeselectedwithoutrequiringinternalregisteraccess.
ThestateofAN_EN,AN0andAN1,uponpower-up/reset,determinesthestateofbits[8:5]oftheANARregister.
TheAuto-Negotiationfunctionselectedatpower-uporresetcanbechangedatanytimebywritingtotheBasicModeControlRegister(BMCR)ataddress00h.
40ConfigurationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table5-1.
Auto-NegotiationModesAN_ENAN1AN0ForcedMode00010BASE-T,Half-Duplex00110BASE-T,Full-Duplex010100BASE-TX,Half-Duplex011100BASE-TX,Full-DuplexAN_ENAN1AN0AdvertisedMode10010BASE-T,Half/Full-Duplex101100BASE-TX,Half/Full-Duplex110100BASE-TXFull-Duplex11110BASE-T,Half/Full-Duplex100BASE-TX,Half/Full-Duplex5.
2.
2Auto-NegotiationRegisterControlWhenAuto-Negotiationisenabled,theDP83640transmitstheabilitiesprogrammedintotheAuto-NegotiationAdvertisementregister(ANAR)ataddress04hviaFLPBursts.
Anycombinationof10Mb/s,100Mb/s,Half-Duplex,andFullDuplexmodesmaybeselected.
Auto-NegotiationPriorityResolution:1.
100BASE-TXFullDuplex(HighestPriority)2.
100BASE-TXHalfDuplex3.
10BASE-TFullDuplex4.
10BASE-THalfDuplex(LowestPriority)TheBasicModeControlRegister(BMCR)ataddress00hprovidescontrolforenabling,disabling,andrestartingtheAuto-Negotiationprocess.
WhenAuto-Negotiationisdisabled,theSPEEDSELECTIONbitintheBMCRcontrolsswitchingbetween10Mb/sor100Mb/soperation,andtheDUPLEXMODEbitcontrolsswitchingbetweenfullduplexoperationandhalfduplexoperation.
TheSPEEDSELECTIONandDUPLEXMODEbitshavenoeffectonthemodeofoperationwhentheAuto-NegotiationEnablebitisset.
TheLinkSpeedcanbeexaminedthroughthePHYStatusRegister(PHYSTS)ataddress10hafteraLinkisachieved.
TheBasicModeStatusRegister(BMSR)indicatesthesetofavailableabilitiesfortechnologytypes,Auto-Negotiationability,andExtendedRegisterCapability.
ThesebitsarepermanentlysettoindicatethefullfunctionalityoftheDP83640(onlythe100BASE-T4bitisnotsetsincetheDP83640doesnotsupportthatfunction).
TheBMSRalsoprovidesstatuson:WhetherornotAuto-NegotiationiscompleteWhetherornottheLinkPartnerisadvertisingthataremotefaulthasoccurredWhetherornotvalidlinkhasbeenestablishedSupportforManagementFramePreamblesuppressionTheAuto-NegotiationAdvertisementRegister(ANAR)indicatestheAuto-NegotiationabilitiestobeadvertisedbytheDP83640.
Allavailableabilitiesaretransmittedbydefault,butanyabilitycanbesuppressedbywritingtotheANAR.
UpdatingtheANARtosuppressanabilityisonewayforamanagementagenttochange(restrict)thetechnologythatisused.
TheAuto-NegotiationLinkPartnerAbilityRegister(ANLPAR)ataddress05hisusedtoreceivethebaselinkcodewordaswellasallnextpagecodewordsduringthenegotiation.
Furthermore,theANLPARwillbeupdatedtoeither0081hor0021hforparalleldetectiontoeither100Mb/sor10Mb/srespectively.
TheAuto-NegotiationExpansionRegister(ANER)indicatesadditionalAuto-Negotiationstatus.
TheANERprovidesstatuson:Copyright2007–2013,TexasInstrumentsIncorporatedConfiguration41SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comWhetherornotaParallelDetectFaulthasoccurredWhetherornottheLinkPartnersupportstheNextPagefunctionWhetherornottheDP83640supportstheNextPagefunctionWhetherornotthecurrentpagebeingexchangedbyAuto-NegotiationhasbeenreceivedWhetherornottheLinkPartnersupportsAuto-Negotiation5.
2.
3Auto-NegotiationParallelDetectionTheDP83640supportstheParallelDetectionfunctionasdefinedintheIEEE802.
3uspecification.
ParallelDetectionrequiresboththe10Mb/sand100Mb/sreceiverstomonitorthereceivesignalandreportlinkstatustotheAuto-Negotiationfunction.
Auto-NegotiationusesthisinformationtoconfigurethecorrecttechnologyintheeventthattheLinkPartnerdoesnotsupportAuto-Negotiationbutistransmittinglinksignalsthatthe100BASE-TXor10BASE-TPMAsrecognizeasvalidlinksignals.
IftheDP83640completesAuto-NegotiationasaresultofParallelDetection,bits5and7withintheANLPARregisterwillbesettoreflectthemodeofoperationpresentintheLinkPartner.
Notethatbits4:0oftheANLPARwillalsobesetto00001basedonasuccessfulparalleldetectiontoindicateavalid802.
3selectorfield.
SoftwaremaydeterminethatnegotiationcompletedviaParallelDetectionbyreadingazerointheLinkPartnerAuto-NegotiationAblebitoncetheAuto-NegotiationCompletebitisset.
Ifconfiguredforparalleldetectmodeandanyconditionotherthanasinglegoodlinkoccursthentheparalleldetectfaultbitwillbeset.
5.
2.
4Auto-NegotiationRestartOnceAuto-Negotiationhascompleted,itmayberestartedatanytimebysettingbit9(RestartAuto-Negotiation)oftheBMCRtoone.
IfthemodeconfiguredbyasuccessfulAuto-Negotiationlosesavalidlink,thentheAuto-Negotiationprocesswillresumeandattempttodeterminetheconfigurationforthelink.
Thisfunctionensuresthatavalidconfigurationismaintainedifthecablebecomesdisconnected.
Arenegotiationrequestfromanyentity,suchasamanagementagent,willcausetheDP83640tohaltanytransmitdataandlinkpulseactivityuntilthebreak_link_timerexpires(~1500ms).
Consequently,theLinkPartnerwillgointolinkfailandnormalAuto-Negotiationresumes.
TheDP83640willresumeAuto-Negotiationafterthebreak_link_timerhasexpiredbyissuingFLP(FastLinkPulse)bursts.
5.
2.
5EnablingAuto-NegotiationviaSoftwareItisimportanttonotethatiftheDP83640hasbeeninitializeduponpower-upasanon-auto-negotiatingdevice(forcedtechnology),anditisthenrequiredthatAuto-Negotiationorre-Auto-Negotiationbeinitiatedviasoftware,bit12(Auto-NegotiationEnable)oftheBasicModeControlRegister(BMCR)mustfirstbeclearedandthensetforanyAuto-Negotiationfunctiontotakeeffect.
5.
2.
6Auto-NegotiationCompleteTimeParalleldetectionandAuto-Negotiationtakeapproximately2-3secondstocomplete.
Inaddition,Auto-Negotiationwithnextpageshouldtakeapproximately2-3secondstocomplete,dependingonthenumberofnextpagessent.
RefertoClause28oftheIEEE802.
3ustandardforafulldescriptionoftheindividualtimersrelatedtoAuto-Negotiation.
5.
3Auto-MDIXWhenenabled,thisfunctionutilizesAuto-NegotiationtodeterminetheproperconfigurationfortransmissionandreceptionofdataandsubsequentlyselectstheappropriateMDIpairforMDI/MDIXoperation.
Thefunctionusesarandomseedtocontrolswitchingofthecrossovercircuitry.
ThisimplementationcomplieswiththecorrespondingIEEE802.
3Auto-NegotiationandCrossoverSpecifications.
Auto-MDIXisenabledbydefaultandcanbeconfiguredviaPHYCR(19h)register,bits[15:14].
42ConfigurationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013NeitherAuto-NegotiationnorAuto-MDIXisrequiredtobeenabledinforcingcrossoveroftheMDIpairs.
ForcedcrossovercanbeachievedthroughtheFORCE_MDIXbit,bit14ofPHYCR(19h)register.
NOTE:Auto-MDIXwillnotworkinaforcedmodeofoperation.
5.
4PHYAddressThefivePHYaddressstrappingpinsaresharedwiththeRXD[3:0]pinsandCOLpinasshownbelow.
Table5-2.
PHYAddressMappingPin#PHYADFunctionRXDFunction42PHYAD0COL43PHYAD1RXD_344PHYAD2RXD_245PHYAD3RXD_146PHYAD4RXD_0TheDP83640canbesettorespondtoanyof32possiblePHYaddressesviastrappins.
TheinformationislatchedintothePHYCRregister(address19h,bits[4:0])atdevicepower-upandhardwarereset.
EachDP83640orportsharinganMDIObusinasystemmusthaveauniquephysicaladdress.
TheDP83640supportsPHYAddressstrappingvalues0()through31().
StrappingPHYAddress0putsthepartintoIsolateMode.
ItshouldalsobenotedthatselectingPHYAddress0viaanMDIOwritetoPHYCRwillnotputthedeviceinIsolateMode.
SeeSection10.
2.
6formoreinformation.
Forfurtherdetailrelatingtothelatch-intimingrequirementsofthePHYAddresspins,aswellastheotherhardwareconfigurationpins,refertotheResetsummaryinSection8.
SincethePHYAD[0]pinhasweakinternalpull-upresistorandPHYAD[4:1]pinshaveweakinternalpull-downresistors,thedefaultsettingforthePHYaddressis00001(01h).
RefertoFigure5-1foranexampleofaPHYADconnectiontoexternalcomponents.
Inthisexample,thePHYADstrappingresultsinaddress00011(03h).
Figure5-1.
PHYADStrappingExample5.
4.
1MIIIsolateModeItisrecommendedthattheuserhaveabasicunderstandingofClause22ofthe802.
3ustandard.
TheDP83640canbeputintoMIIIsolateModebywritinga1tobit10oftheBMCRregister.
StrappingthePHYAddressto0willforcethedeviceintoIsolateModewhenpoweredup.
ItshouldbenotedthatselectingPhysicalAddress0viaanMDIOwritetoPHYCRwillnotputthedeviceintheMIIisolatemode.
Copyright2007–2013,TexasInstrumentsIncorporatedConfiguration43SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comWhenintheMIIIsolateMode,theDP83640doesnotrespondtopacketdatapresentatTXD[3:0]andTX_ENinputsandpresentsahighimpedanceontheTX_CLK,RX_CLK,RX_DV,RX_ER,RXD[3:0],COL,andCRS/CRS_DVoutputs.
WheninIsolateMode,theDP83640willcontinuetorespondtoallserialmanagementtransactionsovertheMII.
WhileinIsolateMode,thePMDoutputpairwillnottransmitpacketdatabutwillcontinuetosource100BASE-TXscrambledidlesor10BASE-Tnormallinkpulses.
TheDP83640canAuto-NegotiateorparalleldetecttoaspecifictechnologydependingonthereceivesignalatthePMDinputpair.
AvalidlinkcanbeestablishedforthereceiverevenwhentheDP83640isinIsolateMode.
5.
4.
2BroadcastModeTheDP83640isalsocapableofacceptingbroadcastmessages(registerwritestoPHYaddress0x1F).
SettingtheBC_WRITEto1,bit11ofthePHYControlRegister2(PHYCR2)ataddress0x1C,willconfigurethedevicetoacceptbroadcastmessagesindependentofthelocalPHYAddressvalue.
5.
5LEDInterfaceTheDP83640supportsthreeconfigurableLightEmittingDiode(LED)pins:LED_LINK,LED_SPEED/FX_SD,andLED_ACT.
SeveralfunctionscanbemultiplexedontothethreeLEDsusingthreedifferentmodesofoperation.
TheLEDoperationmodecanbeselectedbywritingtotheLED_CFG[1:0]registerbitsinthePHYControlRegister(PHYCR)ataddress19h,bits[6:5].
LED_CFG[1]isonlycontrollablethroughregisteraccessandcannotbesetbyastrappin.
SeeTable5-3forLEDModeselection.
Table5-3.
LEDModeSelectionModeLED_CFG[1]LED_CFG[0]LED_LINKLED_SPEEDLED_ACT1don'tcare1ONforGoodLinkONin100Mb/sONforActivityOFFforNoLinkOFFin10Mb/sOFFforNoActivity200ONforGoodLinkONin100Mb/sONforCollisionBLINKforActivityOFFin10Mb/sOFFforNoCollision310ONforGoodLinkONin100Mb/sONforFullDuplexBLINKforActivityOFFin10Mb/sOFFforHalfDuplexTheLED_LINKpininMode1indicatesthelinkstatusoftheport.
In100BASE-TXmode,linkisestablishedasaresultofinputreceiveamplitudecompliantwiththeTP-PMDspecificationswhichwillresultininternalgenerationofsignaldetect.
A10Mb/sLinkisestablishedasaresultofthereceptionofatleastsevenconsecutivenormalLinkPulsesorthereceptionofavalid10BASE-Tpacket.
ThiswillcausetheassertionofLED_LINK.
LED_LINKwilldeassertinaccordancewiththeLinkLossTimerasspecifiedintheIEEE802.
3specification.
In100BASE-TXmode,anoptionalfastlinklossdetectionmaybeenabledbysettingtheSD_TIMEcontrolintheSD_CNFGregister.
EnablingfastlinklossdetectionwillresultintheLED_LINKdeassertionwithinapproximately1.
3soflossofsignalonthewire.
TheLED_LINKpininMode1willbeOFFwhennoLINKispresent.
TheLED_LINKpininMode2andMode3willbeONtoindicateLinkisgoodandBLINKtoindicateactivityispresentonactivity.
TheBLINKfrequencyisdefinedinBLINK_FREQ,bits[7:6]ofregisterLEDCR(18h).
ActivityisdefinedasconfiguredinLEDACT_RX,bit8ofregisterLEDCR(18h).
IfLEDACT_RXis0,Activityissignaledforeithertransmitorreceive.
IfLEDACT_RXis1,Activityisonlysignaledforreceive.
44ConfigurationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013TheLED_SPEED/FX_SDpinindicates10or100Mb/sdatarateoftheport.
ThestandardCMOSdrivergoeshighwhenoperatingin100Mb/soperation.
ThefunctionalityofthisLEDisindependentofmodeselected.
TheLED_ACTpininMode1indicatesthepresenceofeithertransmitorreceiveactivity.
TheLEDwillbeONforActivityandOFFforNoActivity.
InMode2,thispinindicatestheCollisionstatusoftheport.
TheLEDwillbeONforCollisionandOFFforNoCollision.
TheLED_ACTpininMode3indicatesDuplexstatusfor10Mb/sor100Mb/soperation.
TheLEDwillbeONforFullDuplexandOFFforHalfDuplex.
In10Mb/shalfduplexmode,thecollisionLEDisbasedontheCOLsignal.
SincetheseLEDpinsarealsousedasstrapoptions,thepolarityoftheLEDisdependentonwhetherthepinispulledupordown.
5.
5.
1LEDsSincetheAuto-Negotiation(AN)strapoptionssharetheLEDoutputpins,theexternalcomponentsrequiredforstrappingandLEDusagemustbeconsideredinordertoavoidcontention.
Specifically,whentheLEDoutputsareusedtodriveLEDsdirectly,theactivestateofeachoutputdriverisdependentonthelogiclevelsampledbythecorrespondingANinputuponpower-up/reset.
Forexample,ifagivenANinputisresistivelypulledlowthenthecorrespondingoutputwillbeconfiguredasanactivehighdriver.
Conversely,ifagivenANinputisresistivelypulledhigh,thenthecorrespondingoutputwillbeconfiguredasanactivelowdriver.
RefertoFigure5-2foranexampleofANconnectionstoexternalcomponents.
Inthisexample,theANstrappingresultsinAuto-Negotiationdisabledwith100Full-Duplexforced.
TheadaptivenatureoftheLEDoutputshelpstosimplifypotentialimplementationissuesofthesedualpurposepins.
Figure5-2.
ANStrappingandLEDLoadingExample5.
5.
2LEDDirectControlTheDP83640providesanotheroptiontodirectlycontrolanyorallLEDoutputsthroughtheLEDDirectControlRegister(LEDCR),address18h.
TheregisterdoesnotprovidereadaccesstoLEDs.
Copyright2007–2013,TexasInstrumentsIncorporatedConfiguration45SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com5.
6HalfDuplexvs.
fullDuplexTheDP83640supportsbothhalfandfullduplexoperationatboth10Mb/sand100Mb/sspeeds.
Half-duplexreliesontheCSMA/CDprotocoltohandlecollisionsandnetworkaccess.
InHalf-Duplexmode,CarrierSense(CRS)respondstobothtransmitandreceiveactivityinordertomaintaincompliancewiththeIEEE802.
3specification.
SincetheDP83640isdesignedtosupportsimultaneoustransmitandreceiveactivityitiscapableofsupportingfull-duplexswitchedapplicationswithathroughputofupto200Mb/swhenoperatingineither100BASE-TXor100BASE-FX.
BecausetheCSMA/CDprotocoldoesnotapplytofull-duplexoperation,theDP83640disablesitsowninternalcollisionsensingandreportingfunctionsandmodifiesthebehaviorofCRSsuchthatitindicatesonlyreceiveactivity.
Thisallowsafull-duplexcapableMACtooperateproperly.
Allmodesofoperation(100BASE-TX,100BASE-FX,10BASE-T)canruneitherhalf-duplexorfull-duplex.
Additionally,otherthanCRSandcollisionreporting,allremainingMIIsignalingremainsthesameregardlessoftheselectedduplexmode.
ItisimportanttounderstandthatwhileAuto-NegotiationwiththeuseofFastLinkPulsecodewordscaninterpretandconfiguretofull-duplexoperation,paralleldetectioncannotrecognizethedifferencebetweenfullandhalf-duplexfromafixed10Mb/sor100Mb/slinkpartnerovertwistedpair.
Asspecifiedinthe802.
3uspecification,ifafar-endlinkpartnerisconfiguredtoaforcedfull-duplex100BASE-TXability,theparalleldetectionstatemachineinthepartnerwouldbeunabletodetectthefull-duplexcapabilityofthefar-endlinkpartner.
Thislinksegmentwouldnegotiatetoahalf-duplex100BASE-TXconfiguration(samescenariofor10Mb/s).
Auto-Negotiationisnotsupportedin100BASE-FXoperation.
SelectionofHalforFull-duplexoperationiscontrolledbybit8oftheBasicModeControlRegister(BMCR),address00h.
If100BASE-FXmodeisstrappedusingtheRX_ERpin,theAN0strapvalueisusedtosetthevalueofbit8oftheBMCR(00h)register.
NotethattheotherAuto-Negotiationstrappins(AN_ENandAN1)areignoredin100BASE-FXmode.
5.
7InternalLoopbackTheDP83640includesaLoopbackTestmodeforfacilitatingsystemdiagnostics.
TheLoopbackmodeisselectedthroughbit14(Loopback)oftheBasicModeControlRegister(BMCR).
Writing1tothisbitenablesMIItransmitdatatoberoutedtotheMIIreceiveoutputs.
Loopbackstatusmaybecheckedinbit3ofthePHYStatusRegister(PHYSTS).
WhileinLoopbackmodethedatawillnotbetransmittedontothemedia.
Toensurethatthedesiredoperatingmodeismaintained,Auto-NegotiationshouldbedisabledbeforeselectingtheLoopbackmode.
5.
8PowerDown/InterruptThePowerDownandInterruptfunctionsaremultiplexedonpin7ofthedevice.
Bydefault,thispinfunctionsasapowerdowninputandtheinterruptfunctionisdisabled.
Settingbit0(INT_OE)ofMICR(11h)willconfigurethepinasanactivelowinterruptoutput.
5.
8.
1PowerDownControlModeThePWRDOWN/INTNpincanbeassertedlowtoputthedeviceinaPowerDownmode.
Thisisequivalenttosettingbit11(POWERDOWN)intheBasicModeControlRegister,BMCR(00h).
Anexternalcontrolsignalcanbeusedtodrivethepinlow,overcomingtheweakinternalpull-upresistor.
Alternatively,thedevicecanbeconfiguredtoinitializeintoaPowerDownstatebyuseofanexternalpull-downresistoronthePWRDOWN/INTNpin.
Sincethedevicewillstillrespondtomanagementregisteraccesses,settingtheINT_OEbitintheMICRregisterwilldisablethePWRDOWN/INTNinput,allowingthedevicetoexitthePowerDownstate.
46ConfigurationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20135.
8.
2InterruptMechanismsTheinterruptfunctioniscontrolledviaregisteraccess.
Allinterruptsourcesaredisabledbydefault.
Settingbit1(INTEN)ofMICR(11h)willenableinterruptstobeoutput,dependentontheinterruptmasksetinthelowerbyteoftheMISR(12h).
ThePWRDOWN/INTNpinisasynchronouslyassertedlowwhenaninterruptconditionoccurs.
ThesourceoftheinterruptcanbedeterminedbyreadingtheupperbyteoftheMISR.
OneormorebitsintheMISRwillbeset,denotingallcurrentlypendinginterrupts.
ReadingoftheMISRclearsALLpendinginterrupts.
Example:Togenerateaninterruptonachangeoflinkstatusoronachangeofenergydetectpowerstate,thestepswouldbe:Write0003htoMICRtosetINTENandINT_OEWrite0060htoMISRtosetED_INT_ENandLINK_INT_ENMonitorPWRDOWN/INTNpinWhenPWRDOWN/INTNpinassertslow,theuserwouldreadtheMISRregistertoseeiftheED_INTorLINK_INTbitsareset,i.
e.
whichsourcecausedtheinterrupt.
AfterreadingtheMISR,theinterruptbitsshouldclearandthePWRDOWN/INTNpinwillde-assert.
5.
9EnergyDetectModeWhenEnergyDetectisenabledandthereisnoactivityonthecable,theDP83640willremaininalowpowermodewhilemonitoringthetransmissionline.
ActivityonthelinewillcausetheDP83640togothroughanormalpowerupsequence.
Regardlessofcableactivity,theDP83640willoccasionallywakeupthetransmittertoputEDpulsesontheline,butwillotherwisedrawaslittlepoweraspossible.
EnergydetectfunctionalityiscontrolledviaregisterEnergyDetectControl(EDCR),address1Dh.
5.
10LinkDiagnosticCapabilitiesTheDP83640containsseveralsystemdiagnosticcapabilitiesforevaluatinglinkqualityanddetectingpotentialcablingfaultsintwistedpaircabling.
SoftwareconfigurationisavailablethroughtheLinkDiagnosticsRegisters-Page2whichcanbeselectedviaPageSelectRegister(PAGESEL),address13h.
Thesecapabilitiesinclude:LinkedCableStatusLinkQualityMonitorTDR(TimeDomainReflectometry)CableDiagnostics5.
10.
1LinkedCableStatusInanactiveconnectionwithavalidlinkstatus,thefollowingdiagnosticcapabilitiesareavailable:PolarityreversalCableswap(MDIvsMDIX)detection100MbCableLengthEstimationFrequencyoffsetrelativetolinkpartnerCableSignalQualityEstimation5.
10.
1.
1PolarityReversalTheDP83640detectspolarityreversalbydetectingnegativelinkpulses.
ThePolarityindicationisavailableinbit12ofthePHYSTS(10h)orbit4ofthe10BTSCR(1Ah).
Invertedpolarityindicatesthepositiveandnegativeconductorsinthereceivepairareswapped.
Sincepolarityiscorrectedbythereceiver,thisdoesnotnecessarilyindicateafunctionalprobleminthecable.
Sincethepolarityindicationisdependentonlinkpulsesfromthelinkpartner,polarityindicationisonlyvalidin10Mbmodesofoperation,orin100MbAuto-Negotiatedmode.
Polarityindicationisnotavailablein100Mbforcedmodeofoperationorinaparalleldetected100Mbmode.
Copyright2007–2013,TexasInstrumentsIncorporatedConfiguration47SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com5.
10.
1.
2CableSwapIndicationAspartofAuto-Negotiation,theDP83640hastheability(usingAuto-MDIX)toautomaticallydetectacablewithswappedMDIpairsandselecttheappropriatepairsfortransmittingandreceivingdata.
NormaloperationistermedMDI,whilecrossedoperationisMDIX.
TheMDIXstatuscanbereadfrombit14ofthePHYSTS(10h).
5.
10.
1.
3100MbCableLengthEstimationTheDP83640providesamethodofestimatingcablelengthbasedonelectricalcharacteristicsofthe100Mblink.
Thisessentiallyprovidesaneffectivecablelengthratherthanameasurementofthephysicalcablelength.
Thecablelengthestimationisonlyavailablein100Mbmodeofoperationwithavalidlinkstatus.
ThecablelengthestimationisavailableattheLinkDiagnosticsRegisters-Page2,register100MbLengthDetect(LEN100_DET),address14h.
5.
10.
1.
4FrequencyOffsetRelativetoLinkPartnerAspartofthe100Mbclockrecoveryprocess,theDSPimplementationprovidesafrequencycontrolparameter.
Thisvaluemaybeusedtoindicatethefrequencyoffsetofthedevicerelativetothelinkpartner.
Thisoperationisonlyavailablein100Mboperationwithavalidlinkstatus.
Thefrequencyoffsetcanbedeterminedusingtheregister100MbFrequencyOffsetIndication(FREQ100),address15h,oftheLinkDiagnosticsRegisters-Page2.
TwodifferentversionsoftheFrequencyOffsetmaybemonitoredthroughbits[7:0]ofregisterFREQ100(15h).
Thefirstisthelong-termFrequencyOffset.
ThesecondisthecurrentFrequencyControlvalue,whichincludesshort-termphaseadjustmentsandcanprovideinformationontheamountofjitterinthesystem.
5.
10.
1.
5CableSignalQualityEstimationThecablesignalqualityestimatorkeepsasimpletrackingofresultsoftheDSPandcanbeusedtogenerateanapproximateSignal-to-NoiseRatioforthe100Mbreceiver.
ThisinformationisavailabletosoftwarethroughtheLinkDiagnosticsRegisters-Page2:VarianceControlRegister(VAR_CTRL),address1AhandVarianceDataRegister(VAR_DATA),address1Bh.
Thevariancecomputationtimes(VAR_TIMER)canbechosenfromthesetof{2,4,6,8}ms.
The32-bitvariancesumcanbereadbytwoconsecutivereadsoftheVAR_DATAregister.
ThissumcanbeusedtocomputeanSNRestimatebysoftwareusingthefollowingequation:SNR=10log10((37748736*VAR_TIMER)/Variance).
5.
10.
2LinkQualityMonitorTheLinkQualityMonitorallowsamethodtogenerateanalarmwhentheDSPadaptionstraysfromaprogrammablewindow.
Thiscouldoccurduetochangesinthecablewhichcouldindicateapotentialproblem.
SoftwarecanprogramthresholdsforthefollowingDSPparameterstobeusedtointerruptthesystem:DigitalEqualizerC1Coefficient(DEQC1)DigitalAdaptiveGainControl(DAGC)DigitalBase-LineWanderControl(DBLW)RecoveredClockLong-TermFrequencyOffset(FREQ)RecoveredClockFrequencyControl(FC)Signal-to-NoiseRatio(SNR)VarianceSoftwareisexpectedtoreadinitialadaptedvaluesandthenprogramthethresholdsbasedonanexpectedvalidrange.
ThismechanismtakesadvantageofthefactthattheDSPadaptationshouldremaininarelativelysmallrangeonceavalidlinkhasbeenestablished.
48ConfigurationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20135.
10.
2.
1LinkQualityMonitorControlandStatusControloftheLinkQualityMonitorisdonethroughtheLinkQualityMonitorRegister(LQMR),address1DhandtheLinkQualityDataRegister(LQDR),address1BhoftheLinkDiagnosticsRegisters-Page2.
TheLQMRregisterincludesaglobalenabletoenabletheLinkQualityMonitorfunction.
Inaddition,itprovideswarningstatusfrombothhighandlowthresholdsforeachofthemonitoredparametersexceptSNRVariance.
.
TheLQMR2registerprovideswarningstatusforthehighthresholdofSNRVariance(upper16bits);thereisnolowthreshold.
Notethatindividualloworhighparameterthresholdcomparisonscanbedisabledbysettingtotheminimumormaximumvalues.
ToallowtheLinkQualityMonitortointerruptthesystem,theInterruptmustbeenabledthroughtheinterruptcontrolregisters,MICR(11h)andMISR(12h).
TheLinkQualityMonitormayalsobeusedtoautomaticallyresettheDSPandrestartadaption.
SeparateenablebitsinLQMRandLQMR2allowforautomaticresetbasedoneachoftheparametervalues.
Ifenabled,aviolationofoneofthethresholdswillresultinarestartoftheDSPadaption.
InadditionifthePCSR:SD_OPTIONregisterbitissetto0,theviolationwillalsoresultinadropinLinkStatus.
5.
10.
2.
2CheckingCurrentParameterValuesPriortosettingThresholdvalues,itisrecommendedthatsoftwarecheckcurrentadaptedvalues.
Thethresholdsmaythenbesetrelativetotheadaptedvalues.
ThecurrentadaptedvaluescanbereadusingtheLQDRregisterbysettingtheSAMPLE_PARAMbit[13]ofLQDR,address(1Eh).
Forexample,toreadtheDBLWcurrentvalue:1.
Write2400htoLQDR(1Eh)tosettheSAMPLE_PARAMbitandsettheLQ_PARAM_SEL[2:0]to010.
2.
ReadLQDR(1Eh).
CurrentDBLWvalueisreturnedinthelow8bits.
5.
10.
2.
3ThresholdControlTheLQDR(1Eh)registeralsoprovidesamethodofprogramminghighandlowthresholdsforeachofthefiveparametersthatcanbemonitored.
Theregisterimplementsanindirectread/writemechanism.
Writesareaccomplishedbywritingdata,address,andawritestrobetotheregister.
Readsareaccomplishedbywritingtheaddresstotheregister,andreadingbackthevalueoftheselectedthreshold.
Settingthresholdstothemaximumorminimumvalueswilldisablethethresholdcomparisonsincevalueshavetoexceedthethresholdtogenerateawarningcondition.
Warningsarenotgeneratediftheparameterisequaltothethreshold.
Bydefault,allthresholdsaredisabledbysettingtotheminimumormaximumvalues.
TheTable5-4showsthefiveparametersandrangeofvalues:Table5-4.
LinkQualityMonitorParameterRangesParameterMinimumValueMaximumValueMin(2-scomp)Max(2-scomp)DEQ_C1-128+1270x800x7FDAGC0+2550x000xFFDBLW-128+1270x800x7FFrequencyOffset-128+1270x800x7FFrequencyControl-128+1270x800x7FSNRVariance0+23040x00000x900Notethatvaluesaresigned2-scomplementvaluesexceptforDAGCandVariancewhicharealwayspositive.
ThemaximumSNRVarianceiscalculatedbyassumingtheworst-casesquarederror(144)isaccumulatedevery8nsfor8*220ns(roughly8msorexactly1,048,576clockcycles).
Forexample,tosettheDBLWLowthresholdto-38:1.
Write14DAhtoLQDRtosettheWrite_LQ_Thrbit,selecttheDBLWLowThreshold,andwritedataof-38(0xDA).
Copyright2007–2013,TexasInstrumentsIncorporatedConfiguration49SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com2.
Write8000toLQMRtoenabletheLinkQualityMonitor(ifnotalreadyenabled).
5.
10.
3TDRCableDiagnosticsTheDP83640implementsaTimeDomainReflectometry(TDR)methodofcablelengthmeasurementandevaluationwhichcanbeusedtoevaluateaconnectedtwistedpaircable.
TheTDRimplementationinvolvessendingapulseoutoneithertheTransmitorReceiveconductorpairandobservingtheresultsoneitherpair.
Byobservingthetypesandstrengthofreflectionsoneachpair,softwarecandeterminethefollowing:CableshortCableopenDistancetofaultIdentifywhichpairhasafaultPairskewTheTDRcablediagnosticsworksbestincertainconditions.
Forexample,anunterminatedcableprovidesagoodreflectionformeasuringcablelength,whileacablewithanidealterminationtoanunpoweredpartnermayprovidenoreflectionatall.
5.
10.
4TDRPulseGeneratorTheTDRimplementationcansendtwotypesofTDRpulses.
Thefirstoptionistosend50nsor100nslinkpulsesfromthe10MbCommonDriver.
Thesecondoptionistosendpulsesfromthe100MbCommonDriverin8nsincrementsupto56nsinwidth.
The100Mbpulseswillalternatebetweenpositiveandnegativepulses.
Theshorterpulsesprovidebetterabilitytomeasureshortcablelengths,especiallysincetheywilllimitoverlapbetweenthetransmittedpulseandareflectedpulse.
Thelongerpulsesmayprovidebettermeasurementsoflongcablelengths.
Inaddition,ifthepulsewidthisprogrammedto0,nopulsewillbesent,butthemonitorcircuitwillstillbeactivated.
Thisallowssamplingofbackgrounddatatoprovideabaselineforanalysis.
5.
10.
5TDRPulseMonitorTheTDRfunctionmonitorsdatafromtheAnalogtoDigitalConverter(ADC)todetectbothpeakvaluesandvaluesaboveaprogrammablethreshold.
Itcanbeprogrammedtodetectmaximumorminimumvalues.
Inaddition,itrecordsthetime,in8nsintervals,atwhichthepeakorthresholdvaluefirstoccurs.
TheTDRmonitorimplementsatimerthatstartswhenthepulseistransmitted.
Awindowmaybeenabledtoqualifyincomingdatatolookforresponseonlyinadesiredrange.
Thisisespeciallyusefulforeliminatingthetransmittedpulse,butalsomaybeusedtolookformultiplereflections.
5.
10.
6TDRControlInterfaceTheTDRControlInterfaceisimplementedintheLinkDiagnosticsRegisters-Page2throughTDRControl(TDR_CTRL),address16handTDRWindow(TDR_WIN),address17h.
Thefollowingbasiccontrolsare:TDREnable:Enablebit15ofTDR_CTRL(16h)toallowtheTDRfunction.
ThisbypassesnormaloperationandgivescontroloftheCD10andCD100blocktotheTDRfunction.
TDRSendPulse:Enablebit11ofTDR_CTRL(16h)tosendtheTDRpulseandstartstheTDRMonitorThefollowingtransmitmodecontrolsareavailable:TransmitMode:Enablesuseof10MbLinkpulsesfromthe10MbCommonDriverordatapulsesfromthe100MbCommonDriverbyenablingTDR_100Mb,bit14ofTDR_CRTL(16h).
TransmitPulseWidth:Bits[10:8]ofTDR_CTRL(16h)allowssendingof0to7clockwidthpulses.
Actualpulsesaredependentonthetransmitmode.
Ifthepulsewidthissetto0,thennopulsewillbesent.
50ConfigurationCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013TransmitChannelSelect:Thetransmittercansendpulsesdowneitherthetransmitpairorthereceivepairbyenablingbit13ofTDR_CTRL(16h).
Defaultvalueistoselectthetransmitpair.
Thefollowingreceivemodecontrolsareavailable:Min/MaxModeControl:Bit7ofTDR_CTRL(16h)controlstheTDRMonitoroperation.
Indefaultmode,themonitorwilldetectmaximum(positive)values.
InMinMode,themonitorwilldetectminimum(negative)values.
ReceiveChannelSelect:Thereceivercanmonitoreitherthetransmitpairorthereceivepairbyenablingbit12ofTDR_CTRL(16h).
Defaultvalueistoselectthetransmitpair.
ReceiveWindow:ThereceivercanmonitorreceivedatawithinaprogrammablewindowusingtheTDRWindowRegister(TDR_WIN),address17h.
Thewindowiscontrolledbytworegistervalues:TDRStartWindow,bits[15:8]ofTDR_WIN(17h)andTDRStopWindow,bits[7:0]ofTDR_WIN(17h).
TheTDRStartWindowindicatesthefirstclocktostartsampling.
TheTDRStopWindowindicatesthelastclocktosample.
Bydefault,thefullwindowisenabled,withStartsetto0andStopsetto255.
Thewindowrangeisin8nsclockincrements,sothemaximumwindowsizeis2048ns.
5.
10.
7TDRResultsTheresultsofaTDRpeakandthresholdmeasurementareavailableintheTDRPeakMeasurementRegister(TDR_PEAK),address18handTDRThresholdMeasurementRegister(TDR_THR),address19h.
Thethresholdmeasurementmaybeamoreaccuratemethodofmeasuringthelengthoflongercablessinceitprovidesabetterindicationofthestartofthereceivedpulse,ratherthanthepeakvalue.
SoftwareutilizingtheTDRfunctionshouldimplementanalgorithmtosendTDRpulsesandevaluateresults.
Multiplerunsshouldbeusedtobestqualifyanyreceivedpulsesasmultiplereflectionscouldexist.
Inaddition,whenmonitoringthetransmittingpair,thewindowfeatureshouldbeusedtodisqualifythetransmittedpulse.
Multiplerunsmayalsobeusedtoaveragethevaluesprovidingmoreaccurateresults.
Actualdistancemeasurementsaredependentonthevelocityofpropagationofthecable.
Thedelayvalueistypicallyontheorderof4.
6to4.
9ns/m.
5.
11BISTTheDP83640incorporatesaninternalBuilt-inSelfTest(BIST)circuittoaccommodatein-circuittestingordiagnostics.
TheBISTcircuitcanbeutilizedtotesttheintegrityofthetransmitandreceivedatapaths.
BISTtestingcanbeperformedwiththepartintheinternalloopbackmodeorexternallyloopedbackusingaloopbackcablefixture.
BISTtestingcanalsobeperformedbetweentwodirectlyconnectedDP83640devices.
TheBISTisimplementedwithindependenttransmitandreceivepaths,withthetransmitblockgeneratingacontinuousstreamofapseudorandomsequence.
Theusercanselecta9bitor15bitpseudorandomsequencefromthePSR_15bitinthePHYControlRegister(PHYCR).
Thereceiveddataiscomparedtothegeneratedpseudo-randomdatabytheBISTLinearFeedbackShiftRegister(LFSR)todeterminetheBISTpass/failstatus.
Thepass/failstatusoftheBISTisstoredintheBISTstatusbitinthePHYCRregister.
Thestatusbitdefaultsto0(BISTfail)andwilltransitiononasuccessfulcomparison.
Ifanerror(mis-compare)occurs,thestatusbitislatchedandiscleareduponasubsequentwritetotheStart/Stopbit.
FortransmitVODtesting,thePacketBISTContinuousModecanbeusedtoallowcontinuousdatatransmissionbysettingtheBIST_CONT_MODE,bit5,ofCDCTRL1(1Bh).
ThenumberofBISTerrorscanbemonitoredthroughtheBISTErrorCountintheCDCTRL1(1Bh),bits[15:8].
Copyright2007–2013,TexasInstrumentsIncorporatedConfiguration51SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com6MACInterfaceTheDP83640supportsseveralmodesofoperationusingtheMIIinterfacepins.
Theoptionsaredefinedinthefollowingsectionsandinclude:MIIModeRMIIModeSingleClockMIIMode(SCMII)Inaddition,theDP83640supportsthestandard802.
3uMIISerialManagementInterface.
Themodesofoperationcanbeselectedbystrapoptionsorregistercontrol.
ForRMIISlavemode,itisrecommendedtousethestrapoptionsinceitrequiresa50MHzclockinsteadofthenormal25MHz.
Ineachofthesemodes,theIEEE802.
3serialmanagementinterfaceisoperationalfordeviceconfigurationandstatus.
TheserialmanagementinterfaceoftheMIIallowsfortheconfigurationandcontrolofmultiplePHYdevices,gatheringofstatus,errorinformation,andthedeterminationofthetypeandcapabilitiesoftheattachedPHY(s).
6.
1MIIInterfaceTheDP83640incorporatestheMediaIndependentInterface(MII)asspecifiedinClause22oftheIEEE802.
3ustandard.
ThisinterfacemaybeusedtoconnectPHYdevicestoaMACin10/100Mb/ssystems.
ThissectiondescribesthenibblewideMIIdatainterface.
ThenibblewideMIIdatainterfaceconsistsofareceivebusandatransmitbuseachwithcontrolsignalstofacilitatedatatransferbetweenthePHYandtheupperlayer(MAC).
6.
1.
1Nibble-wideMIIDataInterfaceClause22oftheIEEE802.
3uspecificationdefinestheMediaIndependentInterface.
Thisinterfaceincludesadedicatedreceivebusandadedicatedtransmitbus.
Thesetwodatabuses,alongwithvariouscontrolandstatussignals,allowforthesimultaneousexchangeofdatabetweentheDP83640andtheupperlayeragent(MAC).
ThereceiveinterfaceconsistsofanibblewidedatabusRXD[3:0],areceiveerrorsignalRX_ER,areceivedatavalidflagRX_DV,andareceiveclockRX_CLKforsynchronoustransferofthedata.
Thereceiveclockoperatesateither2.
5MHztosupport10Mb/soperationmodesorat25MHztosupport100Mb/soperationalmodes.
ThetransmitinterfaceconsistsofanibblewidedatabusTXD[3:0],atransmitenablecontrolsignalTX_EN,andatransmitclockTX_CLKwhichrunsateither2.
5MHzor25MHz.
Additionally,theMIIincludesthecarriersensesignalCRS,aswellasacollisiondetectsignalCOL.
TheCRSsignalassertstoindicatethereceptionofdatafromthenetworkorasafunctionoftransmitdatainHalfDuplexmode.
TheCOLsignalassertsasanindicationofacollisionwhichcanoccurduringhalf-duplexoperationwhenbothatransmitandreceiveoperationoccursimultaneously.
6.
1.
2CollisionDetectForHalfDuplex,a10BASE-Tor100BASE-TXcollisionisdetectedwhenthereceiveandtransmitchannelsareactivesimultaneously.
CollisionsarereportedbytheCOLsignalontheMII.
IftheDP83640istransmittingin10Mb/smodewhenacollisionisdetected,thecollisionisnotreporteduntilsevenbitshavebeenreceivedwhileinthecollisionstate.
Thispreventsacollisionbeingreportedincorrectlyduetonoiseonthenetwork.
TheCOLsignalremainssetforthedurationofthecollision.
Ifacollisionoccursduringareceiveoperation,itisimmediatelyreportedbytheCOLsignal.
52MACInterfaceCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Whenheartbeatisenabled(onlyapplicableto10Mb/soperation),approximately1safterthetransmissionofeachpacket,aSignalQualityError(SQE)signalofapproximately10bittimesisgenerated(internally)toindicatesuccessfultransmission.
SQEisreportedasapulseontheCOLsignaloftheMII.
CollisionisnotindicatedduringFullDuplexoperation.
6.
1.
3CarrierSenseIn10Mb/soperation,CarrierSense(CRS)isassertedduetoreceiveactivityoncevaliddataisdetectedviatheSmartSquelchfunction.
During100Mb/soperationCRSisassertedwhenavalidlink(SD)andtwonon-contiguouszerosaredetectedontheline.
For10or100Mb/sHalfDuplexoperation,CRSisassertedduringeitherpackettransmissionorreception.
For10or100Mb/sFullDuplexoperation,CRSisassertedonlyduetoreceiveactivity.
CRSisdeassertedfollowinganendofpacket.
6.
2ReducedMIIInterfaceTheDP83640incorporatestheReducedMediaIndependentInterface(RMII)asspecifiedintheRMIIspecification(rev1.
2)fromtheRMIIConsortium.
ThisinterfacemaybeusedtoconnectPHYdevicestoaMACin10/100Mb/ssystemsusingareducednumberofpins.
Inthismode,dataistransferred2-bitsatatimeusingthe50MHzRMII_REFclockforbothtransmitandreceive.
ThefollowingpinsareusedinRMIImode:TX_ENTXD[1:0]RX_ER(optionalforMAC)CRS/CRS_DVRXD[1:0]X1(25MHzinRMIIMastermode,50MHzinRMIISlavemode)RX_CLK,TX_CLK,CLK_OUT(50MHzRMIIreferenceclockinRMIIMastermodeonly)Inaddition,theRMIImodesuppliesanRX_DVsignalwhichallowsforasimplermethodofrecoveringreceivedatawithouthavingtoseparateRX_DVfromtheCRS_DVindication.
ThisisespeciallyusefulforsystemswhichdonotrequireCRS,suchassystemsthatonlysupportfull-duplexoperation.
ThissignalisalsousefulfordiagnostictestingwhereitmaybedesirabletoloopexternalReceiveRMIIdatadirectlytothetransmitter.
TheRX_ERoutputmaybeusedbytheMACtodetecterrorconditions.
Itisassertedforsymbolerrorsreceivedduringapacket,FalseCarrierevents,andalsoforFIFOunderrunoroverrunconditions.
SincethePHYisrequiredtocorruptreceivedataonanerror,aMACisnotrequiredtouseRX_ER.
Sincethereferenceclockoperatesat10timesthedataratefor10Mb/soperation,transmitdataissampledevery10clocks.
Likewise,receivedatawillbegeneratedevery10thclocksothatanattacheddevicecansamplethedataevery10clocks.
RMIISlavemoderequiresa50MHzoscillatortobeconnectedtothedeviceX1pin.
A50MHzcrystalisnotsupported.
RMIIMastermodecanuseeithera25MHzoscillatorconnectedtoX1ora25MHzcrystalconnectedtoX1andX2.
Totoleratepotentialfrequencydifferencesbetweenthe50MHzreferenceclockandtherecoveredreceiveclock,thereceiveRMIIfunctionincludesaprogrammableelasticitybuffer.
Theelasticitybufferisprogrammabletominimizepropagationdelaybasedonexpectedpacketsizeandclockaccuracy.
Thisallowsforsupportingarangeofpacketsizesincludingjumboframes.
Copyright2007–2013,TexasInstrumentsIncorporatedMACInterface53SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTheelasticitybufferwillforceFrameCheckSequenceerrorsforpacketswhichoverrunorunderruntheFIFO.
UnderrunandoverrunconditionscanbereportedintheRMIIandBypassRegister(RBR).
Table6-1indicateshowtoprogramtheelasticitybufferFIFO(in4-bitincrements)basedonexpectedmaximumpacketsizeandclockaccuracy.
Itassumesbothclocks(RMIIReferenceclockandfar-endTransmitterclock)havethesameaccuracy.
Packetlengthscanbescaledlinearlybasedonaccuracy(+/-25ppmwouldallowpacketstwiceaslarge).
Ifthethresholdsettingmustsupportboth10Mband100Mboperation,thesettingshouldbemadetosupportbothspeeds.
Table6-1.
SupportedPacketSizesat+/-50ppmFrequencyAccuracyLatencyToleranceRecommendedPacketSizeat+/-50ppmStartThresholdRBR[1:0]100Mb10Mb100Mb10Mb01(default)2bits8bits2,400bytes9,600bytes106bits4bits7,200bytes4,800bytes1110bits8bits12,000bytes9,600bytes0014bits12bits16,800bytes14,400bytes6.
2.
1RMIIMasterModeInRMIIMasterMode,theDP83640usesa25MHzcrystalonX1/X2andinternallygeneratesthe50MHzRMIIreferenceclockforusebytheRMIIlogic.
The50MHzclockisoutputonRX_CLK,TX_CLK,andCLK_OUTforuseasthereferenceclockforanattachedMAC.
RX_CLKoperatesat25MHzduringreset.
6.
2.
2RMIISlaveModeInRMIISlaveMode,theDP83640takesa50MHzreferenceclockinputonX1fromanexternaloscillatororanotherDP83640inRMIIMasterMode.
The50MHzisinternallydivideddownto25MHzforuseasthereferenceclockfornon-RMIIlogic.
RX_CLK,TX_CLK,andCLK_OUTshouldnotbeusedastheRMIIreferenceclockinthismodebutmaybeusedforothersystemdevices.
6.
3SingleClockMIIModeSingleClockMII(SCMII)ModeallowsMIIoperationusingasingle25MHzreferenceclock.
NormalMIIModerequiresthreeclocks,areferenceclockforphysicallayerfunctions,atransmitMIIclock,andareceiveMIIclock.
SimilartoRMIImode,SingleClockMIImoderequiresonlythereferenceclock.
Inadditiontoreducingthenumberofpinsrequired,thismodeallowstheattachedMACdevicetouseonlythereferenceclockdomain.
ACTimingrequirementsforSCMIIoperationaresimilartotheRMIItimingrequirements.
For10Mboperation,asinRMIImode,dataissampledanddrivenevery10clockssincethereferenceclockisat10timesthedatarate.
SeparatecontrolbitsallowenablingtheTransmitandReceiveSingleClockmodesseparately,allowingjusttransmitorreceivetooperateinthismode.
ControlofSingleClockMIImodeisthroughtheRBRregister.
SingleClockMIImodeincorporatestheuseoftheRMIIelasticitybuffer,whichisrequiredtotoleratepotentialfrequencydifferencesbetweenthe25MHzreferenceclockandtherecoveredreceiveclock.
SettingsfortheelasticitybufferforSCMIImodearedetailedinTable6-2.
54MACInterfaceCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table6-2.
SupportedSCMIIPacketSizesat+/-50ppmFrequencyAccuracyLatencyToleranceRecommendedPacketSizeat+/-50ppmStartThresholdRBR[1:0]100Mb10Mb100Mb10Mb01(default)4bits8bits4,000bytes9,600bytes104bits8bits4,000bytes9,600bytes118bits8bits9,600bytes9,600bytes008bits8bits9,600bytes9,600bytes6.
4IEEE802.
3uMIISerialManagementInterface6.
4.
1SerialManagementRegisterAccessTheserialmanagementMIIspecificationdefinesasetofthirty-two16-bitstatusandcontrolregistersthatareaccessiblethroughthemanagementinterfacepinsMDCandMDIO.
TheDP83640implementsalltherequiredMIIregistersaswellasseveraloptionalregisters.
TheseregistersarefullydescribedinSection10.
Adescriptionoftheserialmanagementaccessprotocolfollows.
Table6-3.
TypicalMDIOFrameFormatMIIManagementSerialProtocolReadOperationWriteOperation6.
4.
2SerialManagementAccessProtocolTheserialcontrolinterfaceconsistsoftwopins,ManagementDataClock(MDC)andManagementDataInput/Output(MDIO).
MDChasamaximumclockrateof25MHzandnominimumrate.
TheMDIOlineisbi-directionalandmaybesharedbyupto32devices.
TheMDIOframeformatisshownbelowinTable6-3.
TheMDIOpinrequiresapull-upresistor(1.
5k)which,duringIDLEandturnaround,willpullMDIOhigh.
TheDP83640alsoincludesanoptiontoenableaninternalpull-upontheMDIOpin,MDIO_PULL_ENbitintheCDCTRL1register.
InordertoinitializetheMDIOinterface,thestationmanagemententitysendsasequenceof32contiguouslogiconesonMDIOtoprovidetheDP83640withasequencethatcanbeusedtoestablishsynchronization.
ThispreamblemaybegeneratedeitherbydrivingMDIOhighfor32consecutiveMDCclockcycles,orbysimplyallowingtheMDIOpull-upresistortopulltheMDIOpinhighduringwhichtime32MDCclockcyclesareprovided.
Inaddition32MDCclockcyclesshouldbeusedtore-syncthedeviceifaninvalidStart,Opcode,orturnaroundbitisdetected.
TheDP83640waitsuntilithasreceivedthispreamblesequencebeforerespondingtoanyothertransaction.
OncetheDP83640serialmanagementporthasbeeninitializednofurtherpreamblesequencingisrequireduntilafterapower-on/reset,invalidStart,invalidOpcode,orinvalidturnaround(TA)bithasoccurred.
Copyright2007–2013,TexasInstrumentsIncorporatedMACInterface55SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTheStartcodeisindicatedbyapattern.
ThisassurestheMDIOlinetransitionsfromthedefaultidlelinestate.
TurnaroundisdefinedasanidlebittimeinsertedbetweentheRegisterAddressfieldandtheDatafield.
Toavoidcontentionduringareadtransaction,nodeviceshallactivelydrivetheMDIOsignalduringthefirstbitofTurnaround.
TheaddressedDP83640drivestheMDIOwithazeroforthesecondbitofturnaroundandfollowsthiswiththerequireddata.
Figure6-1showsthetimingrelationshipbetweenMDCandtheMDIOasdriven/receivedbytheStation(STA)andtheDP83640(PHY)foratypicalregisterreadaccess.
Forwritetransactions,thestationmanagemententitywritesdatatotheaddressedDP83640thuseliminatingtherequirementforMDIOTurnaround.
TheTurnaroundtimeisfilledbythemanagemententitybyinserting.
Figure7-1showsthetimingrelationshipforatypicalMIIregisterwriteaccess.
Figure6-1.
TypicalMDC/MDIOReadOperationFigure6-2.
TypicalMDC/MDIOWriteOperation6.
4.
3SerialManagementPreambleSuppressionTheDP83640supportsaPreambleSuppressionmodeasindicatedbyaoneinbit6oftheBasicModeStatusRegister(BMSR,address01h.
)Ifthestationmanagemententity(i.
e.
MACorothermanagementcontroller)determinesthatallPHYsinthesystemsupportPreambleSuppressionbyreturningaoneinthisbit,thenthestationmanagemententityneednotgeneratepreambleforeachmanagementtransaction.
TheDP83640requiresasingleinitializationsequenceof32bitsofpreamblefollowinghardware/softwarereset.
Thisrequirementisgenerallymetbythemandatorypull-upresistoronMDIOinconjunctionwithacontinuousMDC,orthemanagementaccessmadetodeterminewhetherPreambleSuppressionissupported.
WhiletheDP83640requiresaninitialpreamblesequenceof32bitsformanagementinitialization,itdoesnotrequireafull32-bitsequencebetweeneachsubsequenttransaction.
AminimumofoneidlebitbetweenmanagementtransactionsisrequiredasspecifiedintheIEEE802.
3uspecification.
56MACInterfaceCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20136.
5PHYControlFramesTheDP83640supportsapacket-basedcontrolmechanismforuseinsituationswheretheSerialManagementInterfaceisnotavailableordoesnotprovideenoughthroughput.
Applicationsoftwaremaybuildapacket,calledaPHYControlFrame(PCF),tobepassedtothePHYthroughtheMACTransmitDatainterface.
ThePHYwillinterceptthesepacketsandusethemtoassertwritestoManagementRegistersasiftheyoccurredviatheManagementInterface.
Multipleregisterwritesmaybeincorporatedinasingleframe.
ThePHYControlFramemayalsobeusedtoreadaregisterlocation.
ThereadvaluewillbereturnedinaPHYStatusFrameifthatfunctionisenabled.
Onlyasinglereadmaybeoutstandingatanytime,soonlyonereadshouldbeincludedinasinglePHYControlFrame.
ThePHYControlFrameblockperformsthefollowingfunctions:ParseincomingtransmitpacketstodetectPHYControlFramesTruncatePHYControlFramestopreventcompleteframefromreachingthetransmitphysicalmediumBufferupto15bytesoftheFrametobeinterceptedbythePHYwithnoportionreachingphysicalmediumDetectcommandsinthePHYControlFrameandpassthemtotheregisterblockCheckCRCtodetecterrorconditionsReportCRCandinvalidcommanderrorstothesystemviaregisterstatusand/orinterruptPHYControlFramescanbeenabledthroughthePCF_EnablebitinthePHYControlFramesConfigurationRegister(PCFCR).
PHYControlFramescanalsobeenabledbyusingthePCF_ENstrapoption.
ForamoredetaileddiscussionontheuseofPHYControlFrames,refertotheSoftwareDevelopmentGuidefortheDP83640.
6.
6PHYStatusFramesTheDP83640implementsapacket-basedstatusmechanismthatallowsthePHYtoqueueupeventsandpassthemtothemicrocontrollerthroughthereceivedatainterface.
Thepacket,calledaPHYStatusFrame,maybeusedtoprovideIEEE1588statusfortransmitpackettimestamps,receivepackettimestamps,eventtimestamps,andtriggerconditions.
InadditionthedevicecangeneratestatusmessagesindicatingpacketbufferingerrorsandtoreturndatareadusingthePHYControlFrameregisteraccessmechanism.
EachPHYStatusFramemayincludemultiplestatusmessages.
ThepacketwillbeframedsuchthatitwilllooklikeaIEEE1588frametoensurethatitwillgettotheIEEE1588softwarestack.
ThePHYwillprovidebufferingofanyincomingpackettoallowthestatuspackettobepassedtotheMAC.
Programmableinter-framegapandpreamblelengthallowthePHYtorecoverlostbandwidthinthecaseofheavyreceivetraffic.
InaPHYStatusFrame,statusmessagesarenotprovidedinachronologicalorder.
Instead,theyareprovidedinthefollowingorderofpriority:1.
PHYControlFrameReadData2.
PacketBufferError3.
TransmitTimestamp4.
ReceiveTimestamp5.
TriggerStatus6.
EventTimestampEachofthemessagetypesmaybeindividuallyenabled,allowingoptionsonwhichfunctionsmaybedeliveredinaPHYStatusFrame.
TimestampsthataredeliveredviaPHYStatusFrameswillnotbereflectedinthecorrespondingstatusandtimestampregistersnorwilltheygenerateaninterrupt.
Copyright2007–2013,TexasInstrumentsIncorporatedMACInterface57SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comThepacketformatmaybeconfiguredtolooklikeaLayer2EthernetframeoraUDP/IPv4frame.
ForamoredetaileddiscussionontheuseofPHYStatusFrames,refertotheSoftwareDevelopmentGuidefortheDP83640.
58MACInterfaceCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20137ArchitectureThissectiondescribestheoperationswithineachtransceivermodule,100BASE-TXand10BASE-T.
Eachoperationconsistsofseveralfunctionalblocksandisdescribedinthefollowing:100BASE-TXTransmitter100BASE-TXReceiver100BASE-FXOperation10BASE-TTransceiverModule7.
1100BASE-TXTransmitterThe100BASE-TXtransmitterconsistsofseveralfunctionalblockswhichconvertsynchronous4-bitnibbledata,asprovidedbytheMII,toascrambledMLT-3125Mb/sserialdatastream.
Becausethe100BASE-TXTP-PMDisintegrated,thedifferentialoutputpins,PMDOutputPair,canbedirectlyroutedtothemagnetics.
TheblockdiagraminFigure7-1providesanoverviewofeachfunctionalblockwithinthe100BASE-TXtransmitsection.
TheTransmittersectionconsistsofthefollowingfunctionalblocks:Code-GroupEncoderandInjectionblockScramblerblock(bypassoption)NRZtoNRZIEncoderblockBinarytoMLT-3Converter/CommonDriverblockThebypassoptionforthefunctionalblockswithinthe100BASE-TXtransmitterprovidesflexibilityforapplicationswheredataconversionisnotalwaysrequired.
TheDP83640implementsthe100BASE-TXtransmitstatemachinediagramasspecifiedintheIEEE802.
3uStandard,Clause24.
Figure7-1.
100BASE-TXTransmitBlockDiagramCopyright2007–2013,TexasInstrumentsIncorporatedArchitecture59SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable7-1.
4B5BCode-GroupEncoding/DecodingNamePCS5BCode-GroupMII4BNibbleCodeDATACODES0111100000101001000121010000103101010011401010010050101101016011100110701111011181001010009100111001A101101010B101111011C110101100D110111101E111001110F111011111IDLEANDCONTROLCODESH00100HALTcode-group-ErrorcodeI11111Inter-PacketIDLE-0000(Note1)J11000FirstStartofPacket-0101(Note1)K10001SecondStartofPacket-0101(Note1)T01101FirstEndofPacket-0000(Note1)R00111SecondEndofPacket-0000(Note1)INVALIDCODESV00000V00001V00010V00011V00101V00110V01000V01100V10000V11001Note1:Controlcode-groupsI,J,K,TandRindatafieldswillbemappedasinvalidcodes,togetherwithRX_ERasserted.
60ArchitectureCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL20137.
1.
1Code-GroupEncodingandInjectionThecode-groupencoderconverts4-bit(4B)nibbledatageneratedbytheMACinto5-bit(5B)code-groupsfortransmission.
Thisconversionisrequiredtoallowcontroldatatobecombinedwithpacketdatacode-groups.
RefertoTable7-1for4Bto5Bcode-groupmappingdetails.
Thecode-groupencodersubstitutesthefirst8-bitsoftheMACpreamblewithaJ/Kcode-grouppair(1100010001)upontransmission.
Thecode-groupencodercontinuestoreplacesubsequent4Bpreambleanddatanibbleswithcorresponding5Bcode-groups.
Attheendofthetransmitpacket,uponthedeassertionofTransmitEnablesignalfromtheMAC,thecode-groupencoderinjectstheT/Rcode-grouppair(0110100111)indicatingtheendoftheframe.
AftertheT/Rcode-grouppair,thecode-groupencodercontinuouslyinjectsIDLEsintothetransmitdatastreamuntilthenexttransmitpacketisdetected(reassertionofTransmitEnable).
7.
1.
2ScramblerThescramblerisrequiredtocontroltheradiatedemissionsatthemediaconnectorandonthetwistedpaircable(for100BASE-TXapplications).
Byscramblingthedata,thetotalenergylaunchedontothecableisrandomlydistributedoverawidefrequencyrange.
Withoutthescrambler,energylevelsatthePMDandonthecablecouldpeakbeyondFCClimitationsatfrequenciesrelatedtorepeating5Bsequences(i.
e.
,continuoustransmissionofIDLEs).
Thescramblerisconfiguredasaclosedlooplinearfeedbackshiftregister(LFSR)withan11-bitpolynomial.
TheoutputoftheclosedloopLFSRisX-ORdwiththeserialNRZdatafromthecode-groupencoder.
Theresultisascrambleddatastreamwithsufficientrandomizationtodecreaseradiatedemissionsatcertainfrequenciesbyasmuchas20dB.
TheDP83640usesthePHY_ID(pinsPHYAD[4:0])tosetauniqueseedvalue.
7.
1.
3NRZtoNRZIEncoderAfterthetransmitdatastreamhasbeenserializedandscrambled,thedatamustbeNRZIencodedinordertocomplywiththeTP-PMDstandardfor100BASE-TXtransmissionoverCategory-5Unshieldedtwistedpaircable.
ThereisnoabilitytobypassthisblockwithintheDP83640.
TheNRZIdataissenttothe100MbDriver.
Inaddition,thismodulecreatesanencodedMLTvalueforusein100MbInternalLoopback.
7.
1.
4BinarytoMLT-3ConvertorTheBinarytoMLT-3conversionisaccomplishedbyconvertingtheserialbinarydatastreamoutputfromtheNRZIencoderintotwobinarydatastreamswithalternatelyphasedlogiconeevents.
Thesetwobinarystreamsarethenfedtothetwistedpairoutputdriverwhichconvertsthevoltagetocurrentandalternatelydriveseithersideofthetransmittransformerprimarywinding,resultinginaminimalcurrentMLT-3signal.
The100BASE-TXMLT-3signalsourcedbythePMDOutputPaircommondriverisslewratecontrolled.
ThisshouldbeconsideredwhenselectingACcouplingmagneticstoensureTP-PMDStandardcomplianttransitiontimes(3nsindicatesthatthisdevicesupportsIEEE802.
3u.
86RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
1.
6Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR)(BASEPage)ThisregistercontainstheadvertisedabilitiesoftheLinkPartnerasreceivedduringAuto-Negotiation.
Thecontentchangesafterthesuccessfulauto-negotiationifNext-pagesaresupported.
Table10-8.
Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR)(BASEPage),address0x05BitBitNameDefaultDescription15NP0,RONextPageIndication:0=LinkPartnerdoesnotdesireNextPageTransfer.
1=LinkPartnerdesiresNextPageTransfer.
14ACK0,ROAcknowledge:1=LinkPartneracknowledgesreceptionoftheabilitydataword.
0=Notacknowledged.
TheAuto-NegotiationstatemachinewillautomaticallycontrolthisbitbasedontheincomingFLPbursts.
13RF0,RORemoteFault:1=RemoteFaultindicatedbyLinkPartner.
0=NoRemoteFaultindicatedbyLinkPartner.
12RESERVED0,RORESERVEDforFutureIEEEuse:Writeas0,readas0.
11ASM_DIR0,ROASYMMETRICPAUSE:1=AsymmetricpauseissupportedbytheLinkPartner.
0=AsymmetricpauseisnotsupportedbytheLinkPartner.
10PAUSE0,ROPAUSE:1=PausefunctionissupportedbytheLinkPartner.
0=PausefunctionisnotsupportedbytheLinkPartner.
9T40,RO100BASE-T4Support:1=100BASE-T4issupportedbytheLinkPartner.
0=100BASE-T4notsupportedbytheLinkPartner.
8TX_FD0,RO100BASE-TXFullDuplexSupport:1=100BASE-TXFullDuplexissupportedbytheLinkPartner.
0=100BASE-TXFullDuplexnotsupportedbytheLinkPartner.
7TX0,RO100BASE-TXSupport:1=100BASE-TXissupportedbytheLinkPartner.
0=100BASE-TXnotsupportedbytheLinkPartner.
610_FD0,RO10BASE-TFullDuplexSupport:1=10BASE-TFullDuplexissupportedbytheLinkPartner.
0=10BASE-TFullDuplexnotsupportedbytheLinkPartner.
5100,RO10BASE-TSupport:1=10BASE-TissupportedbytheLinkPartner.
0=10BASE-TnotsupportedbytheLinkPartner.
4:0SELECTOR00000,ROProtocolSelectionBits:LinkPartner'sbinaryencodedprotocolselector.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock87SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
1.
7Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR)(NextPage)Table10-9.
Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR)(NextPage),address0x05BitBitNameDefaultDescription15NP0,RONextPageIndication:1=LinkPartnerdesiresNextPageTransfer.
0=LinkPartnerdoesnotdesireNextPageTransfer.
14ACK0,ROAcknowledge:1=LinkPartneracknowledgesreceptionoftheabilitydataword.
0=Notacknowledged.
TheAuto-NegotiationstatemachinewillautomaticallycontrolthisbitbasedontheincomingFLPbursts.
Softwareshouldnotattempttowritetothisbit.
13MP0,ROMessagePage:1=MessagePage.
0=UnformattedPage.
12ACK20,ROAcknowledge2:1=LinkPartnerdoeshavetheabilitytocomplytonextpagemessage.
0=LinkPartnerdoesnothavetheabilitytocomplytonextpagemessage.
11TOGGLE0,ROToggle:1=PreviousvalueofthetransmittedLinkCodewordequalled0.
0=PreviousvalueofthetransmittedLinkCodewordequalled1.
10:0CODE00000000000,ROCode:Thisfieldrepresentsthecodefieldofthenextpagetransmission.
IftheMPbitisset(bit13ofthisregister),thenthecodeshallbeinterpretedasaMessagePage,asdefinedinIEEE802.
3uAnnex28CofClause28.
Otherwise,thecodeshallbeinterpretedasanUnformattedPage,andtheinterpretationisapplicationspecific.
10.
1.
8Auto-NegotiateExpansionRegister(ANER)ThisregistercontainsadditionalLocalDeviceandLinkPartnerstatusinformation.
Table10-10.
Auto-NegotiateExpansionRegister(ANER),address0x06BitBitNameDefaultDescription15:5RESERVED00000000000,RORESERVED:Writesignored,Readas0.
4PDF0,ROParallelDetectionFault:1=AfaulthasbeendetectedviatheParallelDetectionfunction.
0=Afaulthasnotbeendetected.
3LP_NP_ABLE0,ROLinkPartnerNextPageAble:1=LinkPartnerdoessupportNextPage.
0=LinkPartnerdoesnotsupportNextPage.
2NP_ABLE1,RO/PNextPageAble:1=IndicateslocaldeviceisabletosendadditionalNextPages.
1PAGE_RX0,RO/CORLinkCodeWordPageReceived:1=LinkCodeWordhasbeenreceived,clearedonaread.
0=LinkCodeWordhasnotbeenreceived.
0LP_AN_ABLE0,ROLinkPartnerAuto-NegotiationAble:1=IndicatesthattheLinkPartnersupportsAuto-Negotiation.
0=IndicatesthattheLinkPartnerdoesnotsupportAuto-Negotiation.
88RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
1.
9Auto-NegotiationNextPageTransmitRegister(ANNPTR)ThisregistercontainsthenextpageinformationsentbythisdevicetoitsLinkPartnerduringAuto-Negotiation.
Table10-11.
Auto-NegotiationNextPageTransmitRegister(ANNPTR),address0x07BitBitNameDefaultDescription15NP0,RWNextPageIndication:0=NootherNextPageTransferdesired.
1=AnotherNextPagedesired.
14RESERVED0,RORESERVED:Writesignored,readas0.
13MP1,RWMessagePage:1=MessagePage.
0=UnformattedPage.
12ACK20,RWAcknowledge2:1=Willcomplywithmessage.
0=Cannotcomplywithmessage.
Acknowledge2isusedbythenextpagefunctiontoindicatethatLocalDevicehastheabilitytocomplywiththemessagereceived.
11TOG_TX0,ROToggle:1=ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas0.
0=ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas1.
ToggleisusedbytheArbitrationfunctionwithinAuto-NegotiationtoensuresynchronizationwiththeLinkPartnerduringNextPageexchange.
ThisbitshallalwaystaketheoppositevalueoftheTogglebitinthepreviouslyexchangedLinkCodeWord.
10:0CODE00000000001,RWCode:Thisfieldrepresentsthecodefieldofthenextpagetransmission.
IftheMPbitisset(bit13ofthisregister),thenthecodeshallbeinterpretedasa"MessagePage",asdefinedinAnnex28CofIEEE802.
3u.
Otherwise,thecodeshallbeinterpretedasan"UnformattedPage",andtheinterpretationisapplicationspecific.
ThedefaultvalueoftheCODErepresentsaNullPageasdefinedinAnnex28CofIEEE802.
3u.
10.
1.
10PHYStatusRegister(PHYSTS)Thisregisterprovidesasinglelocationwithintheregistersetforquickaccesstocommonlyaccessedinformation.
Table10-12.
PHYStatusRegister(PHYSTS),address0x10BitBitNameDefaultDescription15RESERVED0,RORESERVED:Writeignored,readas0.
14MDIXMODE0,ROMDIXmodeasreportedbytheAuto-Negotiationlogic:ThisbitwillbeaffectedbythesettingsoftheMDIX_ENandFORCE_MDIXbitsinthePHYCRregister.
WhenMDIXisenabled,butnotforced,thisbitwillupdatedynamicallyastheAuto-MDIXalgorithmswapsbetweenMDIandMDIXconfigurations.
1=MDIpairsswapped(ReceiveonTPTDpair,TransmitonTPRDpair)0=MDIpairsnormal(ReceiveonTPRDpair,TransmitonTPTDpair)Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock89SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-12.
PHYStatusRegister(PHYSTS),address0x10(continued)BitBitNameDefaultDescription13RECEIVEERROR0,RO/LHReceiveErrorLatch:LATCHThisbitwillbecleareduponareadoftheRECRregister.
1=ReceiveerroreventhasoccurredsincelastreadofRXERCNT(address15h,Page0).
0=Noreceiveerroreventhasoccurred.
12POLARITYSTATUS0,ROPolarityStatus:Thisbitisaduplicationofbit4inthe10BTSCRregister.
Thisbitwillbecleareduponareadofthe10BTSCRregister,butnotuponareadofthePHYSTSregister.
1=InvertedPolaritydetected.
0=CorrectPolaritydetected.
11FALSECARRIERSENSE0,RO/LHFalseCarrierSenseLatch:LATCHThisbitwillbecleareduponareadoftheFCSRregister.
1=FalseCarriereventhasoccurredsincelastreadofFCSCR(address14h).
0=NoFalseCarriereventhasoccurred.
10SIGNALDETECT0,RO/LL100Base-TXqualifiedSignalDetectfromPMA:ThisistheSDthatgoesintothelinkmonitor.
ItistheANDofrawSDanddescramblerlock,whenaddress16h,bit8(page0)isset.
Whenbit8ofaddress16hiscleared,itwillbeequivalenttotherawSDfromthePMD.
9DESCRAMBLERLOCK0,RO/LL100Base-TXDescramblerLockfromPMD.
8PAGERECEIVED0,ROLinkCodeWordPageReceived:ThisisaduplicateofthePageReceivedbitintheANERregister,butthisbitwillnotbecleareduponareadofthePHYSTSregister.
1=AnewLinkCodeWordPagehasbeenreceived.
ClearedonreadoftheANER(address06h,bit1).
0=LinkCodeWordPagehasnotbeenreceived.
7MIIINTERRUPT0,ROMIIInterruptPending:1=Indicatesthataninternalinterruptispending.
InterruptsourcecanbedeterminedbyreadingtheMISRRegister(12h).
ReadingtheMISRwillcleartheInterrupt.
0=Nointerruptpending.
6REMOTEFAULT0,RORemoteFault:1=RemoteFaultconditiondetected(clearedonreadofBMSR(address01h)registerorbyreset).
Faultcriteria:notificationfromLinkPartnerofRemoteFaultviaAuto-Negotiation.
0=Noremotefaultconditiondetected.
5JABBERDETECT0,ROJabberDetect:Thisbitonlyhasmeaningin10Mb/smode.
ThisbitisaduplicateoftheJabberDetectbitintheBMSRregister,exceptthatitisnotcleareduponareadofthePHYSTSregister.
1=Jabberconditiondetected.
0=NoJabber.
4AUTO-NEGCOMPLETE0,ROAuto-NegotiationComplete:1=Auto-Negotiationcomplete.
0=Auto-Negotiationnotcomplete.
3LOOPBACKSTATUS0,ROLoopback:1=Loopbackenabled.
0=Normaloperation.
90RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-12.
PHYStatusRegister(PHYSTS),address0x10(continued)BitBitNameDefaultDescription2DUPLEXSTATUS0,RODuplex:ThisbitindicatesduplexstatusandisdeterminedfromAuto-NegotiationorForcedModes.
1=Fullduplexmode.
0=Halfduplexmode.
Note:ThisbitisonlyvalidifAuto-NegotiationisenabledandcompleteandthereisavalidlinkorifAuto-Negotiationisdisabledandthereisavalidlink.
1SPEEDSTATUS0,ROSpeed10:ThisbitindicatesthestatusofthespeedandisdeterminedfromAuto-NegotiationorForcedModes.
1=10Mb/smode.
0=100Mb/smode.
Note:ThisbitisonlyvalidifAuto-NegotiationisenabledandcompleteandthereisavalidlinkorifAuto-Negotiationisdisabledandthereisavalidlink.
0LINKSTATUS0,ROLinkStatus:ThisbitisaduplicateoftheLinkStatusbitintheBMSRregister,exceptthatitwillnotbecleareduponareadofthePHYSTSregister.
1=Validlinkestablished(foreither10or100Mb/soperation).
0=Linknotestablished.
10.
1.
11MIIInterruptControlRegister(MICR)ThisregisterimplementstheMIIInterruptPHYSpecificControlregister.
Sourcesforinterruptgenerationinclude:LinkQualityMonitor,EnergyDetectStateChange,LinkStateChange,SpeedStatusChange,DuplexStatusChange,Auto-NegotiationCompleteoranyofthecountersbecominghalf-full.
TheindividualinterrupteventsmustbeenabledbysettingbitsintheMIIInterruptStatusandEventControlRegister(MISR).
Table10-13.
MIIInterruptControlRegister(MICR),address0x11BitBitNameDefaultDescription15:4RESERVED000000000000,RORESERVED:Writesignored,readas0.
3PTP_INT_SEL0,RWPTPInterruptSelect:MapsPTPInterrupttotheMISRregisterinplaceoftheDuplexInterrupt.
TheDuplexInterruptwillbecombinedwiththeSpeedInterrupt.
1=MapPTPInterrupttoMISR[11],Speed/DuplexInterrupttoMISR[12]0=MapDuplexInterrupttoMISR[11],SpeedInterrupttoMISR[12]2TINT0,RWTestInterrupt:ForcesthePHYtogenerateaninterrupttofacilitateinterrupttesting.
Interruptswillcontinuetobegeneratedaslongasthisbitremainsset.
1=Generateaninterrupt.
0=Donotgenerateinterrupt.
1INTEN0,RWInterruptEnable:EnableinterruptdependentontheeventenablesintheMISRregister.
1=Enableeventbasedinterrupts.
0=Disableeventbasedinterrupts.
0INT_OE0,RWInterruptOutputEnable:EnableinterrupteventstosignalviathePWRDOWN/INTNpinbyconfiguringthePWRDOWN/INTNpinasanoutput.
1=PWRDOWN/INTNisanInterruptOutput.
0=PWRDOWN/INTNisaPowerDownInput.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock91SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
1.
12MIIInterruptStatusandEventControlRegister(MISR)Thisregistercontainseventstatusandenablesfortheinterruptfunction.
Ifaneventhasoccurredsincethelastreadofthisregister,thecorrespondingstatusbitwillbeset.
Ifthecorrespondingenablebitintheregisterisset,aninterruptwillbegeneratediftheeventoccurs.
TheMICRregistercontrolsmustalsobesettoallowinterrupts.
Thestatusindicationsinthisregisterwillbeseteveniftheinterruptisnotenabled.
Table10-14.
MIIInterruptStatusandEventControlRegister(MISR),address0x12BitBitNameDefaultDescription15LQ_INT0,RO/CORLinkQualityInterrupt:1=LinkQualityinterruptispendingandisclearedbythecurrentread.
0=NoLinkQualityinterruptpending.
14ED_INT0,RO/COREnergyDetectInterrupt:1=Energydetectinterruptispendingandisclearedbythecurrentread.
0=Noenergydetectinterruptpending.
13LINK_INT0,RO/CORChangeofLinkStatusInterrupt:1=Changeoflinkstatusinterruptispendingandisclearedbythecurrentread.
0=Nochangeoflinkstatusinterruptpending.
12SPD_INT0,RO/CORChangeofSpeedStatusInterrupt:orChangeofspeedstatusinterrupt.
ThisfunctionisselectedifMICR[3]issetto0.
SPD_DUP_INT1=Speedstatuschangeinterruptispendingandisclearedbythecurrentread.
0=Nospeedstatuschangeinterruptpending.
ChangeofSpeed/DuplexInterrupt:Changeofspeedorduplexstatusinterrupt.
ThisfunctionisselectedifMICR[3]issetto1.
1=Speed/duplexstatuschangeinterruptispendingandisclearedbythecurrentread.
0=Nospeed/duplexstatuschangeinterruptpending.
11DUP_INT0,RO/CORChangeofDuplexStatusInterrupt:orChangeofduplexstatusinterrupt.
ThisfunctionisselectedifMICR[3]issetto0.
PTP_INT1=Duplexstatuschangeinterruptispendingandisclearedbythecurrentread.
0=Noduplexstatuschangeinterruptpending.
PTPInterrupt:PTPinterrupt.
ThisfunctionisselectedifMICR[3]issetto1.
PTPinterruptstatusshouldbereadfromthePTP_STSregister.
ThisinterruptwillnotberearmeduntilthePTP_STSregisterindicatesnofurtherPTPstatusisavailable.
1=PTPinterruptispendingandisclearedbythecurrentread.
0=NoPTPinterruptpending.
10ANC_INT0,RO/CORAuto-NegotiationCompleteInterrupt:1=Auto-negotiationcompleteinterruptispendingandisclearedbythecurrentread.
0=NoAuto-negotiationcompleteinterruptpending.
9FHF_INT0,RO/CORFalseCarrierCounterHalf-FullInterrupt:orFalsecarriercounterhalf-fullinterrupt.
ThisfunctionisselectedifthePHYCR2[8:7]CTR_INTareboth0.
1=Falsecarriercounterhalf-fullinterruptispendingandisclearedbythecurrentread.
0=Nofalsecarriercounterhalf-fullinterruptpending.
CTRInterrupt:FalsecarrierorReceiveErrorcounterhalf-fullinterrupt.
ThisfunctionisselectedifeitherofPHYCR2[8:7]areset.
1=Falsecarrierorreceiveerrorcounterhalf-fullinterruptispendingandisclearedbythecurrentread.
0=Nofalsecarrierorreceiveerrorcounterhalf-fullinterruptpending.
92RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-14.
MIIInterruptStatusandEventControlRegister(MISR),address0x12(continued)BitBitNameDefaultDescription8RHF_INT0,RO/CORReceiveErrorCounterhalf-fullinterrupt:orReceiveerrorcounterhalf-fullinterrupt.
ThisfunctionisselectedifthePCF_INTPHYCR2[8:7]areboth0.
1=Receiveerrorcounterhalf-fullinterruptispendingandisclearedbythecurrentread.
0=Noreceiveerrorcarriercounterhalf-fullinterruptpending.
PCFInterrupt:PHYControlFrameinterrupt.
ThisfunctionisselectedifeitherofPHYCR2[8:7]areset.
1=PHYControlFrameinterruptispendingandisclearedbythecurrentread.
0=NoPHYControlFrameinterruptpending.
7LQ_INT_EN0,RWEnableInterruptonLinkQualityMonitorevent.
6ED_INT_EN0,RWEnableInterruptonenergydetectevent.
5LINK_INT_EN0,RWEnableInterruptonchangeoflinkstatus.
4SPD_INT_EN0,RWEnableInterruptonchangeofspeedstatus.
3DUP_INT_EN0,RWDuplexInterrupt:orEnableInterruptonchangeofduplexstatus.
ThisfunctionisselectedifMICR[3]isPTP_INT_ENsetto0.
PTPInterrupt:PTPinterrupt.
ThisfunctionisselectedifMICR[3]issetto1.
2ANC_INT_EN0,RWEnableInterruptonauto-negotiationcompleteevent.
1FHF_INT_EN0,RWFHFInterrupt:orEnableInterruptonFalseCarrierCounterRegisterhalffullevent.
ThisfunctionisCTR_INT_ENselectedifthePHYCR2[8:7]areboth0.
CTRInterrupt:EnableinterruptoneitherReceiveErrorCounterRegisterhalf-fulleventorFalseCarrierCounterRegisterhalf-fullevent.
ThisfunctionisselectedifeitherofPCFCR[7:6]areset.
0RHF_INT_EN0,RWRHFInterrupt:orEnableInterruptonReceiveErrorCounterRegisterhalffullevent.
ThisfunctionisPCF_INT_ENselectedifthePHYCR2[8:7]areboth0.
PCFInterrupt:EnableInterruptonaPHYControlFrameevent.
ThisfunctionisselectedifeitherofPCFCR[7:6]areset.
10.
1.
13PageSelectRegister(PAGESEL)ThisregisterisusedtoenableaccesstotheLinkDiagnosticsRegisters.
Table10-15.
PageSelectRegister(PAGESEL),address0x13BitBitNameDefaultDescription15:3RESERVED0000000000000,RESERVED:Writesignored,readas0RO2:0PAGE_SEL000,RWPage_SelBits:Selectsbetweenpagedregistersforaddress14hto1Fh.
0=ExtendedRegistersPage01=RESERVED2=LinkDiagnosticsRegistersPage23=RESERVED4=PTP1588BaseRegistersPage45=PTP1588ConfigRegistersPage56=PTP1588ConfigRegistersPage6Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock93SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
2ExtendedRegisters-Page010.
2.
1FalseCarrierSenseCounterRegister(FCSCR)Thiscounterprovidesinformationrequiredtoimplementthe"FalseCarriers"attributewithintheMAUmanagedobjectclassofClause30oftheIEEE802.
3uspecification.
Table10-16.
FalseCarrierSenseCounterRegister(FCSCR),address0x14BitBitNameDefaultDescription15:8RESERVED00000000,RORESERVED:Writesignored,readas07:0FCSCNT[7:0]00000000,RO/CORFalseCarrierEventCounter:This8-bitcounterincrementsoneveryfalsecarrierevent.
Thiscounterstickswhenitreachesitsmaximumcount(FFh).
10.
2.
2ReceiverErrorCounterRegister(RECR)Thiscounterprovidesinformationrequiredtoimplementthe"SymbolErrorDuringCarrier"attributewithinthePHYmanagedobjectclassofClause30oftheIEEE802.
3uspecification.
Table10-17.
ReceiverErrorCounterRegister(RECR),address0x15BitBitNameDefaultDescription15:8RESERVED00000000,RORESERVED:Writesignored,readas0.
7:0RXERCNT[7:0]00000000,RO/CORRX_ERCounter:Whenavalidcarrierispresentandthereisatleastoneoccurrenceofaninvaliddatasymbol,this8-bitcounterincrementsforeachreceiveerrordetected.
Thiseventcanincrementonlyoncepervalidcarrierevent.
Ifacollisionispresent,theattributewillnotincrement.
Thecounterstickswhenitreachesitsmaximumcount.
10.
2.
3100Mb/sPCSConfigurationandStatusRegister(PCSR)Thisregistercontainscontrolandstatusinformationforthe100BASEPhysicalCodingSublayer.
Table10-18.
100Mb/sPCSConfigurationandStatusRegister(PCSR),address0x16BitBitNameDefaultDescription15:12RESERVED0000,RWRESERVED:Mustbe0.
11FREE_CLK0,RWReceiveClock:1=RX_CLKisfree-running.
0=RX_CLKphaseadjustedbasedonalignment.
10TQ_EN0,RW100Mb/sTrueQuietModeEnable:1=TransmitTrueQuietMode.
0=NormalTransmitMode.
9SDFORCEPMA0,RWSignalDetectForcePMA:1=ForcesSignalDetectioninPMA.
0=NormalSDoperation.
8SD_OPTION1,RWSignalDetectOption:1=Defaultoperation.
LinkwillbeassertedfollowingdetectionofvalidsignallevelandDescramblerLock.
Linkwillbemaintainedaslongassignallevelisvalid.
AlossofDescramblerLockwillnotcauseLinkStatustodrop.
0=Modifiedsignaldetectalgorithm.
LinkwillbeassertedfollowingdetectionofvalidsignallevelandDescramblerLock.
LinkwillbemaintainedaslongassignallevelisvalidandDescramblerremainslocked.
94RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-18.
100Mb/sPCSConfigurationandStatusRegister(PCSR),address0x16(continued)BitBitNameDefaultDescription7DESC_TIME0,RWDescramblerTimeout:Increasethedescramblertimeout.
Whenset,thisallowsthedevicetoreceivelargerpackets(>9kbytes)withoutlossofsynchronization.
1=2ms.
0=722s(perANSIX3.
263:1995(TP-PMD)7.
2.
3.
3e).
6FX_ENStrap,RWFXFiberModeEnable:ThisbitissetwhentheFX_ENstrapoptionisselectedfortherespectiveport.
WritePHYCR2[9],SOFT_RESET,afterenablingordisablingFiberModeviaregisteraccesstoensurecorrectconfiguration.
1=EnablesFXoperation.
0=DisablesFXoperation.
5FORCE_100_OK0,RWForce100Mb/sGoodLink:OR'edwithMAC_FORCE_LINK_100signal.
1=Forces100Mb/sGoodLink.
0=Normal100Mb/soperation.
4RESERVED0,RORESERVED:Writesignored,readas0.
3FEFI_ENStrap,RWFarEndFaultIndicationModeEnable:ThisbitissetwhentheFX_ENstrapoptionisselectedfortherespectiveport.
1=FEFIModeEnabled.
0=FEFIModeDisabled.
2NRZI_BYPASS0,RWNRZIBypassEnable:1=NRZIBypassEnabled.
0=NRZIBypassDisabled.
1SCRAMStrap,RWScramblerBypassEnable:BYPASSThisbitissetwhentheFX_ENstrapoptionisselected.
IntheFXmode,thescramblerisbypassed.
1=ScramblerBypassEnabled.
0=ScramblerBypassDisabled.
0DESCRAMStrap,RWDescramblerBypassEnable:BYPASSThisbitissetwhentheFX_ENstrapoptionisselected.
IntheFXmode,thedescramblerisbypassed.
1=DescramblerBypassEnabled.
0=DescramblerBypassDisabled.
10.
2.
4RMIIandBypassRegister(RBR)ThisregisterconfigurestheRMII/MIIInterfaceModeofoperation.
ThisregistercontrolsselectingMII,RMII,orSingleClockMIImodeforReceiveorTransmit.
Inaddition,severaladditionalbitsareincludedtoallowdatapathselectionforTransmitandReceiveinmultiportapplications.
Table10-19.
RMIIandBypassRegister(RBR),address0x17BitBitNameDefaultDescription15RESERVED0,RWRESERVED:Mustbe0.
14RMII_MASTERStrap,RWRMIIMasterMode:Settingthisbitallowsthecoretousea25MHzinputreferenceclockandgenerateitsown50MHzRMIIreferenceclock.
ThegeneratedRMIIreferenceclockwillalsobeusedbytheattachedMAC.
1=RMIIMasterMode(25MHzinputreference)0=RMIISlaveMode(50MHzinputreference)Note:Duetoclockmuxinganddivideroperation,thisbitshouldnormallyonlybereconfiguredviathestrapoption.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock95SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-19.
RMIIandBypassRegister(RBR),address0x17(continued)BitBitNameDefaultDescription13DIS_TX_OPT0,RWDisableRMIITXLatencyOptimization:NormallytheRMIITransmitterwillminimizethetransmitlatencybyrealigningthetransmitclockwiththereferenceclockphaseatthestartofapackettransmission.
SettingthisbitwilldisablephaserealignmentandensurethatIDLEbitswillalwaysbesentinmultiplesofthesymbolsize.
ThiswillresultinalargeruncertaintyinRMIItransmitlatency.
12:9RESERVED0000,RWRESERVED:Mustbe0.
8PMD_LOOP0,RWPMDLoopback:0=NormalOperation.
1=Remote(PMD)Loopback.
SettingthisbitwillcausethedevicetoLoopbackdatareceivedfromthePhysicalLayer.
TheloopbackisdonepriortotheMIIorRMIIinterface.
DatareceivedattheinternalMIIorRMIIinterfacewillbeappliedtothetransmitter.
ThismodeshouldonlybeusedifRMIImodeorSingleClockMIImodeisenabled.
7SCMII_RX0,RWSingleClockRXMIIMode:0=StandardMIImode.
1=SingleClockRXMIIMode.
Settingthisbitwillcausethedevicetogeneratereceivedata(RX_DV,RX_ER,RXD[3:0])synchronoustotheX1Referenceclock.
RX_CLKisnotusedinthismode.
ThismodeusestheRMIIelasticitybuffertotoleratevariationsinclockfrequencies.
ThisbitcannotbesetifRMII_MODEissettoa1.
6SCMII_TX0,RWSingleClockTXMIIMode:0=StandardMIImode.
1=SingleClockTXMIIMode.
Settingthisbitwillcausethedevicetosampletransmitdata(TX_EN,TXD[3:0])synchronoustotheX1Referenceclock.
TX_CLKisnotusedinthismode.
ThisbitcannotbesetifRMII_MODEissettoa1.
5RMII_MODEStrap,RWReducedMIIMode:0=StandardMIIMode.
1=ReducedMIIMode.
4RMII_REV1_00,RWReducedMIIRevision1.
0:ThisbitmodifieshowCRS_DVisgenerated.
0=(RMIIrevision1.
2)CRS_DVwilltoggleattheendofapackettoindicatedeassertionofCRS.
1=(RMIIrevision1.
0)CRS_DVwillremainasserteduntilfinaldataistransferred.
CRS_DVwillnottoggleattheendofapacket.
3RX_OVF_STS0,RORXFIFOOverFlowStatus:0=Normal.
1=Overflowdetected.
2RX_UNF_STS0,RORXFIFOUnderFlowStatus:0=Normal.
1=Underflowdetected.
1:0ELAST_BUF[1:0]01,RWReceiveElasticityBuffer:ThisfieldcontrolstheReceiveElasticityBufferwhichallowsforfrequencyvariationtolerancebetweenthe50MHzRMIIclockandtherecovereddata.
SeeSection6.
2formoreinformationonElasticityBuffersettingsinRMIImode.
SeeSection6.
3formoreinformationonElasticityBuffersettingsinSCMIImode.
96RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
2.
5LEDDirectControlRegister(LEDCR)ThisregisterprovidestheabilitytodirectlycontrolanyorallLEDoutputs.
ItdoesnotprovidereadaccesstoLEDs.
Inaddition,itprovidescontrolfortheActivitysourceandblinkingLEDfrequency.
Table10-20.
LEDDirectControlRegister(LEDCR),address0x18BitBitNameDefaultDescription15:1RESERVED0000,RORESERVED:Writesignored,readas0.
211DIS_SPDLED0,RW1=DisableLED_SPEEDoutput0=EnableLED_SPEEDoutput10DIS_LNKLED0,RW1=DisableLED_LINKoutput0=EnableLED_LINKoutput9DIS_ACTLED0,RW1=DisableLED_ACToutput0=EnableLED_ACToutput8LEDACT_RX0,RW1=ActivityisonlyindicatedforReceivetraffic0=ActivityisindicatedforTransmitorReceivetraffic7:6BLINK_FREQ00,RWLEDBlinkFrequency:ThesebitscontroltheblinkfrequencyoftheLED_LINKoutputwhenblinkingonactivityisenabled.
0=6Hz1=12Hz2=24Hz3=48Hz5DRV_SPDLED0,RW1=DrivevalueofSPDLEDbitontoLED_SPEEDoutput0=Normaloperation4DRV_LNKLED0,RW1=DrivevalueofLNKLEDbitontoLED_LINKoutput0=Normaloperation3DRV_ACTLED0,RW1=DrivevalueofACTLEDbitontoLED_ACToutput0=Normaloperation2SPDLED0,RWValuetoforceonLED_SPEEDoutput1LNKLED0,RWValuetoforceonLED_LINKoutput0ACTLED0,RWValuetoforceonLED_ACToutput10.
2.
6PHYControlRegister(PHYCR)ThisregisterprovidescontrolforPHYfunctionssuchasMDIX,BIST,LEDconfiguration,andPHYaddress.
ItalsoprovidesPauseNegotiationstatus.
Table10-21.
PHYControlRegister(PHYCR),address0x19BitBitNameDefaultDescription15MDIX_EN1,RWAuto-MDIXEnable:1=EnableAuto-negAuto-MDIXcapability.
0=DisableAuto-negAuto-MDIXcapability.
14FORCE_MDIX0,RWForceMDIX:1=ForceMDIpairstocross.
(ReceiveonTDpair,TransmitonRDpair)0=Normaloperation.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock97SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-21.
PHYControlRegister(PHYCR),address0x19(continued)BitBitNameDefaultDescription13PAUSE_RX0,ROPauseReceiveNegotiated:IndicatesthatpausereceiveshouldbeenabledintheMAC.
BasedonANAR[11:10]andANLPAR[11:10]settings.
ThisfunctionshallbeenabledaccordingtoIEEE802.
3Annex28BTable28B-3,"PauseResolution",onlyiftheAuto-NegotiatedHighestCommonDenominatorisafullduplextechnology.
12PAUSE_TX0,ROPauseTransmitNegotiated:IndicatesthatpausetransmitshouldbeenabledintheMAC.
BasedonANAR[11:10]andANLPAR[11:10]settings.
ThisfunctionshallbeenabledaccordingtoIEEE802.
3Annex28BTable28B-3,PauseResolution,onlyiftheAuto-NegotiatedHighestCommonDenominatorisafullduplextechnology.
11BIST_FE0,RW/SCBISTForceError:1=ForceBISTError.
0=Normaloperation.
Thisbitforcesasingleerror,andisselfclearing.
10PSR_150,RWBISTSequenceselect:1=PSR15selected.
0=PSR9selected.
9BIST_STATUS0,LL/ROBISTTestStatus:1=BISTpass.
0=BISTfail.
Latched,clearedwhenaBISTfailureoccursorBISTisstopped.
ForacountnumberofBISTerrors,seetheBISTErrorCountintheCDCTRL1register.
8BIST_START0,RWBISTStart:Writes:1=BISTstart.
Writing1tothisbitenablestransmissionofBISTpacketsandenablesthereceiveBISTenginetostartlookingforpackettraffic.
0=BISTstop.
StoptheBIST.
Writing0tothisbitalsoclearstheBIST_STATUSbit.
Reads:1=BISTactive.
Thisbitreads1afterthetransmitBISTenginehasbeenenabledandthereceiveBISTenginehasdetectedpackettraffic.
0=BISTinactive.
Thisbitwillread0iftheBISTisdisabledoriftheBISTisenabledbutnoreceivetraffichasbeendetected.
7BP_STRETCH0,RWBypassLEDStretching:ThiswillbypasstheLEDstretchingandtheLEDswillreflecttheinternalvalue.
1=BypassLEDstretching.
0=Normaloperation.
98RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-21.
PHYControlRegister(PHYCR),address0x19(continued)BitBitNameDefaultDescription6LED_CNFG[1]0,RWLEDConfiguration5LED_CNFG[0]Strap,RWLED_CNFG[1]LED_CNFG[0]ModeDescriptionDon'tcare1Mode100Mode210Mode3InMode1,LEDsareconfiguredasfollows:LED_LINK=ONforGoodLink,OFFforNoLinkLED_SPEED=ONin100Mb/s,OFFin10Mb/sLED_ACT=ONforActivity,OFFforNoActivityInMode2,LEDsareconfiguredasfollows:LED_LINK=ONforGoodLink,BLINKforActivityLED_SPEED=ONin100Mb/s,OFFin10Mb/sLED_ACT=ONforCollision,OFFforNoCollisionInMode3,LEDsareconfiguredasfollows:LED_LINK=ONforGoodLink,BLINKforActivityLED_SPEED=ONin100Mb/s,OFFin10Mb/sLED_ACT=ONforFullDuplex,OFFforHalfDuplex4:0PHYADDR[4:0]Strap,RWPHYAddress:PHYaddressforport.
Note:ThelocalPHYaddresscannotbechangedviaabroadcastwrite-writingtoPHYaddress0x1Fregister0x19willnotchangethePHYADDRbits.
10.
2.
710Base-TStatus/ControlRegister(10BTSCR)Thisregisterisusedforcontrolandstatusfor10BASE-Tdeviceoperation.
Table10-22.
10Base-TStatus/ControlRegister(10BTSCR),address0x1ABitBitNameDefaultDescription15RESERVED0,RORESERVED:Writesignored,readas0.
14:1RESERVED000,RWRESERVED:Mustbezero.
211:9SQUELCH100,RWSquelchConfiguration:UsedtosettheSquelch'ON'thresholdforthereceiver.
DefaultSquelch'ON'is330mVpeak.
8LOOPBACK_10_DIS0,RW10Base-TLoopbackDisable:ThisbitisOR'edwithbit14(Loopback)intheBMCR.
1=10BTLoopbackisdisabled0=10BTLoopbackisenabled7LP_DIS0,RWNormalLinkPulseDisable:ThisbitisOR'edwiththeMAC_FORCE_LINK_10signal.
1=TransmissionofNLPsisdisabled.
0=TransmissionofNLPsisenabled.
6FORCE_LINK_100,RWForce10MbGoodLink:ThisbitisOR'edwiththeMAC_FORCE_LINK_10signal.
1=ForcedGood10MbLink.
0=NormalLinkStatus.
5FORCE_POLCOR0,RWForce10MbPolarityCorrection:1=Forceinvertedpolarity0=Normalpolarity4POLARITY0,RO/LH10MbPolarityStatus:Thisbitisaduplicationofbit12inthePHYSTSregister.
Bothbitswillbecleareduponareadofeitherregister.
1=InvertedPolaritydetected.
0=CorrectPolaritydetected.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock99SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-22.
10Base-TStatus/ControlRegister(10BTSCR),address0x1A(continued)BitBitNameDefaultDescription3AUTOPOL_DIS0,RWAutoPolarityDetection&CorrectionDisable:1=PolarityCorrectiondisabled0=PolarityCorrectionenabled210BT_SCALE-MSB1,RW10BTScaleConfigurationMostSignificantBitUsedinconjunctionwithbit10ofSD_CNFGregistertosetthesilence'OFF'thresholdforthereceiver.
1HEARTBEAT_DIS0,RWHeartbeatDisable:Thisbitonlyhasinfluenceinhalf-duplex10Mbmode.
1=Heartbeatfunctiondisabled.
0=Heartbeatfunctionenabled.
Whenthedeviceisoperatingat100Mborconfiguredforfullduplexoperation,thisbitwillbeignored-theheartbeatfunctionisdisabled.
0JABBER_DIS0,RWJabberDisable:Thisbitisonlyapplicablein10BASE-T.
1=Jabberfunctiondisabled.
0=Jabberfunctionenabled.
10.
2.
8CDTestandBISTExtensionsRegister(CDCTRL1)Thisregistercontrolstestmodesforthe10BASE-TCommonDriver.
InadditionitcontainsextendedcontrolandstatusforthepacketBISTfunction.
Table10-23.
CDTestandBISTExtensionsRegister(CDCTRL1),address0x1BBitBitNameDefaultDescription15:8BIST_ERROR_COUNT00000000,ROBISTERRORCounter:CountsnumberoferroreddatanibblesduringPacketBIST.
ThisvaluewillresetwhenPacketBISTisrestarted.
ThecounterstickswhenitreachesitsmaximumcountofFFh.
7RESERVED0,RWRESERVED:Mustbe0.
6MII_CLOCK_EN0,RWEnablesMIIClocksTX_CLKandRX_CLKindependentofMACinterfacemodeselected;forexample,normallyTX_CLKandRX_CLKaredisabledinRMIISlavemode.
1=EnableTX_CLKandRX_CLK0=Defaultoperation5BIST_CONT0,RWPacketBISTContinuousMode:Allowscontinuouspseudorandomdatatransmissionwithoutanybreakintransmission.
ThiscanbeusedfortransmitVODtesting.
ThisisusedinconjunctionwiththeBISTcontrolsinthePHYCRRegister(19h).
For10Mboperation,jabberfunctionmustbedisabled,bit0ofthe10BTSCR(1Ah),JABBER_DIS=1.
4CDPATTEN_100,RWCDPatternEnablefor10Mb:1=Enabled.
0=Disabled.
3MDIO_PULL_EN0,RWEnableInternalMDIOPullup:1=InternalMDIOpullupenabled0=InternalMDIOpullupdisabledThisbitisonlyresetonhardreset.
ThisbitshouldnotbesetinsystemsthatsharethemanagementinterfacesamongseveralASICs.
2PATT_GAP_10M0,RWDefinesgapbetweendataorNLPtestsequences:1=15s.
0=10s.
100RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-23.
CDTestandBISTExtensionsRegister(CDCTRL1),address0x1B(continued)BitBitNameDefaultDescription1:0CDPATTSEL[1:0]00,RWCDPatternSelect[1:0]:IfCDPATTEN_10=1:00=Data,EOP0sequence.
01=Data,EOP1sequence.
10=NLPs.
11=ConstantManchester1s(10MHzsinewave)forharmonicdistortiontesting.
10.
2.
9PHYControlRegister2(PHYCR2)Thisregisterprovidesadditionalgeneralcontrol.
Table10-24.
PHYControlRegister2(PHYCR2),address0x1CBitBitNameDefaultDescription15:1RESERVED00,RORESERVED:Writesignored,readas0.
413SYNC_ENETEN0,RWSynchronousEthernetEnable:Whenthisbitis1andthedeviceisin100Mb/smode,andtheMACinterfaceiseitherMIIorRMIIMaster,enablesfullysynchronouscommunicationrelativetotherecoveredreceiveclock.
Thetransmitterissynchronizedtothereceiver.
Whenthisbitis0orthedevicesettingsdonotmatchtheaboveconditions,thetransmitterissynchronoustothelocalreferenceclock.
12CLK_OUTRXCLK0,RWEnableRX_CLKonCLK_OUT:Whenthisbitis1andthedeviceisin100Mb/smode,the25MHzrecoveredreceiveclock(RX_CLK)isdrivenonCLK_OUTinadditiontoRX_CLK.
Whenthisbitis0orthedeviceisin10Mb/smode,CLK_OUTreflectstheReferenceclock.
11BC_WRITE0,RWBroadcastWriteEnable:1=EnablestheSerialManagementInterfacetoacceptregisterwritestoPHYAddressof0x1FindependentofthelocalPHYAddressvalue.
0=Normaloperation10PHYTER_COMP0,RWPhyterCompatibilityMode:1=EnablesPhyter(DP83848)Compatiblepinout.
ReorderstheRXMIIpinsandAutonegotiationstrapstomatchtheDP83848.
AlsoenablestheCLK_OUToutput.
0=Normaloperation9SOFT_RESET0,RW/SCSoftReset:Resetstheentiredeviceminustheregisters-allconfigurationispreserved.
1=Reset,self-clearing.
8:2RESERVED0000000,RORESERVED:Writesignored,readas0.
1CLK_OUT_DISStrap,RWDisableCLK_OUTOutput:DisablestheCLK_OUToutputpin.
0RESERVED0,RWRESERVED:Mustbezero.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock101SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
2.
10EnergyDetectControl(EDCR)ThisregisterprovidescontrolandstatusfortheEnergyDetectfunction.
Table10-25.
EnergyDetectControl(EDCR),address0x1DBitBitNameDefaultDescription15ED_EN0,RWEnergyDetectEnable:AllowEnergyDetectMode.
14ED_AUTO_UP1,RWEnergyDetectAutomaticPowerUp:AutomaticallybeginpowerupsequencewhenEnergyDetectDataThresholdvalue(EDCR[3:0])isreached.
Alternatively,thedevicecouldbepoweredupmanuallyusingtheED_MANbit(ECDR[12]).
13ED_AUTO_DOWN1,RWEnergyDetectAutomaticPowerDown:Automaticallybeginpowerdownsequencewhennoenergyisdetected.
Alternatively,thedevicecouldbepowereddownusingtheED_MANbit(EDCR[12]).
12ED_MAN0,RW/SCEnergyDetectManualPowerUp/Down:Beginpowerup/downsequencewhenthisbitisasserted.
Whenset,theEnergyDetectalgorithmwillinitiateachangeofEnergyDetectstateregardlessofthreshold(errorordata)andtimervalues.
Inmanagedapplications,thisbitcanbesetafterclearingtheEnergyDetectinterrupttocontrolthetimingofchangingthepowerstate.
11ED_BURST_DIS0,RWEnergyDetectBurstDisable:Disableburstingofenergydetectdatapulses.
Bydefault,EnergyDetect(ED)transmitsaburstof4EDdatapulseseachtimetheCDispoweredup.
Whenburstingisdisabled,onlyasingleEDdatapulsewillbesenteachtimetheCDispoweredup.
10ED_PWR_STATE0,ROEnergyDetectPowerState:IndicatescurrentEnergyDetectPowerstate.
Whenset,EnergyDetectisinthepoweredupstate.
Whencleared,EnergyDetectisinthepowereddownstate.
ThisbitisinvalidwhenEnergyDetectisnotenabled.
9ED_ERR_MET0,RO/COREnergyDetectErrorThresholdMet:Noactionisautomaticallytakenuponreceiptoferrorevents.
Thisbitisinformationalonlyandwouldbeclearedonaread.
8ED_DATA_MET0,RO/COREnergyDetectDataThresholdMet:ThenumberofdataeventsthatoccurredmetorsurpassedtheEnergyDetectDataThreshold.
Thisbitisclearedonaread.
7:4ED_ERR_COUNT0001,RWEnergyDetectErrorThreshold:Thresholdtodeterminethenumberofenergydetecterroreventsthatshouldcausethedevicetotakeaction.
Intendedtoallowaveragingofnoisethatmaybeontheline.
Counterwillresetafterapproximately2secondswithoutanyenergydetectdataevents.
3:0ED_DATA_COUNT0001,RWEnergyDetectDataThreshold:Thresholdtodeterminethenumberofenergydetecteventsthatshouldcausethedevicetotakeactions.
Intendedtoallowaveragingofnoisethatmaybeontheline.
Counterwillresetafterapproximately2secondswithoutanyenergydetectdataevents.
102RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
2.
11PHYControlFramesConfigurationRegister(PCFCR)ThisregisterprovidesconfigurationforthePHYControlFramemechanismforregisteraccess.
Table10-26.
PHYControlFramesConfigurationRegister(PCFCR),address0x1FBitBitNameDefaultDescription15PCF_STS_ERR0,RO/CORPHYControlFrameErrorDetected:IndicatesanerrorwasdetectedinaPCFFramesincethelastreadofthisregister.
Thisbitwillbeclearedonread.
14PCF_STS_OK0,RO/CORPHYControlFrameOK:IndicatesaPCFFramehascompletedwithouterrorsincethelastreadofthisregister.
Thisbitwillbeclearedonread.
13:9RESERVED00000,ROReserved:Writesignored,readas08PCF_DA_SEL0,RWSelectMACDestinationAddressforPHYControlFrames:0:UseMACAddress[0800170B6B0F]1:UseMACAddress[080017000000]ThedevicewillalsorecognizepacketswiththeaboveaddresswiththeMulticastbitset(i.
e.
090017.
.
.
).
7:6PCF_INT_CTL00,RWPHYControlFrameInterruptControl:SettingeitherofthesebitsenablescontrolandstatusofthePCFInterruptthroughtheMISRRegister(takingtheplaceoftheRHFInterrupt).
00=PCFInterruptsDisabledx1=InterruptonPCFFrameOK1x=InterruptonPCFFrameError5PCF_BC_DIS0,RWPHYControlFrameBroadcastDisable:Bydefault,thedevicewillacceptbroadcastPHYControlFrameswhichhaveaPHYAddressfieldof0x1F.
Ifthisbitissettoa1,thePHYControlFramemusthaveaPHYAddressfieldthatexactlymatchesthedevicePHYAddress.
4:1PCF_BUF0000,RWPHYControlFrameBufferSize:DeterminesthebuffersizefortransmittoallowPHYControlFramedetection.
Allpacketswillbedelayedastheypassthroughthisbuffer.
Ifsetto0,packetswillnotbedelayedandPHYControlframeswillbetruncatedaftertheDestinationAddressfield.
0PCF_ENStrap,RWPHYControlFrameEnable:EnablesRegisterwritesusingPHYControlFrames.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock103SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
3TestRegisters-Page1Page1TestRegistersareaccessiblebysettingbits[2:0]=001ofPAGESEL(13h).
10.
3.
1SignalDetectConfiguration(SD_CNFG),Page1ThisregistercontainsSignalDetectconfigurationcontrolaswellassometestcontrolstospeedupAuto-negtesting.
Table10-27.
SignalDetectConfiguration(SD_CNFG),address0x1EBitBitNameDefaultDescription15RESERVED1,RWRESERVED:Writeas1,readas1.
14:1RESERVED000,RWRESERVED:Writeas0,readas0.
211RESERVED0,RORESERVED:Writeignored,readas0.
10:9RESERVED00,RWRESERVED:Writeas0,readas0.
8SD_TIME0,RWSignalDetectTimeSettingthisbittoa1enablesafastdetectionoflossofSignalDetect.
ThiswillresultinafastlossofLinkindication.
Approximatetimestodetectsignaldetectdeassertionare:1=1s0=250s7:0RESERVED00000000,RWRESERVED:Writeas0,readas0.
104RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
4LinkDiagnosticsRegisters-Page2Page2LinkDiagnosticsRegistersareaccessiblebysettingbits[2:0]=010ofPAGESEL(13h).
10.
4.
1100MbLengthDetectRegister(LEN100_DET),Page2Thisregistercontainslinkedcablelengthestimationin100Mboperation.
Thecablelengthisanestimationoftheeffectivecablelengthbasedonthecharacteristicsoftherecoveredsignal.
Thecablelengthisvalidonlyduring100MboperationwithavalidLinkstatusindication.
Table10-28.
100MbLengthDetectRegister(LEN100_DET),address0x14BitBitNameDefaultDescription15:8RESERVED00000000,RORESERVED:Writesignored,readas0.
7:0CABLE_LEN11111111,ROCableLengthEstimate:Indicatesanestimateofeffectivecablelengthinmeters.
AvalueofFFhindicatescablelengthcannotbedetermined.
10.
4.
2100MbFrequencyOffsetIndicationRegister(FREQ100),Page2Thisregisterreturnsanindicationofclockfrequencyoffsetrelativetothelinkpartner.
Twovaluescanberead,thelongtermFrequencyOffset,orashorttermFrequencyControlvalue.
TheFrequencyControlvalueincludesshorttermphasecorrection.
ThevariancebetweentheFrequencyControlvalueandtheFrequencyOffsetcanbeusedasanindicationoftheamountofjitterinthesystem.
Table10-29.
100MbFrequencyOffsetIndicationRegister(FREQ100),address0x15BitBitNameDefaultDescription15SAMPLE_FREQ0,WOSampleFrequencyOffset:IfSEL_FCissettoa0,thensettingthisbittoa1willpolltheDSPforthelong-termFrequencyOffsetvalue.
ThevaluewillbeavailableintheFREQ_OFFSETbitsofthisregister.
IfSEL_FCissettoa1,thensettingthisbittoa1willpolltheDSPforthecurrentFrequencyControlvalue.
ThevaluewillbeavailableintheFREQ_OFFSETbitsofthisregister.
Thisregisterbitwillalwaysreadbackas0.
14:9RESERVED000000,RORESERVED:Writesignored,readas0.
8SEL_FC0,RWSelectFrequencyControl:Settingthisbittoa1willselectthecurrentFrequencyControlvalueinsteadoftheFrequencyOffset.
ThisvaluecontainsFrequencyOffsetplustheshorttermphasecorrectionandcanbeusedtoindicateamountofjitterinthesystem.
ThevaluewillbeavailableintheFREQ_OFFSETbitsofthisregister.
7:0FREQ_OFFSET00000000,ROFrequencyOffset:FrequencyoffsetvalueloadedfromtheDSPfollowingassertionoftheSAMPLE_FREQcontrolbit.
TheFrequencyOffsetorFrequencyControlvalueisatwos-complementsignedvalueinunitsofapproximately5.
1562ppm.
Therangeisasfollows:0x7F=+655ppm0x00=0ppm0x80=-660ppmCopyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock105SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
4.
3TDRControlRegister(TDR_CTRL),Page2ThisregistercontainscontrolfortheTimeDomainReflectometry(TDR)cablediagnostics.
TheTDRcablediagnosticssendspulsesdownthecableandcapturesreflectiondatatobeusedtoestimatecablelengthanddetectcertaincablingfaults.
Table10-30.
TDRControlRegister(TDR_CTRL),address0x16BitBitNameDefaultDescription15TDR_ENABLE0,RWTDREnable:EnableTDRmode.
ThisforcesthepowerupstatetothecorrectoperatingconditionforsendingandreceivingTDRpulses.
14TDR_100Mb0,RWTDR100Mb:SetstheTDRcontrollertousethe100MbTransmitter.
Thisallowsforsendingpulsewidthsinmultiplesof8ns.
Pulsesin100Mbmodewillalternatebetweenpositivepulsesandnegativepulses.
Defaultoperationusesthe10MbLinkPulsegenerator.
Pulsesmayincludejustthe50nspre-emphasisportionofthepulseorthe100nsfulllinkpulse(ascontrolledbysettingTDRWidth).
13TX_CHANNEL0,RWTransmitChannelSelect:Selecttransmitchannelforsendingpulses.
ThepulsecanbesentontheTransmitorReceivepair.
0:Transmitchannel1:Receivechannel12RX_CHANNEL0,RWReceiveChannelSelect:Selectreceivechannelfordetectingpulses.
ThepulsecanbemonitoredontheTransmitorReceivepair.
0:Transmitchannel1:Receivechannel11SEND_TDR0,RW/SCSendTDRPulse:SettingthisbitwillsendaTDRpulseandenablethemonitorcircuittocapturetheresponse.
Thisbitwillautomaticallyclearwhenthecaptureiscomplete.
10:8TDR_WIDTH000,RWTDRPulseWidth:Pulsewidthinclocksforthetransmittedpulse.
In100Mbmode,pulsesarein8nsincrements.
In10Mbmode,pulsesarein50nsincrements,butonly50nsor100nspulsescanbesent.
Sendingapulseof0widthwillnottransmitapulse,butallowsforbaselinetesting.
7TDR_MIN_MODE0,RWMin/MaxModecontrol:Thisbitcontrolsdirectionofthepulsetobedetected.
Defaultlooksforapositivepeak.
Thresholdandpeakvalueswillbeinterpretedappropriatelybasedonthisbit.
0:MaxMode,detectpositivepeak1:MinMode,detectnegativepeak6RESERVED0,RWRESERVED:Mustbezero.
5:0RX_THRESHOLD100000,RWRXThreshold:Thisvalueprovidesathresholdformeasurementtothestartofapeak.
IfMinModeissetto0,datamustbegreaterthanthisvaluetotriggeracapture.
IfMinModeis1,datamustbelessthanthisvaluetotriggeracapture.
Datarangesfrom0x00to0x3F,with0x20asthemidpoint.
Positivedataisgreaterthan0x20,negativedataislessthan0x20.
106RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
4.
4TDRWindowRegister(TDR_WIN),Page2ThisregistercontainssamplewindowcontrolfortheTimeDomainReflectometry(TDR)cablediagnostics.
Thetwovaluescontainedinthisregisterspecifythebeginningandendtimesforthewindowtomonitortheresponsetothetransmittedpulse.
Timevaluesarein8nsincrements.
Thisprovidesamethodtosearchformultipleresponsesandalsotoscreenouttheinitialoutgoingpulse.
Table10-31.
TDRWindowRegister(TDR_WIN),address0x17BitBitNameDefaultDescription15:8TDR_START00000000,RWTDRStartWindow:SpecifiesstarttimeformonitoringTDRresponse.
7:0TDR_STOP00000000,RWTDRStopWindow:SpecifiesstoptimeformonitoringTDRresponse.
TheStopWindowshouldbesettoavaluegreaterthanorequaltotheStartWindow.
10.
4.
5TDRPeakRegister(TDR_PEAK),Page2ThisregistercontainstheresultsoftheTDRPeakDetection.
ResultsarevalidiftheTDR_CTRL[11]isclearfollowingsendingtheTDRpulse.
Table10-32.
TDRPeakRegister(TDR_PEAK),address0x18BitBitNameDefaultDescription15:14RESERVED00,RORESERVED:Writesignored,readas0.
13:8TDR_PEAK000000,ROTDRPeakValue:ThisregistercontainsthepeakvaluemeasuredduringtheTDRsamplewindow.
IfMinModecontrol(TDR_CTRL[7])is0,thiscontainsthemaximumdetectedvalue.
IfMinModecontrolis1,thiscontainstheminimumdetectedvalue.
7:0TDR_PEAK_TIME00000000,ROTDRPeakTime:Specifiesthetimeforthefirstoccurrenceofthepeakvalue.
10.
4.
6TDRThresholdRegister(TDR_THR),Page2ThisregistercontainstheresultsoftheTDRThresholdDetection.
ResultsarevalidiftheTDR_CTRL[11]isclearfollowingsendingtheTDRpulse.
Table10-33.
TDRThresholdRegister(TDR_THR),address0x19BitBitNameDefaultDescription15:9RESERVED0000000,RORESERVED:Writesignored,readas0.
8TDR_THR_MET0,ROTDRThresholdMet:ThisbitindicatestheTDRthresholdwasmetduringthesamplewindow.
Avalueof0indicatesthethresholdwasnotmet.
7:0TDR_THR_TIME00000000,ROTDRThresholdTime:SpecifiesthetimeforthefirstdatathatmettheTDRthreshold.
Thisfieldisonlyvalidifthethresholdwasmet.
10.
4.
7VarianceControlRegister(VAR_CTRL),Page2TheVarianceControlandDataRegistersprovidecontrolandstatusfortheCableSignalQualityEstimationfunction.
TheCableSignalQualityEstimationallowsasimplemethodofdetermininganapproximateSignal-to-NoiseRatioforthe100Mbreceiver.
Thisregistercontainstheprogrammablecontrolsandstatusbitsforthevariancecomputation,whichcanbeusedtomakeasimpleSignal-to-NoiseRatioestimation.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock107SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-34.
VarianceControlRegister(VAR_CTRL),address0x1ABitBitNameDefaultDescription15VAR_RDY0,ROVarianceDataReadyStatus:IndicatesnewdataisavailableintheVariancedataregister.
ThisbitwillbeautomaticallyclearedaftertwoconsecutivereadsofVAR_DATA.
14:4RESERVED00000000000,RORESERVED:Writesignored,readas0.
3VAR_FREEZE0,RWFreezeVarianceRegisters:FreezeVAR_DATAregister.
ThisbitisensuresthatVAR_DATAregisterisfrozenforsoftwarereads.
ThisbitisautomaticallyclearedaftertwoconsecutivereadsofVAR_DATA.
2:1VAR_TIMER00,RWVarianceComputationTimer(inms):SelectstheVariancecomputationtimerperiod.
Afteranewvalueiswritten,computationisautomaticallyrestarted.
Newvarianceregistervaluesareloadedafterthetimerelapses.
Var_Timer=0=>2mstimer(default)Var_Timer=1=>4mstimerVar_Timer=2=>6mstimerVar_Timer=3=>8mstimerTimeunitsareactually217cyclesofan8nsclock,or1.
048576ms.
0VAR_ENABLE0,RWVarianceEnable:EnableVariancecomputation.
Offbydefault.
10.
4.
8VarianceDataRegister(VAR_DATA),Page2Thisregistercontainsthe32-bitVarianceSum.
ThecontentsofthedataarevalidonlywhenVAR_RDYisassertedintheVAR_CTRLregister.
UpondetectionofVAR_RDYasserted,softwareshouldsettheVAR_FREEZEbitintheVAR_CTRLregistertopreventloadingofanewvalueintotheVAR_DATAregister.
SincetheVarianceDatavalueis32-bits,tworeadsofthisregisterarerequiredtogetthefullvalue.
Table10-35.
VarianceDataRegister(VAR_DATA),address0x1BBitBitNameDefaultDescription15:0VAR_DATA000000000000VarianceData:0000,ROTworeadsarerequiredtoreturnthefull32-bitVarianceSumvalue.
FollowingsettingtheVAR_FREEZEcontrol,thefirstreadofthisregisterwillreturnthelow16bitsoftheVariancedata.
Asecondreadwillreturnthehigh16bitsofVariancedata.
10.
4.
9LinkQualityMonitorRegister(LQMR),Page2ThisregistercontainsthecontrolsfortheLinkQualityMonitorfunction.
TheLinkQualityMonitorprovidesamechanismforprogrammingasetofthresholdsforDSPparameters.
Ifthethresholdsareviolated,aninterruptwillbeassertedifenabledintheMISR.
Monitorcontrolandstatusareavailableinthisregister,whiletheLQDRregistercontrolsread/writeaccesstothresholdvaluesandcurrentparametervalues.
ReadingtheLQMRregisterclearswarningbitsandre-armstheinterruptgeneration.
Inaddition,thisregisterprovidesamechanimsforallowingautomaticresetofthe100MblinkbasedontheLinkQualityMonitorstatus.
Table10-36.
LinkQualityMonitorRegister(LQMR),address0x1DBitBitNameDefaultDescription15LQM_ENABLE0,RWLinkQualityMonitorEnable:EnablestheLinkQualityMonitor.
Theenableisqualifiedbyhavingavalid100Mblink.
Inaddition,theindividualthresholdscanbedisabledbysettingtothemaximumorminimumvalues.
108RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-36.
LinkQualityMonitorRegister(LQMR),address0x1D(continued)BitBitNameDefaultDescription14RESTART_ON_FC0,RWRestartonFrequencyControlWarning:AllowautomaticresetofDSPandrestartof100MbAdaptionondetectingaFrequencyThresholdviolation.
IftheSD_Optionbit,PCSR[8],issetto0,thethresholdviolationwillalsoresultinadropinLinkstatus.
13RESTART_ON0,RWRestartonFrequencyOffsetWarning:_FREQAllowautomaticresetofDSPandrestartof100MbAdaptionondetectingaFrequencyOffsetThresholdviolation.
IftheSD_Optionbit,PCSR[8],issetto0,thethresholdviolationwillalsoresultinadropinLinkstatus.
12RESTART_ON0,RWRestartonDBLWWarning:_DBLWAllowautomaticresetofDSPandrestartof100MbAdaptionondetectingaDBLWThresholdviolation.
IftheSD_Optionbit,PCSR[8],issetto0,thethresholdviolationwillalsoresultinadropinLinkstatus.
11RESTART_ON0,RWRestartonDAGCWarning:_DAGCAllowautomaticresetofDSPandrestartof100MbAdaptionondetectingaDAGCThresholdviolation.
IftheSD_Optionbit,PCSR[8],issetto0,thethresholdviolationwillalsoresultinadropinLinkstatus.
10RESTART_ON_C10,RWRestartonC1Warning:AllowautomaticresetofDSPandrestartof100MbAdaptionondetectingaC1Thresholdviolation.
IftheSD_Optionbit,PCSR[8],issetto0,thethresholdviolationwillalsoresultinadropinLinkstatus.
9FC_HI_WARN0,RO/CORFrequencyControlHighWarning:ThisbitindicatestheFrequencyControlHighThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
8FC_LO_WARN0,RO/CORFrequencyControlLowWarning:ThisbitindicatestheFrequencyControlLowThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
7FREQ_HI_WARN0,RO/CORFrequencyOffsetHighWarning:ThisbitindicatestheFrequencyOffsetHighThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
6FREQ_LO_WARN0,RO/CORFrequencyOffsetLowWarning:ThisbitindicatestheFrequencyOffsetLowThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
5DBLW_HI_WARN0,RO/CORDBLWHighWarning:ThisbitindicatestheDBLWHighThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
4DBLW_LO_WARN0,RO/CORDBLWLowWarning:ThisbitindicatestheDBLWLowThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
3DAGC_HI_WARN0,RO/CORDAGCHighWarning:ThisbitindicatestheDAGCHighThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
2DAGC_LO_WARN0,RO/CORDAGCLowWarning:ThisbitindicatestheDAGCLowThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
1C1_HI_WARN0,RO/CORC1HighWarning:ThisbitindicatestheDEQC1HighThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
0C1_LO_WARN0,RO/CORC1LowWarning:ThisbitindicatestheDEQC1LowThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
10.
4.
10LinkQualityDataRegister(LQDR),Page2Thisregisterprovidesread/writecontrolofthresholdsforthe100MbLinkQualityMonitorfunction.
Theregisteralsoprovidesamechanismforreadingcurrentadaptedparametervalues.
Thresholdvaluesmaynotbewrittenifthedeviceispowered-down.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock109SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-37.
LinkQualityDataRegister(LQDR),address0x1EBitBitNameDefaultDescription15:14RESERVED00,RORESERVED:Writesignored,readas0.
13SAMPLE_PARAM0,RWSampleDSPParameter:Settingthisbittoa1enablesreadingofcurrentparametervaluesandinitiatessamplingoftheparametervalue.
TheparametertobereadisselectedbytheLQ_PARAM_SELbits.
12WRITE_LQ_THR0,RWWriteLinkQualityThreshold:SettingthisbitwillcauseawritetotheThresholdregisterselectedbyLQ_PARAM_SELandLQ_THR_SEL.
ThedatawritteniscontainedinLQ_THR_DATA.
Thisbitwillalwaysreadbackas0.
11:9LQ_PARAM_SEL000,RWLinkQualityParameterSelect:This3-bitfieldselectstheLinkQualityParameter.
Thisfieldisusedforsamplingcurrentparametervaluesaswellasforreads/writestoThresholdvalues.
Thefollowingencodingsareavailable:000:DEQ_C1001:DAGC010:DBLW011:FrequencyOffset100:FrequencyControl101:Variancemostsignificantbits31:168LQ_THR_SEL0,RWLinkQualityThresholdSelect:ThisbitselectstheLinkQualityThresholdtobereadorwritten.
A0selectstheLowthreshold,whilea1selectsthehighthreshold.
WhencombinedwiththeLQ_PARAM_SELfield,thefollowingencodingsareavailable{LQ_PARAM_SEL,LQ_THR_SEL}:000,0:DEQ_C1Low000,1:DEQ_C1High001,0:DAGCLow001,1:DAGCHigh010,0:DBLWLow010,1:DBLWHigh011,0:FrequencyOffsetLow011,1:FrequencyOffsetHigh100,0:FrequencyControlLow100,1:FrequencyControlHigh101,0:VarianceHighbits7:0(Variancebits23:16)101,1:VarianceHighbits15:8(Variancebits31:24)7:0LQ_THR_DATA10000000,RWLinkQualityThresholdData:TheoperationofthisfieldisdependentonthevalueoftheSAMPLE_PARAMbit.
IfSAMPLE_PARAM=0:Onawrite,thisvaluecontainsthedatatobewrittentotheselectedLinkQualityThresholdregister.
Onaread,thisvaluecontainsthecurrentdataintheselectedLinkQualityThresholdregister.
IfSAMPLE_PARAM=1:Onaread,thisvaluecontainsthesampledparametervalue.
Thisvaluewillremainunchangeduntilanewreadsequenceisstarted.
110RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
4.
11LinkQualityMonitorRegister2(LQMR2),Page2ThisregistercontainsadditionalcontrolsfortheLinkQualityMonitorfunction.
TheLinkQualityMonitorprovidesamechanismforprogrammingasetofthresholdsforDSPparameters.
Ifthethresholdsareviolated,aninterruptwillbeassertedifenabledintheMISR.
Monitorcontrolandstatusareavailableinthisregister,whiletheLQDRregistercontrolsread/writeaccesstothresholdvaluesandcurrentparametervalues.
ReadingofLQMR2registerclearsitswarningbitsbutdoesNOTre-armtheinterruptgeneration;LQMRmustbereadtore-arminterruptgeneration.
Inaddition,thisregisterprovidesamechanismforallowingautomaticresetofthe100MblinkbasedontheLinkQualityMonitorvariancestatus.
Table10-38.
LinkQualityMonitorRegister2(LQMR2),address0x1FBitBitNameDefaultDescription15:1RESERVED00000,ROReserved:Writesignored,Readas0110RESTART_ON_VAR0,RWRestartonVarianceWarning:AllowautomaticresetofDSPandrestartof100MbAdaptionondetectingaFrequencyOffsetThresholdviolation.
IftheSD_Optionbit,PCSR[8],issetto0,thethresholdviolationwillalsoresultinadropinLinkstatus.
9:2RESERVED00000000,ROReserved:Writesignored,Readas01VAR_HI_WARN0,RO/CORVarianceHighWarning:ThisbitindicatestheVarianceHighThresholdwasexceeded.
Thisregisterbitwillbeclearedonread.
0RESERVED0,ROReserved:Writesignored,Readas0Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock111SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
5PTP1588BaseRegisters-Page4Page4PTP1588BaseRegistersareaccessiblebysettingbits[2:0]=100ofPAGESEL(13h).
10.
5.
1PTPControlRegister(PTP_CTL),Page4ThisregisterprovidesbasiccontrolofthePTP1588operation.
Table10-39.
PTPControlRegister(PTP_CTL),address0x14BitBitNameDefaultDescription15:1RESERVED000,ROReserved:Writesignored,Readas0312:1TRIG_SEL000,RWPTPTriggerSelect:0ThisfieldselectstheTriggerforloadingcontrolinformationorforenablingtheTrigger.
9TRIG_DIS0,RW/SCDisablePTPTrigger:SettingthisbitwilldisabletheselectedTrigger.
ThisbitdoesnotindicateDisablestatusforTriggers.
ThePTPTriggerStatusRegistershouldbeusedtodetermineTriggerStatus.
Thisbitisself-clearingandwillalwaysreadbackas0.
DisablingaTriggerwillnotdisconnectitfromaGPIOpin.
TheTriggervaluewillstillbedriventotheGPIOiftheTriggerisassignedtoaGPIO.
8TRIG_EN0,RW/SCEnablePTPTrigger:SettingthisbitwillenabletheselectedTrigger.
ThisbitdoesnotindicateEnablestatusforTriggers.
ThePTPTriggerStatusRegistershouldbeusedtodetermineTriggerStatus.
Thisbitisself-clearingandwillalwaysreadbackas0.
7TRIG_READ0,RW/SCReadPTPTrigger:SettingthisbitwillbegintheTriggerReadprocess.
TheTriggerisselectedbasedonthesettingoftheTRIG_SELbitsinthisregister.
Uponsettingthisbit,subsequentreadsofthePTP_TDRwillreturntheTriggerControlvalues.
Fieldsarereadinthesameorderaswritten.
6TRIG_LOAD0,RW/SCLoadPTPTrigger:SettingthisbitwilldisabletheselectedTriggerandbegintheTriggerloadprocess.
TheTriggerisselectedbasedonthesettingoftheTRIG_SELbitsinthisregister.
Uponsettingthisbit,subsequentwritestothePTP_TDRwillsettheTriggerControlfieldsfortheselectedTrigger.
TheTriggerLoadiscompletedonceallfieldshavebeenwritten,ortheTRIG_ENbithasbeensetinthisregister.
Thisbitisself-clearingandwillreadbackas0whentheTriggerLoadiscompletedeitherbywritingallTriggerControlfields,orbysettingtheTriggerEnable.
5PTP_RD_CLK0,RW/SCReadPTPClock:SettingthisbitwillcausethedevicetosamplethePTPClocktimevalue.
ThetimevaluewillbemadeavailableforreadingthroughthePTP_TDRregister.
Thisbitisself-clearingandwillalwaysreadbackas0.
4PTP_LOAD_CLK0,RW/SCLoadPTPClock:SettingthisbitwillcausethedevicetoloadthePTPClocktimevaluefromdatapreviouslywrittentothePTP_TDRregister.
Thisbitisself-clearingandwillalwaysreadbackas0.
3PTP_STEP_CLK0,RW/SCStepPTPClock:SettingthisbitwillcausethedevicetoaddavaluetothePTPClock.
ThevaluetobeaddedisthevaluepreviouslywrittentothePTP_TDRregister.
Thisbitisselfclearingandwillalwaysreadbackas0.
2PTP_ENABLE0,RWEnablePTPClock:SettingthisbitwillenablethePTPClock.
Readingthisbitwillreturnthecurrentenabledvalue.
Writinga0tothisbitwillhavenoeffect.
1PTP_DISABLE0,RW/SCDisablePTPClock:SettingthisbitwilldisablethePTPClock.
Writinga0tothisbitwillhavenoeffect.
Thisbitisself-clearingandwillalwaysreadbackas0.
0PTP_RESET0,RWResetPTPClock:SettingthisbitwillresetthePTPClockandassociatedlogic.
Inaddition,the1588registerswillbereset,withtheexceptionofthePTP_COCandPTP_CLKSRCregisters.
Unlikeotherbitsinthisregister,thisbitisnotself-clearingandmustbewrittento0toreleasetheclockandlogicfromreset.
112RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
5.
2PTPTimeDataRegister(PTP_TDR),Page4Thisregisterprovidesamechanismforreadingandwritingthe1588TimeandTriggerControlvalues.
ThefunctionofthisregisterisdeterminedbycontrolsinthePTP_CTLregister.
Table10-40.
PTPTimeDataRegister(PTP_TDR),address0x15BitBitNameDefaultDescription15:0TIME_DATAXXXXXXXXXXXXTimeData:XXXX,ROOnReads,successivelyreturns16-bitvaluesoftheClocktimeorTriggerControlXXXXXXXXXXXXinformationasselectedbycontrolsinthePTPControlRegister.
AdditionalreadsXXXX,WObeyondtheavaliablefieldswillalwaysreturn0.
OnWrites,successivelystoresthe16-bitvaluesofClocktimeorTriggerControlInformationasselectedbycontrolsinthePTPControlRegister.
10.
5.
3PTPStatusRegister(PTP_STS),Page4ThisregisterprovidesbasicstatusandinterruptcontrolforthePTP1588operation.
Table10-41.
PTPStatusRegister(PTP_STS),address0x16BitBitNameDefaultDescription15:1RESERVED0000,ROReserved:Writesignored,Readas0211TXTS_RDY0,ROTransmitTimestampReady:ATransmitTimestampisavailableforanoutboundPTPMessage.
ThisbitwillbecleareduponreadoftheTransmitTimestampifnoothertimestampsareready.
10RXTS_RDY0,ROReceiveTimestampReady:AReceiveTimestampisavailableforaninboundPTPMessage.
ThisbitwillbecleareduponreadoftheReceiveTimestampifnoothertimestampsareready.
9TRIG_DONE0,RO/CORPTPTriggerDone:APTPTriggerhasoccured.
Thisbitwillbecleareduponread.
ThisbitwillonlybesetifTriggerNotificationisturnedonfortheTriggerthroughtheTriggerConfigurationRegisters.
8EVENT_RDY0,ROPTPEventTimestampReady:APTPEventTimestampisavailable.
ThisbitwillbecleareduponreadofthePTPEventStatusRegisterifnoothereventtimestampsareready.
7:4RESERVED0000,ROReserved:Writesignored,Readas03TXTS_IE0,RWTransmitTimestampInterruptEnable:EnableInterruptonTransmitTimestampReady.
2RXTS_IE0,RWReceiveTimestampInterruptEnable:EnableInterruptonReceiveTimestampReady.
1TRIG_IE0,RWTriggerInterruptEnable:EnableInterruptonTriggerCompletion.
0EVENT_IE0,RWEventInterruptEnable:EnableInterruptonEventTimestampReady.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock113SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
5.
4PTPTriggerStatusRegister(PTP_TSTS),Page4ThisregisterprovidesstatusofthePTP1588Triggers.
ThebitsinthisregisterindicatethecurrentstatusofeachoftheTriggermodules.
Theerrorbitswillbesetiftheassociatednotificationenable(TRIGN_NOTIFY)issetinthePTPTriggerConfigurationRegisters.
Table10-42.
PTPTriggerStatusRegister(PTP_TSTS),address0x17BitBitNameDefaultDescription15TRIG7_ERROR0,RO/SCTrigger7Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
14TRIG7_ACTIVE0,RO/SCTrigger7Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
13TRIG6_ERROR0,RO/SCTrigger6Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
12TRIG6_ACTIVE0,RO/SCTrigger6Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
11TRIG5_ERROR0,RO/SCTrigger5Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
10TRIG5_ACTIVE0,RO/SCTrigger5Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
9TRIG4_ERROR0,RO/SCTrigger4Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
8TRIG4_ACTIVE0,RO/SCTrigger4Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
7TRIG3_ERROR0,RO/SCTrigger3Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
6TRIG3_ACTIVE0,RO/SCTrigger3Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
5TRIG2_ERROR0,RO/SCTrigger2Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
4TRIG2_ACTIVE0,RO/SCTrigger2Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
3TRIG1_ERROR0,RO/SCTrigger1Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
2TRIG1_ACTIVE0,RO/SCTrigger1Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
1TRIG0_ERROR0,RO/SCTrigger0Error:ThisbitindicatestheTriggerwasimproperlyprogrammedtotriggeratatimepriortothecurrenttime.
ThisbitwillbeclearedwhentheTriggerisdisabledand/orre-armed.
0TRIG0_ACTIVE0,RO/SCTrigger0Active:ThisbitindicatestheTriggerisenabledandhasnotcompleted.
114RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
5.
5PTPRateLowRegister(PTP_RATEL),Page4Thisregistercontainsthelow16-bitsofthePTPRatecontrol.
ThePTPRateControlindicatesapositiveornegativeadjustmenttothereferenceclockperiodinunitsof2-32ns.
Oneachreferenceclockcycle,thePTPClockwillbeadjustedbyaddingREF_CLK_PERIOD+/-PTP_RATE.
ThePTPRateshouldbewrittenasPTP_RATEH,followedbyPTP_RATEL.
TheratewilltakeeffectonthewritetothePTP_RATELregister.
Table10-43.
PTPRateLowRegister(PTP_RATEL),address0x18BitBitNameDefaultDescription15:0PTP_RATE_LO000000000000PTPRateLow16-bits:0000,RWWritingtothisregisterwillsetthelow16-bitsoftheRateControlvalue.
TheRateControlvalueisinunitsof2-32ns.
Uponwritingtothisregister,thefullRateControlvaluewillbeloadedtothedevice.
10.
5.
6PTPRateHighRegister(PTP_RATEH),Page4ThisregistercontainstheupperbitsofthePTPRatecontrol.
Inaddition,itcontainsadirectioncontroltoindicatewhetherthedeviceisoperatingfasterorslowerthanthereferenceclockfrequency.
WhensettingthePTPRate,thisregistershouldbewrittenfirst,followedbyawritetothePTP_RATELregister.
TheratewilltakeeffectonthewritetothePTP_RATELregister.
Table10-44.
PTPRateHighRegister(PTP_RATEH),address0x19BitBitNameDefaultDescription15PTP_RATE_DIR0,RWPTPRateDirection:Thesettingofthisbitcontrolswhetherthedevicewilloperateatahigherorlowerfrequencythanthereferenceclock.
0:HigherFrequency.
ThePTP_RATEvaluewillbeaddedtotheclockoneverycycle.
1:LowerFrequency.
ThePTP_RATEvaluewillbesubtractedfromtheclockoneverycycle.
14PTP_TMP_RATE0,RWPTPTemporaryRate:SettingthisbitwillcausetheratetobeappliedtotheclockforthedurationsetinthePTPTemporaryRateDurationRegister(PTP_TRD).
1:TemporaryRate0:NormalRate13:1RESERVED0000,ROReserved:Writesignored,Readas009:0PTP_RATE_HI0000000000,RWPTPRateHigh10-bits:Writingtothisregisterwillsetthehigh10-bitsoftheRateControlvalue.
TheRateControlvalueisinunitsof2-32ns.
10.
5.
7PTPReadChecksum(PTP_RDCKSUM),Page4Thisregisterkeepsarunningone'scomplementchecksumof16-bitreaddatavaluesforvalidPage4readaccesses.
Clearthechecksumonareadtothisregister;readdatafromthisregisterisnotaccumulatedinthereadchecksumsincetheregisterisclearedonread.
However,readdatafromthewritechecksumregisterisaccumulatedtoallowcrosschecking.
ChecksumsarenotaccumulatedforPHYControlFrameregisteraccesses,butareclearedonmanagementorPHYControlFramereads.
Table10-45.
PTPReadChecksum(PTP_RDCKSUM),address0x1ABitBitNameDefaultDescription15:0RD_CKSUMXXXXXXXXXXXXPTPReadChecksum.
XXXX,RO/CORCopyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock115SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
5.
8PTPWriteChecksum(PTP_WRCKSUM),Page4Thisregisterkeepsarunningone'scomplementchecksumof16-bitwritedatavaluesforPage4writeaccesses.
Clearthechecksumonaread.
WritedatatothisregisterorthereadchecksumregisterAREaccumulatedinthewritechecksumtoallowcrosschecking.
Readdatafromthisregisterisaccumulatedinthereadchecksumtoallowcrosschecking.
ChecksumsarenotaccumulatedforPHYControlFrameregisteraccesses,butareclearedonmanagementorPHYControlFramereads.
Table10-46.
PTPWriteChecksum(PTP_WRCKSUM),address0x1BBitBitNameDefaultDescription15:0WR_CKSUMXXXXXXXXXXXXPTPWriteChecksum.
XXXX,RO/COR10.
5.
9PTPTransmitTimestampRegister(PTP_TXTS),Page4ThisregisterprovidesamechanismforreadingtheTransmitTimestamp.
Thefieldsarereadinthefollowingorder:Timestamp_ns[15:0]Overflow_cnt[1:0],Timestamp_ns[29:16]Timestamp_sec[15:0]Timestamp_sec[31:16]TheOverflow_cntvalueindicatesiftimestampsweredroppedduetoanoverflowoftheTransmitTimestampqueue.
Theoverflowcounterwillstickatavalueofthreeifadditionaltimestampsweremissed.
Table10-47.
PTPTransmitTimestampRegister(PTP_TXTS),address0x1CBitBitNameDefaultDescription15:0PTP_TX_TS000000000000PTPTransmitTimestamp:0000,ROReadingthisregisterwillreturntheTransmitTimestampinfour16-bitreads.
10.
5.
10PTPReceiveTimestampRegister(PTP_RXTS),Page4ThisregisterprovidesamechanismforreadingtheReceiveTimestampandidentificationinformation.
Thefieldsarereadinthefollowingorder:Timestamp_ns[15:0]Overflow_cnt[1:0],Timestamp_ns[29:16]Timestamp_sec[15:0]Timestamp_sec[31:16]sequenceId[15:0]messageType[3:0],source_hash[11:0]TheOverflow_cntvalueindicatesiftimestampsweredroppedduetoanoverflowoftheTransmitTimestampqueue.
Theoverflowcounterwillstickatavalueofthreeifadditionaltimestampsweremissed.
Table10-48.
PTPReceiveTimestampRegister(PTP_RXTS),address0x1DBitBitNameDefaultDescription15:0PTP_RX_TS000000000000PTPReceiveTimestamp:0000,ROReadingthisregisterwillreturntheReceiveTimestampinfour16-bitreads.
116RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
5.
11PTPEventStatusRegister(PTP_ESTS),Page4ThisregisterprovidesStatusfortheEventTimestampunit.
ReadingthisregisterprovidesstatusforthenextEventTimestampcontainedintheEventDataRegister.
Ifthisregisteris0,noEventTimestampisavailableintheEventDataRegister.
ReadingthisregisterwillautomaticallymovetothenextEventinthequeue.
Table10-49.
PTPEventStatusRegister(PTP_ESTS),address0x1EBitBitNameDefaultDescription15:1RESERVED00000,ROReserved:Writesignored,Readas0110:8EVNTS_MISSED000,RO/SCEventMissed:IndicatesnumberofeventshavebeenmissedpriortothistimestampfortheEVNT_NUMindicated.
Thiscountvaluewillstickat7ifmorethan7eventsaremissed.
7:6EVNT_TS_LEN00,RO/SCEventTimestampLength:IndicateslengthoftheTimestampfieldin16-bitwordsminus1.
Althoughallfieldsareavailable,thisindicateshowmanyofthefieldscontaindatadifferentfromthepreviousEventTimestamp.
Thisallowssoftwaretoavoidreadingmoresignificantfieldsiftheyhavenotchangedsincetheprevioustimestamp.
Thisfieldisvalidforbothsingleandmultipleevents.
ThefollowingshowsthenumberofleastsignificantfieldswhichhavenewdataforeachsettingofTS_LENGTH:00:One16-bitfieldisnew(Timestamp_ns[15:0])01:Two16-bitfieldsarenew10:Three16-bitfieldsarenew11:Allfour16-bitfieldsarenew5EVNT_RF0,RO/SCEventRise/Falldirection:Indicateswhethertheeventisariseorfallingevent.
IftheMULT_EVNTbitissetto1,thisbitindicatestheRise/FalldirectionfortheeventindicatedbyEVNT_NUM.
0=Fallingedgedetected1=Risingedgedetected4:2EVNT_NUM000,RO/SCEventNumber:IndicatesEventTimestampUnitwhichdetectedanevent.
IftheMULT_EVNTbitissetto0,thisindicatesthelowesteventnumbercaptured.
Ifeventshavebeenmissedpriortothistimestamp,itindicatesthelowesteventnumbercapturedwhichhadatleastonemissedevent.
1MULT_EVNT0,RO/SCMultipleEventDetect:Indicatesmultipleeventsweredetectedatthesametime.
Ifmultipleeventsaredetected,anextendedeventstatusfieldisavailableasthefirstdatareadfromtheEventDataRegister.
0=Singleeventdetected1=Multipleeventsdetected0EVENT_DET0,RO/SCPTPEventDetected:IndicatesanEventhasbeendetectedbyoneoftheEventTimestampUnits.
10.
5.
12PTPEventDataRegister(PTP_EDATA),Page4ThisregisterprovidesamechanismforreadingtheEventTimestampandextendedeventstatus.
Ifpresent,theextendedeventstatusisreadpriortoreadingtheEventTimestamp.
PresenceoftheExtendedEventStatusfieldisindicatedbytheMULT_EVNTbitinthePTPEventStatusRegister.
Thetimestampconsistsoffour16-bitfields.
ThisregistercontainsavalidtimestampifthePTP_ESTSregisterindicatesanEventTimestampisavailable.
Notallfieldshavetobereadforeachtimestamp.
Forexample,iftheEVNT_TS_LENindicatesthesecondsfieldhasnotchangedfromthepreviousevent,softwaremayskipthatread.
ReadingthePTP_ESTSregisterwillcausethedevicetomovetothenextavailabletimestamp.
Thefieldsarereadinthefollowingorder:ExtendedEventStatus[15:0](onlyavailableifPTP_ESTSindicatesdetectionofmultipleevents)Timestamp_ns[15:0]Timestamp_ns[29:16](upper2bitsarealways0)Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock117SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTimestamp_sec[15:0]Timestamp_sec[31:16]ForExtendedEventStatus,thefollowingdefinitionisusedforthePTPEventDataRegister:Table10-50.
PTPEventDataRegister(PTP_EDATA),address0x1FBitBitNameDefaultDescription15E7_RISE0,RO/SCRise/FalledgedirectionforEvent7:IndicatesdirectionofEvent70=Fall1=Rise14E7_DET0,RO/SCEvent7detected:IndicatesEvent7detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
13E6_RISE0,RO/SCRise/FalledgedirectionforEvent6:IndicatesdirectionofEvent60=Fall1=Rise12E6_DET0,RO/SCEvent6detected:IndicatesEvent6detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
11E5_RISE0,RO/SCRise/FalledgedirectionforEvent5:IndicatesdirectionofEvent50=Fall1=Rise10E5_DET0,RO/SCEvent5detected:IndicatesEvent5detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
9E4_RISE0,RO/SCRise/FalledgedirectionforEvent4:IndicatesdirectionofEvent40=Fall1=Rise8E4_DET0,RO/SCEvent4detected:IndicatesEvent4detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
7E3_RISE0,RO/SCRise/FalledgedirectionforEvent3:IndicatesdirectionofEvent30=Fall1=Rise6E3_DET0,RO/SCEvent3detected:IndicatesEvent3detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
5E2_RISE0,RO/SCRise/FalledgedirectionforEvent2:IndicatesdirectionofEvent20=Fall1=Rise4E2_DET0,RO/SCEvent2detected:IndicatesEvent2detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
3E1_RISE0,RO/SCRise/FalledgedirectionforEvent1:IndicatesdirectionofEvent10=Fall1=Rise2E1_DET0,RO/SCEvent1detected:IndicatesEvent1detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
1E0_RISE0,RO/SCRise/FalledgedirectionforEvent0:IndicatesdirectionofEvent00=Fall1=Rise0E0_DET0,RO/SCEvent0detected:IndicatesEvent0detectedarisingorfallingedgeatthetimecontainedinthePTP_EDATAregistertimestamp.
118RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Fortimestampfields,thefollowingdefinitionisusedforthePTPEventDataRegister:Table10-51.
PTPEventDataRegister(PTP_EDATA),address0x1FBitBitNameDefaultDescription15:0PTP_EVNT_TSXXXXXXXXXXXXPTPEventTimestamp:XXXX,ROReadingthisregisterwillreturn16bitsoftheEventTimestamp.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock119SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
6PTP1588ConfigurationRegisters-Page5Page5PTP1588ConfigurationRegistersareaccessiblebysettingbits[2:0]=101ofPAGESEL(13h).
10.
6.
1PTPTriggerConfigurationRegister(PTP_TRIG),Page5ThisregisterprovidesbasicconfigurationforIEEE1588Triggers.
TowriteconfigurationtoaTrigger,settheTRIG_WRbitalongwiththeTRIG_SELandothercontrolinformation.
ToreadconfigurationfromaTrigger,settheTRIG_SELencodingtotheTriggerdesired,andsettheTRIG_WRbitto0.
ThesubsequentreadofthePTP_TRIGregisterwillreturntheconfigurationinformation.
Table10-52.
PTPTriggerConfigurationRegister(PTP_TRIG),address0x14BitBitNameDefaultDescription15TRIG_PULSE0,RWTriggerPulse:SettingthisbitwillcausetheTriggertogenerateaPulseratherthanasinglerisingorfallingedge.
14TRIG_PER0,RWTriggerPeriodic:SettingthisbitwillcausetheTriggertogenerateaperiodicsignal.
Ifthisbitis0,theTriggerwillgenerateasinglePulseorEdgedependingontheTriggerControlsettings.
13TRIG_IF_LATE0,RWTrigger-if-lateControl:SettingthisbitwillallowanimmediateTriggerintheeventtheTriggerisprogrammedtoatimevaluewhichislessthanthecurrenttime.
Thisprovidesamechanismforgeneratinganimmediatetriggerortoimmediatelybegingeneratingaperiodicsignal.
Foraperiodicsignal,nonotificationbegeneratedifthisbitissetandaLateTriggeroccurs.
12TRIG_NOTIFY0,RWTriggerNotificationEnable:SettingthisbitwillenableTriggerstatustobereportedoncompletionofaTriggeroronanerrordetectionduetolatetrigger.
IfTriggerinterruptsareenabled,thenotificationwillalsoresultinaninterruptbeinggenerated.
11:8TRIG_GPIO0000,RWTriggerGPIOConnection:Settingthisfieldtoanon-zerovaluewillconnecttheTriggertotheassociatedGPIOpin.
Validsettingsforthisfieldare1thru12.
7TRIG_TOGGLE0,RWTriggerToggleModeEnable:Settingthisbitwillputthetriggerintotogglemode.
Intogglemode,theinitialvaluewillbeignoredandthetriggeroutputwillbetoggledatthetriggertime.
6:4RESERVED000,ROReserved:Writesignored,Readas03:1TRIG_CSEL000,RWTriggerConfigurationSelect:ThisfieldselectstheTriggerforconfigurationreadorwrite.
0TRIG_WR0,RW/SCTriggerConfigurationWrite:SettingthisbitwillgenerateaConfigurationWritetotheselectedTrigger.
Thisbitwillalwaysreadbackas0.
10.
6.
2PTPEventConfigurationRegister(PTP_EVNT),Page5ThisregisterprovidesbasicconfigurationforIEEE1588Events.
TowriteconfigurationtoanEventTimestampUnit,settheEVNT_WRbitalongwiththeEVNT_SELandothercontrolinformation.
ToreadconfigurationfromanEventTimestampUnit,settheEVNT_SELencodingtotheEventdesired,andsettheEVNT_WRbitto0.
ThesubsequentreadofthePTP_EVNTregisterwillreturntheconfigurationinformation.
Table10-53.
PTPEventConfigurationRegister(PTP_EVNT),address0x15BitBitNameDefaultDescription15RESERVED0,ROReserved:Writesignored,Readas014EVNT_RISE0,RWEventRiseDetectEnable:EnableDetectionofRisingedgeonEventinput.
13EVNT_FALL0,RWEventFallDetectEnable:EnableDetectionofFallingedgeonEventinput.
120RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-53.
PTPEventConfigurationRegister(PTP_EVNT),address0x15(continued)BitBitNameDefaultDescription12EVNT_SINGLE0,RWSingleEventCapture:Settingthisbittoa1willenablesingleeventcaptureoperation.
TheEVNT_RISEandEVNT_FALLenableswillbecleareduponavalideventtimestampcapture.
11:8EVNT_GPIO0000,RWEventGPIOConnection:Settingthisfieldtoanon-zerovaluewillconnecttheEventtotheassociatedGPIOpin.
Validsettingsforthisfieldare1thru12.
7:4RESERVED0000,ROReserved:Writesignored,Readas03:1EVNT_SEL000,RWEventSelect:ThisfieldselectstheEventTimestampUnitforconfigurationreadorwrite.
0EVNT_WR0,RWEventConfigurationWrite:SettingthisbitwillgenerateaConfigurationWritetotheselectedEventTimestampUnit.
10.
6.
3PTPTransmitConfigurationRegister0(PTP_TXCFG0),Page5ThisregisterprovidesconfigurationforIEEE1588TransmitTimestampoperation.
Table10-54.
PTPTransmitConfigurationRegister0(PTP_TXCFG0),address0x16BitBitNameDefaultDescription15SYNC_1STEP0,RWSyncMessageOne-StepEnable:EnableautomaticinsertionoftimestampintotransmitSyncMessages.
Devicewillautomaticallyparsemessageandinsertthetimestampinthecorrectlocation.
UPDchecksumandCRCfieldswillberegenerated.
14RESERVED0,ROReserved:Writesignored,Readas013DR_INSERT0,RWInsertDelay_ReqTimestampinDelay_Resp:Ifthisbitissettoa1,thedeviceinsertthetimestampfortransmittedDelay_ReqmessagesintoinboundDelay_Respmessages.
ThemostrecenttimestampwillbeusedforanyinboundDelay_Respmessage.
ThereceivetimestampinsertionlogicmustbeenabledthroughthePTPReceiveConfigurationRegisters.
12NTP_TS_EN0,RWEnableTimestampingofNTPPackets:Ifthisbitissetto0,thedevicewillchecktheUDPprotocolfieldforaPTPEventmessage(value319).
Ifthisbitissetto1,thedevicewillchecktheUDPprotocolfieldforanNTPmessage(value123).
Thissettingappliestothetransmitandreceivepacketparsingengines.
11IGNORE_2STEP0,RWIgnoreTwo_StepflagforOne-Stepoperation:Ifthisbitissettoa0,thedevicewillnotinsertatimestampiftheTwo_StepbitissetintheflagsfieldofthePTPheader.
Ifthisbitissetto1,thedevicewillinsertatimestampindependentofthesettingoftheTwo_Stepflag.
10CRC_1STEP0,RWDisablecheckingofCRCforOne-Stepoperation:Ifthisbitissettoa0,thedevicewillforceaCRCerrorforOne-StepoperationiftheincomingframehasaCRCerror.
Ifthisbitissettoa1,thedevicewillsendtheOne-StepframewithavalidCRC,eveniftheincomingCRCisinvalid.
9CHK_1STEP0,RWEnableUDPChecksumcorrectionforOne-StepOperation:EnablescorrectionoftheUDPchecksumformessageswhichincludeinsertionofthetimestamp.
ThechecksumiscorrectedbymodifyingthelasttwobytesoftheUDPdata.
ThelasttwobytesmustbetransmittedbytheMACas0's.
ThiscontrolmustbesetforproperIPv6/UDPOne-Stepoperation.
ThiscontrolwillhavenoeffectforLayer2Ethernetmessages.
8IP1588_EN0,RWEnableIEEE1588definedIPaddressfilter:EnablefilteringofUDP/IPEventmessagesusingtheIANAassignedIPDestinationaddresses.
Ifthisbitissetto1,packetswithIPDestinationaddresseswhichdonotmatchtheIANAassignedaddresseswillnotbetimestamped.
ThisfieldaffectsoperationforbothIPv4andIPv6.
Ifthisfieldissetto0,IPdestinationaddresseswillbeignored.
7TX_L2_EN0,RWLayer2TimestampEnable:EnablesdetectionofIEEE802.
3/EthernetencapsulatedPTPeventmessages.
6TX_IPV6_EN0,RWIPv6TimestampEnable:EnablesdetectionofUDP/IPv6encapsulatedPTPeventmessages.
5TX_IPV4_EN0,RWIPv4TimestampEnable:EnablesdetectionofUDP/IPv4encapsulatedPTPeventmessages.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock121SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-54.
PTPTransmitConfigurationRegister0(PTP_TXCFG0),address0x16(continued)BitBitNameDefaultDescription4:1TX_PTP_VER0000,RWPTPVersion:EnableTimestampcaptureforaspecificversionoftheIEEE1588specification.
Thisfieldmaybeprogrammedtoanyvaluebetween1and15andallowssupportforfutureversionsoftheIEEE1588specification.
Avalueof0willdisableversionchecking(notrecommended).
0TX_TS_EN0,RWTransmitTimestampEnable:EnableTimestampcaptureforTransmit.
10.
6.
4PTPTransmitConfigurationRegister1(PTP_TXCFG1),Page5ThisregisterprovidesdataandmaskfieldstofilterthefirstbyteinaPTPMessage.
Thisfunctionwillbedisabledifallthemaskbitsaresetto0.
Table10-55.
PTPTransmitConfigurationRegister1(PTP_TXCFG1),address0x17BitBitNameDefaultDescription15:8BYTE0_MASK00000000,RWByte0Data:BitmasktobeusedformatchingByte0ofthePTPMessage.
Aoneinanybitenablesmatchingfortheassociateddatabit.
Ifnomatchingisrequired,allbitsofthemaskshouldbesetto0.
7:0BYTE0_DATA00000000,RWByte0Mask:DatatobeusedformatchingByte0ofthePTPMessage.
10.
6.
5PHYStatusFrameConfigurationRegister0(PSF_CFG0),Page5ThisregisterprovidesconfigurationforthePHYStatusFramefunction.
Table10-56.
PHYStatusFrameConfigurationRegister0(PSF_CFG0),address0x18BitBitNameDefaultDescription15:1RESERVED000,ROReserved:Writesignored,Readas0312:1MAC_SRC_ADD00,RWPHYStatusFrameMacSourceAddress:1Selectssourceaddressasfollows:00:UseMacAddress[0800170B6B0F]01:UseMacAddress[080017000000]10:UseMacMulticastDestAddress11:UseMacAddress[000000000000]10:8MIN_PRE000,RWPHYStatusFrameMinimumPreamble:DeterminestheminimumpreamblebytesrequiredforsendingpacketsontheMIIinterface.
ItisrecommendedthatthisbesettothesmallestvaluetheMACwilltolerate.
7PSF_ENDIAN0,RWPHYStatusFrameEndianControl:Foreach16-bitfieldinaStatusMessage,thedatawillnormallybepresentedinnetworkbyteorder(Mostsignificantbytefirst).
Ifthisbitissettoa1,thebytedatafieldswillbereversedsothattheleastsignificantbyteisfirst.
6PSF_IPV40,RWPHYStatusFrameIPv4Enable:ThisbitcontrolsthetypeofpacketusedforPHYStatusFrames.
0=Layer2Ethernetpackets1=IPv4packets.
5PSF_PCF_RD0,RWPHYControlFrameReadPHYStatusFrameEnable:EnablePHYStatusFramedeliveryofPHYControlFramereaddata.
DatareadviaaPHYControlFramewillbereturnedinaPHYStatusFrame.
4PSF_ERR_EN0,RWPSFErrorPHYStatusFrameEnable:EnablePHYStatusFramedeliveryofPHYStatusFrameErrors.
ThisbitwillnotindependentlyenablePHYStatusFrameoperation.
OneoftheotherenablebitsmustbesetforPHYStatusFramestobegenerated.
3PSF_TXTS_EN0,RWTransmitTimestampPHYStatusFrameEnable:EnablePHYStatusFramedeliveryofTransmitTimestamps.
122RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-56.
PHYStatusFrameConfigurationRegister0(PSF_CFG0),address0x18(continued)BitBitNameDefaultDescription2PSF_RXTS_EN0,RWReceiveTimestampPHYStatusFrameEnable:EnablePHYStatusFramedeliveryofReceiveTimestamps.
1PSF_TRIG_EN0,RWTriggerPHYStatusFrameEnable:EnablePHYStatusFramedeliveryofTriggerStatus.
0PSF_EVNT_EN0,RWEventPHYStatusFrameEnable:EnablePHYStatusFramedeliveryofEventTimestamps.
10.
6.
6PTPReceiveConfigurationRegister0(PTP_RXCFG0),Page5,ThisregisterprovidesconfigurationforIEEE1588ReceiveTimestampoperation.
Table10-57.
PTPReceiveConfigurationRegister0(PTP_RXCFG0),address0x19BitBitNameDefaultDescription15DOMAIN_EN0,RWDomainMatchEnable:Ifsetto1,theReceiveTimestampunitwillrequiretheDomainfieldtomatchthevalueprogrammedinthePTP_DOMAINfieldofthePTP_RXCFG3register.
Ifsetto0,theReceiveTimestampwillignorethePTP_DOMAINfield.
14ALT_MAST_DIS0,RWAlternateMasterTimestampDisable:DisablestimestampgenerationiftheAlternate_Masterflagisset:1=DonotgeneratetimestampifAlternate_Master=10=IgnoreAlternate_Masterflag13USER_IP_SEL0,RWIPAddressdataselect:SelectsportionofIPaddressaccessiblethroughthePTP_RXCFG2register:0=MostSignificantOctets1=LeastSignificantOctets12USER_IP_EN0,RWEnableUser-programmedIPaddressfilter:EnabledetectionofUDP/IPEventmessagesusingaprogrammableIPaddresses.
TheIPAddressissetusingthePTP_RXCFG2register.
11RX_SLAVE0,RWReceiveSlaveOnly:Bydefault,theReceiveTimestampUnitwillprovideTimestampsforeventmessagesmeetingotherrequirements.
Settingthisbittoa1willpreventDelay_ReqmessagesfrombeingTimestampedbyrequiringthattheControlField(offset32inthePTPmessage)besettoavalueotherthan1.
10:8IP1588_EN000,RWEnableIEEE1588definedIPaddressfilters:EnabledetectionofUDP/IPEventmessagesusingtheIANAassignedIPDestinationaddresses.
ThisfieldaffectsoperationforbothIPv4andIPv6.
ATimestampiscapturedforthePTPmessageiftheIPdestinationaddressmatchesthefollowing:IP1588_EN[0]:DestIPaddress=224.
0.
1.
129IP1588_EN[1]:DestIPaddress=224.
0.
1.
130-132IP1588_EN[2]:DestIPaddress=224.
0.
0.
1077RX_L2_EN0,RWLayer2TimestampEnable:EnablesdetectionofIEEE802.
3/EthernetencapsulatedPTPeventmessages.
6RX_IPV6_EN0,RWIPv6TimestampEnable:EnablesdetectionofUDP/IPv6encapsulatedPTPeventmessages.
5RX_IPV4_EN0,RWIPv4TimestampEnable:EnablesdetectionofUDP/IPv4encapsulatedPTPeventmessages.
4:1RX_PTP_VER0000,RWPTPVersion:EnableTimestampcaptureforaspecificversionoftheIEEE1588specification.
Thisfieldmaybeprogrammedtoanyvaluebetween1and15andallowssupportforfutureversionsoftheIEEE1588specification.
Avalueof0willdisableversionchecking(notrecommended).
0RX_TS_EN0,RWReceiveTimestampEnable:EnableTimestampcaptureforReceive.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock123SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
6.
7PTPReceiveConfigurationRegister1(PTP_RXCFG1),Page5ThisregisterprovidesdataandmaskfieldstofilterthefirstbyteinaPTPMessage.
Thisfunctionwillbedisabledifallthemaskbitsaresetto0.
Table10-58.
PTPReceiveConfigurationRegister1(PTP_RXCFG1),address0x1ABitBitNameDefaultDescription15:8BYTE0_MASK00000000,RWByte0Data:BitmasktobeusedformatchingByte0oftheReceivePTPMessage.
Aoneinanybitenablesmatchingfortheassociateddatabit.
Ifnomatchingisrequired,allbitsofthemaskshouldbesetto0.
7:0BYTE0_DATA00000000,RWByte0Mask:DatatobeusedformatchingByte0oftheReceivePTPMessage.
10.
6.
8PTPReceiveConfigurationRegister2(PTP_RXCFG2),Page5ThisregisterprovidesforprogramminganIPaddresstobeusedforfilteringpacketstodetectPTPEventMessages.
SincetheIPv4addressis32-bits,towriteanIPaddress,softwaremustwritetwo16-bitvalues.
TheUSER_IP_SELbitinthePTP_RXCFG0registerselectswhichoctectsoftheIPaddressareaccessiblethroughthisregister.
Forexample,towriteanIPaddressof224.
0.
1.
129,softwareshoulddothefollowing:1.
SetUSER_IP_SELbitinPTP_RXCFG0registerto02.
Write0xE000(224.
00)toPTP_RXCFG23.
SetUSER_IP_SELbitinthePTP_RXCFG0registerto14.
Write0x0181(01.
129)toPTP_RXCFG2ReadingthisregisterwillreturntheIPaddressfieldselectedbyUSER_IP_SEL.
Table10-59.
PTPReceiveConfigurationRegister2(PTP_RXCFG2),address0x1BBitBitNameDefaultDescription15:0IP_ADDR_DATA000000000000ReceiveIPAddressData:0000,RW16-bitsoftheIPAddressfieldtobereadorwritten.
TheUSER_IP_SELbitinthePTP_RXCFG0RegisterselectstheportionoftheIPaddressistobereadorwritten.
10.
6.
9PTPReceiveConfigurationRegister3(PTP_RXCFG3),Page5ThisregisterprovidesextendedconfigurationforIEEE1588ReceiveTimestampoperation.
Table10-60.
PTPReceiveConfigurationRegister3(PTP_RXCFG3),address0x1CBitBitNameDefaultDescription15:1TS_MIN_IFG1100,RWMinimumInter-frameGap:2WhenaTimestampisappendedtoaPTPMessage,thelengthofthepacketmaygetextended.
ThiscouldreducetheInter-frameGap(IFG)betweenpacketsbyasmuchas8bytetimes(640nsat100Mb).
ThisfieldsetsaminimumontheIFGbetweenpacketsinnumberofbytetimes.
IftheIFGissetlargerthantheactualIFG,preamblebytesofthesubsequentpacketwillgetdropped.
ThisvalueshouldbesettothelowestpossiblevaluethattheattachedMACcansupport.
11ACC_UDP0,RWRecordTimestampifUDPChecksumError:Bydefault,TimestampswillbediscardedforpacketswithUDPChecksumerrors.
Ifthisbitisset,thentheTimestampwillbemadeavailableinthenormalmanner.
10ACC_CRC0,RWRecordTimestampifCRCError:Bydefault,TimestampswillbediscardedforpacketswithCRCerrors.
Ifthisbitisset,thentheTimestampwillbemadeavailableinthenormalmanner.
9TS_APPEND0,RWAppendTimestampforL2:ForLayer2encapsulatedPTPmessages,ifthisbitisset,alwaysappendtheTimestamptoendofthePTPmessageratherthaninsertedinunusedmessagefields.
ThisbitwillbeignoredifTS_INSERTis0.
124RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013Table10-60.
PTPReceiveConfigurationRegister3(PTP_RXCFG3),address0x1C(continued)BitBitNameDefaultDescription8TS_INSERT0,RWEnableTimestampInsertion:EnablesTimestampinsertionintoapacketcontainingaPTPEventMessage.
Ifthisbitisset,theTimestampwillnotbeavailablethroughthePTPReceiveTimestampRegister.
7:0PTP_DOMAIN00000000,RWPTPDomain:ValueofthePTPMessagedomainNumberfield.
IfPTP_RXCFG0:DOMAIN_ENissetto1,theReceiveTimestampunitwillonlycaptureaTimestampifthedomainNumberinthereceivePTPmessagematchesthevalueinthisfield.
IftheDOMAIN_ENbitissetto0,thedomainNumberfieldwillbeignored.
10.
6.
10PTPReceiveConfigurationRegister4(PTP_RXCFG4),Page5ThisregisterprovidesextendedconfigurationforIEEE1588ReceiveTimestampoperation.
Table10-61.
PTPReceiveConfigurationRegister4(PTP_RXCFG4),address0x1DBitBitNameDefaultDescription15IPV4_UDP_MOD0,RWEnableIPV4UDPModification:Whentimestampinsertionisenabled,thisbitcontrolshowUDPchecksumsarehandledforIPV4PTPeventmessages.
Ifsettoa0,thedevicewillcleartheUDPchecksum.
IfaUDPchecksumerrorisdetectedthedevicewillforceaCRCerror.
Ifsettoa1,thedevicewillnotcleartheUDPchecksum.
Insteaditwillgeneratea2-bytevaluetocorrecttheUDPchecksumandappendthisimmediatelyfollowingthePTPmessage.
IfanincomingUDPchecksumerrorisdetected,thedevicewillcauseaUDPchecksumerrorinthemodifiedfield.
ThisfunctionshouldonlybeusediftheincomingpacketscontaintwoextrabytesofUDPdatafollowingthePTPmessage.
Thisshouldnotbeenabledforsystemsusingversion1oftheIEEE1588specification.
14TS_SEC_EN0,RWEnableTimestampSeconds:Settingthisbittoa1enablesinsertingasecondsfieldwhenTimestampInsertionisenabled.
Ifsetto0,onlythenanosecondsportionoftheTimestampwillbeinsertedinthepacket.
ThisbitwillbeignoredifTS_INSERTis0.
13:1TS_SEC_LEN00,RWInsertedTimestampSecondsLength:2ThisfieldindicatesthelengthoftheSecondsfieldtobeinsertedinthePTPmessage.
ThisfieldwillbeignoredifTS_INSERTis0orifTS_SEC_ENis0.
Themappingisasfollows:00:LeastSignificantByteonlyofSecondsfield01:TwoLeastSignificantBytesofSecondsfield10:ThreeLeastSignificantBytesofSecondsfield11:AllfourBytesofSecondsfield11:6RXTS_NS_OFF000000,RWReceiveTimestampNanosecondsoffset:ThisfieldprovidesanoffsettotheNanosecondsfieldwheninsertingaTimestampintoareceivedPTPmessage.
IfTS_APPENDissetto1,theoffsetindicatesanoffsetfromtheendofthePTPmessage.
IfTS_APPENDissetto0,theoffsetindicatesthebyteoffsetfromthebeginningofthePTPmessage.
ThisfieldwillbeignoredifTS_INSERTis0.
5:0RXTS_SEC_OFF000000,RWReceiveTimestampSecondsoffset:ThisfieldprovidesanoffsettotheSecondsfieldwheninsertingaTimestampintoareceivedPTPmessage.
IfTS_APPENDissetto1,theoffsetindicatesanoffsetfromtheendoftheinsertedNanosecondsfield.
IfTS_APPENDissetto0,theoffsetindicatesthebyteoffsetfromthebeginningofthePTPmessage.
ThisfieldwillbeignoredifTS_INSERTis0.
10.
6.
11PTPTemporaryRateDurationLowRegister(PTP_TRDL),Page5Thisregistercontainsthelow16bitsofthedurationinclockcyclestousetheTemporaryRateasprogrammedinthePTP_RATEHandPTP_RATELregisters.
SincetheTemporaryRatetakesaffectuponwritingthePTP_RATELregister,thisregistershouldbeprogrammedbeforesettingtheTemporaryRate.
ThisregisterdoesnotneedtobereprogrammedforeachuseoftheTemporaryRateregisters.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock125SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-62.
PTPTemporaryRateDurationLowRegister(PTP_TRDL),address0x1EBitBitNameDefaultDescription15:0PTP_TR_DURL000000000000PTPTemporaryRateDurationLow16bits:0000,RWThisregistersetsthedurationfortheTemporaryRateinnumberofclockcycles.
TheactualTimedurationisdependentonthevalueoftheTemporaryRate.
10.
6.
12PTPTemporaryRateDurationHighRegister(PTP_TRDH),Page5Thisregistercontainsthehigh10bitsofthedurationinclockcyclestousetheTemporaryRateasprogrammedinthePTP_RATEHandPTP_RATELregisters.
SincetheTemporaryRatetakesaffectuponwritingthePTP_RATELregister,thisregistershouldbeprogrammedbeforesettingtheTemporaryRate.
ThisregisterdoesnotneedtobereprogrammedforeachuseoftheTemporaryRateregisters.
Table10-63.
PTPTemporaryRateDurationHighRegister(PTP_TRDH),address0x1FBitBitNameDefaultDescription15:1RESERVED000000,ROReserved:Writesignored,Readas009:0PTP_TR_DURH0000000000,RWPTPTemporaryRateDurationHigh10bits:ThisregistersetsthedurationfortheTemporaryRateinnumberofclockcycles.
TheactualTimedurationisdependentonthevalueoftheTemporaryRate.
126RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
7PTP1588ConfigurationRegisters-Page6Page6PTP1588ConfigurationRegistersareaccessiblebysettingbits[2:0]=110ofPAGESEL(13h).
10.
7.
1PTPClockOutputControlRegister(PTP_COC),Page6ThisregisterprovidesconfigurationforthePTPclock-synchronizedoutputdivide-by-Nclock.
Table10-64.
PTPClockOutputControlRegister(PTP_COC),address0x14BitBitNameDefaultDescription15PTP_CLKOUTEN1,RWPTPClockOutputEnable:1=EnablePTPdivide-by-Nclockoutput.
0=DisablePTPdivide-by-Nclockoutput.
14PTP_CLKOUTSEL0,RWPTPClockOutputSourceSelect:1=SelectthePhaseGenerationModule(PGM)astherootclockforgeneratingthedivide-by-Noutput.
0=SelecttheFrequency-ControlledOscillator(FCO)astherootclockforgeneratingthedivide-by-Noutput.
ForadditionalinformationrelatedtothePTPclockoutputselection,refertoapplicationnoteAN–1729(SNLA099).
13PTP_CLKOUT0,RWPTPClockOutputI/OSpeedSelect:SPEEDSEL1=Enablefasterrise/falltimeforthedivide-by-Nclockoutputpin.
0=Enablenormalrise/falltimeforthedivide-by-Nclockoutputpin.
12:8RESERVED00000,ROReserved:Writesignored,Readas07:0PTP_CLKDIV00001010,RWPTPClockDivide-byValue:Thisfieldsetsthedivide-byvaluefortheoutputclock.
Theoutputclockisdividedfromaninternal250MHzclock.
Validvaluesrangefrom2to255(0x02to0xFF),givinganominaloutputfrequencyrangeof125MHzdownto980.
4kHz.
Divide-byvaluesof0and1arenotvalidandwillstoptheoutputclock.
10.
7.
2PHYStatusFrameConfigurationRegister1(PSF_CFG1),Page6ThisregisterprovidesconfigurationforthePHYStatusFramefunction.
Specifically,the16-bitvalueinthisregisterisusedasthefirst16-bitsofthePTPHeaderdataforthePHYStatusFrame.
Table10-65.
PHYStatusFrameConfigurationRegister1(PSF_CFG1),address0x15BitBitNameDefaultDescription15:1PTPRESERVED0000,RWPTPv2reservedfield:2Thisfieldcontainsthereserved4-bitfield(atoffset1)tobesentinstatuspacketsfromthePHYtothelocalMACusingtheMIIreceivedatainterface.
11:8VERSIONPTP0000,RWPTPv2versionPTPfield:ThisfieldcontainstheversionPTPfieldtobesentinstatuspacketsfromthePHYtothelocalMACusingtheMIIreceivedatainterface.
7:4TRANSPORT-0000,RWPTPv2HeadertransportSpecificfield:SPECIFICThisfieldcontainstheMESSAGETYPEfieldtobesentinstatuspacketsfromthePHYtothelocalMACusingtheMIIreceivedatainterface.
3:0MESSAGETYPE0000,RWPTPv2messageTypefield:ThisfieldcontainstheMESSAGETYPEfieldtobesentinstatuspacketsfromthePHYtothelocalMACusingtheMIIreceivedatainterface.
10.
7.
3PHYStatusFrameConfigurationRegister2(PSF_CFG2),Page6ThisregisterprovidesconfigurationforthePHYStatusFramefunction.
Specifically,the16-bitvalueinthisregisterisusedasthefirst16-bitsoftheIPSourceaddressforanIPv4PHYStatusFrame.
Table10-66.
PHYStatusFrameConfigurationRegister2(PSF_CFG2),address0x16BitBitNameDefaultDescription15:8IP_SA_BYTE100000000,RWSecondbyteofIPsourceaddress:ThisfieldcontainsthesecondbyteoftheIPsourceaddress.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock127SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
comTable10-66.
PHYStatusFrameConfigurationRegister2(PSF_CFG2),address0x16(continued)BitBitNameDefaultDescription7:0IP_SA_BYTE000000000,RWFirstbyteofIPsourceaddress:ThisfieldcontainsthemostsignificantbyteoftheIPsourceaddress.
10.
7.
4PHYStatusFrameConfigurationRegister3(PSF_CFG3),Page6ThisregisterprovidesconfigurationforthePHYStatusFramefunction.
Specifically,the16-bitvalueinthisregisterisusedasthesecond16-bitsoftheIPSourceaddressforanIPv4PHYStatusFrame.
Table10-67.
PHYStatusFrameConfigurationRegister3(PSF_CFG3),address0x17BitBitNameDefaultDescription15:8IP_SA_BYTE300000000,RWFourthbyteofIPsourceaddress:ThisfieldcontainsthefourthbyteoftheIPsourceaddress.
7:0IP_SA_BYTE200000000,RWThirdbyteofIPsourceaddress:ThisfieldcontainsthethirdbyteoftheIPsourceaddress.
10.
7.
5PHYStatusFrameConfigurationRegister4(PSF_CFG4),Page6ThisregisterprovidesconfigurationforthePHYStatusFramefunction.
Specifically,the16-bitvalueinthisregisterisusedtoassistincomputationoftheIPchecksumforanIPv4PHYStatusFrame.
Table10-68.
PHYStatusFrameConfigurationRegister4(PTP_PKTSTS4),address0x18BitBitNameDefaultDescription15:0IP_CHKSUM000000000000IPChecksum:0000,RWThisfieldcontainsaprecomputedvalueones-complementadditionofallfixedvaluesintheIPHeader.
ThedevicewilladdtheTotalLengthandIdentificationvaluestogeneratethefinalchecksum.
10.
7.
6PTPSFDConfigurationRegister(PTP_SFDCFG),Page6ThisregisterprovidesconfigurationtoenableoutputtingtheRXandTXStart-of-Frame(SFD)signalsonGPIOpins.
NotethatGPIOassignmentsarenotexclusive.
Table10-69.
PTPSFDConfigurationRegister(PTP_SFDCFG),address0x19BitBitNameDefaultDescription15:8RESERVED00000000,ROReserved:Writesignored,Readas07:4TX_SFD_GPIO0000,RWTXSFDGPIOSelect:ThisfieldcontrolstheGPIOoutputtowhichtheTXSFDsignalisassigned.
Validvaluesare0(disabled)or1-12.
3:0RX_SFD_GPIO0000,RWRXSFDGPIOSelect:ThisfieldcontrolstheGPIOoutputtowhichtheRXSFDsignalisassigned.
Validvaluesare0(disabled)or1-12.
10.
7.
7PTPInterruptControlRegister(PTP_INTCTL),Page6ThisregisterprovidesconfigurationfortheIEEE1588interruptfunction,allowingthePTPInterrupttouseanyoftheGPIOpins.
Table10-70.
PTPInterruptControlRegister(PTP_INTCTL),address0x1ABitBitNameDefaultDescription15:4RESERVED000000000000,Reserved:Writesignored,Readas0RO3:0PTP_INT_GPIO0000,RWPTPInterruptGPIOSelect:ToenableinterruptsonaGPIOpin,thisfieldshouldbesettotheGPIOnumber.
Settingthisfieldto0willdisableinterruptsviatheGPIOpins.
128RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL201310.
7.
8PTPClockSourceRegister(PTP_CLKSRC),Page6ThisregisterprovidesconfigurationforthereferenceclocksourcedrivingtheIEEE1588logic.
Thesourceclockperiodisalsousedbythe1588clocknanosecondsaddertoaddthepropervalueeveryreferenceclockcycle.
Table10-71.
PTPClockSourceRegister(PTP_CLKSRC),address0x1BBitBitNameDefaultDescription15:1CLK_SRC00,RWPTPClockSourceSelect:4SelectsamongthreepossiblesourcesforthePTPreferenceclock:00:125MHzfrominternalPGM(default)01:Divide-by-Nfrom125MHzinternalPGM1x:Externalreferenceclock13:7RESERVED0000000,ROReserved:Writesignored,Readas06:0CLK_SRC_PER0000000,RWPTPClockSourcePeriod:ThisfieldconfiguresthePTPclocksourceperiodinnanoseconds.
Valueslessthan8areinvalidandcannotbewritten;attemptingtowriteavaluelessthan8willcauseCLK_SRC_PERtobe8.
WhentheclocksourceselectionistheDivide-by-NfromtheinternalPGM,bits6:3areusedastheNvalue;bits2:0areignoredinthismode.
10.
7.
9PTPEthernetTypeRegister(PTP_ETR),Page6ThisregisterprovidestheEthernetType(Ethertype)fieldforPTPtransportoverEthernet(Layer2).
Table10-72.
PTPEthernetTypeRegister(PTP_ETR),address0x1CBitBitNameDefaultDescription15:0PTP_ETYPE111101111000PTPEthernetType:1000,RWThisfieldcontainstheEthernetTypefieldusedtodetectPTPmessagestransportedoverEthernetlayer2.
10.
7.
10PTPOffsetRegister(PTP_OFF),Page6ThisregisterprovidesthebyteoffsettothePTPmessageinaLayer2Ethernetframe.
Table10-73.
PTPOffsetRegister(PTP_OFF),address0x1DBitBitNameDefaultDescription15:8RESERVED00000000,ROReserved:Writesignored,Readas07:0PTP_OFFSET00000000,ROPTPOffset:ThisfieldcontainstheoffsetinbytestothePTPMessagefromtheprecedingheader.
ForLayer2,thisistheoffsetfromtheEthernetTypeField.
ForUDP/IP,itistheoffsetfromtheendoftheUDPHeader.
10.
7.
11PTPGPIOMonitorRegister(PTP_GPIOMON),Page6Thisregisterprovidesread-onlyaccesstothecurrentvaluesonGPIOinputs.
Table10-74.
PTPGPIOMonitorRegister(PTP_GPIOMON),address0x1EBitBitNameDefaultDescription15:1RESERVED0000,ROReserved:Writesignored,Readas0211:0PTP_GPIO_IN000000000000,PTPGPIOInputs:ROThisfieldreflectsthecurrentvaluesseenontheGPIOinputs.
GPIOs12through1aremappedtobits11:0inorder.
Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock129SubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640SNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013www.
ti.
com10.
7.
12PTPReceiveHashRegister(PTP_RXHASH),Page6ThisregisterprovidesconfigurationforthesourceidentityhashfilterofthePTPreceivepacketparser.
Ifenabled,thereceiveparselogicwilldeliverareceivetimestamponlyifthehashfunctiononthetenoctetsourcePortIdentityfieldcorrectlymatchestheprogrammedvalue.
Thesourceidentityhashfilterdoesnotaffecttimestampinsertion.
Table10-75.
PTPReceiveHashRegister(PTP_RXHASH),address0x1FBitBitNameDefaultDescription15:1RESERVED000,ROReserved:Writesignored,Readas0312RX_HASH_EN0,RWReceiveHashEnable:EnablesfilteringofPTPmessagesbasedonthehashfunctiononthetenoctetsourcePortIdentityfield.
11:0PTP_RX_HASH000000000000,ReceiveHash:RWThisfieldcontainstheexpectedsourceidentityhashvalueforincomingPTPeventmessages.
130RegisterBlockCopyright2007–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:DP83640DP83640www.
ti.
comSNOSAY8E–SEPTEMBER2007–REVISEDAPRIL2013RevisionHistoryNOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionD(April2013)toRevisionEPageChangedlayoutofNationalDataSheettoTIformat130Copyright2007–2013,TexasInstrumentsIncorporatedRegisterBlock131SubmitDocumentationFeedbackProductFolderLinks:DP83640PACKAGEOPTIONADDENDUMwww.
ti.
com24-Nov-2013Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDP83640TVVNRNDLQFPPT48250TBDCallTICallTI-40to85DP83640TVVDP83640TVV/NOPBACTIVELQFPPT48250Green(RoHS&noSb/Br)CUSNLevel-3-260C-168HR-40to85DP83640TVVDP83640TVVX/NOPBACTIVELQFPPT481000Green(RoHS&noSb/Br)CUSNLevel-3-260C-168HR-40to85DP83640TVV(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
ti.
com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandPACKAGEOPTIONADDENDUMwww.
ti.
com24-Nov-2013Addendum-Page2continuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDP83640TVVX/NOPBLQFPPT481000330.
016.
49.
39.
32.
212.
016.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com24-Apr-2013PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DP83640TVVX/NOPBLQFPPT481000367.
0367.
038.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com24-Apr-2013PackMaterials-Page2MECHANICALDATAMTQF003A–OCTOBER1994–REVISEDDECEMBER19961POSTOFFICEBOX655303DALLAS,TEXAS75265PT(S-PQFP-G48)PLASTICQUADFLATPACK4040052/C11/960,13NOM0,170,272524SQ121336376,807,201485,50TYP0,250,450,750,05MINSQ9,208,801,351,451,60MAXGagePlaneSeatingPlane0,100°–7°0,50M0,08NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
FallswithinJEDECMS-026D.
Thismayalsobeathermallyenhancedplasticpackagewithleadsconectedtothediepads.
IMPORTANTNOTICETexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,enhancements,improvementsandotherchangestoitssemiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.
Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentandcomplete.
Allsemiconductorproducts(alsoreferredtohereinas"components")aresoldsubjecttoTI'stermsandconditionsofsalesuppliedatthetimeoforderacknowledgment.
TIwarrantsperformanceofitscomponentstothespecificationsapplicableatthetimeofsale,inaccordancewiththewarrantyinTI'stermsandconditionsofsaleofsemiconductorproducts.
TestingandotherqualitycontroltechniquesareusedtotheextentTIdeemsnecessarytosupportthiswarranty.
Exceptwheremandatedbyapplicablelaw,testingofallparametersofeachcomponentisnotnecessarilyperformed.
TIassumesnoliabilityforapplicationsassistanceorthedesignofBuyers'products.
BuyersareresponsiblefortheirproductsandapplicationsusingTIcomponents.
TominimizetherisksassociatedwithBuyers'productsandapplications,Buyersshouldprovideadequatedesignandoperatingsafeguards.
TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanypatentright,copyright,maskworkright,orotherintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIcomponentsorservicesareused.
InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservicesorawarrantyorendorsementthereof.
Useofsuchinformationmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI.
ReproductionofsignificantportionsofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandisaccompaniedbyallassociatedwarranties,conditions,limitations,andnotices.
TIisnotresponsibleorliableforsuchaltereddocumentation.
Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.
ResaleofTIcomponentsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatcomponentorservicevoidsallexpressandanyimpliedwarrantiesfortheassociatedTIcomponentorserviceandisanunfairanddeceptivebusinesspractice.
TIisnotresponsibleorliableforanysuchstatements.
Buyeracknowledgesandagreesthatitissolelyresponsibleforcompliancewithalllegal,regulatoryandsafety-relatedrequirementsconcerningitsproducts,andanyuseofTIcomponentsinitsapplications,notwithstandinganyapplications-relatedinformationorsupportthatmaybeprovidedbyTI.
Buyerrepresentsandagreesthatithasallthenecessaryexpertisetocreateandimplementsafeguardswhichanticipatedangerousconsequencesoffailures,monitorfailuresandtheirconsequences,lessenthelikelihoodoffailuresthatmightcauseharmandtakeappropriateremedialactions.
BuyerwillfullyindemnifyTIanditsrepresentativesagainstanydamagesarisingoutoftheuseofanyTIcomponentsinsafety-criticalapplications.
Insomecases,TIcomponentsmaybepromotedspecificallytofacilitatesafety-relatedapplications.
Withsuchcomponents,TI'sgoalistohelpenablecustomerstodesignandcreatetheirownend-productsolutionsthatmeetapplicablefunctionalsafetystandardsandrequirements.
Nonetheless,suchcomponentsaresubjecttotheseterms.
NoTIcomponentsareauthorizedforuseinFDAClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersofthepartieshaveexecutedaspecialagreementspecificallygoverningsuchuse.
OnlythoseTIcomponentswhichTIhasspecificallydesignatedasmilitarygradeor"enhancedplastic"aredesignedandintendedforuseinmilitary/aerospaceapplicationsorenvironments.
BuyeracknowledgesandagreesthatanymilitaryoraerospaceuseofTIcomponentswhichhavenotbeensodesignatedissolelyattheBuyer'srisk,andthatBuyerissolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsinconnectionwithsuchuse.
TIhasspecificallydesignatedcertaincomponentsasmeetingISO/TS16949requirements,mainlyforautomotiveuse.
Inanycaseofuseofnon-designatedproducts,TIwillnotberesponsibleforanyfailuretomeetISO/TS16949.
ProductsApplicationsAudiowww.
ti.
com/audioAutomotiveandTransportationwww.
ti.
com/automotiveAmplifiersamplifier.
ti.
comCommunicationsandTelecomwww.
ti.
com/communicationsDataConvertersdataconverter.
ti.
comComputersandPeripheralswww.
ti.
com/computersDLPProductswww.
dlp.
comConsumerElectronicswww.
ti.
com/consumer-appsDSPdsp.
ti.
comEnergyandLightingwww.
ti.
com/energyClocksandTimerswww.
ti.
com/clocksIndustrialwww.
ti.
com/industrialInterfaceinterface.
ti.
comMedicalwww.
ti.
com/medicalLogiclogic.
ti.
comSecuritywww.
ti.
com/securityPowerMgmtpower.
ti.
comSpace,AvionicsandDefensewww.
ti.
com/space-avionics-defenseMicrocontrollersmicrocontroller.
ti.
comVideoandImagingwww.
ti.
com/videoRFIDwww.
ti-rfid.
comOMAPApplicationsProcessorswww.
ti.
com/omapTIE2ECommunitye2e.
ti.
comWirelessConnectivitywww.
ti.
com/wirelessconnectivityMailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265Copyright2013,TexasInstrumentsIncorporatedMouserElectronicsAuthorizedDistributorClicktoViewPricing,Inventory,Delivery&LifecycleInformation:TexasInstruments:DP83640TVVDP83640TVV/NOPBDP83640TVVX/NOPB