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XAPP529(v1.
3)May12,2004www.
xilinx.
com11-800-255-77782003Xilinx,Inc.
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SummaryMicroBlazeTMhastheabilitytouseitsdedicatedFSLbusinterfacetointegrateacustomizedIPcoreintoaMicroBlazeTMsoftprocessor-basedsystem.
ThisdocumentdescribespossiblemethodstoincludecustomizedIPcoresintoaSoftCoreProcessor(SCP)-baseddesign.
TheFSLinterfaceisdescribedingreatdetail,andareferenceapplicationinvolvinga1-dimensionalInverseDirectCosineTransform(IDCT)isusedtoshowhowtheimplementationofacustomizedcorecanbedoneinsoftwareandhardware.
ThefirstpartofthisdocumentdealswiththedifferentmethodsofintegratinguserIPcoresintoasoftprocessor-basedsystem.
ThesecondpartcontainsashortoverviewonMicroBlazeandtheFSLinterface.
Afterthat,thereferencedesign,whichcanbedownloadedfromtheXilinxwebsite,isexplained.
ThelastpointofthisdocumentcontainstheconclusionregardingtheuseoftheFSLinterfaceIntroductionOneadvantageofaSoftCoreProcessor(SCP)isitsflexibility:itusesonlytheprocessorfeaturesrequiredforaspecificapplication.
AnotheradvantageisitsabilitytointegratecustomizeduserIntellectualProperty(IP)cores,whichcanresultinadramaticaccelerationinsoftwareexecutiontimeduetoalgorithmsbeingexecutedinparallelinhardwareandnotsequentiallyinsoftware.
MicroBlazeisapowerfulandinexpensiveSCPsolutionfortheVirtexTMandSpartanTM-II/3-basedFPGAseries.
MicroBlazecombinesalltheflexibilityadvantagesofSCP.
Generally,therearetwowaystointegrateacustomizedIPcoreintoaMicroBlaze-basedembeddedsoftprocessorsystem.
OnewayistoconnecttheIPontheOn-chipPeripheralBus(OPB).
TheOPBispartoftheIBMCoreConnectTMon-chipbusstandard.
ThesecondwayistoconnecttheuserIPtotheMicroBlazededicatedFastSimplexLink(FSL)bussystem.
Iftheapplicationistime-critical,theuserIPshouldbeconnectedtotheFSLbussystem;otherwise,itcanbeconnectedasaslaveormasterontheOPB.
IfthecustomizedcoreisconnectedtothededicatedFSLinterface,itisthenpossibletousepredefinedCfunctionstousetheusercoreintheapplicationsoftware.
ThisdocumentdealsprimarilywiththeconnectionofauserIPontheMicroBlazeFSLinterface.
FormoreinformationregardingtheconnectionofauserIPontheOPB,pleaserefertotheusercoretemplatedocument:www.
xilinx.
com/ise/embedded/edk_docs.
htmIntegrationofaUserIPintoaSoftProcessor-BasedSystemTherearedifferentwaystoconnectauserIPintoasoftmicroprocessor-basedsystem.
Ingeneral,everyapplicationcanberealizedandimplementedeitherassoftwarealgorithmorasstructuralhardware.
Itisimportanttousethehardwareimplementationadvantage(parallelexecution),whichallowstherealizationofstricttiming-drivenapplicationsandtheabilitytocontroltheuserIPinsoftware(e.
g.
,CorC++).
Figure1demonstrateshowtheparallelexecutionadvantagecanbeused.
Thesoftwareroutineneeds12clockcyclestocalculatetheresultG;however,inhardwareittakesonly2clockcyclestocomputethesameresult.
ApplicationNote:MicroBlazeXAPP529(v1.
3)May12,2004ConnectingCustomizedIPtotheMicroBlazeSoftProcessorUsingtheFastSimplexLink(FSL)ChannelAuthor:Hans-PeterRosingerR2www.
xilinx.
comXAPP529(v1.
3)May12,20041-800-255-7778IntegrationofaUserIPintoaSoftProcessor-BasedSystemRFigure1:SoftwareversushardwareItisimportanttobeabletousethecustomizedIPcoreintheapplicationprogram.
WithoutaneasywaytocontroltheuserIP,itdoesn'tmakesensetoincludethecore.
OnepossiblewayistointegratetheuserIPasanon-chipbussystem(likethecoreconnectbus).
Duringthedesignstageofthecore,thedesignerhastotakethebusstandardintoaccount;thatis,thedesignerhastomakesurethatheorsheconformstothebusspecificationifthecoregetsconnectedtothebus.
Thiscanbeverytime-consuming,aliabilitywhichnoengineercanaffordtoday.
Insomecases,templates,forexample,theXilinxIPIFusercoretemplate,exist.
ThesetemplatesmakeiteasyandfasttoconnectanIPcoreontheCoreconnectbus.
ThenextandmorecriticaldrawbacktoconnectingtheuserIPtoanon-chipbusisthatmostofthetimethebusprotocoloverheadtakestoomuchtimeandthespeedadvantagegetslost.
Therefore,otherdifferentwaystoincludeacustomizeduserIPcorearepossible.
OneistointegratetheuserIPasco-processor(iftheprocessorhassuchaco-processorinterface).
IfthesoftprocessorhasaspecialdedicatedinterfaceliketheARCTangent,Tensilica,NIOS,orMicroBlazesoftprocessor,itisalsopossibletointegrateauserIP.
AsoftprocessorisavailableasHDLsourcecodeorasastructuralnetlist.
Therefore,itcanbeintegratedintoanASICoraFPGA.
SoftProcessorsTargetingASICVersusFPGAItisimportanttounderstandtheadvantageoftheflexibilitymadepossiblebyusinganFPGAdesigninsteadofanASICdesign.
AftertheASICismanufactured,thereisnowaytoreconfigurethelogicinsidetheASICdevice.
ItwouldevenbetoocostlytochangethemaskandmanufactureanewASIC.
ForaSCP,whichtargetstheASICmarket,itisessentialtobeflexibleinsoftware.
Aftertheprocessor-basedsystemwiththecustomizedinstructionismappedinanASIC,itispossibletochangetheapplicationonlyinsoftware(changingtheC-Code).
Figure2showsanexampleonthis.
Thefirstbarshowstheexecutiontimeofawholesoftwareprogram.
UsingaSCPwithcustomizedinstructionsreducestheoverallexecutiontimeofthesoftwareprogramdramatically.
If,forinstance,theASICalreadyexistsbutanaspectoftheapplicationchangesforonecustomizedinstruction,thensomemodificationsmustbedone.
loadAloadBsubstoreDloadCloadFaddstoreEloadEloadDdivstoreGD=A-BE=C+FG=D/EAlgorithmHW-Solution2clockcyclesSW-Solution12clockcyclesABCFDEGXAPP529_01_101503IntegrationofaUserIPintoaSoftProcessor-BasedSystemXAPP529(v1.
3)May12,2004www.
xilinx.
com31-800-255-7778RFigure2:IncreasingsoftwareexecutionspeedInanASICdesign,theonlywayistonotusethecustomizedinstructionbuttoaddressthenewapplicationrequirementinsoftware.
Now,theoverallsoftwareexecutiontimewillincreaseagain;however,foranASICsolution,itistheonlyway.
SoftprocessorssuchastheARCTangent,theTensilica,andtheNIOSsoftprocessorintegratethecustomizedinstructioncompletelyintheirexecutionunitandareusefulifthetargethardwareisnotchangeable(ASIC).
FPGAdevicesinsteadallowforthereconfigurationoftheinternallogicveryeasily,quickly,andcheaply.
Eveninthelaststagesofthedesign,itisstillpossibletoeasilychangethehardwareinsidethechip.
Ifwelookattheaboveexampleagain,itispossibletochangethenewapplicationrequirementatanystageofthedesigninhardware,anditisnotnecessarytodothechangeinsoftware.
Itisnotthatimportanttohavetheflexibilityinsoftware,becausetheflexibilityinhardwarehasnotbeenlost.
ForFPGAdesigns,itisnotnecessaryorusefultoincludethecustomizeduserIPintheinstructionsetandinsidetheprocessorcore,theRISCarchitecture.
ThenextsectiondetailsproblemsencounteredwhenthecustomizedIPcoreisincludedintheRISCarchitecture.
MicroBlazeFSLInterfaceVersusCustomizedInstructionTheintegrationofacustomizedIPcorewithintheexecutionunitisveryrestrictive.
OneofthebiggestrestrictionsisduetothenatureofRISCprocessorarchitectureitself.
Figure3showsausualRISCprocessorarchitecture.
ModernRISCarchitectureshaveatwo-inputandaone-outputexecutionunit(ALU).
Applicationsthatrequiremorethantwoinputvaluesandmorethanoneoutputvaluearenotoptimalforthesearchitectures,andseveralinstructionshavetobegenerated.
Custompacketprocessingapplications,forinstance,requirealotofdifferentdynamicallychangeableinputs(maskbits)andoutputs.
Thoseapplicationsarenotsuitableforcustomizedinstructionsbecauseitispossibletouseonlytwoinputs(usually64bits)andoneoutput(usually32bits).
SW_F1SW_F2SW_F3SW_F4IIIIIIISW_F4FlexibilityOverallsoftwareexecutiontimeXAPP529_02_1015034www.
xilinx.
comXAPP529(v1.
3)May12,20041-800-255-7778IntegrationofaUserIPintoaSoftProcessor-BasedSystemRFigure3:IncludingacustomizedIPwithintheRISCarchitecture(CustomizedInstruction)Anotherbottleneckisthecustomizedinstructionitself.
IfthecriticalpathofthewholesystemisthroughtheuserIP,thewholesoftprocessorwilldecreaseinperformance(processorfrequency),becausetheuserIPisincludedwithinthesoftprocessorarchitectureitself.
IftheRISCarchitecturedoesn'tallowthedesignertostallthepipeline,theprocessorcan'trunatahigherfrequencythanthecriticalpathwouldallow.
ThebiggerthecustomizedIPis,themorethedesignermustbecarefulnottodecreasethewholeprocessorperformance.
Itisevennotacceptabletocascadelogicwithinonecustomizedinstruction,andseveralcustomizedinstructionshavetobebuilt.
Thesoftwareintegrationofcustomizedinstructioncan'tbehandleddirectlyfromthecompiler,thustheuserhastouseinlineassemblytoworkwiththem.
Thecustomizedinstructionshavetobeimplementedinsoftwareasinlineassemblercodeandinlinepragmas.
ThiscouldproduceaCapplicationcode,whichisneitherverycleannorportable.
Xilinxprovides,withtheMicroBlazesoftprocessorandthededicatedFSLinterface,averypowerful,easyandflexiblewaytoimplementacustomizeduserIP.
RegardingtheI/Osofthecore,itispossibletousemorethan2dynamicinputsandmorethan1outputbecauseupto16FSLinterfacebussesareprovided.
Theusercanuse8inputstothecustomizedIPcoreand8outputs.
Figure4showsthebasicideaofconnectingthecustomizeduserIPviatheFSLinterfaceontotheMicroBlaze.
ItispossibletoprovidethecustomizeduserIPcorewithmanymoreinputs/outputsfromanotherprocessororexternallogic,andthebigadvantageisitisnotnecessarytochangeorextendtheMicroBlazecoreortheRISCarchitectureitself.
Instruction-FetchInstruction-FetchInstruction-FetchInterface32x32RegisterALUInstruction-DecodeSUBADDMOVUSWDecodecustomizeduserIPDecodeExecuteWriteback1234RISCProcessorCriticalPath!
CriticalPath!
XAPP529_03_101503IntegrationofaUserIPintoaSoftProcessor-BasedSystemXAPP529(v1.
3)May12,2004www.
xilinx.
com51-800-255-7778RFigure4:IncludingacustomizedIPviatheFSLinterfaceontoMicroBlazeRegardingthemaximumfrequencyofthecustomizeduserIP,itwon'tdecreasetheclockfrequencyofMicroBlaze,becauseitisindependentandtheusercoredoesn'taffecttheinternalMicroBlazeRISCarchitecture.
ItisnoproblemthatthecustomizeduserIPisasubsetofseveralIPcoresthatarecascadedtogether.
Thefactthatthecustomizedusercoreisimplementedoutsidetheprocessorarchitectureitselfbringsanotheradvantage.
If,forinstance,thecoretakes100clockcyclestocalculateacomplexresult,MicroBlazecanexecuteinthemeantimeadifferentapplicationcodeanddoesn'thavetowaitforthe100clockcycles.
Theintegrationofthehardwareinsoftwaredoesn'trequireinlineassembledcodebecausetheFSLinterfacehaspredefinedC-macrosthatcanbeusedforsendingparameterstothehardwareunitandtoreceivetheresult.
AnotherpowerfulusageoftheFSLisinter-processorcommunication.
TwoMicroBlazeprocessorshaveaveryfastandcleanwaytocommunicatewitheachother.
Inthefollowingsections,firstMicroBlazeandthentheFSLinterfacearediscussedingreaterdetail.
Oneexampleshowshowa1-dimensionIDCTcoregetsconnectedinhardwarewithintheEDK–XPSsystembuilderandhowtointegratethecoreinsoftware.
GeneralDescriptionoftheMicroBlazeSoftProcessorMicroBlazeisastandard32-bitRISCHarvard-styleSoftProcessor,whichisespeciallydevelopedfortheVirtexandSpartan-II/3-basedFPGAarchitecture.
The32by32-bitregistersarelookuptable(LUT)RAMbased.
Itguaranteesaveryshortregisteraccesstime.
Formemory,eithertheon-chipblockRAMoroff-chipmemorycanbeused.
Theaccesstimetotheon-chipblockRAMisminimalbecausetherearededicatedroutingresourcestoaccessthem.
DuetothefactthatMicroBlazeisusingtheavailableFPGAresourcesveryefficiently,itispossibletoclockMicroBlazeupto150MHz.
Thus,upto125DhrystoneMIPScanbereached.
Itisconsequentlytheindustry'sfastestSCPforFPGAs.
TheMicroBlazeSCPcanbecustomizedforanyapplication.
Itsbarrelshifter,divideunit,datacache,instructioncache,andtheFSLbussystemareoptional.
Thesizesofthecachesareconfigurablefrom2to64Kbytes.
StandardperipheralsareprovidedaswellandareCoreConnectcompatible.
Consequently,theycanbeintegratedinanembeddeddesignveryeasy.
Theseperipheralsareeitherfree,suchasthememorycontroller,UART,interruptcontroller,andtimer,orcommercialcoressuchastheEthernetcontroller,gigabitEthernetcontroller,PCI,HDLC,etc.
AllcommercialIPCorescanbeevaluated.
Forallfreecores,theVHDLandtheC-Code(TCP/IPstack)arereadable.
MicroBlazeisusedindifferentareassuchasInstruction-FetchInstruction-FetchInterface32x32RegisterALUInstruction-DecodegetngetputnputDecodeExecuteWriteback1234MicroBlazecustomizeduser-IPFSL-InterfaceCriticalPath!
XAPP529_04_1015036www.
xilinx.
comXAPP529(v1.
3)May12,20041-800-255-7778IntegrationofaUserIPintoaSoftProcessor-BasedSystemRnetworkapplications,telecommunicationapplications,control,andconsumermarkets.
Figure5showsatypicalMicroBlazeSCPwithitsperipherals.
TheEmbeddedDevelopmentKit(EDK)includesthesoftprocessorcoreandastandardsetofperipheralsandisavailablefromXilinxanditsdistributionpartners.
ThekitincludesacompletesetofGNU-basedsoftwaretoolsincludingthecompiler,assembler,debugger,andlinker.
VariationsofthekitincludedevelopmentboardsthatsupporttheVirtex-E,Virtex-II,Virtex-IIPro,Spartan-II,Spartan-IIE,andSpartan-3seriesofFPGAs.
FormoreinformationregardingMicroBlaze,pleaserefertothefollowinglink:http://www.
xilinx.
com/ipcenter/processor_central/microblaze/index.
htmDetailedDescriptionoftheFSLInterfaceThissectiondescribesthespecialFSLinterfaceindetail.
MicroBlazecontainseightinputandeightoutputFSLinterfaces.
TheFSLchannelsarededicatedunidirectionalpoint-to-pointdatastreaminginterfaces.
TheFSLinterfacesonMicroBlazeare32bitswide.
Further,thesameFSLchannelscanbeusedtotransmitorreceiveeithercontrolordatawords.
Aseparatebitindicateswhetherthetransmitted(received)wordiscontrolordatainformation.
TheperformanceoftheFSLinterfacecanreachupto300MB/sec.
Thisthroughputdependsonthetargetdeviceitself.
TheFSLbussystemisidealforMicroBlaze-to-MicroBlazeorstreamingI/Ocommunications.
ThemainfeaturesoftheFSLinterfaceare:Unidirectionalpoint-to-pointcommunicationFigure5:MicroBlaze-basedembeddedprocessorsystemAddresssideLMBDebugLogicLocalLinkI/FLogical/ShiftDataSideLMBOff-ChipMemory0-4GBTimer/CountersGeneralPurposeI/OWatchdogTimerInterruptControllerPERIPHERALSOPBCoreConnectTMOPBCoreConnectTMD-OPBD-LMBI-LMBI-OPBPROCESSORLocalLinkMDMUARTOff-ChipMemory0-4GBInstructionCacheBarrelShifterDividerALUMultiplyMachineStatusRegRegisterFile32x32bitr31r1r0ProgramCounterControlUnitInstructionBufferInstructionBusControllerDataBusControllerXAPP529_05_101503DataCacheIntegrationofaUserIPintoaSoftProcessor-BasedSystemXAPP529(v1.
3)May12,2004www.
xilinx.
com71-800-255-7778RUnsharednon-arbitratedcommunicationmechanismControlandDatacommunicationsupportFIFO-basedcommunicationConfigurabledatasize600MHzstandaloneoperationTheFSLbusisdrivenbyoneMasteranddrivesoneSlave.
Figure6showstheprincipleoftheFSLbussystemandtheavailablesignals.
Figure6:FSLinterfaceFSLperipheralsmaybecreatedasaMasteroraSlavetotheFSLbus.
AperipheralconnectedtothemasterportsoftheFSLbuspushesdataandcontrolsignalsontotheFSL.
AllperipheralsthatactasamastertotheFSLbusshouldcreateabusinterfaceofthetypeMASTERforthebusstandardFSLintheMicroprocessorPeripheralDescription(MPD)file.
AperipheralconnectedtotheslaveportsoftheFSLbusreadsandpopsdataandcontrolsignalsfromtheFSL.
AllperipheralsthatareaslavetotheFSLbusshouldcreateabusinterfaceofthetypeSLAVEforthebusstandardFSLintheMPDfile.
TheputandgetinstructionsofMicroBlazecanbeusedtotransferthecontentsofaMicroBlazeregisterontotheFSLbusandvice-versa.
TheFSLbusconfigurationofMicroBlazecanbeusedinconjunctionwithanyoftheotherbusconfigurations.
BelowisabriefoverviewoftheFSL-relatedpredefinedC-functionsavailableinEDK.
//BlockingDataReadandWritetoLocalLinkno.
idmicroblaze_bread_datafsl(val,id)microblaze_bwrite_datafsl(val,id)//Non-blockingDataReadandWritetoLocalLinkno.
idmicroblaze_nbread_datafsl(val,id)microblaze_nbwrite_datafsl(val,id)//BlockingControlReadandWritetoLocalLinkno.
idmicroblaze_bread_cntlfsl(val,id)microblaze_bwrite_cntlfsl(val,id)//Non-blockingControlReadandWritetoLocalLinkno.
idmicroblaze_nbread_cntlfsl(val,id)microblaze_nbwrite_cntlfsl(val,id)FormoredetailedinformationregardingtheFSLbusinformation,pleaserefertotheFSLbusdatasheet(containingtimingdiagrams)andtotheMicroBlazeuserguide.
FSL_M_ClkFSL_M_DataFSL_M_ControlFSL_M_WriteFSL_M_FullFSL_S_ClkFSL_S_DataFSL_S_ControlFSL_S_ReadFSL_S_ExistsFIFOXAPP529_06_1015038www.
xilinx.
comXAPP529(v1.
3)May12,20041-800-255-7778DescriptionoftheApplicationRDescriptionoftheApplicationAsanapplicationtodemonstratetheuseoftheFSLinterface,a1-dimensionIDCTisused.
ThisDSPapplicationhighlightsverywelltheperformancewinthatcouldbereached.
A1-dimensionIDCTrealizedinsoftwarewouldrequireahighexecutiontimebecausetheC-programwouldconsistmainlyofloopswhichgetexecutedsequentiallybytheprocessor.
Iftheapplicationisimplementedasitsownhardwaremodule,theexecutiontimerequiresmuchfewerclockcycles.
Theused1-IDCTcoreontheFSLinterfaceisanexampleandneedsapproximately150LUTsandthelatencyof64clockcycles.
PleasenotethisIDCTcoreisusedtoshowhowtoimplementausercoreontheFSLinterface.
Thesoftwareapplicationwrites8valuesfrommemorytotheFSL.
TheIDCTcoregetsthedataandcalculatestheresult.
Whentheresultisavailable,MicroBlazereadsthedata(8words)backfromtheFSL.
TheIDCTcoreisconnectedtotheFSLinterfaceasshowninFigure7.
Figure7:Includingthe1-dimensionalIDCTIPviatheFSLinterfaceontoMicroBlazeFortheFSL0connection,theMicroBlazeistheMasterontheFSLbusandtheIDCTcoreistheSlave.
Thus,MicroBlazecontrolsthedatasentontheFSL0bustotheIDCTcore.
FortheFSL1bus,itisviceversa,andtheIDCTcoreistheMasterandtheMicroBlazetheSlave.
TheIDCTcontrolsthedataontheFSL1bus.
Bycascadingthe1-dimensionalIDCTcore,itispossibletointegratea2-dimensionalIDCTcore(Figure8).
The1-DIDCTblockwillreadfromtheFSL0inputandputthedataoutontheFSL1bus.
Thecorner-turnmodulealsoreadsfromFSL1andputsoutonFSL2.
Thelast1-DIDCTisalsoreadingfromtheFSL2andputsoutthedataonFSL3,whichtransferstheresultbacktoMicroBlaze.
Bydoingthis,thecurrent1-IDCTblockcanbeusedwithoutanymodificationasapartina2-dimensionalIDCTcore.
Italsogivestheusermuchmoreflexibilitysinceitispossibletodecideforanotherconnectionschemeatanytime.
Figure8:BlockDiagramforusinga1-DIDCTtoimplementa2-DIDCTFSL0MicroBlazeFSL1IDCTR0R1R2R30R31FSL-interfaceXAPP529_07_101503XAPP529_08_101503FSL0InputFSL3Output1-DIDCT(rowengine)CornerTurn2-DIDCT1-DIDCT(columnengine)FSL1FSL2DescriptionoftheApplicationXAPP529(v1.
3)May12,2004www.
xilinx.
com91-800-255-7778RIntegrationinHardwareThissectiondescribeshowtointegratetheuserIPinaMicroBlaze-basedembeddedprocessordesign.
Forthisintegration,theEDK6.
1softwaretoolisused.
Figure9showstheembeddedMicroBlazedesignwiththecustomizedIDCTcoreandsomeOPBstandardperipherals.
ThewholeembeddedsystemconsistsoftheMicroBlazeitself,twoFSLbussystems,theusercore,anOPBon-chipbus,twoOPBperipherals(UARTliteandtheMicroBlazeDebugmodule),andtheon-chipblockRAM.
Theapplicationprogramisstoredintheon-chipblockRAM.
Figure10showsindetailhowtheIDCTcoreisconnectedontotheMicroBlazeFSLinterface.
TheIDCTisavailableinVHDLcode.
Itisalsopossibletouseanetlistinstead.
Figure9:Embeddedprocessorsystem-hardwareIDCTSlaveMasterMicroBlazeMasterSlaveFSL0BusFSL1BusOPBBusLMBBusBRAMDebugmoduleUARTmoduleXAPP529_09_10150310www.
xilinx.
comXAPP529(v1.
3)May12,20041-800-255-7778DescriptionoftheApplicationRFigure10:Figure10:Detailedconnectionofthe1-dimensionalIDCTIPtoMicroBlazeThecontrolsignalsareprovidedfromtheFSLinterface.
Externalsignalsliketheglobalsystemclockorthesystemresetcanbeintegratedeasily.
InadditiontotheVHDLsourcecode,aMicroprocessorPeripheralDefinition(MPD)fileandaPeripheralAnalyzeOrder(PAO)filearenecessary.
TheMPDfiledefinestheinterfaceoftheperipheral.
ThePAOfilecontainsalistofHDLfilesthatareneededforsynthesis,anddefinestheanalyzeorderforcompilation.
Itisnecessarytosaveallthefilesinadedicateddirectory.
ThefilestructureintheXPSprojectshouldlooklikethefollowing:wherethexil_idct_v1_00_a/datafoldercontainstheMPDandthePAOfile.
ThevhdlfoldercontainstheVHDLsourcecodeoftheuserIP.
Ifallthefilesareimplementedcorrectly,thecustomizedusercorecanbeintegratedintheXilinxPlatformStudio(XPS)andthebitstreamofthehardwaresystemcanbegenerated.
XAPP529_10_101503MicroBlazeR0R1R2FSL-interfaceSys_clkSys_resetSys_clkSys_resetIDCT_Core.
vhdIDCT.
vhdData_Out[31:0]Read_Data_InIn_FIFO_ReadOut_Data_FIFO[0:31]FSL0_M_Data[0:31]FSL0_S_ReadFSL0_M_WriteFSL1_S_ExistsFSL1_M_FullFSL1_S_Data[0:31]Out_FIFO_WriteIn_Data_ExistsOut_FIFO_FullIn_Data_FIFO[16:31]Data_Out_ValidData_In_ValidData_Out_FullData_In[15:]R30R31ReferenceDesignXAPP529(v1.
3)May12,2004www.
xilinx.
com111-800-255-7778RIntegrationinSoftwareThenextstepistointegratetheusercoreintothesoftware,theCapplicationprogram.
Theapplicationprogramisverysimpleandwritessomedatatothecoreandreadsitback.
Thedatablockwhichwillbewrittentothecoreconsistsof8inputvalues.
BeforethenextdatablockiswrittentotheIDCTcore,MicroBlazewaitsfortheresultingdatablock.
Obviously,theresultingdatablockcontainsthe8outputvaluesfromtheIDCTcore.
Forwritingintotheusercore,thepredefinedfunctionsareused.
Fortheexample,thenon-blockingwriteandreadcommandsareused.
Thepredefinedfunctionsaredefinedinthemb_interface.
hfile.
VerificationoftheHardwareTheverificationofthehardwarecanbedoneinverydifferentways.
TheaimistoverifytheFSLbussystemandtobesurethedataistransferredtotheIPcoreandreadbackfromtheIPcorecorrectly.
ItwillbeassumedthatthecustomizedIPcore,inthiscasetheIDCTcore,alreadyhasthecorrectfunctionality.
Forthereferencedesign,theverificationwasdonewithModelSim5.
7e,anddoscriptfilesareprovidedwiththereferencedesign.
Itcanbeseenfromtheoutputwavewindowthatboththewritetothecoreandthereadfromthecorearesuccessful.
VerificationoftheSoftwareToverifythesoftware,theGNUdebuggerisused.
ThedebuggercanbestartedfromXPSandisincludedinEDK.
Theopb_mdmdebugmoduleisusedforthecommunicationbetweenMicroBlazeandtheXilinxMicroprocessorDebugger(XMD)interface.
OntopofXMD,theGNUdebuggerGUIcanbeused.
ReferenceDesignThereferencedesigntargetstheMemecInsight2vp7demoboard(XC2VP7-4,FG456package).
IthasbeenimplementedwiththeXilinxEDK/ISE6.
2isoftware.
Theutilizationvaluesarecompletelydeviceandimplementationtooldependent.
Thetotaldesignrequires4IOBs,4MULT18x18elements,4RAMB16sandabout1300slices,andtheembeddedsoftprocessordesignrunsatafrequencyof100MHz.
TheMicroBlaze–FSL1dimensionIDCTreferencedesigncanbedownloadedfrom:http://www.
xilinx.
com/bvdocs/appnotes/xapp529_6_1.
ziphttp://www.
xilinx.
com/bvdocs/appnotes/xapp529_6_2.
zipConclusionTheMicroBlazeSCPwithitspowerfulFSLinterfacecanimprovetheperformanceofawholeapplicationdramaticallybyoutsourcingtime-criticaltasksintohardware.
Besidesthetremendousperformancewin,thesolutionischangeableuntilthelaststageoftheprojectbytakingadvantageoftheflexibilityofSCPandtheFPGAarchitecture.
Byusingcustomizedinstructions,theuserisboundedtoonlytwoinputsandoneoutputfromthecustomizedlogic.
WiththeFSLinterfaceitispossibletohaveupto8inputsand8outputs,whichallowsmuchmoreflexibility,andcascadedlogicwithinthecustomizedcoredoesn'taffectorlocktheMicroBlazeRISCunit.
TheRISCarchitecturedoesn'tgetmanipulatedandstaysself-containedbecauseitisnotnecessarytoextendtheprocessorRISCcore.
PredefinedCfunctionsareprovidedinEDKforintegratingthecustomizeduserIPinaveryeasyandcleanwayintheC/C++applicationprogram.
IfthetargetFPGAarchitectureisaSpartan-II,Spartan-IIE,orSpartan-3,itisevenbetter,asthesefamiliesarethemostcost-effectivesolutionthatisavailableforhigh-performanceembeddedprocessordesigns.
RevisionHistoryThefollowingtableshowstherevisionhistoryofthisdocument.
12www.
xilinx.
comXAPP529(v1.
3)May12,20041-800-255-7778RevisionHistoryRDateVersionRevision11/30/031.
0InitialXilinxrelease.
12/19/031.
1Correctedbrokenlink.
3/16/041.
2EditSCPtoSoftCoreProcessor(1stuse)andfixrefdesignlink.
5/12/041.
3Editedlinkstoreferencedesigns.