independentwww.55kkk.com

UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011DigitalPWMSystemControllerwith4-bit,6-bit,or8-bitVIDSupportCheckforSamples:UCD92221FEATURESAPPLICATIONSNetworkingEquipment2FullyConfigurableTwo-OutputNon-IsolatedDC/DCPWMControllerwithsupportforTelecommunicationsEquipmentTMS320C6670andTMS320C6678DSPVIDFPGA,DSP,andMemoryPowerinterfaceDESCRIPTIONSupportsSwitchingFrequenciesUpto2MHzWith250psDuty-CycleResolutionTheUCD9222isatwo-railsynchronousbuckdigitalUpTo1mVClosedLoopResolutionPWMcontrollerdesignedfornon-isolatedDC/DCpowerapplications.
ThisdeviceintegratesdedicatedHardware-Accelerated,3-Pole/3-ZerocircuitryforDC/DCloopmanagementwithsupportforCompensatorwithNon-LinearGainforuptotwoVIDinterfaces.
Additionally,theUCD9222ImprovedTransientPerformancehasflashmemoryandaserialinterfacetosupportSupportsMultipleSoft-StartandSoft-Stopconfigurability,monitoringandmanagement.
ConfigurationsIncludingPrebiasStart-upSeveralVoltageIdentification(VID)modesareSupportsVoltageMarginingandSequencingsupported,includinga4-bitparallelinterface,a6-bitSyncIn/OutPinsAlignDPWMClocksBetweeninterfaceandan8-bitserialinterface.
MultipleUCD92xxDevicesTheUCD9222wasdesignedtoprovideawide12-BitDigitalMonitoringofPowerSupplyvarietyofdesirablefeaturesfornon-isolatedDC/DCParametersIncluding:converterapplicationswhileminimizingthetotalsystemcomponentcountbyreducingexternal–InputCurrentandVoltagecircuits.
Thesolutionintegratesmulti-loop–OutputCurrentandVoltagemanagementwithsequencing,marginingand–TemperatureatEachPowerStagetrackingtooptimizefortotalsystemefficiency.
Additionally,loopcompensationandcalibrationare–AuxiliaryADCInputssupportedwithouttheneedtoaddexternalMultipleLevelsofOver-currentFaultcomponents.
Protection:Tofacilitateconfiguringthedevice,theTexas–ExternalCurrentFaultInputsInstrumentsFusionDigitalPowerDesigneris–AnalogComparatorsMonitorCurrentprovided.
ThisPCbasedGraphicalUserInterfaceSenseVoltageoffersanintuitiveinterfacetothedevice.
Thistool–CurrentContinuallyDigitallyMonitoredallowsthedesignengineertoconfigurethesystemoperatingparametersfortheapplication,storetheOverandUnder-voltageFaultProtectionconfigurationtoon-chipnon-volatilememoryandOver-temperatureFaultProtectionobservebothfrequencydomainandtimedomainEnhancedNonvolatileMemoryWithErrorsimulationsforeachofthepowerstageoutputs.
CorrectionCode(ECC)TIhasalsodevelopedmultiplecomplementarypowerDeviceOperatesFromaSingleSupplyWithanstagesolutions–fromdiscretedriversintheUCD7kInternalRegulatorControllerThatAllowsfamilytofullytestedpowertrainmodulesinthePTDOperationOveraWideSupplyVoltageRangefamily.
ThesesolutionshavebeendevelopedtocomplementtheUCD92xxfamilyofsystempowerSupportedbyFusionDigitalPowercontrollers.
Designer,aFullFeaturedPCBasedDesignTooltoSimulate,Configure,andMonitorPowerSupplyPerformance.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2TMS320C6670,TMS320C6678,FusionDigitalPower,Auto-IDaretrademarksofTexasInstruments.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
2010–2011,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
ti.
comThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
ORDERINGINFORMATIONOPERATINGTEMPERATURETOPSIDEORDERABLEPARTNUMBERPINCOUNTSUPPLYPACKAGERANGE,TAMARKINGUCD9222RGZR48-pinReelof2500QFNUCD9222–40°Cto125°CUCD9222RGZT48-pinReelof250QFNUCD9222ABSOLUTEMAXIMUMRATINGS(1)overoperatingfree-airtemperaturerange(unlessotherwisenoted)VALUEUNITVoltageappliedatV33DtoDGND–0.
3to3.
8VVoltageappliedatV33AtoAGND–0.
3to3.
8VVoltageappliedtoanypin(2)–0.
3to3.
8VStoragetemperature(TSTG)–55to150°C(1)Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)AllvoltagesreferencedtoGND.
RECOMMENDEDOPERATINGCONDITIONSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)MINNOMMAXUNITVSupplyvoltageduringoperation,V33D,V33DIO,V33A33.
33.
6VTAOperatingfree-airtemperaturerange–40125°CTJJunctiontemperature125°C2SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011ELECTRICALCHARACTERISTICSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINNOMMAXUNITSUPPLYCURRENTIV33AV33A=3.
3V815mAIV33DIOV33DIO=3.
3V210SupplycurrentIV33DV33D=3.
3V4045IV33DV33D=3.
3Vstoringconfigurationparameters5055inflashmemoryINTERNALREGULATORCONTROLLERINPUTS/OUTPUTSV333.
3-VlinearregulatorEmitterofNPNtransistor3.
253.
33.
6VV33FB3.
3-Vlinearregulatorfeedback44.
6IV33FBSeriespassbasedriveVIN=12V0.
20.
48mABetaSeriesNPNpassdevice40100EXTERNALLYSUPPLIED3.
3VPOWERV33D,V33DIO1,Digital3.
3-VpowerTA=25°C3.
03.
6VV33DIO2V33AAnalog3.
3-VpowerTA=25°C3.
03.
6VERRORAMPLIFIERINPUTSEAPn,EANnVCMCommonmodevoltageeachpin–0.
151.
848VVERRORInternalerrorVoltagerangeAFE_GAINfieldofCLA_GAINS=1X(1)–256248mVEAP-EANErrorvoltagedigitalresolutionAFE_GAINfieldofCLA_Gains=8X1mVREAInputImpedanceGroundreference0.
51.
53MIOFFSETInputoffsetcurrent1ksourceimpedance–55AVref10-bitDACVrefReferenceVoltageSetpoint01.
6VVrefresReferenceVoltageResolution1.
56mVANALOGINPUTSCS1A,CS2A,VinMon,IinMon,Vtrack,Temp1,Temp2,Addr0,Addr1VADC_RANGEMeasurementrangeforvoltageInputs:VinMon,IinMon,Vtrack,Temp1,02.
5VmonitoringTemp2,CS1A,CS2AVoffsetinputoffsetvoltage–1515mVVOC_THRSOver-currentcomparatorthresholdInputs:CS1A,CS2A0.
0322Vvoltagerange(2)VOC_RESOver-currentcomparatorthresholdInputs:CS1A,CS2A31.
25mVvoltagerangeTempinternalInt.
temperaturesenseaccuracyOverrangefrom0°Cto100°C–1515°CINLADCintegralnonlinearity–2.
52.
5mVIlkgInputleakagecurrent3Vappliedtopin100nARINInputimpedanceGroundreference8MCINCurrentSenseInputcapacitance10pF(1)SeetheUCD92xxPMBusCommandReferenceforthedescriptionoftheAFE_GAINfieldofCLA_GAINScommand.
(2)Canbedisabledbysettingto'0'2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comELECTRICALCHARACTERISTICS(Continued)overoperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINNOMMAXUNITDIGITALINPUTS/OUTPUTSDgndVOLLow-leveloutputvoltageIOL=6mA(1),V33DIO=3VV+0.
25V33DIOVOHHigh-leveloutputvoltageIOH=-6mA(2),V33DIO=3VV–0.
6VVIHHigh-levelinputvoltageV33DIO=3V2.
13.
6VVILLow-levelinputvoltageV33DIO=3.
5V1.
4VSYSTEMPERFORMANCEVRESETVoltagewheredevicecomesoutofresetV33DPin2.
32.
4VtRESETPulsewidthneededforresetnRESETpin2sVrefcommandedtobe1V,at25°CAFEgain=4,SetpointReferenceAccuracy–1010mV1VinputtoEAP/NmeasuredatoutputoftheEADC(3)VRefAccSetpointReferenceAccuracyover–40°Cto125°C–2020mVtemperatureAFEgain=4comparedtoVDiffOffsetDifferentialoffsetbetweengainsettings–44mVAFEgain=1,2,or8240+1tDelayDigitalCompensatorDelay240switchingnscycleFSWSwitchingFrequency15.
2602000kHzAccuracy–5%5%DutyMaxandMinDutyCycle0%100%V33SlewMinimumV33slewrateV33slewratebetween2.
3Vand2.
9V0.
25V/mstretentionRetentionofconfigurationparametersTJ=25°C100YearsWrite_CyclesNumberofnonvolatileerase/writecyclesTJ=25°C20KcyclesAllrailsconfiguredtoaccept4-bitVIDmessages(4)1RateVIDMaxVIDmessagerateAllrailsconfiguredtoaccept6-bitVIDmessages(4)4msg/msecAllrailsconfiguredtoaccept8-bitVIDmessages(5)4(1)ThemaximumIOL,foralloutputscombined,shouldnotexceed12mAtoholdthemaximumvoltagedropspecified.
(2)ThemaximumIOH,foralloutputscombined,shouldnotexceed48mAtoholdthemaximumvoltagedropspecified.
(3)Withdefaultdevicecalibration.
PMBuscalibrationcanbeusedtoimprovetheregulationtolerance.
(4)VIDmessagerateoneachinterface.
Measuredovera1.
0msecinterval(5)VIDmessagerateonPMBusinterface.
4SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011ADCMONITORINGINTERVALSANDRESPONSETIMESTheADCoperatesinacontinuousconversionsequencethatmeasureseachrail'soutputvoltageandoutputcurrent,plussixothervariables(inputvoltage,inputcurrent,internaltemperature,trackingsource,andtwoexternaltemperaturesensors).
Thelengthofthesequenceisdeterminedbythenumberofoutputrails(NumRails)configuredforuse.
Thetimetocompletethemonitoringsamplingsequenceisgivebytheformula:tADC_SEQ=tADC*(2*NumRAILS+6)PARAMETERTESTCONDITIONSMINTYPMAXUNITtADCADCsingle-sampletime3.
84stADC_SEQADCsequencerintervalMin=2*1Rail+6=8samples30.
7238.
40sMax=2*2Rails+6=10samplesThemostrecentADCconversionresultsareperiodicallyconvertedintothepropermeasurementunits(volts,amperes,degrees),andeachmeasurementiscomparedtoitscorrespondingfaultandwarninglimits.
ThemonitoringoperatesasynchronouslytotheADC,atintervalsshowninthetablebelow.
PARAMETERTESTCONDITIONSMINTYPMAXUNITtVoutOutputvoltagemonitoringinterval200stIoutOutputcurrentmonitoringinterval200*NRailsstVinInputvoltagemonitoringinterval1mstIinInputcurrentmonitoringinterval1mstTEMPTemperaturemonitoringinterval100mstAUXADCAuxiliaryADCmonitoringinterval100msBecausetheADCsequencerandthemonitoringcomparisonsareasynchronoustoeachother,theresponsetimetoafaultconditiondependsonwheretheeventoccurswithinthemonitoringintervalandwithintheADCsequenceinterval.
Onceafaultconditionisdetected,someadditionaltimeisrequiredtodeterminethecorrectactionbasedontheFAULT_RESPONSEcode,andthentoperformtheappropriateresponse.
Thefollowingtableliststheworse-casefaultresponsetimes.
MAXMAXPARAMETERTESTCONDITIONSTYPUNITnoVID/wVID(1)tOVF,Over-/under-voltagefaultresponsetimeNormalregulation,noPMBusactivity,250800stUVFduringnormaloperation4stagesenabledtOVF,Over-/under-voltagefaultresponsetime,Duringdataloggingtononvolatile8001000stUVFduringdataloggingmemory(2)tOVF,Over-/under-voltagefaultresponsetime,Duringtrackingandsoft-startramp.
400stUVFwhentrackingorsequencingenabletOCF,Over-/under-currentfaultresponsetimeNormalregulation,noPMBusactivity,100+5000stUCFduringnormaloperation4stagesenabled75%to125%current(600*NRails)step(3)tOCF,Over-/under-currentfaultresponsetime,Duringdataloggingtononvolatile600+5000stUCFduringdataloggingmemory75%to125%currentstep(600*NRails)tOTFOver-temperaturefaultresponsetimeTemperatureriseof10°C/sec,atOT1.
60secthresholdt3-StateTimetotristatethePWMoutputafteraDRIVER_CONFIG=0x015.
5sshutdownisinitiated(1)ControllerreceivingVIDcommandsatarateof4000msg/sec.
(2)DuringaSTORE_DEFAULT_ALLcommand,whichstorestheentireconfigurationtononvolatilememory,thefaultdetectionlatencycanbeupto10ms.
(3)Becausethecurrentmeasurementisaveragedwithasmoothingfilter,theresponsetimetoanover-currentconditiondependsonacombinationofthetimeconstant(τ)fromTable3,therecentmeasurementhistory,andhowmuchthemeasuredvalueexceedstheover-currentlimit.
2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comHARDWAREFAULTDETECTIONLATENCYThecontrollercontainshardwarefaultdetectioncircuitsthatareindependentoftheADCmonitoringsequencer.
PARAMETERTESTCONDITIONSMAXTIMEUNITTimetodisableDPWMoutputbaseonactiveFAULTpintFAULTHighlevelonFAULTpin18ssignalTimetodisabletheDPWMAoutputbasedoninternalSwitchtCLFStepchangeinCSvoltagefrom0Vto2.
5V4analogcomparatorCyclesPMBUS/SMBUS/I2CThetimingcharacteristicsandtimingdiagramforthecommunicationsinterfacethatsupportsI2C,SMBusandPMBusareshownbelow.
Figure1.
I2C/SMBus/PMBusTiminginExtendedModeDiagramI2C/SMBus/PMBusTIMINGREQUIREMENTSTA=–40°Cto125°C,3V50mscausesresetofanytransactioninvolvingUCD9222thatisinprogress.
(3)t(LOW:SEXT)isthecumulativetimeaslavedeviceisallowedtoextendtheclockcyclesinonemessagefrominitialstarttothestop.
6SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011FUNCTIONALBLOCKDIAGRAM2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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com(1)IncaseofconflictbetweenFigure2andTable1thetableshalltakeprecedence(2)PreliminaryversionsofthisdatasheetpriortoJune14,2010hadadifferentdefinitionforpins17,18,and21.
Boarddesignsmadewiththatearlierpinoutshouldbeupdated.
Figure2.
PinAssignmentDiagram8SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011Table1.
PINFUNCTIONSPINNO.
PINLABELDESCRIPTION1IinMon/AuxADC4Inputcurrentmonitor,orAuxiliaryADCinput42Temp2/AuxADC2TemperaturesenseinputforRail2,orAuxiliaryADCinput23CS2APowerstage2Acurrentsenseinputandinputtoanalogcomparator24VinMonInputvoltagemonitor5nRESETActivelowdeviceresetinput.
Pullupto3.
3Vwitha10kohmresistor6FLT1AFaultindicatorforstage1A7VID1SVIDSelectpinforRail18FLT2AFaultindicatorforstage2A9VID2SVIDSelectpinforRail210PMBus_ClkPMBusClock.
Pullupto3.
3Vwitha2kohmresistor11PMBus_DataPMBusData.
Pullupto3.
3Vwitha2kohmresistor12DPWM1ADigitalPulseWidthModulatoroutput1A13PG1Rail1PowerGoodIndicator14DPWM2ADigitalPulseWidthModulatoroutput2A15PG2Rail2PowerGoodIndicator16VID1AVIDinputpinforRail1–leastsignificantbit17PowerGoodPowerGoodIndication18VID1BVIDinputpinforRail119PMBus_AlertPMBusAlert.
Pullupto3.
3Vwitha10kohmresistor20PMBus_CntrlPMBusControl.
Pullupto3.
3Vwitha10kohmresistor21VID1CVIDinputpinforRail1–mostsignificantbit22VID2AVIDinputpinforRail2–leastsignificantbit23VID2BVIDinputpinforRail224VID2CVIDinputpinforRail2–mostsignificantbit25EN1Rail1Enable26EN2Rail2Enable27JTAG_TCKJTAGTestClock28SyncOut/JTAG_TDOMux'edpinJTAGTestDataOutput,DPWMSyncOutput29SyncIn/JTAG_TDIMux'edpin–JTAGTestDataIn,DPWMSyncInput30JTAG_TMSJTAGTestmodeselect.
Pullupto3.
3Vwitha10kohmresistor31(JTAG)nTRSTJTAGTestReset–Tietogroundwitha10kohmresistor32Dgnd3DigitalGround33V33DIO3.
3VsupplyforDigitalI/OandCore34V33AAnalog3.
3Vsupply35BPCap1.
8VBypassCapacitor–tie0.
1Fcaptoanalogground36Agnd2Analogground37EAp1Erroranalog,differentialvoltage,Positivechannel1input38EAn1Erroranalog,differentialvoltage,Negativechannel1input39EAp2Erroranalog,differentialvoltage,Positivechannel2input40EAn2Erroranalog,differentialvoltage,Negativechannel2input41V33FBConnectiontothebaseof3.
3Vlinearregulatortransistor(noconnectifunused)42CS1APowerstage1Acurrentsenseinputandinputtoanalogcomparator143Addr1PMBusAddresssense.
Channel1.
44Addr0PMBusAddresssense.
Channel0.
45Vtrack/AuxADC3Trackingvoltageinput,orAuxiliaryADCinput346Temp1/AuxADC1TemperaturesenseinputforRail1,orAuxiliaryADCinput147Agnd3Analogground2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comTable1.
PINFUNCTIONS(continued)PINNO.
PINLABELDESCRIPTION48ADC_RefADCReference.
Tietoanaloggroundthrough0.
1FcapacitorPowerPadItisrecommendedthatthispadbeconnectedtoanaloggroundTYPICALAPPLICATIONSCHEMATICFigure3showstheUCD9222powersupplycontrolleraspartofasystemthatprovidestheregulationoftwoindependentpowersupplies.
TheloopforeachpowersupplyiscreatedbytherespectivevoltageoutputsfeedingintothedifferentialvoltageerrorADC(EADC)inputs,andcompletedbyDPWMoutputsfeedingintothegatedriversforeachpowerstage.
The±VsenserailsignalsmustberoutedtotheEAp/EAninputthatmatchestheDPWMnumberthatcontrolstheoutputpowerstage.
Forexample,thepowerstagedrivenbyDPWM1AmusthaveitsfeedbackroutedtoEAP1andEAN1.
Figure3.
TypicalApplicationSchematic10SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011FUNCTIONALOVERVIEWTheUCD9222containstwoFusionPowerPeripherals(FPP).
EachFPPconsistsof:Adifferentialinputerrorvoltageamplifier.
A10-bitDACusedtosettheoutputregulationreferencevoltage.
AfastADCwithprogrammableinputgaintodigitallymeasuretheerrorvoltage.
Adedicated3-pole/3-zerodigitalfiltertocompensatetheerrorvoltageAdigitalPWM(DPWM)enginethatgeneratesthePWMpulsewidthbasedonthecompensatoroutput.
EachcontrollerisconfigurablethroughthePMBusserialinterface.
PMBusInterfaceThePMBusisaserialinterfacespecificallydesignedtosupportpowermanagement.
ItisbasedontheSMBusinterfacethatisbuiltontheI2Cphysicalspecification.
TheUCD9222supportsrevision1.
2ofthePMBusstandard.
Whereverpossible,standardPMBuscommandsareusedtosupportthefunctionofthedevice.
ForuniquefeaturesoftheUCD9222,MFR_SPECIFICcommandsaredefinedtoconfigureoractivatethosefeatures.
ThesecommandsaredefinedintheUCD92xxPMBUSCommandReference.
TheUCD9222isPMBuscompliant,inaccordancewiththe"Compliance"sectionofthePMBusspecification.
ThefirmwareisalsocompliantwiththeSMBus2.
0specification,includingsupportfortheSMBusALERTfunction.
Thehardwarecansupport100kHz,400kHz,or1MHzPMBusoperation.
ResistorProgrammedPMBusAddressDecodeThePMBusAddressisselectedusingresistorsattachedtotheADDR0andADDR1pins.
Atpower-up,thedeviceappliesabiascurrenttoeachaddressdetectpin.
ThemeasuredvoltageoneachpindeterminesthePMBusaddressasdefinedinTable2.
Forexample,a133kΩresistoronADDR1anda75kΩonADDR0willselectPMBusaddress=100.
ResistorsarechosenfromthestandardEIA-E96series,andshouldhaveaccuracyof1%orbetter.
Figure4.
PMBusAddressDetectionMethodAshortoropenoneitheraddresspincausesthePMBusaddresstodefaulttoaddress126.
Toavoidpotentialconflictsbetweenmultipledevices,itisbesttoavoidusingaddress126.
Someaddressesshouldbeavoided;seeTable2fordetails.
2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comTable2.
PMBusAddressBins(1)ADDR0(short)(open)42.
2k48.
7k56.
2k64.
9k75k86.
6k100k115k133k154k178k205k237k237k126126126126126126126126126126126126126126(open)(1)Shadedaddressesarenotrecommendedastheywillcauseconflictwhenmultipledevicesareused.
(2)Reserved.
Donotuse.
(3)ConflictswithROM.
Donotuse.
VIDInterfaceTheUCD9222supportsVID(VoltageIdentification)inputsfromuptotwoexternalVIDenableddevices.
TheVIDcodesmaybe4-,6-,or8-bitvalues;theformatisselectedusingtheVID_CONFIGPMBuscommand.
In4-and6-bitmode,eachhostusesfourVIDinputsignals(VID_A,VID_B,VID_C,andVID_S)tosendVIDcodestotheUCD9222.
In8-bitmode,thePMBusinputisusedtoreceiveVIDcommandsfromtheVIDdevices'I2Cinterfaces.
Figure5.
OneUCD9222ControlledbyTwoDSP/ASICsUsing4-bitor6-bitVIDFormatRegardlessofwhichVIDmodeisused,thecommandedoutputvoltagereferenceissetaccordingtothisformula:Vref_cmd=(VID_CODE*VID_Slope)+VID_Offset,whereVID_Slope=(VID_Vout_High–VID_Vout_Low)/((2^VID_Format)-1),andVID_Offset=VID_Vout_Low.
12SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011TheVID_Vout_High,VID_Vout_Low,andVID_FormatvaluesaresetusingtheVID_CONFIGPMBuscommand.
ThesamecommandisusedtosettheinitialVIDcodethatwillbeusedatpower-up.
Inaddition,theVID_CONFIGcommandalsosetstheinitialvoltagethatthedevicerampstoattheendofthesoftstart;anddefinesalockoutintervaloverwhichtheVIDisignoredduringthesoftstart.
VIDLockoutInterval:BecausetheVIDsignalsmaybeoriginatingfromadevicethatisbeingpoweredbytheUCD9222,thevoltagelevelsontheVIDsignalmaynotbevalidlogiclevelsuntilthesupplyvoltageatthepowereddevicehasstabilized.
Forthisreasonaconfigurablelockoutintervalisappliedeachtimetheregulatedoutputvoltageisturnedon.
Thelockoutintervaltimerstartswhentheoutputvoltagereachesthetopofthesoft-startramp.
Positivevaluesrangefrom1to32767ms,with1msresolution.
Avalueof0willenabletheVIDinputsimmediatelyatthetopofthestartramp.
Negativevaluesdisablethelockout,allowingtheVIDinputstoremainactiveallthetimeregardlessoftheoutputvoltagestate.
Thedefaultvalueis0.
4-BitVIDMode:In4-bitVIDmode,thefourVIDinputsignalsareusedtoprovidethefourbitsofVIDdata,asshowninthetablebelow.
TheVIDlinesarelevel-sensitive,andareperiodicallypolledevery400s.
WhentheVIDlinesarechangedtocommandanewvoltage,theremaybeadelayof500to600swhiletheUCD9222confirmsthattheVIDsignallevelsarestable.
TheoutputvoltagewillthenslewtothenewsetpointvoltageattheratespecifiedbythePMBusVOUT_TRANSITION_RATEcommand.
PINPURPOSERAIL1RAIL2VID_ADatabit0(leastsignificantbit)VID1AVID2AVID_BDatabit1VID1BVID2BVID_CDatabit2VID1CVID2CVID_SDatabit3(mostsignificantbit)VID1SVID2S6-BitVIDMode:In6-bitVIDmode,thefourVIDinputsignalsareusedtoprovidethesixbitsofVIDdata,asshowninthetablebelow.
Eachofthethreedatalines(VID_A,VID_B,andVID_C)carriestwobitsofdataperVIDcode.
ThebitsareclockedandselectedbytheVID_Sselectline.
PINPURPOSERAIL1RAIL2VID_ADatabit0whenVID_Sislow,VID1AVID2ADatabit3whenVID_SishighVID_BDatabit1whenVID_Sislow,VID1BVID2BDatabit4whenVID_SishighVID_CDatabit2whenVID_Sislow,VID1CVID2CDatabit5whenVID_SishighVID_SSelectLine:VID1SVID2SLow=LSB,High=MSB2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comThefallingedgeoftheVID_SlinetriggerstheUCD9222toreadbits2:0onthethreeVIDdatalines.
TherisingedgeofVID_StriggerstheUCD9222toreadbits5:3onthethreeVIDdatalinesandcalculateanewVOUTsetpoint.
Thiscalculationtakesfrom35to135s.
TheoutputvoltagewillthenslewtothenewsetpointvoltageattheratespecifiedbytheVOUT_TRANSITION_RATEPMBuscommand.
Figure6.
6-BitVIDDataTransferTheset-uptimeonthedatalinesis0s.
AllfourVIDlinesmustholdatthesamelevelforsometimeafterachangeintheVID_SlinetoallowtheUCD9222toreadandvalidatethedatasignalsandperformnecessaryvoltagecalculations.
TheUCD9222cantoleratesingleholdtimesasshortas70s,butdoesnothavesufficientcomputationpowertosustaincontinuousVIDmessagingthatquickly.
Itisexpectedthattheholdtimewillbeatleast125sforsustainedoperations.
ItisrecommendedthattheDSPonlysendVIDmessageswhentheregulatedvoltageneedstochange;sendingthesameVIDcoderepeatedlyandcontinuouslyprovidesnobenefit.
Figure7andTable3illustratethecriticaltimingmeasurementsastheyapplytothe6-bitVIDinterface.
Figure7.
6-bitVIDTiming14SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011Table3.
6-bitVIDTimingSYMBOPARAMETERMINTYPMAXUNITSLTrDataandclockrisetime–2.
5sTfDataandclockfalltime–0.
3sTsuDatasetupbeforechangingclock0sThdDataholduntilnextclockchange70sTchiClockhightime70125sTcloClocklowtime70125sTvoResponsetimefromrisingedgeofVID_Stostartof35135sVoutslewingtonewsetpoint8-BitVIDMode:In8-bitVIDmode,thefourVIDinputsignalsarenotused.
Instead,an8-bitVIDcodeistransmittedtotheUCD9222throughthePMBus/I2CportusingoneoftheVID_CODE_RAILncommands,wherenistherailnumberfrom1to2.
NAMEDESCRIPTION(1)CODEVID_CONFIGSelectstheVIDmode,setstheupperandlowervoltagelimits,andthestartingvoltagecodeatpower-up.
0xBBVID_CODE_RAIL1SelectstheVIDcodeusedtosettheoutputvoltageforRail1.
0xBCVID_CODE_RAIL2SelectstheVIDcodeusedtosettheoutputvoltageforRail2.
0xBD(1)ForacompletedescriptionoftheserialVIDcommands,seetheUCD92xxPMBusCommandReference(SLUU337)2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comFigure8.
PMBusTimingforVID_CODE_RAILnCommandTable4.
TypicalPMBusTimingforVID_CODE_RAILnCommand@400kHzSYMBOLPARAMETERCONDITIONSTYPUNITSTmsgPECMessageTransmitTime,withPEC400kHzclock,PECenabled162–256sMessageTransmitTime,withoutPEC400kHzclock,PECenabled126–221TvoEndofmessageuntilVoutstartschanging28–140sTmsgvoStartofmessageuntilVoutstartchanging400kHzclock,PECdisabled169–314sThetotaltimetotransmittheserialVIDcommandwillvarydependingontheothertasksthattheUCD92xxprocessorisperforming.
Typicalpackettimesvariedfrom162to256swhenthePMBusisconfiguredfora400kb/stransferraterunningandtheoptionalPECbyteisenabled.
DisablingthePECbytesavesabout35sandthetransfertimesarefrom126to221s.
Notethatthesearenotspecifiedbest-case/worst-casetimings,butindicatearangegiventhetypicalacknowledgeoverheadinthehostandcontroller.
AftertheVIDpackethasbeenreceivedbythecontrollerthereisadelaybeforetheset-pointreferenceDACisupdated.
Thisdelaytimevariesfrom~28sto140s(typical)dependingontheexistingpriorityofupdatingset-pointreferenceDACwhenthecommandisreceived.
Witha221spackettransfertime,itwouldseempossibletosend4500VIDmessagespersecondtothedevice.
Veryshortburstsatthisratemightbeacceptable,butdoingsoforsustainedperiodscouldoverwhelmtheavailableprocessingresourcesintheUCD92xx,causingittobedelayedinperformingitsothermonitoringandfaultresponsetasks.
Inaddition,ifmultiplehostsaretryingtotalkonthePMBusatsuchhighratesthenbuscontentionwilloccurwithgreatregularity.
Topreventtheseissues,itisprudenttolimitthetotalVIDmessagingratetolessthan4messagespermillisecond.
Inasystemwithfourindependenthosts,eachhostmightneedtobelimitedtolessthan1messagepermillisecond.
Therefore,tominimizePMBustraffic,itisbesttoonlyissuetheVIDcommandwhenavoltagechangeisrequired.
ThereisnobenefittosendingthesameVIDcodecontinuouslyandrepeatedly.
JTAGInterfaceTheJTAGinterfacecanprovideanalternateinterfaceforprogrammingthedevice.
TwooftheJTAGpins(TDIandTDO)aresharedwiththeSyncInandSyncOutfunction.
JTAGisdisabledbydefault.
TherearethreeconditionsunderwhichtheJTAGinterfaceisenabled:1.
WhentheROM_MODEPMBuscommandisissued.
2.
Onpower-upiftheDataFlashisblank.
ThisallowsJTAGtobeusedforwritingtheconfigurationparameterstoaprogrammeddevicewithnoPMBusinteraction.
3.
Whenaninvalidaddressisdetectedatpower-up.
Byopeningorshortingoneoftheaddresspinstoground,aninvalidaddresscanbegeneratedthatenablesJTAG.
WhentheJTAGportisenabledthesharedpinsarenotavailableforuseasSyncpins.
IfJTAGistobeused,anexternalmechanismsuchasjumpersoramuxmustbeusedtopreventconflictbetweenJTAGandtheSyncpins.
16SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011BiasSupplyGenerator(ShuntRegulatorController)TheI/OandanalogcircuitsintheUCD9222require3.
3Vtooperate.
Thiscanbeprovidedusingastand-aloneexternal3.
3Vsupply,oritcanbegeneratedfromthemaininputsupplyusinganinternalshuntregulatorandanexternaltransistor.
Regardlessofwhichmethodisusedtogeneratethe3.
3Vsupply,bypasscapacitorsof0.
1Fand4.
7FshouldbeconnectedfromV33AandV33Dtogroundnearthedevice.
Anadditionalbypasscapacitorfrom0.
1to1FmustbeconnectedfromtheBPCappintogroundfortheinternal1.
8Vsupplytothedevice'slogiccircuits.
Figure9showsatypicalapplicationusingtheexternaltransistor.
ThebaseofthetransistorisdrivenbyaresistorR1toVinandatransconductanceamplifierwhoseoutputisontheV33FBpin.
TheNPNemitterbecomesthe3.
3Vsupplyforthechip.
Figure9.
3.
3VShuntRegulatorControllerI/OInordertogeneratethecorrectvoltageonthebaseoftheexternalpasstransistor,theinternaltransconductanceamplifiersinkscurrentintotheV33FBpinandavoltageisproducedacrossR1.
ThisresistorvalueshouldbechosensothatISINKisintherangefrom0.
2to0.
4mA.
R1isdefinedas(1)WhereISINKisthecurrentintotheV33FBpin;Vinisthepowersupplyinputvoltage,typically12V;IEisthecurrentdrawofthedeviceandanypullupresistorstiedtothe3.
3Vsupply;andβisthebetaofthepasstransistor.
ForISINK=0.
3mA,Vin=12V,β=99,Vbe=0.
7VandIE=50mA,thisformulaselectsR1=10kΩ.
WeakertransistorsorlargercurrentloadswillrequirelessresistancetomaintainthedesiredISINKcurrent.
Forexample,loweringβto40wouldrequireR1=5.
23kΩ;likewise,aninputvoltageof5Vrequiresavalueof1.
24kΩforR1.
Power-OnResetTheUCD9222hasanintegratedpower-onreset(POR)circuitthatmonitorsthesupplyvoltage.
Atpower-up,thePORcircuitdetectstheV33Drise.
WhenV33DisgreaterthanVRESET,thedeviceinitiatesaninternalstartupsequence.
Attheendofthestartupsequence,thedevicebeginsnormaloperation,asdefinedbythedownloadeddevicePMBusconfiguration.
ExternalResetThedevicecanbeforcedintotheresetstatebyanexternalcircuitconnectedtothenRESETpin.
Alogiclowvoltageonthispinholdsthedeviceinreset.
Toavoidanerroneoustriggercausedbynoise,a10kΩpullupresistorto3.
3Visrecommended.
2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comON_OFF_CONFIGTheON_OFF_CONFIGcommandisusedtoselectthemethodofturningrailsonandoff.
Itcanbeconfiguredsothattherail:staysoff,turnsonautomatically,respondstothePMBus_Cntrlpin,respondstoOPERATIONcommand,orrespondstological-ANDofthePMBus_CntrlpinandtheOPERATIONcommand.
TheON_OFF_CONFIGcommandalsosetstheactivepolarityofthePMBus_Cntrlpin.
EN1/EN2InadditiontothePMBus_CntrlpinsupportedbyallUCD92xxproducts,theUCD9222alsosupportsseparateEnablepinsforeachrail.
ThepolarityoftheEN1/EN2pinisuser-configurable,andwillbethesameasthepolaritychosenforthePMBus_CntrlpinbytheON_OFF_CONFIGcommand.
WhentheON_OFF_CONFIGsettingisconfiguredtorespondthePMBus_Cntrlpin,thePMBus_CntrlpinsignalwillbelogicallyANDedwiththerail'sENpinsignal.
PG1/PG2InadditiontothePowerGoodoutputsignalsupportedbyallUCD92xxproducts,theUCD9222alsosupportsseparatePGindicatorsforeachrail.
ThePowerGoodsignalisthelogical-ANDofallrails,whilePG1andPG2indicatethestatusofasinglerail.
Allthreeoftheseindicatorsareopen-drainoutputs,sotheyrequirepull-upresistors.
Whendrivingexternalcircuitswithlogicvoltageslessthan3.
3V,thepull-upsmaybetiedtothatlowersupplyvoltage,thusavoidingtheneedforlevel-shifters.
OutputVoltageAdjustmentTheoutputvoltagemaybesettomaintainasteadyvoltageoritmaybecontrolleddynamicallybytheVIDinterface,dependingontheVID_CONFIGsetting.
WhennotbeingcommandedbytheVIDinterface,thenominaloutputvoltageisprogrammedbyacombinationofPMBussettings:VOUT_COMMAND,VOUT_CAL_OFFSET,VOUT_SCALE_LOOP,andVOUT_MAX.
TheirrelationshipisshowninFigure10.
ThesePMBusparametersneedtobesetsuchthattheresultingVrefDACvaluedoesnotexceedthemaximumvalueofVref.
OutputvoltagemarginingisconfiguredbytheVOUT_MARGIN_HIGHandVOUT_MARGIN_LOWcommands.
TheOPERATIONcommandselectsbetweenthenominaloutputvoltageandeitherofthemarginvoltages.
TheOPERATIONcommandalsoincludesanoptiontosuppresscertainvoltagefaultsandwarningswhileoperatingatthemarginsettings.
Figure10.
PMBusVoltageAdjustmentMechanisms18SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011ForacompletedescriptionofthecommandssupportedbytheUCD9222seetheUCD92xxPMBUSCommandReference(SLUU337).
EachofthesecommandscanalsobeissuedfromtheTexasInstrumentsFusionDigitalPowerDesignerprogram.
ThisGraphicalUserInterface(GUI)PCprogramissuestheappropriatecommandstoconfiguretheUCD9222device.
CalibrationTooptimizetheoperationoftheUCD9222,PMBuscommandsaresuppliedtoenablefinecalibrationofoutputvoltage,outputcurrent,andtemperaturemeasurements.
ThesupportedcommandsandrelatedcalibrationformulasmaybefoundintheUCD92xxPMBUSCommandReference(SLUU337).
AnalogFrontEnd(AFE)Figure11.
AnalogFrontEndBlockDiagramTheUCD9222sensesthepowersupplyoutputvoltagedifferentiallythroughtheEAPandEANpins.
Theerroramplifierutilizesaswitchedcapacitortopologythatprovidesawidecommonmoderangefortheoutputvoltagesensesignals.
Thefullydifferentialnatureoftheerroramplifieralsoensureslowoffsetperformance.
Theoutputvoltageissampledataprogrammabletime(setbytheEADC_SAMPLE_TRIGGERPMBuscommand).
Whenthedifferentialinputvoltageissampled,thevoltageiscapturedininternalcapacitorsandthentransferredtotheerroramplifierwherethevalueissubtractedfromtheset-pointreferencewhichisgeneratedbythe10-bitVrefDACasshowninFigure11.
TheresultingerrorvoltageisthenamplifiedbyaprogrammablegaincircuitbeforetheerrorvoltageisconvertedtoadigitalvaluebytheerrorADC(EADC).
ThisprogrammablegainisconfiguredthroughthePMBusandaffectsthedynamicrangeandresolutionofthesensederrorvoltageasshowninTable5.
Theinternalreferencegainsandoffsetsarefactory-trimmedatthe4xgainsetting,soitisrecommendedthatthissettingbeusedwheneverpossible.
Table5.
AnalogFrontEndResolutionAFE_GAINforEFFECTIVEADCDIGITALERRORVOLTAGEAFEGainPMBusCommandRESOLUTION(mV)DYNAMICRANGE(mV)01x8–256to24812x4–128to1242(Recommended)4x2–64to6238x1–32to31TheAFEvariablegainisoneofthecompensationcoefficientsthatarestoredwhenthedeviceisconfiguredbyissuingtheCLA_GAINSPMBuscommand.
Compensatorcoefficientsarearrangedinseveralbanks:onebankforstart/stopramportracking,onebankfornormalregulationmodeandonebankforlightloadmode.
Thisallowstheusertotrade-offresolutionanddynamicrangeforeachoperationalmode.
TheEADC,whichsamplestheerrorvoltage,hashighaccuracy,highresolution,andafastconversiontime.
However,itsrangeislimitedasshowninTable5.
Iftheoutputvoltageisdifferentfromthereferencebymorethanthis,theEADCreportsasaturatedvalueat–32LSBsor31LSBs.
TheUCD9222overcomesthislimitationbyadjustingtheVrefDACupordowninordertobringtheerrorvoltageoutofsaturation.
Inthisway,theeffectiverangeoftheADCisextended.
WhentheEADCsaturates,theVrefDACisslewedatarateof0.
156V/ms,referredtotheEAdifferentialinputs.
2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comThedifferentialfeedbackerrorvoltageisdefinedasVEA=VEAP–VEAN.
AnattenuatornetworkusingresistorsR1andR2(Figure12)shouldbeusedtoensurethatVEAdoesnotexceedthemaximumvalueofVrefwhenoperatingatthecommandedvoltagelevel.
ThecommandedvoltagelevelisdeterminedbythePMBussettingsdescribedintheOutputVoltageAdjustmentsection.
Figure12.
InputOffsetEquivalentCircuitVoltageSenseFilteringConditioningshouldbeprovidedontheEAPandEANsignals.
Figure12showsadividernetworkbetweentheoutputvoltageandthevoltagesenseinputtothecontroller.
Theresistordividerisusedtobringtheoutputvoltagewithinthedynamicrangeofthecontroller.
Whennoattenuationisneeded,R2canbeleftopenandthesignalconditionedbythelow-passfilterformedbyR1andC2.
Aswithanypowersupplysystem,maximizetheaccuracyoftheoutputvoltagebysensingthevoltagedirectlyacrossanoutputcapacitorasclosetotheloadaspossible.
Routethepositiveandnegativedifferentialsensesignalsasabalancedpairoftracesorasatwistedpaircablebacktothecontroller.
Putthedividernetworkclosetothecontroller.
Thisensuresthatthereislowimpedancedrivingthedifferentialvoltagesensesignalfromthevoltagerailoutputbacktothecontroller.
Theresistanceofthedividernetworkisatrade-offbetweenpowerlossandminimizinginterferencesusceptibility.
Aparallelresistance(Rp)of1kΩto4kisagoodcompromise.
OnceRPischosen,R1andR2canbedeterminedfromthefollowingformulas.
(2)Itisrecommendedthatacapacitorbeplacedacrossthelowerresistorofthedividernetwork.
Thisactsasanadditionalpoleinthecompensationandasananti-aliasfilterfortheEADC.
Tobeeffectiveasananti-aliasfilter,thecornerfrequencyshouldbe35%to40%oftheswitchingfrequency.
Thenthecapacitoriscalculatedas:(3)Toobtainthebestpossibleaccuracy,theinputresistanceandoffsetcurrentonthedeviceshouldbeconsideredwhencalculatingthegainofavoltagedividerbetweentheoutputvoltageandtheEAsenseinputsoftheUCD9222.
Theinputresistanceandinputoffsetcurrentarespecifiedintheparametrictablesinthisdatasheet.
VEA=VEAP–VEANintheequationbelow.
(4)Theeffectoftheoffsetcurrentcanbereducedbymakingtheresistanceofthedividernetworklow.
20SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011DigitalCompensatorEachvoltagerailcontrollerintheUCD9222includesadigitalcompensator.
Thecompensatorconsistsofanonlineargainstage,followedbyadigitalfilterconsistingofasecondorderinfiniteimpulseresponse(IIR)filtersectioncascadedwithafirstorderIIRfiltersection.
TheTexasInstrumentsFusionDigitalPowerDesignerdevelopmenttoolcanbeusedtoassistindefiningthecompensatorcoefficients.
Thedesigntoolallowsthecompensatortobedescribedintermsofthepolefrequencies,zerofrequenciesandgaindesiredforthecontrolloop.
Inaddition,theFusionDigitalPowerDesignercanbeusedtocharacterizethepowerstagesothatthecompensatorcoefficientscanbechosenbasedonthetotalloopgainforeachfeedbacksystem.
Thecoefficientsofthefiltersectionsaregeneratedthroughmodelingthepowerstageandload.
Additionally,theUCD9222hasthreebanksoffiltercoefficients:Bank-0isusedduringthesoftstart/stopramportracking;Bank-1isusedwhileinregulationmode;andBank-2isusedwhenthemeasuredoutputcurrentisbelowtheconfiguredlightloadthreshold.
Figure13.
DigitalCompensatorTocalculatethevaluesofthedigitalcompensationfiltercontinuous-timedesignparametersKDC,FZandsQZareenteredintotheFusionDigitalPowerDesignersoftware(oritcalculatesthemautomatically).
Wherethecompensatingfiltertransferfunctionis(5)ThereareapproximatelimitsthedesignparametersKDC,FZandsQZ.
Thoughdesignparametersbeyondtheseupperalowerboundscanbeusedtocalculatethediscrete-timefiltercoefficients,therewillbesignificantround-offerrorwhenthecontinuous-timefloating-pointdesignparametersareconvertedtothediscrete-timefixed-pointintegercoefficientstobedownloadedtothecontroller.
2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comAPPROXIMATEDESIGNPARAMETERUNITSLOWERBOUNDUPPERBOUNDKDC60103dBFZ3kHzFsw/5kHzQZ0.
15.
0n/aThenonlineargainblockallowsadifferentgaintobeappliedtothesystemwhentheerrorvoltagedeviatesfromzero.
TypicallyLimit0andLimit1wouldbeconfiguredwithnegativevaluesbetween–1and–32andLimit2andLimit3wouldbeconfiguredwithpositivevaluesbetween1and31.
However,thegainthresholdsdonothavetobesymmetrical.
Forexample,thefourlimitregisterscouldallbesettopositivevaluescausingtheGain0valuetosetthegainforallnegativeerrorsandanonlineargainprofilewouldbeappliedtoonlypositiveerrorvoltages.
Thecascaded1storderfiltersectionisusedtogeneratethethirdzeroandthirdpole.
DPWMEngineTheoutputofthecompensatorfeedsthehighresolutionDPWMengine.
TheDPWMengineproducesthepulsewidthmodulatedgatedriveoutputfromthedevice.
Inoperation,thecompensatorcalculatesthenecessarydutycycleasadigitalnumberrepresentingapercentagefrom0to100%.
Thedutycyclevalueismultipliedbytheconfiguredperiodtogenerateacomparatorthresholdvalue.
ThisthresholdiscomparedagainstthehighspeedswitchingperiodcountertogeneratethedesiredDPWMpulsewidth.
ThisisshowninFigure14.
EachDPWMenginecanbesynchronizedtoanotherDPWMengineortoanexternalsyncsignalviatheSyncInandSyncOutpins.
ConfigurationofthesynchronizationfunctionisdonethroughaMFR_SPECIFICPMBuscommand.
SeetheDPWMSynchronizationsectionformoredetails.
Figure14.
DPWMEngineRail/PowerStageConfigurationUnlikemanyotherproductsintheUCD92xxfamily,theUCD9222doesnotsupportassigningpowerstagestoarbitraryrails,orcombiningmultiplepowerstagesonthesamerail.
TheUCD9222supportsuptotwosingle-phaserails,andthechannelnumberofeachrail'sDPWMoutputmustmatchthatofitsEAP/EANfeedbackinputs.
22SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011DPWMPhaseSynchronizationDPWMsynchronizationprovidesamethodtolinkthetimingbetweenvoltagerailscontrolledbytheUCD92xxdevice--eitherinternallyorbetweendevices.
TheconfigurationofthesynchronizationbetweenrailsisperformedbytheissuingtheSYNC_CONFIGcommand.
Fordetailsofissuingthiscommand,seetheUCD92xxPMBUSCommandReference(SLUU337).
ThesynchronizationbehaviorcanalsobeconfiguredusingtheFusionDigitalPowerDesignersoftware.
Belowisasummaryofthefunction.
Eachdigitalpulsewidthmodulator(PWM)engineintheUCD92xxcontrollercanacceptasyncsignalthatresetsthePWMrampgenerator.
Therampgeneratorcanbesettofree-run,acceptaresetsignalfromanotherinternalPWMengine,oracceptaresetsignalfromtheexternalSyncInpin(UCD9222only).
Inaddition,eachdigitalPWMenginecangenerateaphasedelayedsyncsignalthatcanbedirectedtoanotherPWMresetinputordirectedtotheexternalSyncOutpin.
InthiswaythePWMtimerscanbe"daisy-chained"tosetupthedesiredphaserelationshipbetweenpowerstages.
ThePWMengineresetinputcanacceptthefollowinginputsTable6.
SyncTriggerInputsNone(freerun)DPWM1DPWM2SyncInPinWhenconfiguringaPWMenginetorunsynchronoustoanotherinternalPWMoutput,settheswitchingfrequencyofeachPWMoutputtothesamevalueusingtheFREQUENCY_SWITCHPMBuscommand.
SetthetimepointwherethecontrollersamplesthevoltagetoberegulatedbysettingtheEADC_SAMPLE_TRIGGERvaluetotheminimumvalue(228-240nsecbeforetheendoftheswitchingperiod).
WhenconfiguringaPWMenginetorunsynchronoustorunanexternalsyncsignal,theswitchingperiodmustbesettobelongerthantheperiodofthesyncsignalbysettingthevalueoftheFREQUENCY_SWITCHcommandtobelowerthanthefrequencyofthesyncsignal.
ThiswaytheexternalsyncsignalwillresetthePWMrampcounterbeforeitisinternallyreset.
Inthisoperatingcondition,theerrorADCsampletriggertimemustbesetto:(6)whereFSWistheswitchingfrequencysetbyFREQUENCY_SWITCHandFsyncistheminimumsynchronizationfrequency.
Thefactorof0.
95isduetothe5%toleranceontheinternalclockinthecontroller.
Thiswillensurethattheregulationvoltageissampled"justintime"tocalculatetheappropriatecontroleffortforeachswitchingperiod.
ThisisshowninFigure15.
Figure15.
RelationshipofEADCTriggertoexternalSyncIftworailsshareacommonsyncsourceotherthantheSyncInpin,theymusthavethesamedelay.
Whenthe2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
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comSyncInpinisusedasasyncsource,thedelayisappliedusingadifferentregister(EV1)thanwhenusingtheothersources(whichusethePhaseTrigregisters).
UsingtheEV1registerintroducesdelayinthecontrolloopcalculationthatwillintroducephaselossthatmustbetakenintoconsiderationwhencalculatingtheloopcompensation.
Therefore,undermostconditionsitwillbedesirabletosetthedelaytozeroforthePWMsignalsynchronizedbytheSyncInpin.
OutputCurrentMeasurementPinsCS1AandCS2Aareusedtomeasureeitheroutputcurrentorinductorcurrentineachofthecontrolledpowerstages.
PMBuscommandsIOUT_CAL_GAINandIOUT_CAL_OFFSETareusedtocalibrateeachmeasurement.
SeetheUCD92xxPMBusCommandReference(SLUU337)forspecificsonconfiguringthisvoltagetocurrentconversion.
Whenthemeasuredcurrentisoutsidetherangeofeithertheover-currentorunder-currentfaultthreshold,acurrentlimitfaultisdeclaredandtheUCD9222performsthePMBusconfiguredfaultrecovery.
ADCcurrentmeasurementsaredigitallyaveragedbeforetheyarecomparedagainsttheover-currentandunder-currentwarningandfaultthresholds.
TheoutputcurrentismeasuredatarateofoneoutputrailpertIoutmicroseconds.
Thecurrentmeasurementsarethenpassedthroughadigitalsmoothingfiltertoreducenoiseonthesignalandpreventfalseerrors.
Theoutputofthesmoothingfilterasymptoticallyapproachestheinputvaluewithatimeconstantthatisapproximately3.
5timesthesamplinginterval.
Table7.
OutputCurrentFilterTimeConstantsNUMBEROFOUTPUTCURRENTFILTEROUTPUTRAILSSAMPLINGINTERVALS(s)TIMECONSTANTτ(ms)12000.
724001.
4Thissmoothedcurrentmeasurementisusedforoutputcurrentfaultdetection;seetheOver-currentDetectionsection.
ThesmoothedcurrentmeasurementisalsoreportedinresponsetoaPMBusrequestforacurrentreading.
CurrentSenseInputFilteringEachpowerstagecurrentismonitoredbythedeviceattheCSpins.
Thedevicemonitorsthecurrentwitha12-bitADCandalsomonitorsthecurrentwithadigitallyprogrammableanalogcomparator.
ThecomparatorcanbedisabledbywritingazerototheFAST_OC_FAULT_LIMIT.
Becausethecurrentsensesignalisbothdigitallysampledandcomparedtotheprogrammableover-currentthreshold,itshouldbeconditionedwithanRCnetworkactingasananti-aliasfilter.
Ifthecomparatorisdisabled,theCSinputshouldbefilteredat35%ofthesamplingrate.
AnRCnetworkwiththischaracteristiccanbecalculatedas(7)whereNrailsisthenumberofrailsconfiguredandTIoutisthesampleperiodforthecurrentsenseinputs.
Therefore,whenthecomparatorisnotused,therecommendedcomponentvaluesfortheRCnetworkareC=10nFandR=35.
7kΩ.
Whenthefastover-currentcomparatorisused,thefiltercornerfrequencybasedontheADCsampleratemaybetooslowandacornerfrequencythatisacompromisebetweentherequirementsoffastover-currentdetectionandattenuatingaliasedcontentinthesampledcurrentmustbesought.
Inthiscase,thefiltercornerfrequencycanbecalculatedbasedonthetimetocrosstheover-currentthreshold.
(8)whereVOC_thresistheprogrammedOCcomparatorthreshold,VCS_nomisthenominalCSvoltage,ΔVImonisthechangeinCSvoltageduetoanover-currentfaultandτisthefiltertimeconstant.
Usingtheequationforthecomparatorvoltageabove,theRCnetworkvaluescanbecalculatedas24SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
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comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011(9)whereTdetisthetimetocrosstheover-currentcomparatorthreshold.
ForTdet=10s,ΔVImon=1.
5V,VOC_thres=2.
0VandVCS_nom=1.
5V,thecornerfrequencyis6.
4kHzandtherecommendedRCnetworkcomponentvaluesareC=10nFandR=2.
49kΩ.
Over-CurrentDetectionSeveralmechanismsareprovidedtosenseoutputcurrentfaultconditions.
Thisallowsforthedesignofpowersystemswithmultiplelayersofprotection.
1.
IntegratedgatedriverssuchastheUCD72xxfamilycanbeusedtogeneratetheFLTsignal.
ThedrivermonitorsthevoltagedropacrossthehighsideFETandifitexceedsaresistor/voltageprogrammedthreshold,thedriveractivatesitsfaultoutput.
AlogichighsignalontheFLTinputcausesahardwareinterrupttotheinternalCPU,whichthendisablestheDPWMoutput.
Thisprocesstakesabout14microseconds.
2.
InputsCS1AandCS2Aeachdriveaninternalanalogcomparator.
Thesecomparatorscanbeusedtodetectthevoltageoutputofacurrentsensecircuit.
EachcomparatorhasaseparatethresholdthatcanbesetbytheFAST_OC_FAULT_LIMITPMBuscommand.
Thoughthecommandisspecifiedinamperes,thehardwarethresholdisprogrammedwithavaluebetween31mVand2Vin64steps.
TherelationshipbetweenamperestosensedvoltsisconfiguredbytheIOUT_CAL_GAINcommand.
Whenthecurrentsensevoltageexceedsthethreshold,thecorrespondingDPWMoutputisdrivenlowonthevoltagerailwiththefault.
3.
EachCurrentSenseinputtotheUCD9222isalsomonitoredbythe12-bitADC.
EachmeasuredvalueisscaledusingtheIOUT_CAL_GAINandIOUT_CAL_OFFSETcommandsandthenpassedthroughadigitalsmoothingfilter.
ThesmoothedcurrentmeasurementsarecomparedtofaultandwarninglimitssetbytheIOUT_OC_FAULT_LIMITandIOUT_OC_WARN_LIMITcommands.
TheactiontakenwhenanOCfaultisdetectedisdefinedbytheIOUT_OC_FAULT_RESPONSEcommand.
Becausethecurrentmeasurementisaveragedwithasmoothingfilter,theresponsetimetoanover-currentconditiondependsonacombinationofthetimeconstant(τ)fromTable7,therecentmeasurementhistory,andhowmuchthemeasuredvalueexceedstheover-currentlimit.
Whenthecurrentstepsfromacurrent(I1)thatislessthanthelimittoahighercurrent(I2)thatisgreaterthanthelimit,theoutputofthesmoothingfilteris(10)AtthepointwhenIsmoothedexceedsthelimit,thesmoothingfilterlagstime,tlagis(11)Theworstcaseresponsetimetoanover-currentconditionisthesumofthesamplinginterval(Table7)andthesmoothingfilterlag,tlagfromEquation11.
CurrentFoldbackModeWhenthemeasuredoutputcurrentexceedsthevaluespecifiedbytheIOUT_OC_FAULT_LIMITcommand,theUCD9222attemptstocontinuetooperatebyreducingtheoutputvoltageinordertomaintaintheoutputcurrentatthevaluesetbyIOUT_OC_FAULT_LIMIT.
ThiscontinuesindefinitelyaslongastheoutputvoltageremainsabovetheminimumvaluespecifiedbyIOUT_OC_LV_FAULT_LIMIT.
Iftheoutputvoltageispulleddowntolessthanthatvalue,thedevicerespondsasprogrammedbytheIOUT_OC_LV_FAULT_RESPONSEcommand.
InputVoltageMonitoringTheVinMonpinontheUCD9222monitorstheinputvoltage.
TheVinMonpinismonitoredusingtheinternal12-bitADCwhichhasadynamicrangeof0to2.
5V.
ThefaultthresholdsfortheinputvoltagearesetusingtheVIN_OV_FAULT_LIMITandVIN_UV_FAULT_LIMITcommands.
ThescalingforVinissetusingtheVIN_SCALE_MONITORcommand.
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comInputUVLockoutTheinputsupplylock-outvoltagethresholdsareconfiguredwiththeVIN_ONandVIN_OFFcommands.
WheninputsupplyvoltagedropsbelowthevaluesetbyVIN_OFF,thedevicestartsanormalsoftstopramp.
WhentheinputsupplyvoltagedropsbelowthevoltagesetbyVIN_UV_FAULT_LIMIT,thedeviceperformsasconfiguredbytheVIN_UV_FAULT_RESPONSEcommand.
Forexample,whenthebiassupplyforthecontrollerisderivedfromanothersource,theresponsecodecanbesetto"Continue"or"Continuewithdelay,"andthecontrollerattemptstofinishthesoftstopramp.
Ifthebiasvoltagesforthecontrollerandgatedriverareuncertainbelowsomevoltage,theusercansettheUVfaultlimittothatvoltageandspecifytheresponsecodetobe"shutdownimmediately,"disablingallDPWMoutputs.
VIN_OFFsetsthevoltageatwhichtheoutputvoltagesoft-stoprampisinitiated,andVIN_UV_FAULT_LIMITsetsthevoltagewherepowerconversionisstopped.
TemperatureMonitoringTheUCD9222monitorstemperatureusingthe12-bitADC.
TheADC12isreadevery100usandcombinedintoarunningsum.
Attheendofeach100msmonitoringinterval,the~1000sampleintherunningsumareaveragedtogetherandtherunningsumisrestarted.
Theseaveragedvaluesareusedtocalculatethetemperaturefromexternaltemperaturesensors.
ThesesamevaluesmaybereaddirectlyusingtheREAD_AUX_ADCSPMBuscommand.
Theaveragedvaluesarepassedthroughanadditionaldigitalsmoothingfiltertofurtherreducethechanceofreportingfalseover-temperatureevents.
Thesmoothingfilterhasatimeconstantof1.
55seconds.
AuxiliaryADCInputMonitoringUnusedexternaltemperaturesensorinputsmaybeusedforgeneral-purposeanalogmonitoring.
TheREAD_AUX_ADCSPMBuscommandreturnsablockoffour16-bitvalues,eachofwhichistheaverageofmultiplerawmeasurementsfromtheAuxADCinputs.
TheseAuxADCinputsshareusagewithothersignalssuchasTemp1,Temp2,Vtrack,andIinMon.
Avalueof0correspondsto0.
00Vandavalueof65535correspondsto2.
50V.
UnlikemanyothervariablesthatcanbemonitoredviaPMBus,nomechanismisprovidedforadjustingthegainoroffsetoftheAuxADCmeasurements.
WhenusingthetemperaturesensorinputsasAuxiliaryADCs,thetemperaturewarningandfaultsshouldbedisabledtopreventshut-downsduetonon-existentover-temperatureconditions.
SoftStart,SoftStopRampSequenceTheUCD9222performssoftstartandsoftstoprampsunderclosed-loopcontrol.
Performingastartorstopramportrackingisconsideredaseparateoperationalmode.
Theotheroperationalmodesarenormalregulationandlightloadregulation.
Eachoperationalmodecanbeconfiguredtohaveanindependentloopgainandcompensation.
Eachsetofloopgaincoefficientsiscalleda"bank"andisconfiguredusingtheCLA_GAINSPMBuscommand.
StartrampsareperformedbywaitingfortheconfiguredstartdelayTON_DELAYandthenrampingtheinternalreferencetowardthecommandedreferencevoltageattheratespecifiedbytheTON_RISEtimeandVOUT_COMMAND.
TheDPWMoutputsareenabledwhentheinternalrampreferenceequalsthepreexistingvoltage(pre-bias)ontheoutputandthecalculatedDPWMpulsewidthexceedsthepulsewidthspecifiedbyDRIVER_MIN_PULSE.
Thisensuresthataconstantramprateismaintained,andthattherampiscompletedatthesametimeitwouldbeiftherehadnotbeenapre-biascondition.
Figure16showstheoperationofsoft-startrampsandsoft-stopramps.
26SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
ti.
comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011Figure16.
StartandStopRampsWhenavoltagerailisinitsidlestate,theDPWMoutputsaredisabled,andthedifferentialvoltageontheEAP/EANpinsaremonitoredbythecontroller.
DuringidletheVrefDACisadjustedtomatchthefeedbackvoltage.
Ifthereisapre-bias(thatis,anon-zerovoltageontheregulatedoutput),thenthedevicecanbeginthestartrampfromthatvoltagewithaminimumofdisturbance.
Thisisdonebycalculatingthedutycyclethatisrequiredtomatchthemeasuredvoltageontherail.
NominallythisiscalculatedasVout/Vin.
Ifthepre-biasvoltageontheoutputrequiresasmallerpulsewidththanthedrivercandeliver,asdefinedbytheDRIVER_MIN_PULSEPMBuscommand,thenthestartrampisdelayeduntiltheinternalrampreferencevoltagehasincreasedtothepointwheretherequireddutycycleexceedsthespecifiedminimumduty.
Onceasoftstart/stopramphasbegun,theoutputiscontrolledbyadjustingtheVrefDACatafixedrateandallowingthedigitalcompensatorcontrolenginetogenerateadutycyclebasedontheerror.
TheVrefDACadjustmentsaremadeatarateof10kHzandarebasedontheTON_RISEorTOFF_FALLPMBusconfigurationparameters.
Althoughthepresenceofapre-biasvoltageoraspecifiedminimumDPWMpulsewidthaffectsthetimewhentheDPWMsignalsbecomeactive,thetimefromwhenthecontrollerstartsprocessingtheturn-oncommandtothetimewhenitreachesregulationisTON_DELAYplusTON_RISE,regardlessofthepre-biasorminimumdutycycle.
Duringanormalramp(i.
e.
notracking,nocurrentlimitingeventsandnoEADCsaturation),thesetpointslewsatapre-calculatedratebasedonthecommandedoutputvoltageandTON_RISE.
Underclosedloopcontrol,thecompensatorfollowsthisrampuptotheregulationpoint.
BecausetheEADCinthecontrollerhasalimitedrange,itmaysaturateduetoalargetransientduringastart/stopramp.
Ifthisoccurs,thecontrolleroverridesthecalculatedsetpointrampvalue,andadjuststheVrefDACinthedirectiontominimizetheerror.
ItcontinuestosteptheVrefDACinthisdirectionuntiltheEADCcomesoutofsaturation.
Onceitisoutofsaturation,thestartrampcontinues,butfromthisnewsetpointvoltage;andtherefore,hasanimpactontheramptime.
Non-volatileMemoryErrorCorrectionCodingTheUCD9222usesErrorCorrectingCode(ECC)toimprovedataintegrityandprovidehighreliabilitystorageofDataFlashcontents.
ECCusesdedicatedhardwaretogenerateextracheckbitsfortheuserdataasitiswrittenintotheFlashmemory.
Thisaddsanadditionalsixbitstoeach32-bitmemorywordstoredintotheFlasharray.
Theseextracheckbits,alongwiththehardwareECCalgorithm,allowforanysinglebiterrortobedetectedandcorrectedwhentheDataFlashisread.
2010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback27ProductFolderLink(s):UCD9222UCD9222SLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011www.
ti.
comAPPLICATIONINFORMATIONAutomaticSystemIdentification(Auto-ID)Byusingdigitalcircuitstocreatethecontrolfunctionforaswitch-modepowersupply,additionalfeaturescanbeimplemented.
Oneofthosefeaturesisthemeasurementoftheopenloopgainandstabilitymarginofthepowersupplywithouttheuseofexternaltestequipment.
ThiscapabilityiscalledautomaticsystemidentificationorAuto-ID.
Toidentifythefrequencyresponse,theUCD9222internallysynthesizesasinewavesignalandinjectsitintotheloopattheVrefDAC.
Thissignalexcitesthesystem,andtheclosed-loopresponsetothatexcitationcanbemeasuredatanotherpointintheloop.
TheUCD9222measurestheresponsetotheexcitationattheoutputofthedigitalcompensator.
Fromtheclosed-loopresponse,theopen-looptransferfunctioniscalculated.
Theopen-looptransferfunctionmaybecalculatedfromtheclosed-loopresponse.
NotethatsincethecompensatorandDPWMaredigital,theirtransferfunctionsareknownexactlyandcanbedividedoutofthemeasuredopen-loopgain.
InthiswaytheUCD9222canaccuratelymeasurethepowerstage/loadplanttransferfunctioninsitu(inplace),onthefactoryfloororinanendequipmentapplicationandsendthemeasurementdatabacktoahostthroughthePMBusinterfacewithouttheneedforexternaltestequipment.
DetailsoftheAuto-IDPMBusmeasurementcommandscanbefoundintheUCD92xxPMBusCommandReference(SLUU337).
DataLoggingTheUCD9222maintainsadataloginnon-volatilememory.
Thislogtracksthepeakinternalandexternaltemperaturesensormeasurements,peakcurrentmeasurementsandfaulthistory.
ThePMBuscommandsanddataformatfortheDataLoggingcanbefoundintheUCD92xxPMBusCommandReference(SLUU337).
28SubmitDocumentationFeedback2010–2011,TexasInstrumentsIncorporatedProductFolderLink(s):UCD9222UCD9222www.
ti.
comSLVSAL7A–NOVEMBER2010–REVISEDFEBRUARY2011REVISIONHISTORYNote:Pagenumbersofthecurrentversionmaydifferfrompreviousversions.
ChangesfromOriginal(November2010)toRevisionAPageAdded"4-bit,6-bit,or8-bitVIDSupport"toTitleline1AddedTIDSPdevicenumbersto1stFeaturebullet1AddedsecondparagraphtoDESCRIPTIONsection1ChangedMaxoperatingtemperaturespec.
TAfrom110°Cto125°C2AddedVIDLockoutIntervalsection132010–2011,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29ProductFolderLink(s):UCD9222PACKAGEOPTIONADDENDUMwww.
ti.
com11-Apr-2013Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinishMSLPeakTemp(3)OpTemp(°C)Top-SideMarkings(4)SamplesUCD9222RGZRACTIVEVQFNRGZ482500Green(RoHS&noSb/Br)CUNIPDAULevel-3-260C-168HR-40to125UCD9222UCD9222RGZTACTIVEVQFNRGZ48250Green(RoHS&noSb/Br)CUNIPDAULevel-3-260C-168HR-40to125UCD9222(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
ti.
com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.
TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)MultipleTop-SideMarkingswillbeinsideparentheses.
OnlyoneTop-SideMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireTop-SideMarkingforthatdevice.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantUCD9222RGZRVQFNRGZ482500330.
016.
47.
37.
31.
112.
016.
0Q2UCD9222RGZTVQFNRGZ48250180.
016.
47.
37.
31.
112.
016.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com25-Mar-2015PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)UCD9222RGZRVQFNRGZ482500367.
0367.
038.
0UCD9222RGZTVQFNRGZ48250210.
0185.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
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