XC2V8000not

AlgorithmIterationsBandwidthefficiencyMNDvDcEdgesCPUsVPUsTotalMakeModelNumber[49]A54Mbps(3,6)-regularFPGALDPCdecoderZhangT.
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K.
200246089216Reg3Reg627648Uni*556Semiparallel1836541XilinxVirtexEXCV2600E-1827M*54M1179215933235840.
6755851593310105235840.
42846815933*90360*1.
851.
65890.
50NoneOnecodepresented,pickedfrom"asemi-random(3,k)-regularLDPCcodeensemble"[51]AFPGAandASICimplementationofrate1/2,8088-birregularlowdensityparitycheckdecoderChenY.
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200340448088---Uni644Semiparallel--241XilinxVirtex2XC2V8000ff1152Log-BP2540M80M*-72621--726216779--72621*32576*--0.
50NoneOnecodepresented,but"thedecodercouldbeextendedtovariouscoderateandblocksizes".
CodeisQC.
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R.
20047681536Reg3Reg64608Uni5121Semiparallel48961441XilinxVirtex23000Modifiedmin-sum2063.
5M*127M1135220374227040.
89737520374-22704-20374*661188*2.
792.
59890.
50NoneDesign-timeconfigurableforany(3,6)-regularQCcodewithblocklengthN=6*2^s(s=integer)[63]DesignofirregularLDPCcodeconasinglechipFPGAPeiY.
,YinL.
,LuJ.
200430486096Irr2.
6Irr6.
53--64Semiparallel2448721XilinxVirtexEXCV3200E-2432M*64M663512303132700.
927129123031562132700.
11770912303*205820*--0.
50NoneDesign-timeconfigurableforirregularQCcodes,withsub-blocksizeL=(2^p-1)wherepisaprimenumber[47]FPGAbasedimplementationofdecoderforarraylow-densityparity-checkcodesBhagawatP.
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20055191038Reg3Reg63114Uni*426.
3Semiparallel3691XilinxVirtexEXCV2000E-1836M*72M1088319419217660.
892171194193598217660.
16530419419*120480*--0.
50NoneOneALDPCcodepresented,but"canbeeasilychangedtoaccommodateadifferentsetof[ALDPC]parameters"[59]AnFPGAimplementationofastructuredirregularLDPCdecoderCaoZ.
,KangJ.
,FanP.
200515523104---Non698Semiparallel1632481AlteraCyclone2EP2C70F672C7Beliefpropagation3026M*52M33043-33043---33043-330431041.
481.
28890.
50NoneSpecifictooneQCcode,flexibilitynotdiscussed[48]-1Partially-parallelLDPCdecoderbasedonhigh-efficiencymessage-passingalgorithm-7ITERATIONSShimizuK.
,IshikawaT.
,TogawaN.
,IkenagaT.
,GotoS.
20057681536Reg3Reg64608Uni*8100Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Min-sum75.
88M*11.
8M**1296178525920.
6886571785135825920.
523921785*1021836*3.
36***3.
16890.
5NoneNotmentioned.
OneQCcodeimplemented.
CalculatedfromN,iterations,fandTiter[48]-2Partially-parallelLDPCdecoderbasedonhigh-efficiencymessage-passingalgorithm-20ITERATIONSShimizuK.
,IshikawaT.
,TogawaN.
,IkenagaT.
,GotoS.
20057681536Reg3Reg64608Uni*8100Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Min-sum202.
11M*4.
23M**1296178525920.
6886571785135825920.
523921785*1021836*2.
98***2.
78890.
5NoneNotmentioned.
OneQCcodeimplemented.
CalculatedfromN,iterations,fandTiter[78]Reducedcomplexity,FPGAimplementationofquasi-cyclicLDPCdecoderSpagnolC.
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,PopoviciE.
2005Uni*427Semiparallel---1XilinxVirtexEXCV2000-6--994168919880.
8495981689-1988-1689*2496*---NoneOneQCcodepresented,butarchitectureis"easilyadaptableforaclassofQCcodes"withspecificH((3,6)-regular)[76]-1EPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-MSALGORITHM-ECChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Uni891.
8*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Min-sum204.
59M*9.
18M**1167206623340.
885176206666423340.
284492066*36648*2.
952.
75890.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Throughputderivedfor20iterations.
Clockspeedgivenas1/criticalpathdelay.
[76]-1TPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-MSALGORITHM-TPChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Uni891.
8*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Min-sum330.
6M*61.
2M1167206623340.
885176206666423340.
284492066*36648*--0.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Clockspeedgivenas1/criticalpathdelay.
Avg.
iterationsandthroughputatSNR=4.
5dB[76]-2EPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-SP834bu,INTRAPIPELINE-ECChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Uni884*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Balancedsum-product204.
3M*8.
59M**2166390143320.
900508390177843320.
1795943901*36648*2.
372.
17890.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Throughputderivedfor20iterations.
Clockspeedgivenas1/criticalpathdelay.
[76]-2TPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-SP834bu,INTRAPIPELINE-TPChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Uni884*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Balancedsum-product3.
226.
8M*53.
7M2166390143320.
900508390177843320.
1795943901*36648*--0.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Clockspeedgivenas1/criticalpathdelay.
Avg.
iterationsandthroughputatSNR=4.
5dB[76]-3EPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-SP834bu,COMB.
PIPELINE-ECChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Uni879.
1*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Balancedsum-product204.
04M*8.
08M**1919340338380.
886663403114138380.
297293403*36648*2.
372.
17890.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Throughputderivedfor20iterations.
Clockspeedgivenas1/criticalpathdelay.
[76]-3TPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-SP834bu,COMB.
PIPELINE-TPChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Uni879.
1*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Balancedsum-product3.
225.
2M*50.
5M1919340338380.
886663403114138380.
297293403*36648*--0.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Clockspeedgivenas1/criticalpathdelay.
Avg.
iterationsandthroughputatSNR=4.
5dB[76]-4EPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-SP833bnu-ECChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Non880.
5*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Balancedsum-product204.
21M*8.
42M**2808490856160.
8739324908124056160.
2207984908*36648*2.
962.
76890.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Throughputderivedfor20iterations.
Clockspeedgivenas1/criticalpathdelay.
[76]-4TPartlyparalleloverlappedsum-productdecoderarchitecturesforquasi-cyclicLDPCcodes-SP833bnu-TPChenN.
,DaiY.
,YanZ.
20067681536Reg3Reg64608Non880.
5*Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Balancedsum-product3.
325.
5M*51M2808490856160.
8739324908124056160.
2207984908*36648*--0.
50NoneNotdiscussed,butarchitecturepresentedingeneralterms.
OneQCcodeimplemented.
Clockspeedgivenas1/criticalpathdelay.
Avg.
iterationsandthroughputatSNR=4.
5dB[41]A170Mbps(8176,7156)quasi-cyclicLDPCdecoderimplementationwithFPGACuiZ.
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200610228176Reg4Reg3232704Non6193Semiparallel432361XilinxVirtex26000Modifiedsum-product(balanced)15172M197M*2746036848549200.
670943684838266549200.
69675938266*1282304*3.
780.
869350.
88NoneOnecodepresented,but"suitedforotherQC-LDPCcodesaswell".
[42]Abit-serialapproximatemin-sumLDPCdecoderandFPGAimplementationDarabihaA.
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C.
,KschischangF.
R.
2006125480---Uni*361Fullyparallel1254806052AlteraStratixEP1S80Min-sumwithsimplifiedcheckupdatefunction15481M*650M66588-66588---66588-66588--4.
693.
13430.
74NoneNotmentioned.
One"RS-based"codeimplemented.
[80]Themoderate-throughputandmemory-efficientLDPCdecoderXiongL.
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,YaoD.
2006298980Irr2.
89Irr9.
52831Uni6136Serial1121AlteraCycloneEP1C6Improvedbeliefpropagation-997-997---997-997-33.
24.
4**3.
13230.
70NoneNotmentioned.
Onecodeimplemented.
MaxIteronlydiscussedforBERsimulation.
[54]AhighspeedlowmemoryFPGAbasedLDPCdecoderarchitectureforquasi-cyclicLDPCcodesSaundersP.
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D.
200617283200---Uni*5180Semiparallel--321XilinxVirtex4XC4VLX2512FF668Modifiedturbodecodingalgorithm10103M*223M694610743138920.
77332310743-13892-10743*16288*2.
332.
32190.
46NoneOnecodepresented,butarchitecturecandecode"codesofvaryingcoderatesandlengthseachexhibitingthequasi-cyclicstructure"[58]AnFPGAimplementationofarrayLDPCdecoderShaJ.
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20061882209Reg4Reg478836Uni*650Semiparallel188472351AlteraStratixEP1S30Modifiedmin-sum20108M*118M2353523535235351235356405235350.
27214823535*-25.
95.
12**1.
58290.
92NoneSpecifictooneALDPCcode,flexibilitynotdiscussed[61]-1CodeconstructionandFPGAimplementationofalow-error-floormulti-ratelow-densityparity-checkcodedecoder-1/2RATECODEYangL.
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J.
R.
200641589036Irr3.
25Irr6.
527027Uni6100Semiparallel1836541XilinxVirtex2XC2V8000Min-sumwithcorrection60*15M30M*3412753327682540.
7813025332724570682540.
35997953327*1021836*1.
17*0.
978930.
503specificPCMswithdifferentratesbutsimilarblocksizesRuntimeconfigurableforthreedifferentcoderates(similarblocksizes).
UsesspecificQCcodes.
[61]-2CodeconstructionandFPGAimplementationofalow-error-floormulti-ratelow-densityparity-checkcodedecoder-5/8RATECODEYangL.
,LiuH.
,ShiC.
J.
R.
200635769536Reg3Reg828608Uni6100Semiparallel1232441XilinxVirtex2XC2V8000Min-sumwithcorrection24*40M64M*3412753327682540.
7813025332724570682540.
35997953327*1021836*2.
01*1.
16270.
633specificPCMswithdifferentratesbutsimilarblocksizesRuntimeconfigurableforthreedifferentcoderates(similarblocksizes).
UsesspecificQCcodes.
[61]-3CodeconstructionandFPGAimplementationofalow-error-floormulti-ratelow-densityparity-checkcodedecoder-7/8RATECODEYangL.
,LiuH.
,ShiC.
J.
R.
200612249792Reg3Reg2429376Uni6100Semiparallel324271XilinxVirtex2XC2V8000Min-sumwithcorrection24*40M45.
7M*3412753327682540.
7813025332724570682540.
35997953327*1021836*3.
93*1.
01930.
883specificPCMswithdifferentratesbutsimilarblocksizesRuntimeconfigurableforthreedifferentcoderates(similarblocksizes).
UsesspecificQCcodes.
[72]Investigationoferrorfloorsofstructuredlow-densityparity-checkcodesbyhardwareemulationZhangZ.
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20063842048Reg6Reg3212288Uni6100Semiparallel132331XilinxVirtex2ProXC2VP50Messagepassingalgorithm1019.
5M*24M**73203780146400.
258197378013658146400.
93292313658*1292322*4.
07***1.
93630.
81NoneDesign-timeconfigurableforanycodewith"paritycheckmatricescomposedofpermutationsubmatrices"Throughputgivenis240Mfor1iteration[55]AhighthroughputH-QCLDPCdecoderChienY.
-H.
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-K.
20076144#####Reg3Reg636864Uni696Semiparallel961922881AlteraStratix2EP2S130Min-Sum15149M*298M55491-110982---110982-91988**-300.
01.
481.
28890.
50NoneAnyQCcode[64]-1FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=16200,R=1/5,45FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
200712960#####Irr3.
00Irr3.
7548600-70.
8Semiparallel--451XilinxVirtex2ProXC2VP100-15*14.
4M*71.
8M1190622048238120.
92592220485292238120.
22224122048*1783204*--0.
2All63HsinDVB-S2standard.
[64]-2FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=16200,R=1/5,90FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
200712960#####Irr3.
00Irr3.
7548600-74Semiparallel--901XilinxVirtex2ProXC2VP100-15*29.
6M*148M2204840568440960.
919993405689701440960.
21999740568*1953510*--0.
2All63HsinDVB-S2standard.
[64]-3FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=16200,R=1/5,180FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
200712960#####Irr3.
00Irr3.
7548600-73.
2Semiparallel--1801XilinxVirtex2ProXC2VP100-15*60.
2M*301M3880470554776080.
9091077055420284776080.
26136570554*2223996*--0.
2All63HsinDVB-S2standard.
[64]-4FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=16200,R=7/9,45FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
20073600#####Irr2.
78Irr12.
545000-70.
8Semiparallel--451XilinxVirtex2ProXC2VP100-15*36.
3M*46.
7M1190622048238120.
92592220485292238120.
22224122048*1783204*--0.
78All63HsinDVB-S2standard.
[64]-5FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=16200,R=7/9,90FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
20073600#####Irr2.
78Irr12.
545000-74Semiparallel--901XilinxVirtex2ProXC2VP100-15*75.
6M*97.
2M2204840568440960.
919993405689701440960.
21999740568*1953510*--0.
78All63HsinDVB-S2standard.
[64]-6FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=16200,R=7/9,180FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
20073600#####Irr2.
78Irr12.
545000-73.
2Semiparallel--1801XilinxVirtex2ProXC2VP100-15*149M*191M3880470554776080.
9091077055420284776080.
26136570554*2223996*--0.
78All63HsinDVB-S2standard.
[64]-7FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=64800,R=3/5,45FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
200725920#####Irr4.
40Reg11285120-70.
8Semiparallel--451XilinxVirtex2ProXC2VP100-15*17.
1M*28.
5M1190622048238120.
92592220485292238120.
22224122048*1783204*--0.
6All63HsinDVB-S2standard.
[64]-8FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=64800,R=3/5,90FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
200725920#####Irr4.
40Reg11285120-74Semiparallel--901XilinxVirtex2ProXC2VP100-15*37.
1M*61.
9M2204840568440960.
919993405689701440960.
21999740568*1953510*--0.
6All63HsinDVB-S2standard.
[64]-9FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=64800,R=3/5,180FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
200725920#####Irr4.
40Reg11285120-73.
2Semiparallel--1801XilinxVirtex2ProXC2VP100-15*73.
2M*122M3880470554776080.
9091077055420284776080.
26136570554*2223996*--0.
6All63HsinDVB-S2standard.
[64]-10FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=64800,R=9/10,45FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
20076480#####Irr3.
00Reg30194400-70.
8Semiparallel--451XilinxVirtex2ProXC2VP100-15*34.
8M*38.
7M1190622048238120.
92592220485292238120.
22224122048*1783204*--0.
9All63HsinDVB-S2standard.
[64]-11FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=64800,R=9/10,90FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
20076480#####Irr3.
00Reg30194400-74Semiparallel--901XilinxVirtex2ProXC2VP100-15*71.
7M*79.
7M2204840568440960.
919993405689701440960.
21999740568*1953510*--0.
9All63HsinDVB-S2standard.
[64]-12FlexibleparallelarchitectureforDVB-S2LDPCdecoders-N=64800,R=9/10,180FUsGomesM.
,FalcaoG.
,SilvaV.
,FerreiraV.
,SengoA.
20076480#####Irr3.
00Reg30194400-73.
2Semiparallel--1801XilinxVirtex2ProXC2VP100-15*141M*157M3880470554776080.
9091077055420284776080.
26136570554*2223996*--0.
9All63HsinDVB-S2standard.
[69]-1EFPGAimplementationofLDPCdecodersbasedonjointrow-columndecodingalgorithm-40-PARALLEL-ECHeZ.
,RoyS.
,FortierP.
20076401920Irr3.
33Reg106400Uni8150Semiparallel--401XilinxVirtex4XC4VLX160Jointrow-columndecodingalgorithm50211M*320M**2.
291.
27950.
66NoneNotdiscussed,asfocusisonadecodingalgorithmthat"isapplicabletovariousLDPCcodes"includingrandom&QCThroughputderivedfor50iterations.
[69]-1TFPGAimplementationofLDPCdecodersbasedonjointrow-columndecodingalgorithm-40-PARALLEL-TPHeZ.
,RoyS.
,FortierP.
20076401920Irr3.
33Reg106400Uni8150Semiparallel--401XilinxVirtex4XC4VLX160Jointrow-columndecodingalgorithm81.
33G*2G0.
66NoneNotdiscussed,asfocusisonadecodingalgorithmthat"isapplicabletovariousLDPCcodes"includingrandom&QC[69]-2EFPGAimplementationofLDPCdecodersbasedonjointrow-columndecodingalgorithm-4-PARALLEL-ECHeZ.
,RoyS.
,FortierP.
20076401920Irr3.
33Reg106400Uni8150Semiparallel--41XilinxVirtex4XC4VLX160Jointrow-columndecodingalgorithm5023.
8M*36M**2.
291.
27950.
66NoneNotdiscussed,asfocusisonadecodingalgorithmthat"isapplicabletovariousLDPCcodes"includingrandom&QCThroughputderivedfor50iterations.
[69]-2TFPGAimplementationofLDPCdecodersbasedonjointrow-columndecodingalgorithm-4-PARALLEL-TPHeZ.
,RoyS.
,FortierP.
20076401920Irr3.
33Reg106400Uni8150Semiparallel--41XilinxVirtex4XC4VLX160Jointrow-columndecodingalgorithm8183M*225M0.
66NoneNotdiscussed,asfocusisonadecodingalgorithmthat"isapplicabletovariousLDPCcodes"includingrandom&QC[69]-3EFPGAimplementationofLDPCdecodersbasedonjointrow-columndecodingalgorithm-SERIAL-ECHeZ.
,RoyS.
,FortierP.
20076401920Irr3.
33Reg106400Uni8300Serial--11XilinxVirtex4XC4VLX160Jointrow-columndecodingalgorithm5011.
8M*17.
9M**2.
291.
27950.
66NoneNotdiscussed,asfocusisonadecodingalgorithmthat"isapplicabletovariousLDPCcodes"includingrandom&QCThroughputderivedfor50iterations.
[69]-3TFPGAimplementationofLDPCdecodersbasedonjointrow-columndecodingalgorithm-SERIAL-TPHeZ.
,RoyS.
,FortierP.
20076401920Irr3.
33Reg106400Uni8300Serial--11XilinxVirtex4XC4VLX160Jointrow-columndecodingalgorithm874.
6M*112M0.
66NoneNotdiscussed,asfocusisonadecodingalgorithmthat"isapplicabletovariousLDPCcodes"includingrandom&QC[45]Anarea-efficientFPGA-basedarchitectureforfully-parallelstochasticLDPCdecodingTehraniS.
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20075121024Reg3Reg63072NA212Fullyparallel512102415361XilinxVirtex4XC4VLX200StochasticNA353M*706M32875-65750---65750-54497**--2.
432.
23890.
50NoneNotmentioned.
Onecodeimplemented.
Stochasticbitstream,sodoesnotuseconventionaliterations.
[74]Multi-GbpsFPGA-basedlowdensityparitycheck(LDPC)decoderdesignZarubicaR.
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G.
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20076001200Reg3Reg63600Uni3100Fullyparallel600120018001XilinxVirtex4XC4VLX200Min-sum106G12G*4061369038812260.
849956903818945812260.
23323869038*--3.
763.
56890.
50NoneNotmentioned.
Onecodeimplemented.
[66]FPGAimplementationofaflexibledecoderforlongLDPCcodesBeuschelC.
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2008Uni874Semiparallel1616321XilinxVirtex4XC4LX160-11NormalizedBP-based155M**10M*18483-36966---36966-30639**2023636*--0.
50"AnyregularorirregularLDPCcode"subjecttosizeconstraintsSomeconstraints(egNmax)"75Mbpsperiteration",assumed15iterations.
[57]Anewpowerfulscalablegenericmulti-standardLDPCdecoderarchitectureCharotF.
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2008Uni*6160Semiparallel4481XilinxVirtex5XC5VLX110T-2021.
6M25.
9M*-19000--3800010000--38000*9211.
3--0.
83All114PCMsin802.
16(WiMax)Anystandard[75]-1Optimaloverlappedmessagepassingdecodingofquasi-cyclicLDPCcodes-OMPDaiY.
,YanZ.
,ChenN.
20087681536Reg3Reg64608Uni8149Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Min-sum349.
6M*99.
1M1616288732320.
8932552887107332320.
3319932887*36648*--0.
50NoneDesign-timeconfigurableforanyQCcode.
AvgiterationsandthroughputatSNR=4.
5dB[75]-2Optimaloverlappedmessagepassingdecodingofquasi-cyclicLDPCcodes-Non-OMPDaiY.
,YanZ.
,ChenN.
20087681536Reg3Reg64608Uni8147Semiparallel3691XilinxVirtex2XC2V6000-5ff1152Min-sum329.
4M*58.
8M1477264829540.
8964122648101229540.
3425862648*36648*--0.
50NoneDesign-timeconfigurableforanyQCcode.
AvgiterationsandthroughputatSNR=4.
5dB[60]-1AreconfigurableFPGAimplementationofanLDPCdecoderforunstructuredcodes-(4095,3358)CODEHosseiniS.
M.
E.
,ChanK.
S.
,GohW.
L.
20087374095Reg3Irr16.
712285Uni9-Serial1121XilinxVirtex2ProXC2VP30Min-sumwithcorrectionfactor10*729-1458---1458-1208**--3.
42**1.
18860.
82"AnykindofLDPCcoderegardlessofitsstructure"[60]-2AreconfigurableFPGAimplementationofanLDPCdecoderforunstructuredcodes-(4161,3430)CODEHosseiniS.
M.
E.
,ChanK.
S.
,GohW.
L.
20087314161Reg4Irr22.
816644Uni9-Serial1121XilinxVirtex2ProXC2VP30Min-sumwithcorrectionfactor10*729-1458---1458-1208**--3.
52**1.
28860.
82"AnykindofLDPCcoderegardlessofitsstructure"[60]-3AreconfigurableFPGAimplementationofanLDPCdecoderforunstructuredcodes-(4376,4094)CODEHosseiniS.
M.
E.
,ChanK.
S.
,GohW.
L.
20082824376Reg4Irr62.
117504Uni9-Serial1121XilinxVirtex2ProXC2VP30Min-sumwithcorrectionfactor10*729-1458---1458-1208**--5.
19**1.
24810.
94"AnykindofLDPCcoderegardlessofitsstructure"[17]-1ConfigurableLDPCdecoderarchitecturesforregularandirregularcodes-REGULARDECODERKarkootiM.
,RadosavljevicP.
,CavallaroJ.
R.
20087681536Reg3Reg64608Uni5211Semiparallel48961441XilinxVirtex4XC4VFX60Modifiedmin-sumwithscaling-397M794M*988118174197620.
919644181743455197620.
1748318174*661188*--0.
50NoneDesign-timeconfigurableforany(3,6)-regularQCcodewithblocklengthN=6*2^s(s=integer)[17]-2ConfigurableLDPCdecoderarchitecturesforregularandirregularcodes-IRREGULARDECODERKarkootiM.
,RadosavljevicP.
,CavallaroJ.
R.
20084321296Irr3.
67Reg114752Uni8160Semiparallel--811XilinxVirtex4XC4VFX60Modifiedmin-sumwithcorrectingoffset15*95M143M*1263319265252660.
7624871926513823252660.
54709919265*871566*2.
49*1.
40840.
67All12PCMsin802.
11n(Wifi)Can"beextendedtosupportothercodefamilies"UsesaverageiterationstomeetFERtargetof10^-4,numbersnotgiven.
[36]FullyparallelstochasticLDPCdecodersTehraniS.
S.
,MannorS.
,GrossW.
J.
20085281056Irr3.
17Irr6.
333344NA222Fullyparallel528105615841XilinxVirtex4XC4VLX200-11FF1513StochasticNA348M*697M**4609768163921940.
7393436816344502921940.
482768163*--2.
452.
25890.
50NoneNotdiscussed.
Onecodeimplemented(from802.
16e),buttechniquepossiblyapplicabletoanycodeReadfromgraphatsameEb/N0asECresults.
Stochasticbitstream,sodoesnotuseconventionaliterations.
[65]FPGAbasedlow-complexityhigh-throughputtri-modedecoderforquasi-cyclicLDPCcodesChenX.
,HuangQ.
,LinS.
,AkellaV.
200940954095Reg64Reg64262080Uni1191Semiparallel65651302XilinxVirtexEXC4VLX160Softreliability-basediterativemajoritylogicdecoding51.
56G*1.
9G12857-25714---25714-21313**153612*4.
362.
12860.
82NoneArchitecturefocusesononecode,but"theproposedtechniquesaregeneralenoughtohandleanyquasi-cycliccode"[52]-1AgenericarchitectureofCCSDSlowdensityparitycheckdecoderfornear-earthapplications-LOW-COSTDECODER,10ITERsDemangelF.
,FauN.
,DrabikN.
,CharotF.
,WolinskiC.
200910228176Reg4Reg3232704-200Semiparallel216181AlteraCyclone2EP2C50FBeliefpropagation-basedalgorithm10130M149M*-8000--80006000--8000*-283.
2--0.
88None1code[52]-2AgenericarchitectureofCCSDSlowdensityparitycheckdecoderfornear-earthapplications-LOW-COSTDECODER,18ITERsDemangelF.
,FauN.
,DrabikN.
,CharotF.
,WolinskiC.
200910228176Reg4Reg3232704-200Semiparallel216181AlteraCyclone2EP2C50FBeliefpropagation-basedalgorithm1870M80M*-8000--80006000--8000*-283.
23.
80.
889350.
88None1code[52]-3AgenericarchitectureofCCSDSlowdensityparitycheckdecoderfornear-earthapplications-LOW-COSTDECODER,50ITERsDemangelF.
,FauN.
,DrabikN.
,CharotF.
,WolinskiC.
200910228176Reg4Reg3232704-200Semiparallel216181AlteraCyclone2EP2C50FBeliefpropagation-basedalgorithm5025M28.
6M*-8000--80006000--8000*-283.
23.
730.
819350.
88None1code[52]-4AgenericarchitectureofCCSDSlowdensityparitycheckdecoderfornear-earthapplications-HIGH-SPEEDDECODER,10ITERsDemangelF.
,FauN.
,DrabikN.
,CharotF.
,WolinskiC.
200910228176Reg4Reg3232704-200Semiparallel216181AlteraStratix2EP2S180Beliefpropagation-basedalgorithm101.
02G1.
17G*-38000--3800030000--38000*-1300--0.
88None1code[52]-5AgenericarchitectureofCCSDSlowdensityparitycheckdecoderfornear-earthapplications-HIGH-SPEEDDECODER,18ITERsDemangelF.
,FauN.
,DrabikN.
,CharotF.
,WolinskiC.
200910228176Reg4Reg3232704-200Semiparallel216181AlteraStratix2EP2S180Beliefpropagation-basedalgorithm18560M640M*-38000--3800030000--38000*-13003.
80.
889350.
88None1code[52]-6AgenericarchitectureofCCSDSlowdensityparitycheckdecoderfornear-earthapplications-HIGH-SPEEDDECODER,50ITERsDemangelF.
,FauN.
,DrabikN.
,CharotF.
,WolinskiC.
200910228176Reg4Reg3232704-200Semiparallel216181AlteraStratix2EP2S180Beliefpropagation-basedalgorithm50200M229M*-38000--3800030000--38000*-13003.
730.
819350.
88None1code[62]-1DesignandimplementationforHighSpeedLDPCDecoderwithlayereddecoding-1DECODERDingH.
,YangS.
,LuoW.
,DongM.
200923041152---Uni*7155Semiparallel--121AlteraStratix2EP2S180Min-Sum8233M465M*-17259--172596598--17259*-264.
81.
941.
74890.
50None1code[62]-2DesignandimplementationforHighSpeedLDPCDecoderwithlayereddecoding-4DECODERSDingH.
,YangS.
,LuoW.
,DongM.
200923041152---Uni*7128Semiparallel--124AlteraStratix2EP2S180Min-Sum8768M1.
54G*-69112--6911226392--69112*-1059.
01.
941.
74890.
50None1code[43]FPGAimplementationofnonbinaryquasi-cyclicLDPCdecoderbasedonEMSalgorithmSunY.
,ZhangY.
,HuJ.
,ZhangZ.
2009486972Irr2.
5Reg52430-131Semiparallel315181XilinxVirtex4XC4VLX160Extendedmin-sum(nonbinary)2050M100M*4619087783923800.
9502388778334908923800.
37787487783*1382484*2.
492.
29890.
50NoneNotmentioned.
Onenon-binaryQCcodeimplemented.
[68]-1EFPGAimplementationofhighperformanceLDPCdecoderusingmodified2-bitmin-sumalgorithm-1200-BITCODE-ECChandrasettyV.
A.
,AzizS.
M.
20106001200Reg3Reg63600Uni2123Fullyparallel600120018001XilinxVirtex4XC4VLX200Modified2-bitmin-sumalgorithm8.
9**8.
3G**16.
6G*3334558053666900.
870495805315691666900.
23528358053*--3.
383.
18890.
50NoneNotdiscussed,probablybecausefocusisonadecodingalgorithmmorethananarchitecture-couldworkforanycodeIterationsandthroughputderivedforsameEb/N0asECresults[68]-1TFPGAimplementationofhighperformanceLDPCdecoderusingmodified2-bitmin-sumalgorithm-1200-BITCODE-TPChandrasettyV.
A.
,AzizS.
M.
20106001200Reg3Reg63600Uni2123Fullyparallel600120018001XilinxVirtex4XC4VLX200Modified2-bitmin-sumalgorithm7.
210.
2G20.
4G*3334558053666900.
870495805315691666900.
23528358053*0.
50NoneNotdiscussed,probablybecausefocusisonadecodingalgorithmmorethananarchitecture-couldworkforanycodeAvgiterationsandthroughputforEb/N0=4dB[68]-2EFPGAimplementationofhighperformanceLDPCdecoderusingmodified2-bitmin-sumalgorithm-648-BITCODE-ECChandrasettyV.
A.
,AzizS.
M.
2010324648Reg3Reg61944Uni2113Fullyparallel3246489721XilinxVirtex5XC5VLX110TModified2-bitmin-sumalgorithm8.
4**4.
33G**8.
67G*775522014310200.
709671440288555310200.
2757944028*--3.
643.
44890.
50NoneNotdiscussed,probablybecausefocusisonadecodingalgorithmmorethananarchitecture-couldworkforanycodeIterationsandthroughputderivedforsameEb/N0asECresults[68]-2TFPGAimplementationofhighperformanceLDPCdecoderusingmodified2-bitmin-sumalgorithm-648-BITCODE-TPChandrasettyV.
A.
,AzizS.
M.
2010324648Reg3Reg61944Uni2113Fullyparallel3246489721XilinxVirtex5XC5VLX110TModified2-bitmin-sumalgorithm6.
85.
4G10.
8G*775522014310200.
709671440288555310200.
2757944028*0.
50NoneNotdiscussed,probablybecausefocusisonadecodingalgorithmmorethananarchitecture-couldworkforanycodeAvgiterationsandthroughputforEb/N0=4.
25dB[50]-1AconfigurableFPGAimplementationofPEG-basedPS-LDPCdecoder-(1152,3,8)CODEWangK.
,LiuN.
,SunB.
,SunH.
20104321152Reg3Reg83456Uni5119Semiparallel4321445761AlteraStratix2EP2S60F484C3Min-sum16**484M**774M*-36195--3619520777--36195*-16.
02.
952.
10270.
63NoneDesign-timeconfigurablefor"PS-LDPC"codesGivenas2.
422Gbps,butincludesfactorqn=5.
Iterationscalculatedfromthroughputequation°rees[50]-2AconfigurableFPGAimplementationofPEG-basedPS-LDPCdecoder-(1152,3,9)CODEWangK.
,LiuN.
,SunB.
,SunH.
20103841152Reg3Reg93456Uni5118Semiparallel3841285121AlteraStratix2EP2S60F484C3Min-sum16**471M**707M*-33543--3354318480--33543*-16.
13.
332.
24840.
67NoneDesign-timeconfigurablefor"PS-LDPC"codesGivenas2.
353Gbps,butincludesfactorqn=5.
Iterationscalculatedfromthroughputequation°rees[50]-3AconfigurableFPGAimplementationofPEG-basedPS-LDPCdecoder-(1440,3,10)CODEWangK.
,LiuN.
,SunB.
,SunH.
20104321440Reg3Reg104320Uni4138Semiparallel4321445761AlteraStratix2EP2S60F484C3Min-sum16**668M**954M*-31638--3163818034--31638*-14.
13.
412.
14230.
70NoneDesign-timeconfigurablefor"PS-LDPC"codesGivenas2.
672Gbps,butincludesfactorqn=4.
Iterationscalculatedfromthroughputequation°rees[70]FPGAimplementationofrate-compatibleQC-LDPCcodedecoderBladA.
,GustafssonO.
2011Uni8100Semiparallel--271AlteraCyclone2EP2C70Min-sumwithchecknodemerging-175M*350M-7727--772713529--13529*-67.
6--0.
50Withina"rate-compatible"codefamilyTestedon802.
16e&802.
11n,butworks"withcodesobtainedthroughothermeans"[56]-1Amulti-levelhierarchicalquasi-cyclicmatrixforimplementationofflexiblepartially-parallelLDPCdecoders-576BITCODEChandrasettyV.
A.
,AzizS.
M.
2011288576Reg3Reg61728Uni264Semiparallel1616321XilinxVirtex2XC2V8000-5FF1152ModifiedMin-Sum7.
2**42.
7M**85.
3M*2778518855560.
933765518885755560.
1542485188*299.
56**3.
543.
34890.
503codesin802.
16WiMaxAnyQCcode.
IterationsandthroughputderivedforsameEb/N0asECresults[56]-2Amulti-levelhierarchicalquasi-cyclicmatrixforimplementationofflexiblepartially-parallelLDPCdecoders-1152BITCODEChandrasettyV.
A.
,AzizS.
M.
20115761152Reg3Reg63456Uni264Semiparallel1616321XilinxVirtex2XC2V8000-5FF1152ModifiedMin-Sum8.
5**38M**76.
1M*2778518855560.
933765518885755560.
1542485188*2919.
1**3.
273.
07890.
503codesin802.
16WiMaxAnyQCcode.
IterationsandthroughputderivedforsameEb/N0asECresults[56]-3Amulti-levelhierarchicalquasi-cyclicmatrixforimplementationofflexiblepartially-parallelLDPCdecoders-2304BITCODEChandrasettyV.
A.
,AzizS.
M.
201111522304Reg3Reg66912Uni264Semiparallel1616321XilinxVirtex2XC2V8000-5FF1152ModifiedMin-Sum9.
5**35M**69.
9M*2778518855560.
933765518885755560.
1542485188*2938.
3**3.
072.
87890.
503codesin802.
16WiMaxAnyQCcode.
IterationsandthroughputderivedforsameEb/N0asECresults[73]-1MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(1536,768)CODEVECTORISATIONK=1ChenX.
,KangJ.
,LinS.
,AkellaV.
20117681536Reg3Reg64608Uni8162Semiparallel3691XilinxVirtex2XC2V6000-5Min-sum3114M*229M1472244929440.
8318612449217829440.
739812449*24432*--0.
50NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
AvgiterationsatEb/N0=4.
5dB[73]-2MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(1536,768)CODEVECTORISATIONK=4ChenX.
,KangJ.
,LinS.
,AkellaV.
20117681536Reg3Reg64608Uni8150Semiparallel1224361XilinxVirtex2XC2V6000-5Min-sum3415M*831M61029698122040.
79465796989263122040.
7590139698*24432*--0.
50NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
AvgiterationsatEb/N0=4.
5dB[73]-3MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(3969,3213)CODEVECTORISATIONK=1ChenX.
,KangJ.
,LinS.
,AkellaV.
20117563969Irr4.
24Irr22.
316821Uni6226Semiparallel---1XilinxVirtex4XC4VLX-200Normalizedmin-sum15372M*460M1463625836292720.
8826182583621509292720.
73479825836*3305940*--0.
81NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[73]-4MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(3969,3213)CODEVECTORISATIONK=4ChenX.
,KangJ.
,LinS.
,AkellaV.
20117563969Irr4.
24Irr22.
316821Uni6196Semiparallel---1XilinxVirtex4XC4VLX-200Normalizedmin-sum151.
19G*1.
47G623621110351247240.
890246111035980031247240.
785759111035*3305940*--0.
81NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[73]-5MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(3969,3213)CODEFOLDINGF=2ChenX.
,KangJ.
,LinS.
,AkellaV.
20117563969Irr4.
24Irr22.
316821Uni6204Semiparallel---1XilinxVirtex4XC4VLX-160Normalizedmin-sum15168M*207M1260418208252080.
722311820818392252080.
7296118392*1662988*--0.
81NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[73]-6MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(3969,3213)CODEFOLDINGF=4ChenX.
,KangJ.
,LinS.
,AkellaV.
20117563969Irr4.
24Irr22.
316821Uni6200Semiparallel---1XilinxVirtex4XC4VLX-160Normalizedmin-sum1582.
4M*102M66799303133580.
696437930310029133580.
75078610029*831494*--0.
81NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[73]-7MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(8176,7156)CODEVECTORISATIONK=1ChenX.
,KangJ.
,LinS.
,AkellaV.
201110228176Reg4Reg3232704Uni6229Semiparallel432361XilinxVirtex4XC4VLX-160Normalizedmin-sum15171M*195M4021738580420.
9183047385590780420.
7345197385*801440*3.
760.
849350.
88NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
PaperclaimsHis2044x8176,butassumingthatisatypo.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[73]-8MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(8176,7156)CODEVECTORISATIONK=4ChenX.
,KangJ.
,LinS.
,AkellaV.
201110228176Reg4Reg3232704Uni6212Semiparallel161281441XilinxVirtex4XC4VLX-160Normalizedmin-sum15625M*714M1785727046357140.
7572942704627210357140.
76188627210*801440*3.
760.
849350.
88NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
PaperclaimsHis2044x8176,butassumingthatisatypo.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[73]-9MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(8176,7156)CODEFOLDINGF=2ChenX.
,KangJ.
,LinS.
,AkellaV.
201110228176Reg4Reg3232704Uni6201Semiparallel216181XilinxVirtex4XC4VLX-160Normalizedmin-sum1545.
3M*51.
8M2938542158760.
9225665421369158760.
6281485421*40720*3.
760.
849350.
88NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
PaperclaimsHis2044x8176,butassumingthatisatypo.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[73]-10MemorysystemoptimizationforFPGA-basedimplementationofquasi-cyclicLDPCcodesdecoders-(8176,7156)CODEFOLDINGF=4ChenX.
,KangJ.
,LinS.
,AkellaV.
201110228176Reg4Reg3232704Uni6196Semiparallel1891XilinxVirtex4XC4VLX-160Normalizedmin-sum1522.
1M*25.
3M1579290831580.
9208362908193831580.
613682908*20360*3.
760.
849350.
88NoneDesign-timeconfigurableforanyQCcode.
HDLauto-generatedbyPythonscriptbasedonQCHandFPGAresources.
PaperclaimsHis2044x8176,butassumingthatisatypo.
Avgiterationstargetnotspecified-assumeatEb/N0=4.
5dB[67]EFPGAimplementationofaLDPCdecoderusingareducedcomplexitymessagepassingalgorithm-ECChrandrasettyV.
A.
,AzizS.
M.
2011324648Reg3Reg61944Uni1188Fullyparallel3246489721XilinxVirtex5XC5VLX110TSimplifiedMessagePassingAlgorithm106.
16G**12.
3G*404614239161840.
87982284785963161840.
3684528478*--5.
415.
21890.
50NoneNotdiscussed,probablybecausefocusisonadecodingalgorithmmorethananarchitectureThroughputderivedfor10iterations.
[67]TFPGAimplementationofaLDPCdecoderusingareducedcomplexitymessagepassingalgorithm-TPChrandrasettyV.
A.
,AzizS.
M.
2011324648Reg3Reg61944Uni1188Fullyparallel3246489721XilinxVirtex5XC5VLX110TSimplifiedMessagePassingAlgorithm3.
816.
2G32.
4G*404614239161840.
87982284785963161840.
3684528478*0.
50NoneNotdiscussed,probablybecausefocusisonadecodingalgorithmmorethananarchitectureAvgiterationsandthroughputforEb/N0=6.
25dB[53]-1AhighlyflexibleLDPCdecoderusinghierarchicalquasi-cyclicmatrixwithlayeredpermutation-648BITCODEChandrasettyV.
A.
,AzizS.
M.
2012324648Reg3Reg61944Uni*4128Semiparallel1818361XilinxVirtex2XC2V8000-5FF1152Min-Sum6.
9**100M**200M*590810816118160.
915369108161604118160.
13574810816*4718.
4**3.
082.
88890.
503codesin802.
11WLANAnyQCcode.
IterationsandthroughputderivedforsameEb/N0asECresults[53]-2AhighlyflexibleLDPCdecoderusinghierarchicalquasi-cyclicmatrixwithlayeredpermutation-1296BITCODEChandrasettyV.
A.
,AzizS.
M.
20126481296Reg3Reg63888Uni*4128Semiparallel1818361XilinxVirtex2XC2V8000-5FF1152Min-Sum8.
4**86.
6M**173M*590810816118160.
915369108161604118160.
13574810816*4736.
7**2.
742.
54890.
503codesin802.
11WLANAnyQCcode.
IterationsandthroughputderivedforsameEb/N0asECresults[53]-3AhighlyflexibleLDPCdecoderusinghierarchicalquasi-cyclicmatrixwithlayeredpermutation-1944BITCODEChandrasettyV.
A.
,AzizS.
M.
20129721944Reg3Reg65832Uni*4128Semiparallel1818361XilinxVirtex2XC2V8000-5FF1152Min-Sum9.
1**61.
6M**123M*590810816118160.
915369108161604118160.
13574810816*4755.
1**2.
592.
39890.
503codesin802.
11WLANAnyQCcode.
IterationsandthroughputderivedforsameEb/N0asECresults[28]EAnareaefficientLDPCdecoderusingareducedcomplexitymin-sumalgorithmChandrasettyV.
A.
,AzizS.
M.
20125761152Reg3Reg63456Uni2138Fullyparallel576115217281XilinxVirtex5XC5VLX110T-3FF1136ModifiedMin-Sum8.
5**9.
35G**18.
7G*1082339024432920.
9014147804815107432920.
34895678048*--3.
433.
23890.
50NoneAlgorithmIterationsandthroughputderivedforsameEb/N0asECresults[28]TAnareaefficientLDPCdecoderusingareducedcomplexitymin-sumalgorithmChandrasettyV.
A.
,AzizS.
M.
20125761152Reg3Reg63456Uni2138Fullyparallel576115217281XilinxVirtex5XC5VLX110T-3FF1136ModifiedMin-Sum6.
811.
7G23.
4G*1082339024432920.
9014147804815107432920.
34895678048*0.
50NoneAlgorithmAverageiterationsandthroughputatEb/N0=4dB[71]ImproveddecoderdesignforLDPCcodesbasedonselectivenodeprocessingKhatiS.
S.
,BishtP.
,PujariS.
C.
20124321296Irr3.
67Reg114752Uni11228Semiparallel48121XilinxVirtex5XC5VLX110ModifiedSPA-4483-17932--4789179320.
26706429726**923312*2.
611.
59950.
66None1code[77]-1ReconfigurablearchitectureandautomateddesignflowforrapidFPGA-basedLDPCcodeemulation-802.
11adLiH.
,ParkY.
S.
,ZhangZ.
2012336672Irr3.
25Irr6.
52184Uni5100Semiparallel--966XilinxVirtex5XC5VLX155TOffsetmin-sum10475M*950M1256835723502720.
7105947144622323502720.
44404471446*1314716*3.
022.
82890.
50WithinfamiliesofcodesAnyQCcode.
Designauto-generatedfromH(foroneFPGA).
Correspondencewithauthor.
[77]-2ReconfigurablearchitectureandautomateddesignflowforrapidFPGA-basedLDPCcodeemulation-802.
11nLiH.
,ParkY.
S.
,ZhangZ.
20129721944Irr3.
58Irr7.
176966Uni5100Semiparallel--964XilinxVirtex5XC5VLX155TOffsetmin-sum10348M*695M1356538883542600.
7166057776622221542600.
40952877766*1304680*2.
832.
63890.
50WithinfamiliesofcodesAnyQCcode.
Designauto-generatedfromH(foroneFPGA).
Correspondencewithauthor.
[77]-3ReconfigurablearchitectureandautomateddesignflowforrapidFPGA-basedLDPCcodeemulation-802.
15cLiH.
,ParkY.
S.
,ZhangZ.
2012336672Irr3.
38Irr6.
752268Uni5100Semiparallel--963XilinxVirtex5XC5VLX155TOffsetmin-sum10190M*380M1181931497472760.
6662376299419971472760.
42243462994*1304680*2.
972.
77890.
50WithinfamiliesofcodesAnyQCcode.
Designauto-generatedfromH(foroneFPGA).
Correspondencewithauthor.
[77]-4ReconfigurablearchitectureandautomateddesignflowforrapidFPGA-basedLDPCcodeemulation-802.
16eLiH.
,ParkY.
S.
,ZhangZ.
201211522304Irr3.
17Irr6.
337296Uni5100Semiparallel--964XilinxVirtex5XC5VLX155TOffsetmin-sum10355M*710M1321939214528760.
7416227842822689528760.
42909878428*1786408*2.
792.
59890.
50WithinfamiliesofcodesAnyQCcode.
Designauto-generatedfromH(foroneFPGA).
Correspondencewithauthor.
[88]-1TrellisWare-Flexible-LDPCDecoderFP-800TrellisWare2008XilinxVirtex7320PCMsincustom"Flexible-LDPC"designThroughputgivenasmaximumfor"StratixV&Virtex7",butnosizeresults.
[88]-2TrellisWare-Flexible-LDPCDecoderFP-500(throughput)TrellisWare2008XilinxVirtex7--16320PCMsincustom"Flexible-LDPC"designThroughputgivenasmaximumforVirtex7,butnosizeresultsforthisFPGA[88]-2TrellisWare-Flexible-LDPCDecoderFP-500(size)TrellisWare2008XilinxSpartan6XC6SLX150-3--41112507491644480.
308602101498-328896-101498*128----320PCMsincustom"Flexible-LDPC"designCorrespondencewithauthorgaveapproximatethroughputsforSpartan6[88]-3TrellisWare-Flexible-LDPCDecoderFP-400(throughput)TrellisWare2008XilinxVirtex7--16320PCMsincustom"Flexible-LDPC"designThroughputgivenasmaximumforVirtex7,butnosizeresultsforthisFPGA[88]-3TrellisWare-Flexible-LDPCDecoderFP-400(size)TrellisWare2008XilinxSpartan6XC6SLX150-3--2193128715877240.
32733357430-175448-57430*95----320PCMsincustom"Flexible-LDPC"designCorrespondencewithauthorgaveapproximatethroughputsforSpartan6[88]-4TrellisWare-Flexible-LDPCDecoderFP-300(throughput)TrellisWare2008XilinxVirtex7--16320PCMsincustom"Flexible-LDPC"designThroughputgivenasmaximumforVirtex7,butnosizeresultsforthisFPGA[88]-4TrellisWare-Flexible-LDPCDecoderFP-300(size)TrellisWare2008XilinxSpartan6XC6SLX75-3--1369217204547680.
31412534408-109536-34408*78----320PCMsincustom"Flexible-LDPC"designCorrespondencewithauthorgaveapproximatethroughputsforSpartan6[88]-5TrellisWare-Flexible-LDPCDecoderFP-200(throughput)TrellisWare2008XilinxVirtex7--16320PCMsincustom"Flexible-LDPC"designThroughputgivenasmaximumforVirtex7,butnosizeresultsforthisFPGA[88]-5TrellisWare-Flexible-LDPCDecoderFP-200(size)TrellisWare2008XilinxSpartan6XC6SLX75-3--972911198389160.
28774822396-77832-22396*84----320PCMsincustom"Flexible-LDPC"designCorrespondencewithauthorgaveapproximatethroughputsforSpartan6[83]-1Unicore-WiMaxLDPCDecoder-R=1/2Unicore200911522304Irr3.
17Irr6.
337296Uni*8160Semiparallel---1XilinxVirtex4XC4VLX60-12Offsetmin-sum1571M142M*21981-43962---43962-36438**29522*1.
841.
64890.
5All114PCMsin802.
16(WiMax)[83]-2Unicore-WiMaxLDPCDecoder-R=2/3AUnicore20097682304Irr3.
33Reg107680Uni*8160Semiparallel---1XilinxVirtex4XC4VLX60-12Offsetmin-sum15110M167M*21981-43962---43962-36438**29522*2.
431.
34840.
67All114PCMsin802.
16(WiMax)[83]-3Unicore-WiMaxLDPCDecoder-R=2/3BUnicore20097682304Irr3.
38Irr10.
137776Uni*8160Semiparallel---1XilinxVirtex4XC4VLX60-12Offsetmin-sum15109M163M*21981-43962---43962-36438**29522*2.
511.
42840.
67All114PCMsin802.
16(WiMax)[83]-4Unicore-WiMaxLDPCDecoder-R=3/4AUnicore20095762304Irr3.
54Irr14.
178160Uni*8160Semiparallel---1XilinxVirtex4XC4VLX60-12Offsetmin-sum15132M176M*21981-43962---43962-36438**29522*2.
981.
34910.
75All114PCMsin802.
16(WiMax)[83]-5Unicore-WiMaxLDPCDecoder-R=3/4BUnicore20095762304Irr3.
67Irr14.
678448Uni*8160Semiparallel---1XilinxVirtex4XC4VLX60-12Offsetmin-sum15129M172M*21981-43962---43962-36438**29522*2.
891.
25910.
75All114PCMsin802.
16(WiMax)[83]-6Unicore-WiMaxLDPCDecoder-R=5/6Unicore20093842304Irr3.
33Reg207680Uni*8160Semiparallel---1XilinxVirtex4XC4VLX60-12Offsetmin-sum15169M204M*21981-43962---43962-36438**29522*3.
661.
32880.
83All114PCMsin802.
16(WiMax)[82]-1Unicore-CCSDSLDPCDecoder-HSVERSIONUnicore2011Uni*9180----1XilinxVirtex5XC5VLX85Offsetmin-sum12330M-9744-38976---38976-64611**511836*3.
71--All10PCMsinCCSDSC2[82]-2Unicore-CCSDSLDPCDecoder-HSVERSIONUnicore2011Uni*9180----1XilinxVirtex5XC5VLX85Offsetmin-sum8480M-9744-38976---38976-64611**511836*3.
78--All10PCMsinCCSDSC2[82]-3Unicore-CCSDSLDPCDecoder-HSVERSIONUnicore2011Uni*9180----1XilinxVirtex5XC5VLX85Offsetmin-sum5600M-9744-38976---38976-64611**511836*3.
84--All10PCMsinCCSDSC2[82]-4Unicore-CCSDSLDPCDecoder-LSVERSIONUnicore2011Uni*9150----1AlteraStratix2EP2S35Offsetmin-sum1230M-5289-10578---10578-8768**61244*3.
71--All10PCMsinCCSDSC2[82]-5Unicore-CCSDSLDPCDecoder-LSVERSIONUnicore2011Uni*9150----1AlteraStratix2EP2S35Offsetmin-sum840M-5289-10578---10578-8768**61244*3.
78--All10PCMsinCCSDSC2[82]-6Unicore-CCSDSLDPCDecoder-LSVERSIONUnicore2011Uni*9150----1AlteraStratix2EP2S35Offsetmin-sum552M-5289-10578---10578-8768**61244*3.
84--All10PCMsinCCSDSC2[87]-1Iprium-ITU-TG.
975.
1I.
6LDPCDecoderIprium20132048Uni*1126AlteraCyclone4EP4CE115-7HarddecisionXOR128G8.
54G*39995-39995---39995-39995----0.
94NoneNone[87]-2Iprium-ITU-TG.
975.
1I.
6LDPCDecoderIprium20132048Uni*1190XilinxVirtex6XC6VLX240T-3HarddecisionXOR1212.
2G13G*7192-28768---57536-47689*0.
94NoneNone[84]BlueRum-802.
11n/acWiFiLDPCDecoderBlueRumConsulting240SemiparallelOffsetmin-sumAll12PCMsin802.
11n/ac(WiFi)BlueRum-802.
11adWiGigLDPCDecoderBlueRumConsultingSemiparallelOffsetmin-sumAll4PCMsin802.
11ad(WiGig)"SupportsallMCS(thehighest,MCS24,being6.
756Gbps)".
Creonic-DVB-S2BCHandLDPCDecoderCreonicAll63PCMsinDVB-S2.
[86]Creonic-802.
11adWiGigLDPCDecoderCreonic10-2.
1GAll4PCMsin802.
11ad(WiGig)Creonic-802.
11n/acWiFiLDPCDecoderCreonicAll12PCMsin802.
11n/ac(WiFi)Creonic-WiMedia1.
5UWBLDPCDecoderCreonic1GAll8PCMsinWiMedia1.
5Creonic-802.
15.
3cLDPCDecoderCreonicAll5PCMsin802.
15.
3c[89]ELogicFruit-LDPCDecoderLogicFruit9721944Offsetmin-sum151.
661.
46890.
512PCMswithrates/sizescomparableto802.
11n/ac[89]TLogicFruit-LDPCDecoderLogicFruit16201944----200Offsetmin-sum100.
8312PCMswithrates/sizescomparableto802.
11n/ac[81]-1Softjin-LDPCDecoderforDVB-S2-180PUs,R=1/4Softjin140Semiparallel---1XilinxVirtex5-Minsum--105000--21000042000--210000*31911484*--0.
25All63PCMsinDVB-S2.
[81]-2Softjin-LDPCDecoderforDVB-S2-180PUs,R=2/3Softjin140Semiparallel---1XilinxVirtex5-Minsum--105000--21000042000--210000*31911484*--0.
67All63PCMsinDVB-S2.
[81]-3Softjin-LDPCDecoderforDVB-S2-360PUs,R=1/4Softjin140Semiparallel---1XilinxVirtex5-Minsum--194000--38800042000--388000*1515436*--0.
25All63PCMsinDVB-S2.
[81]-4Softjin-LDPCDecoderforDVB-S2-360PUs,R=2/3Softjin140Semiparallel---1XilinxVirtex5-Minsum--194000--38800042000--388000*1515436*--0.
67All63PCMsinDVB-S2.
TurboConcept-WiMaxLDPCdecoderTurboConcept200MAll114PCMsin802.
16(WiMax)TurboConcept-CMMBLDPCdecoderTurboConceptAll2PCMsinCMMB[85]TurboConcept-ITUG.
hnLDPCdecoderTurboConcept1GAll9PCMsinITUG.
hnNotes50M50M25M866MThroughputDecoded(bps)100M(coderate)FlexibilityEb/N0(dB)whereBER=10^-4ECloss(dB)150MPublicationRun-timeDesign-time6.
76G100M137MArchitectureLDPCcodeHardwareResourceRequirementsAvailableregistersMemory(Kbits)BRAMsstatedELBsRegisterusageTransmissionenergyefficiencyResearchpublicationsCommercialdesignsParametersCharacteristics15M7M2M1.
45M2.
43M522M3.
2G400M200M200M100MRegistersstated96M206M145MRefEquiv.
4LUTsTitleAvailablenLUTsnLUTsstatedOperandbitwidthnLUTusageNumber(max)ParallelframesAuthorsYearClock(MHz)Checknodealgorithm(stated)ParallelismHPUsFPGASlices/LEsstatedEncoded(bps)