封装机械键盘黑轴

AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,intellectualpropertymattersandotherimportantdisclaimers.
PRODUCTIONDATA.
EnglishDataSheet:SCPS215TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018具具有有集集成成ESD保保护护的的TCA8418I2C控控制制型型键键盘盘扫扫描描IC11特特性性1工作电源电压范围:1.
65V至3.
6V可借助18个通用输入输出(GPIO)支持80个按钮支持QWERTY键盘操作和通用输入输出(GPIO)扩展低待机(空闲)电流消耗:3μA支持1MHz快速模式加上I2C总线10字节先入先出(FIFO)可存储10次按键按压和释放操作开漏电路低电平有效中断输出集成消抖时间为50μs施密特触发器操作可在SCL和SDA输入端实现缓慢输入转换和更好的开关噪声抗扰度:1.
8V时的Vhys典型值为0.
18V锁断性能超过200mA,符合JESD78II类规范的要求全部18个GPIO引脚和非GPIO引脚上的ESD保护均超出JESD22规范要求–2000V人体放电模型(A114-A)–1000V器件充电模型(C101)2应应用用范范围围智能电话平板电脑人机界面(HMI)面板全球卫星定位(GPS)设备MP3播放器数码照相机3说说明明TCA8418是一款具有集成ESD保护的键盘扫描器件.
它能够在1.
65V至3.
6V电源电压下运行,具有18个GPIO.
这些GPIO可通过I2C接口支持多达80个按键.
按键控制器可对输入进行消抖以及保持用于存储按键按压和释放事件的10字节FIFO.
该FIFO借助溢出绕回功能可存储多达10个按键事件.
中断(INT)输出可配置为在发生按键按压和按键释放事件时,或这些事件达到最大速率时报警.
器器件件信信息息(1)器器件件型型号号封封装装封封装装尺尺寸寸((标标称称值值))TCA8418WQFN(24)4.
00mm*4.
00mm(1)如需了解所有可用封装,请参阅产品说明书末尾的可订购产品附录.
简简化化原原理理图图仅显示7个GPIO(共18个)2TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated目目录录1特特性性.
12应应用用范范围围.
13说说明明.
14修修订订历历史史记记录录25PinConfigurationandFunctions.
36Specifications.
46.
1AbsoluteMaximumRatings46.
2ESDRatings.
46.
3RecommendedOperatingConditions.
46.
4ThermalInformation.
46.
5ElectricalCharacteristics.
56.
6I2CInterfaceTimingRequirements.
66.
7ResetTimingRequirements66.
8SwitchingCharacteristics.
76.
9KeypadSwitchingCharacteristics.
76.
10TypicalCharacteristics.
87ParameterMeasurementInformation118DetailedDescription158.
1Overview158.
2FunctionalBlockDiagram158.
3FeatureDescription.
158.
4DeviceFunctionalModes.
208.
5Programming218.
6RegisterMaps259ApplicationandImplementation379.
1ApplicationInformation.
379.
2TypicalApplication3910PowerSupplyRecommendations4211Layout.
4411.
1LayoutGuidelines4411.
2LayoutExample4412器器件件和和文文档档支支持持4512.
1接收文档更新通知4512.
2社区资源.
4512.
3商标.
4512.
4静电放电警告.
4512.
5术语表4513机机械械、、封封装装和和可可订订购购信信息息.
454修修订订历历史史记记录录注:之前版本的页码可能与当前版本有所不同.
ChangesfromRevisionF(July2017)toRevisionGPageAddedsentence:"Ifdebouncingisenabled,theseregistersreturn.
.
.
"toGPIODataStatusRegisters,GPIO_DAT_STAT1–3(Address0x14–0x16)31ChangesfromRevisionE(November2015)toRevisionFPage将WQFN封装尺寸从"4.
00mm*3.
00mm"更改为"4.
00mm*4.
00mm",删除了器件信息表中的DSBGA(25)封装.
1ChangesfromRevisionD(July2014)toRevisionEPage已添加ESD额定值表,特性描述部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分.
1UpdatedRegisterDescriptionstable.
25ChangesfromRevisionB(March2010)toRevisionCPageAddedCADInterruptErratasection.
35AddedOverflowErratasection.
363TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated5PinConfigurationandFunctionsRTWPackage24-PinWQFNTopViewPinFunctionsPINTYPEDESCRIPTIONNo.
NAME1ROW7I/OGPIOorrow7inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
2ROW6I/OGPIOorrow6inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
3ROW5I/OGPIOorrow5inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
4ROW4I/OGPIOorrow4inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
5ROW3I/OGPIOorrow3inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
6ROW2I/OGPIOorrow2inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
7ROW1I/OGPIOorrow1inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
8ROW0I/OGPIOorrow0inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
9COL0I/OGPIOorcolumn0inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
10COL1I/OGPIOorcolumn1inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
11COL2I/OGPIOorcolumn2inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
12COL3I/OGPIOorcolumn3inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
13COL4I/OGPIOorcolumn4inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
14COL5I/OGPIOorcolumn5inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
15COL6I/OGPIOorcolumn6inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
16COL7I/OGPIOorcolumn7inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
17COL8I/OGPIOorcolumn8inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
18COL9I/OGPIOorcolumn9inkeypadmatrix.
Ifunused,connecttoVCCthroughapull-upresistor.
19GND–Ground20RESETIActive-lowresetinput.
ConnecttoVCCthroughapull-upresistor,ifnoactiveconnectionisused.
21VCC-Supplyvoltageof1.
65Vto3.
6V22SDAI/OSerialdatabus.
ConnecttoVCCthroughapull-upresistor.
23SCLISerialclockbus.
ConnecttoVCCthroughapull-upresistor.
24INTOActive-lowinterruptoutput.
Opendrainstructure.
ConnecttoVCCthroughapull-upresistor.
4TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditionsisnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved.
6Specifications6.
1AbsoluteMaximumRatings(1)overoperatingfree-airtemperaturerange(unlessotherwisenoted)MINMAXUNITVCCSupplyvoltagerange–0.
54.
6VVIInputvoltagerange(2)–0.
54.
6VVOVoltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2)–0.
54.
6VOutputvoltagerangeinthehighorlowstate(2)–0.
54.
6IIKInputclampcurrentVI(CAD)keypress.
Thisfeatureallowsthehosttorecognizeaspecifickeypressandalertthehostthatthecombinationhasoccurred.
TheTCA8418willrecognizeakeypressifkeys1,11,and21areallpressedatthesametime.
ThesekeysarereferencedtothekeyvalueslistedintheKeyEventTable.
NotethatthiskeycombinationthattriggersaCADinterruptisnotadjustable,andmustbekeys1,11,and21.
PleaseseeCADInterruptErrataformoreinformation.
8.
3.
5InterruptOutputAninterruptisgeneratedbyanyrisingorfallingedgeoftheportinputsintheinputmode.
Aftertimetiv,thesignalINTisvalid.
Resettingtheinterruptcircuitisachievedwhendataontheportischangedtotheoriginalsettingordataisreadfromtheportthatgeneratedtheinterrupt.
Resettingoccursinthereadmodeattheacknowledge(ACK)ornotacknowledge(NACK)bitaftertherisingedgeoftheSCLsignal.
InterruptsthatoccurduringtheACKorNACKclockpulsecanbelost(orbeveryshort)duetotheresettingoftheinterruptduringthispulse.
EachchangeoftheI/OsafterresettingisdetectedandistransmittedasINT.
Readingfromorwritingtoanotherdevicedoesnotaffecttheinterruptcircuit,andapinconfiguredasanoutputcannotcauseaninterrupt.
ChanginganI/Ofromanoutputtoaninputmaycauseafalseinterrupttooccur,ifthestateofthepindoesnotmatchthecontentsoftheinputportregister.
TheINToutputhasanopen-drainstructureandrequiresapull-upresistortoVCCdependingontheapplication.
IftheINTsignalisconnectedbacktotheprocessorthatprovidestheSCLsignaltotheTCA8418,thentheINTpinhastobeconnectedtoVCC.
Ifnot,theINTpincanbeconnectedtoVCC.
8.
3.
5.
150Micro-secondInterruptConfigurationTheTCA8418providesthecapabilityofdeassertingtheinterruptfor50μswhilethereisapendingevent.
WhentheINT_CFGbitinRegister0x01isset,anyattempttocleartheinterruptbitwhiletheinterruptpinisalreadyassertedresultsina50μsdeassertion.
WhentheINT_CFGbitiscleared,INTremainsassertedifthehosttriestocleartheinterrupt.
Thisfeatureisparticularlyusefulforsoftwaredevelopmentandedgetriggeringapplications.
8.
4DeviceFunctionalModes8.
4.
1Power-OnReset(POR)Whenpower(from0V)isappliedtoVCC,aninternalpower-onresetcircuitholdstheTCA8418inaresetconditionuntilVCChasreachedVPORR.
Atthattime,theresetconditionisreleased,andtheTCA8418registersandI2C/SMBusstatemachineinitializetotheirdefaultstates.
Afterthat,VCCmustbeloweredtobelowVPORFandbackuptotheoperatingvoltageforapower-resetcycle.
SeePowerSupplyRecommendationsformoreinformationonpowerupresetrequirements.
8.
4.
2Powered(KeyScanMode)TheTCA8418canbeusedtoreadGPIfromsinglebuttons,orconfiguredinkeyscanmodetoreadanarrayofkeys.
Inkeyscanmode,therearetwomodesofoperation.
8.
4.
2.
1IdleKeyScanModeOncetheTCA8418hashadthekeypadarrayconfigured,itwillenteridlemodewhennokeysarebeingpressed.
Allcolumnsconfiguredaspartofthekeypadarraywillbedrivenlowandallrowsconfiguredaspartofthekeypadarraywillbesettoinputs,withpull-upresistorsenabled.
Duringidlemode,theinternaloscillatoristurnedoffsothatpowerconsumptionislowasthedeviceawaitsakeypress.
8.
4.
2.
2ActiveKeyScanModeWhentheTCA8418isinidlekeyscanmode,thedeviceawaitsakeypress.
Onceakeyispressedinthearray,alowsignalononeoftheROWpininputstriggersaninterrupt,whichwillturnontheinternaloscillatorandentertheactivekeyscanmode.
Atthispoint,theTCA8418willstartthekeyscanalgorithmtodeterminewhichkeyisbeingpressed,and/oritwillusetheinternaloscillatorfordebouncing.
Onceallkeyshavebeenreleased,thedevicewillenteridlekeyscanmode.
21TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated8.
5Programming8.
5.
1I2CInterfaceTheTCA8418hasastandardbidirectionalI2Cinterfacethatiscontrolledbyamasterdeviceinordertobeconfiguredorreadthestatusofthisdevice.
EachslaveontheI2CbushasaspecificdeviceaddresstodifferentiatebetweenotherslavedevicesthatareonthesameI2Cbus.
Manyslavedeviceswillrequireconfigurationuponstartuptosetthebehaviorofthedevice.
Thisistypicallydonewhenthemasteraccessesinternalregistermapsoftheslave,whichhaveuniqueregisteraddresses.
Adevicecanhaveoneormultipleregisterswheredataisstored,written,orread.
ThephysicalI2Cinterfaceconsistsoftheserialclock(SCL)andserialdata(SDA)lines.
BothSDAandSCLlinesmustbeconnectedtoVCCthroughapull-upresistor.
Thesizeofthepull-upresistorisdeterminedbytheamountofcapacitanceontheI2Clines.
(Forfurtherdetails,refertoI2Cpull-upResistorCalculation(SLVA689).
)Datatransfermaybeinitiatedonlywhenthebusisidle.
AbusisconsideredidleifbothSDAandSCLlinesarehighafteraSTOPcondition.
Thefollowingisthegeneralprocedureforamastertoaccessaslavedevice:1.
Ifamasterwantstosenddatatoaslave:–Master-transmittersendsaSTARTconditionandaddressestheslave-receiver.
–Master-transmittersendsdatatoslave-receiver.
–Master-transmitterterminatesthetransferwithaSTOPcondition.
2.
Ifamasterwantstoreceiveorreaddatafromaslave:–Master-receiversendsaSTARTconditionandaddressestheslave-transmitter.
–Master-receiversendstherequestedregistertoreadtoslave-transmitter.
–Master-receiverreceivesdatafromtheslave-transmitter.
–Master-receiverterminatesthetransferwithaSTOPcondition.
Figure21.
DefinitionofStartandStopConditions22TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporatedProgramming(continued)Figure22.
BitTransfer8.
5.
2BusTransactionsDatamustbesenttoandreceivedfromtheslavedevices,andthisisaccomplishedbyreadingfromorwritingtoregistersintheslavedevice.
Registersarelocationsinthememoryoftheslavewhichcontaininformation,whetheritbetheconfigurationinformationorsomesampleddatatosendbacktothemaster.
Themastermustwriteinformationtotheseregistersinordertoinstructtheslavedevicetoperformatask.
WhileitiscommontohaveregistersinI2Cslaves,notethatnotallslavedeviceswillhaveregisters.
Somedevicesaresimpleandcontainonly1register,whichmaybewrittentodirectlybysendingtheregisterdataimmediatelyaftertheslaveaddress,insteadofaddressingaregister.
Anexampleofasingle-registerdevicewouldbean8-bitI2Cswitch,whichiscontrolledviaI2Ccommands.
Sinceithas1bittoenableordisableachannel,thereisonly1registerneeded,andthemastermerelywritestheregisterdataaftertheslaveaddress,skippingtheregisternumber.
8.
5.
2.
1WritesTowriteontheI2Cbus,themasterwillsendaSTARTconditiononthebuswiththeaddressoftheslave,aswellasthelastbit(theR/Wbit)setto0,whichsignifiesawrite.
Aftertheslavesendstheacknowledgebit,themasterwillthensendtheregisteraddressoftheregistertowhichitwishestowrite.
Theslavewillacknowledgeagain,lettingthemasterknowitisready.
Afterthis,themasterwillstartsendingtheregisterdatatotheslaveuntilthemasterhassentallthedatanecessary(whichissometimesonlyasinglebyte),andthemasterwillterminatethetransmissionwithaSTOPcondition.
Figure23showsanexampleofwritingasinglebytetoaregister.
23TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporatedProgramming(continued)Figure23.
WritetoRegisterFigure24.
WritetoConfigurationRegister24TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporatedProgramming(continued)8.
5.
2.
2ReadsReadingfromaslaveisverysimilartowriting,butrequiressomeadditionalsteps.
Inordertoreadfromaslave,themastermustfirstinstructtheslavewhichregisteritwishestoreadfrom.
Thisisdonebythemasterstartingoffthetransmissioninasimilarfashionasthewrite,bysendingtheaddresswiththeR/Wbitequalto0(signifyingawrite),followedbytheregisteraddressitwishestoreadfrom.
Oncetheslaveacknowledgesthisregisteraddress,themasterwillsendaSTARTconditionagain,followedbytheslaveaddresswiththeR/Wbitsetto1(signifyingaread).
Thistime,theslavewillacknowledgethereadrequest,andthemasterwillreleasetheSDAbusbutwillcontinuesupplyingtheclocktotheslave.
Duringthispartofthetransaction,themasterwillbecomethemaster-receiver,andtheslavewillbecometheslave-transmitter.
Themasterwillcontinuetosendouttheclockpulses,butwillreleasetheSDAlinesothattheslavecantransmitdata.
Attheendofeverybyteofdata,themasterwillsendanACKtotheslave,lettingtheslaveknowthatitisreadyformoredata.
Oncethemasterhasreceivedthenumberofbytesitisexpecting,itwillsendaNACK,signalingtotheslavetohaltcommunicationsandreleasethebus.
ThemasterwillfollowthisupwithaSTOPcondition.
Figure25showsanexampleofreadingasinglebytefromaslaveregister.
Figure25.
ReadfromRegister25TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated8.
6RegisterMaps8.
6.
1DeviceAddressTheaddressoftheTCA8418isshowninTable8.
Table8.
TCA8418DeviceAddressesBYTEBIT7(MSB)6543210(LSB)I2Cslaveaddress0110100R/WThelastbitoftheslaveaddressdefinestheoperation(readorwrite)tobeperformed.
Ahigh(1)selectsareadoperation,whilealow(0)selectsawriteoperation.
8.
6.
2ControlRegisterandCommandByteFollowingthesuccessfulacknowledgmentoftheaddressbyte,thebusmastersendsacommandbyte,whichisstoredinthecontrolregisterintheTCA8418.
Thecommandbyteindicatestheregisterthatwillbeupdatedwithinformation.
Allregisterscanbereadandwrittentobythesystemmaster.
Table9showsalltheregisterswithinthisdeviceandtheirdescriptions.
Thedefaultvalueinallregistersis0.
Table9.
RegisterDescriptionsADDRESSREGISTERNAMEREGISTERDESCRIPTION765432100x00ReservedReserved0x01CFGConfigurationregister(interruptprocessorinterruptenables)AIGPI_E_CGFOVR_FLOW_MINT_CFGOVR_FLOW_IENK_LCK_IENGPI_IENKE_IEN0x02INT_STATInterruptstatusregisterN/A0N/A0N/A0CAD_INTOVR_FLOW_INTK_LCK_INTGPI_INTK_INT0x03KEY_LCK_ECKeylockandeventcounterregisterN/A0K_LCK_ENLCK2LCK1KLEC3KLEC2KLEC1KLEC00x04KEY_EVENT_AKeyeventregisterAKEA70KEA60KEA50KEA40KEA30KEA20KEA10KEA000x05KEY_EVENT_BKeyeventregisterBKEB70KEB60KEB50KEB40KEB30KEB20KEB10KEB000x06KEY_EVENT_CKeyeventregisterCKEC70KEC60KEC50KEC40KEC30KEC20KEC10KEC000x07KEY_EVENT_DKeyeventregisterDKED70KED60KED50KED40KED30KED20KED10KED000x08KEY_EVENT_EKeyeventregisterEKEE70KEE60KEE50KEE40KEE30KEE20KEE10KEE000x09KEY_EVENT_FKeyeventregisterFKEF70KEF60KEF50KEF40KEF30KEF20KEF10KEF000x0AKEY_EVENT_GKeyeventregisterGKEG70KEG60KEG50KEG40KEG30KEG20KEG10KEG000x0BKEY_EVENT_HKeyeventregisterHKEH70KEH60KEH50KEH40KEH30KEH20KEH10KEH000x0CKEY_EVENT_IKeyeventregisterIKEI70KEI60KEI50KEI40KEI30KEI20KEI10KEI000x0DKEY_EVENT_JKeyeventregisterJKEJ70KEJ60KEJ50KEJ640KEJ30KEJ20KEJ10KEJ000x0EKP_LCK_TIMERKeypadlock1tolock2timerKL7KL6KL5KL4KL3KL2KL1KL00x0FUNLOCK1Unlockkey1UK1_7UK1_6UK1_5UK1_4UK1_3UK1_2UK1_1UK1_00x10UNLOCK1Unlockkey2UK2_7UK2_6UK2_5UK2_4UK2_3UK2_2UK2_1UK2_026TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporatedTable9.
RegisterDescriptions(continued)ADDRESSREGISTERNAMEREGISTERDESCRIPTION765432100x11GPIO_INT_STAT1GPIOinterruptstatusR7IS0R6IS0R5IS0R4IS0R3IS0R2IS0R1IS0R0IS00x12GPIO_INT_STAT2GPIOinterruptstatusC7IS0C6IS0C5IS0C4IS0C3IS0C2IS0C1IS0C0IS00x13GPIO_INT_STAT3GPIOinterruptstatusN/A0N/A0N/A0N/A0N/A0N/A0C9IS0C8IS00x14GPIO_DAT_STAT1(readtwicetoclear)GPIOdatastatusR7DSR6DSR5DSR4DSR3DSR2DSR1DSR0DS0x15GPIO_DAT_STAT2(readtwicetoclear)GPIOdatastatusC7DSC6DSC5DSC4DSC3DSC2DSC1DSC0DS0x16GPIO_DAT_STAT3(readtwicetoclear)GPIOdatastatusN/A0N/A0N/A0N/A0N/A0N/A0C9DSC8DS0x17GPIO_DAT_OUT1GPIOdataoutR7DO0R6DO0R5DO0R4DO0R3DO0R2DO0R1DO0R0DO00x18GPIO_DAT_OUT2GPIOdataoutC7DO0C6DO0C5DO0C4DO0C3DO0C2DO0C1DO0C0DO00x19GPIO_DAT_OUT3GPIOdataoutN/A0N/A0N/A0N/A0N/A0N/A0C9DO0C8DO00x1AGPIO_INT_EN1GPIOinterruptenableR7IE0R6IE0R5IE0R4IE0R3IE0R2IE0R1IE0R0IE00x1BGPIO_INT_EN2GPIOinterruptenableC7IE0C6IE0C5IE0C4IE0C3IE0C2IE0C1IE0C0IE00x1CGPIO_INT_EN3GPIOinterruptenableN/A0N/A0N/A0N/A0N/A0N/A0C9IE0C8IE00x1DKP_GPIO1KeypadorGPIOselection0:GPIO1:KPmatrixROW70ROW60ROW50ROW40ROW30ROW20ROW10ROW000x1EKP_GPIO2KeypadorGPIOselection0:GPIO1:KPmatrixCOL70COL60COL50COL40COL30COL20COL10COL000x1FKP_GPIO3KeypadorGPIOselection0:GPIO1:KPmatrixN/A0N/A0N/A0N/A0N/A0N/A0COL90COL800x20GPI_EM1GPIeventmode1ROW70ROW60ROW50ROW40ROW30ROW20ROW10ROW000x21GPI_EM2GPIeventmode2COL70COL60COL50COL40COL30COL20COL10COL000x22GPI_EM3GPIeventmode3N/A0N/A0N/A0N/A0N/A0N/A0COL90COL800x23GPIO_DIR1GPIOdatadirection0:input1:outputR7DD0R6DD0R5DD0R4DD0R3DD0R2DD0R1DD0R0DD00x24GPIO_DIR2GPIOdatadirection0:input1:outputC7DD0C6DD0C5DD0C4DD0C3DD0C2DD0C1DD0C0DD00x25GPIO_DIR3GPIOdatadirection0:input1:outputN/A0N/A0N/A0N/A0N/A0N/A0C9DD0C8DD027TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporatedTable9.
RegisterDescriptions(continued)ADDRESSREGISTERNAMEREGISTERDESCRIPTION765432100x26GPIO_INT_LVL1GPIOedge/leveldetect0:falling/low1:rising/highR7IL0R6IL0R5IL0R4IL0R3IL0R2IL0R1IL0R0IL00x27GPIO_INT_LVL2GPIOedge/leveldetect0:falling/low1:rising/highC7IL0C6IL0C5IL0C4IL0C3IL0C2IL0C1IL0C0IL00x28GPIO_INT_LVL3GPIOedge/leveldetect0:falling/low1:rising/highN/A0N/A0N/A0N/A0N/A0N/A0C9IL0C8IL00x29DEBOUNCE_DIS1Debouncedisable0:debounceenabled1:debouncedisabledR7DD0R6DD0R5DD0R4DD0R3DD0R2DD0R1DD0R0DD00x2ADEBOUNCE_DIS2Debouncedisable0:debounceenabled1:debouncedisabledC7DD0C6DD0C5DD0C4DD0C3DD0C2DD0C1DD0C0DD00x2BDEBOUNCE_DIS3Debouncedisable0:debounceenabled1:debouncedisabledN/A0N/A0N/A0N/A0N/A0N/A0C9DD0C8DD00x2CGPIO_PULL1GPIOpull-updisable0:pull-upenabled1:pull-updisabledR7PD0R6PD0R5PD0R4PD0R3PD0R2PD0R1PD0R0PD00x2DGPIO_PULL2GPIOpull-updisable0:pull-upenabled1:pull-updisabledC7PD0C6PD0C5PD0C4PD0C3PD0C2PD0C1PD0C0PD00x2EGPIO_PULL3GPIOpull-updisable0:pull-upenabled1:pull-updisabledN/A0N/A0N/A0N/A0N/A0N/A0C9PD0C8PD00x2FReserved28TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated8.
6.
2.
1ConfigurationRegister(Address0x01)BITNAMEDESCRIPTION7AIAuto-incrementforreadandwriteoperations;Seebelowtableformoreinformation0=disabled1=enabled6GPI_E_CFGGPIeventmodeconfiguration0=GPIeventsaretrackedwhenkeypadislocked1=GPIeventsarenottrackedwhenkeypadislocked5OVR_FLOW_MOverflowmode0=disabled;Overflowdataislost1=enabled;Overflowdatashiftswithlasteventpushingfirsteventout4INT_CFGInterruptconfiguration0=processorinterruptremainsasserted(orlow)ifhosttriestoclearinterruptwhilethereisstillapendingkeypress,keyreleaseorGPIinterrupt1=processorinterruptisdeassertedfor50μsandreassertwithpendinginterrupts3OVR_FLOW_IENOverflowinterruptenable0=disabled;INTisnotassertediftheFIFOoverflows1=enabled;INTbecomesassertediftheFIFOoverflows2K_LCK_IENKeypadlockinterruptenable0=disabled;INTisnotassertedafteracorrectunlockkeysequence1=enabled;INTbecomesassertedafteracorrectunlockkeysequence1GPI_IENGPIinterruptenabletohostprocessor0=disabled;INTisnotassertedforachangeonaGPI1=enabled;INTbecomesassertedforachangeonaGPI0KE_IENKeyeventsinterruptenabletohostprocessor0=disabled;INTisnotassertedwhenakeyeventoccurs1=enabled;INTbecomesassertedwhenakeyeventoccursBit7inthisregisterisusedtodeterminetheprogrammingmode.
Ifitislow,alldatabytesarewrittentotheregisterdefinedbythecommandbyte.
Ifbit7ishigh,thevalueofthecommandbyteisautomaticallyincrementedaftereachbyteiswritten,andthenextdatabyteisstoredinthecorrespondingregister.
RegistersarewritteninthesequenceshowninTable9.
OncetheGPIO_PULL3register(0x2E)iswrittento,thecommandbytereturnstoregister0.
Registers0and2FarereservedandacommandbytethatreferencestheseregistersisnotacknowledgedbytheTCA8418.
Thekeypadlockinterruptenabledeterminesiftheinterruptpinisassertedwhenthekeylockinterrupt(seeInterruptStatusRegister)bitisset.
29TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated8.
6.
2.
2InterruptStatusRegister,INT_STAT(Address0x02)BITNAMEDESCRIPTION7N/AAlways06N/AAlways05N/AAlways04CAD_INTCTRL-ALT-DELkeysequencestatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetected3OVR_FLOW_INTOverflowinterruptstatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetected2K_LCK_INTKeypadlockinterruptstatus.
Thisistheinterrupttotheprocessorwhenthekeypadlocksequenceisstarted.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetected1GPI_INTGPIinterruptstatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetectedCanbeusedtomaskinterrupts0K_INTKeyeventsinterruptstatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetected(1)KEC[3:0]indicateshowmanykeyeventsareintheFIFO.
Forexample,KEC[3:0]=0b0000=0events,KEC[3:0]=0b0001=1eventandKEC[3:0]=0b1010=10events.
Aseventshappen(pressorrelease),thecountincreasesaccordingly.
TheINT_STATregisterisusedtocheckwhichtypeofinterrupthasbeentriggered.
IfthecorrespondinginterruptenablebitsaresetintheConfigurationRegister,thenavalueof1inthecorrespondingbitwillasserttheINTlinelow.
AnexceptiontothisistheCAD_INTbit,whichwillasserttheCAD_INTpinonYFPpackages.
Areadtothisregisterwillreturnwhichtypesofeventshaveoccurred.
Writinga1tothebitwillcleartheinterrupt,unlessthereisstilldatawhichhassettheInterrupt(unreadkeysintheFIFO).
8.
6.
2.
3KeyLockandEventCounterRegister,KEY_LCK_EC(Address0x03)BITNAMEDESCRIPTION7N/AAlways06K_LCK_ENKeylockenable0=disabled;Writea0tothisbittounlockthekeypadmanually1=enabled;Writea1tothisbittolockthekeypad5LCK2Keypadlockstatus0=unlock(ifLCK1is0too)1=locked(ifLCK1is1too)4LCK1Keypadlockstatus0=unlock(ifLCK2is0too)1=locked(ifLCK2is1too)3KEC3(1)Keyeventcount,Bit32KEC2Keyeventcount,Bit21KEC1Keyeventcount,Bit10KEC0Keyeventcount,Bit030TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated(1)OnlyKEY_EVENT_Aregisterisshown8.
6.
2.
4KeyEventRegisters(FIFO),KEY_EVENT_A–J(Address0x04–0x0D)ADDRESSREGISTERNAME(1)REGISTERDESCRIPTIONBIT765432100x04KEY_EVENT_AKeyeventregisterAKEA7KEA6KEA5KEA4KEA3KEA2KEA1KEA0Theseregisters–KEY_EVENT_A-J–functionasaFIFOstackwhichcanstoreupto10keypressesandreleases.
TheuserfirstcheckstheINT_STATregistertoseeifthereareanyinterrupts.
Ifso,thentheKeyLockandEventCounterRegister(KEY_LCK_EC,register0x03)isreadtoseehowmanyinterruptsarestored.
TheINT_STATregisteristhenreadagaintoensurenoneweventshavecomein.
TheKEY_EVENT_Aregisteristhenreadasmanytimesasthereareinterrupts.
Eachtimeareadhappens,thecountintheKEY_LCK_ECregisterreducesby1.
ThedataintheFIFOalsomovesdownthestackby1too(fromKEY_EVENT_JtoKEY_EVENT_A).
Oncealleventshavebeenread,thekeyeventcountisat0andthenKE_INTbitcanbeclearedbywritinga'1'toit.
IntheKEY_EVENT_Aregister,KEA[6:0]indicatesthekey#pressedorreleased.
Avalueof0to80indicatewhichkeyhasbeenpressedorreleasedinakeypadmatrix.
Valuesof97to114areforGPIevents.
Bit7orKEA[7]indicateifakeypressorkeyreleasehashappened.
A'0'meansakeyreleasehappened.
A'1'meansakeyhasbeenpressed(whichcanbeclearedonaread).
Forexample,3keypressesand3keyreleasesarestoredas6wordsintheFIFO.
Aseachwordisread,theuserknowsifitisakeypressorkeyreleasethatoccurred.
KeypressessuchasCTRL+ALT+DELarestoredas3simultaneouskeypresses.
Keypressesandreleasesgeneratekeyeventinterrupts.
TheKE_INTbitand/INTpinwillnotcleareduntiltheFIFOisclearedofallevents.
AllregisterscanbereadbutforthepurposeoftheFIFO,theusershouldonlyreadKEY_EVENT_Aregister.
OncealltheeventsintheFIFOhavebeenread,readingofKEY_EVENT_Aregisterwillyieldazerovalue.
8.
6.
2.
5KeypadLock1toLock2TimerRegister,KP_LCK_TIMER(Address0x0E)ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x0EKP_LCK_TIMERKeypadlockinterruptmasktimerandlock1tolock2timerKL7KL6KL5KL4KL3KL2KL1KL0KL[2:0]arefortheLock1toLock2timerKL[7:3]arefortheinterruptmasktimerLock1toLock2timermustbenon-zeroforkeylocktobeenabled.
Thelock1tolock2bits(KL[2:0])definethetimeinsecondstheuserhastopressunlockkey2afterunlockkey1beforethekeylocksequencetimesout.
Formoreinformation,pleaseseeKeypadLock/Unlock.
Ifthekeypadlockinterruptmasktimerisnon-zero,akeyeventinterrupt(K_INT)willbegeneratedonanyfirstkeypress.
Thesecondinterrupt(K_LCK_IN)willonlybegeneratedwhenthecorrectunlocksequencehasbeencompleted.
Ifeithertimerexpires,thekeylockstatemachinewillreset.
Whentheinterruptmasktimerisdisabled('0'),akeylockinterruptwilltriggeronlywhenthecorrectunlocksequenceiscompleted.
TheinterruptmasktimershouldbesetforthetimeittakesfortheLCDtodimorturnoff.
Formoreinformation,pleaseseeKeypadLockInterruptMaskTimer.
31TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated8.
6.
2.
6Unlock1andUnlock2Registers,UNLOCK1/2(Address0x0F-0x10)ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x0FUnlock1Unlockkey1UK1_7UK1_6UK1_5UK1_4UK1_3UK1_2UK1_1UK1_00x10Unlock2Unlockkey2UK2_7UK2_6UK2_5UK2_4UK2_3UK2_2UK2_1UK2_0UK1[6:0]containsthekeynumberusedtounlockkey1UK2[6:0]containsthekeynumberusedtounlockkey2A'0'ineitherregisterdisablesthekeylockfunction.
8.
6.
2.
7GPIOInterruptStatusRegisters,GPIO_INT_STAT1–3(Address0x11–0x13)TheseregistersareusedtocheckGPIOinterruptstatus.
IftheGPI_INTbitissetinINT_STATregister,thentheGPIwhichsettheinterruptismarkedwitha1inthecorrespondingtable.
TocleartheGPI_INTbit,theseregistersmustallbe0x00.
Areadtotheregisterclearsthebit.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x11GPIO_INT_STAT1GPIOInterruptStatus1R7ISR6ISR5ISR4ISR3ISR2ISR1ISR0IS0x12GPIO_INT_STAT2GPIOInterruptStatus2C7ISC6ISC5ISC4ISC3ISC2ISC1ISC0IS0x13GPIO_INT_STAT3GPIOInterruptStatus3N/AN/AN/AN/AN/AN/AC9ISC8IS8.
6.
2.
8GPIODataStatusRegisters,GPIO_DAT_STAT1–3(Address0x14–0x16)TheseregistersshowtheGPIOstatewhenreadforinputsandoutputs.
Readthesetwicetoclearthem.
Ifdebouncingisenabled,theseregistersreturntheirdefaultvaluesuntilachangeofstateoccursataninput.
Initialpinstatescanbereadbydisablingdebouncing.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x14GPIO_DAT_STAT1GPIODataStatus1R7DSR6DSR5DSR4DSR3DSR2DSR1DSR0DS0x15GPIO_DAT_STAT2GPIODataStatus2C7DSC6DSC5DSC4DSC3DSC2DSC1DSC0DS0x16GPIO_DAT_STAT3GPIODataStatus3N/AN/AN/AN/AN/AN/AC9DSC8DS8.
6.
2.
9GPIODataOutRegisters,GPIO_DAT_OUT1–3(Address0x17–0x19)TheseregisterscontainGPIOdatatobewrittentoGPIOoutdriver;inputsarenotaffected.
ThissetstheoutputforthecorrespondingGPIOoutput.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x17GPIO_DAT_OUT1GPIODataOut1R7DOR6DOR5DOR4DOR3DOR2DOR1DOR0DO0x18GPIO_DAT_OUT2GPIODataOut2C7DOC6DOC5DOC4DOC3DOC2DOC1DOC0DO0x19GPIO_DAT_OUT3GPIODataOut3N/AN/AN/AN/AN/AN/AC9DOC8DO32TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated8.
6.
2.
10GPIOInterruptEnableRegisters,GPIO_INT_EN1–3(Address0x1A–0x1C)Theseregistersenableinterrupts(bitvalue1)ordisableinterrupts(bitvalue'0')forgeneralpurposeinputs(GPI)only.
IftheinputchangesonapinwhichissetupasaGPI,thentheGPI_INTbitwillbesetintheINT_STATregister.
Abitvalueof'0'inanyoftheunreservedbitsdisablesthecorrespondingpin'sabilitytogenerateaninterruptwhenthestateoftheinputchanges.
Thisisthedefaultvalue.
Abitvalueof1inanyoftheunreservedbitsenablesthecorrespondingpin'sabilitytogenerateaninterruptwhenthestateoftheinputchanges.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x1AGPIO_INT_EN1GPIOInterruptEnable1R7IER6IER5IER4IER3IER2IER1IER0IE0x1BGPIO_INT_EN2GPIOInterruptEnable2C7IEC6IEC5IEC4IEC3IEC2IEC1IEC0IE0x1CGPIO_INT_EN3GPIOInterruptEnable3N/AN/AN/AN/AN/AN/AC9IEC8IE8.
6.
2.
11KeypadorGPIOSelectionRegisters,KP_GPIO1–3(Address0x1D–0x1F)Abitvalueof'0'inanyoftheunreservedbitsputsthecorrespondingpininGPIOmode.
ApininGPIOmodecanbeconfiguredasaninputoranoutputintheGPIO_DIR1-3registers.
Thisisthedefaultvalue.
A1inanyofthesebitsputsthepininkeyscanmodeandbecomespartofthekeypadarray,thenitisconfiguredasaroworcolumnaccordingly(thisisnotadjustable).
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x1DKP_GPIO1Keypad/GPIOSelect1ROW7ROW6ROW5ROW4ROW3ROW2ROW1ROW00x1EKP_GPIO2Keypad/GPIOSelect2COL7COL6COL5COL4COL3COL2COL1COL00x1FKP_GPIO3Keypad/GPIOSelect3N/AN/AN/AN/AN/AN/ACOL9COL88.
6.
2.
12GPIEventModeRegisters,GPI_EM1–3(Address0x20–0x22)Abitvalueof'0'inanyoftheunreservedbitsindicatesthatitisnotpartoftheeventFIFO.
Thisisthedefaultvalue.
A1inanyofthesebitsmeansitispartoftheeventFIFO.
WhenapinissetupasaGPIandhasavalueof1intheEventModeregister,thenanykeypresseswillbeaddedtotheFIFO.
PleaseseeKeyEventTableformoreinformation.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x20GPI_EM1GPIEventModeSelect1ROW7ROW6ROW5ROW4ROW3ROW2ROW1ROW00x21GPI_EM2GPIEventModeSelect2COL7COL6COL5COL4COL3COL2COL1COL00x23GPI_EM3GPIEventModeSelect3N/AN/AN/AN/AN/AN/ACOL9COL88.
6.
2.
13GPIODataDirectionRegisters,GPIO_DIR1–3(Address0x23–0x25)Abitvalueof'0'inanyoftheunreservedbitssetsthecorrespondingpinasaninput.
Thisisthedefaultvalue.
A1inanyofthesebitssetsthepinasanoutput.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x23GPIO_DIR1GPIODirection1R7DDR6DDR5DDR4DDR3DDR2DDR1DDR0DD0x24GPIO_DIR2GPIODirection2C7DDC6DDC5DDC4DDC3DDC2DDC1DDC0DD0x25GPIO_DIR3GPIODirection3N/AN/AN/AN/AN/AN/AC9DDC8DD33TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated8.
6.
2.
14GPIOEdge/LevelDetectRegisters,GPIO_INT_LVL1–3(Address0x26–0x28)Abitvalueof'0'indicatesthatinterruptwillbetriggeredonahigh-to-low/low-leveltransitionfortheinputsinGPIOmode.
Thisisthedefaultvalue.
Abitvalueof1indicatesthatinterruptwillbetriggeredonalow-to-high/high-levelvaluefortheinputsinGPIOmode.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x26GPIO_INT_LVL1GPIOEdge/LevelDetect1R7ILR6ILR5ILR4ILR3ILR2ILR1ILR0IL0x27GPIO_INT_LVL2GPIOEdge/LevelDetect2C7ILC6ILC5ILC4ILC3ILC2ILC1ILC0IL0x28GPIO_INT_LVL3GPIOEdge/LevelDetect3N/AN/AN/AN/AN/AN/AC9ILC8IL8.
6.
2.
15DebounceDisableRegisters,DEBOUNCE_DIS1–3(Address0x29–0x2B)Thisisforpinsconfiguredasinputs.
Abitvalueof'0'inanyoftheunreservedbitsenablesthedebounce.
ThisisthedefaultvalueAbitvalueof'1'disablesthedebounce.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x29DEBOUNCE_DIS1DebounceDisable1R7DDR6DDR5DDR4DDR3DDR2DDR1DDR0DD0x30DEBOUNCE_DIS2DebounceDisable2C7DDC6DDC5DDC4DDC3DDC2DDC1DDC0DD0x2BDEBOUNCE_DIS3DebounceDisable3N/AN/AN/AN/AN/AN/AC9DDC8DDDebouncedisablewillhavethesameeffectforGPImodeorforrowsinkeypadscanningmode.
TheRESETinputalwayshasa50-μsdebouncetime.
Thedebouncetimeforinputsisthetimerequiredfortheinputtobestabletobenoticed.
Thistimeis50μs.
Thedebouncetimeforthekeypadisforthecolumnsonly.
Theminimumtimeis25ms.
Allcolumnsarescannedonceevery25mstodetectanykeypresses.
Twofullscansarerequiredtoseeifanykeyswerepressed.
Ifthefirstscanisdonejustafterakeypress,ittakes25mstodetectthekeypress.
Ifthefirstscanisdownmuchlaterthanthekeypress,itwilltake40mstodetectakeypress.
34TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated8.
6.
2.
16GPIOpull-upDisableRegister,GPIO_PULL1–3(Address0x2C–0x2E)Thisregisterenablesordisablespull-upregistersfrominputs.
Abitvalueof'0'willenabletheinternalpull-upresistors.
Thisisthedefaultvalue.
Abitvalueof1willdisabletheinternalpull-upresistors.
ADDRESSREGISTERNAMEREGISTERDESCRIPTIONBIT765432100x2CGPIO_PULL1GPIOpull-upDisable1R7PDR6PDR5PDR4PDR3PDR2PDR1PDR0PD0x3DGPIO_PULL2GPIOpull-upDisable2C7PDC6PDC5PDC4PDC3PDC2PDC1PDC0PD0x2EGPIO_PULL3GPIOpull-upDisable3N/AN/AN/AN/AN/AN/AC9PDC8PD35TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated8.
6.
3CADInterruptErrata8.
6.
3.
1DescriptionIntheInterruptStatusRegister(seeTable10),bit4isusedtoindicatethedetectionofaCTRL-ALT-DELkeysequence.
CertainkeypresssequencestriggerthisbittoregisteraCAD_INTimproperly.
Table10.
InterruptStatusRegister,INT_STAT(Address0x02)BITNAMEDESCRIPTION7N/AAlways06N/AAlways05N/AAlways04CAD_INTCTRL-ALT-DELkeysequencestatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetected3OVR_FLOW_INTOverflowinterruptstatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetected2K_LCK_INTKeypadlockinterruptstatus.
Thisistheinterrupttotheprocessorwhenthekeypadlocksequenceisstarted.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetected1GPI_INTGPIinterruptstatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetectedCanbeusedtomaskinterrupts0K_INTKeyeventsinterruptstatus.
Requireswritinga1toclearinterrupts.
0=interruptnotdetected1=interruptdetectedThefollowingkeypresscombinationswillcauseafalseCAD_INT:1+111+2121+1+118.
6.
3.
2SystemImpactThisdevicehasanindividualpinfortheCAD_INTunliketheTCA8418.
TheCAD_INTpinfalselyflagtheprocessorinadditiontotheInterruptStatusRegister'sCAD_INTbitbeingHighwhenaCADsequencedidnotoccur.
8.
6.
3.
3SystemWorkaroundThereisnosystemworkaroundtoavoidtheInterruptStatusRegistertoindicateaCAD_INTsequencebeingdetected.
36TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated8.
6.
4OverflowErrata8.
6.
4.
1DescriptionTheTCA8418allowsforoverflowdetectionofthe10byteFIFOofkey-pressandreleaseevents.
Foroverflowtobeenabled,bothBit_3andBit_5oftheConfigurationRegister(seeTable11)mustbesetHigh.
IfonlyBit_3sethigh,nooverflowinterruptisgenerated.
Table11.
ConfigurationRegister(Address0x01)BITNAMEDESCRIPTION7AIAuto-incrementforreadandwriteoperation0=disabled1=enabled6CPI_E_CFGGPIevenmodeconfiguration0=GPIeventsaretrackedwhenkeypadislocked1=GPIeventsarenottrackedwhenkeypadislocked5OVR_FLOW_MOverflowmode0=disabled;overflowdataislost1=enabled.
4INT_CFGOverflowdatashiftswithlasteventpushingfirsteventoutinterruptconfiguration.
0=processorinterruptremainsasserted(orlow)ifhosttriestoclearinterruptwhilethereisstillapendingkeypress,keyreleaseorGPIinterrupt1=processorinterruptisdeassertedfor50sandreassertwithpendinginterrupts3OVR_FLOW_IENOverflowinterruptenable0=disabled1=enabled2K_LCK_IENKeypadlockinterruptenable0=disabled1=enabled8.
6.
4.
2SystemImpactEnablingtheOverflowimproperlymayleadtodataloss.
8.
6.
4.
3SystemWorkaroundTheFIFOstackshouldbereadasnewinformationispassedin.
SincetheOverflowinterruptistriggeredoncethatstackhasbeguntooverflow,meaningdataisalreadybeinglost.
37TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated9ApplicationandImplementationNOTEInformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.
TI'scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.
Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.
9.
1ApplicationInformation9.
1.
1GhostingConsiderationsTheTCA8418supportsmultiplekeypressesaccurately.
Applicationsrequiringthree-keycombinations(suchas,oranyothercombinations)mustensurethatthethreekeysarewiredinappropriatekeypositionstoavoidghosting(orappearinglikea4thkeyhasbeenpressed).
Toavoidghosting,itisbesttokeep3-buttoncombinationsthatarepressedonseparaterowsandcolumns.
ConsiderthesituationwiththekeypaddescribedinFigure26.
Figure26.
ExampleKeypadInthekeypadsetupinFigure26,thereisa4x3keypadmatrix,connectedtoROW0-ROW3,andCOL0-COL2.
AlloftheROWsareconfiguredasinputswithpullupresistors.
TheCOLsareconfiguredasoutputs,drivinglow.
Whenakeypressismade,oneoftheROWinputswillbepulledlow,lettingtheTCA8418knowthatakeyhasbeenpressed,andtheTCA8418willthenstartthekeyscanningalgorithm.
Duringthisalgorithm,Itsweepstheoutputlowacrossthecolumns,suchthatonly1columnisdrivenlowatatime.
Whilethisisdonetoeachcolumn,theTCA8418willreadtheROWinputs,todeterminewhichkeysonacolumnarebeingpressed.
Ghostingcanoccurwhenmultiplekeysarepressedthatcanmakeitappearthatadditionalkeys(whicharenotbeingpressed)arebeingpressed.
38TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporatedApplicationInformation(continued)Figure27.
Incorrect3ButtonCombinationInFigure27,keys1,2,and11arepressed,whichcausesaghostingissue.
SinceR1becomespulledtogroundthroughkey1(whichispulledthroughkey2whenC1istransmittingalow),whenC1isdrivinglow,theTCA8418willseealowsignalatbothR0andR1.
Thiswillfalselytriggerkey12asbeingpressed(thekeyhighlightedasyellow).
Thereasonforthisisthatkeypadmatriceswillshortthecolumnstotherowsconnectedtogether.
WhenC1isdrivinglow,thelowgetstransmittedontoR0viakey2.
Key1isbeingpressed,whichalsoshortsC0toground.
Key11ispressed,whichthenshortsR1toC0.
Inthisprocess,R1isshortedtoC1,whichisthereasonghostingoccurs.
Keypadmatricescansupportmultiplekeypressesproperly,ifcareistakenwhenchoosingthelayout.
InFigure28,weseea3buttoncombinationwhichworkasexpected.
Keys1,11,and21arepressed(thisalsoisthecombinationthatwillsettheinterrupt,seeControl-Alt-DeleteSupportformoreinformation).
Figure28.
Correct3ButtonCombination39TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporated9.
2TypicalApplicationFigure29showsatypicalapplicationoftheTCA8418.
Inthisspecificexample,acommon12keynumberpadlayoutisused.
Thisnumberpadhaskeysfornumbers0to9,*,and#.
Figure29.
TypicalApplication9.
2.
1DesignRequirementsThesystemdesignerneedstoknowafewkeypiecesinordertodesigntheirsystemfortheTCA8418.
ThenumberofkeysdesiredWhetherthekeyswillbemultiplexedornotThelayoutofthemultiplexedkeysUnusedkeysbetiedtoVCCthroughapullupresistor(10kΩ)9.
2.
2DetailedDesignProcedure9.
2.
2.
1DesigningtheHardwareLayoutThefirststepstowardsdesigningakeypadarrayistodeterminethedesiredlayout,andtomapeachkeytotheappropriatevaluewhichwillshowupintheFIFO.
Forthisexample,thenumberpadbelowisthephysicallocationofthekeysthataredesired.
Thelayoutisa4x3array,usingrows0-3andcolumns0-2.
Forthisexample,wewillnotassumeanyoftheotherpinswillbeused.
ThefollowingbehaviorisdesiredforthisexampledesignAllkeysinthekeypadarraytobeaddedtotheFIFOuponakeypressAttemptingtocleartheinterruptbeforetheproperregistershavebeenclearedtode-asserttheINTpinfor50μs,thenasserttheINTpin.
Noadditionalpinsarebeingused,otherthanthekeypadarrayKeypadlocksupport,requiringthattheunlockcombinationbe'#,1'whichmustbepressedwithin2secondsofeachotherKeypadlockinterruptmasktimerof10secondstomatchthebacklightauto-turnoffwith10secondsofnointerruptHardwaredebouncingtobeenabled40TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporatedTypicalApplication(continued)Figure30.
ExampleKeypadSincetheTCA8418reportskeyspressedaccordingtothevaluesinthekeyvaluetable,itisimportanttoknowtheTCA8418valuesforthekeylocations.
Accordingtothekeyeventtable,thekeypressesareassignedinTable12.
Table12.
KeyPressAssignmentKeypadButton123456789*0#KeyEventTableValue(Decimal)12311121321222331323341TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporatedTheschematicforthiskeypadlayoutisshowninfigure(schematicbelow)withthekeyeventtablevalues.
Notethatnoexternalpullupresistorsareneeded,becausetheTCA8418hasintegratedpullupresistors.
Figure31.
KeypadSchematic9.
2.
2.
2ConfiguringtheRegistersThenextsteptodesignakeypadarrayfortheTCA8418istoconfiguretheappropriatehardwareregisters.
TheregistersthatmustbemodifiedforthedesiredfeaturesarethefollowingSTEPREGISTERTOEDITVALUETOWRITEDESCRIPTIONSetupkeypadarrayKP_GPIO1(0x1D)0x0FSetROW0-ROW3toKPMatrixKP_GPIO2(0x1E)0x07SetCOL0-COL2toKPMatrixKP_GPIO3(0x1F)0x00SetCOL8-COL9toGPIOSetupInterruptsCFG(0x01)0x95SettheKE_IEN,K_LCK_IEN,INT_CFG,andAIbitsSetupUnlockKeyCombinationUNLOCK1(0x0F)0x21Setfirstunlockkeytokey33UNLOCK2(0x10)0x01Setsecondunlockkeytokey1SetKeypadLockTimersKP_LCK_TIMER(0x0E)0x52Lock1toLock2setto2seconds.
Interruptmasktimersetto10seconds42TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cnCopyright2009–2018,TexasInstrumentsIncorporated9.
2.
3ApplicationCurvesFigure32.
InitialKeyPresstoInterruptOutputFigure33.
ZoomOnSecondScan(1)TA=–40°Cto85°C(unlessotherwisenoted)10PowerSupplyRecommendationsIntheeventofaglitchordatacorruption,TCA8418canberesettoitsdefaultconditionsbyusingthepower-onresetfeature.
Power-onresetrequiresthatthedevicegothroughapowercycletobecompletelyreset.
Thisresetalsohappenswhenthedeviceispoweredonforthefirsttimeinanapplication.
Thetwotypesofpower-onresetareshowninFigure34andFigure35.
Figure34.
VCCisLoweredBelow0.
2Vor0VandThenRampedUptoVCCFigure35.
VCCisLoweredBelowthePORThreshold,ThenRampedBackUptoVCCTable13specifiestheperformanceofthepower-onresetfeatureforTCA8418forbothtypesofpower-onreset.
Table13.
RecommendedSupplySequencingandRampRates(1)PARAMETERMINTYPMAXUNITVCC_FTFallrateSeeFigure341100msVCC_RTRiserateSeeFigure340.
01100msVCC_TRR_GNDTimetore-ramp(whenVCCdropstoGND)SeeFigure340.
001msVCC_TRR_POR50Timetore-ramp(whenVCCdropstoVPOR_MIN–50mV)SeeFigure350.
001ms43TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018Copyright2009–2018,TexasInstrumentsIncorporatedTable13.
RecommendedSupplySequencingandRampRates()(continued)PARAMETERMINTYPMAXUNITVCC_GHLevelthatVCCcanglitchdownto,butnotcauseafunctionaldisruptionwhenVCCX_GW=1μsSeeFigure361.
2VVCC_GWGlitchwidththatwillnotcauseafunctionaldisruptionwhenVCCX_GH=0.
5*VCCxSeeFigure3610μsVPORFVoltagetrippointofPORonfallingVCC0.
761.
15VVPORRVoltagetrippointofPORonrisingVCC1.
031.
43VGlitchesinthepowersupplycanalsoaffectthepower-onresetperformanceofthisdevice.
Theglitchwidth(VCC_GW)andheight(VCC_GH)aredependentoneachother.
Thebypasscapacitance,sourceimpedance,anddeviceimpedancearefactorsthataffectpower-onresetperformance.
Figure36andTable13providemoreinformationonhowtomeasurethesespecifications.
Figure36.
GlitchWidthandGlitchHeightVPORiscriticaltothepower-onreset.
VPORisthevoltagelevelatwhichtheresetconditionisreleasedandalltheregistersandtheI2C/SMBusstatemachineareinitializedtotheirdefaultstates.
ThevalueofVPORdiffersbasedontheVCCbeingloweredtoorfrom0.
Figure37andTable13providemoredetailsonthisspecification.
Figure37.
VPORForproperoperationofthepower-onresetfeature,useasdirectedinthepreviousfiguresandtableabove.
44TCA8418ZHCS290G–SEPTEMBER2009–REVISEDJUNE2018www.
ti.
com.
cn版权2009–2018,TexasInstrumentsIncorporated11Layout11.
1LayoutGuidelinesForprintedcircuitboard(PCB)layoutoftheTCA8418,commonPCBlayoutpracticesshouldbefollowed,butadditionalconcernsrelatedtohigh-speeddatatransfer,suchasmatchedimpedancesanddifferentialpairsarenotaconcernforI2Csignalspeeds.
InallPCBlayouts,itisbestpracticetoavoidrightanglesinsignaltraces,tofanoutsignaltracesawayfromeachotheruponleavingthevicinityofanintegratedcircuit(IC),andtousethickertracewidthstocarryhigheramountsofcurrentthatcommonlypassthroughpowerandgroundtraces.
Bypassandde-couplingcapacitorsarecommonlyusedtocontrolthevoltageontheVCCpin,usingalargercapacitortoprovideadditionalpowerintheeventofashortpowersupplyglitchandasmallercapacitortofilterouthigh-frequencyripple.
ThesecapacitorsshouldbeplacedasclosetotheTCA8418aspossible.
ForthelayoutexampleprovidedinLayoutExample,a4layerboardisrequiredtorouteallofthesignals.
Thelayoutexampleshowsawaytoroutethesignalsoutfromthedevice,whichcaneventuallybebroughtuptothetoplayer(oranyrequiredlayer)withtheuseofavia.
Thistechniqueisnotdemonstratedinthisexampleduetothecomplexityofthelayout.
11.
2LayoutExampleFigure38.
RTWPackageLayoutExample45TCA8418www.
ti.
com.
cnZHCS290G–SEPTEMBER2009–REVISEDJUNE2018版权2009–2018,TexasInstrumentsIncorporated12器器件件和和文文档档支支持持12.
1接接收收文文档档更更新新通通知知要接收文档更新通知,请导航至TI.
com.
cn上的器件产品文件夹.
单击右上角的通知我进行注册,即可每周接收产品信息更改摘要.
有关更改的详细信息,请查阅已修订文档中包含的修订历史记录12.
2社社区区资资源源下列链接提供到TI社区资源的连接.
链接的内容由各个分销商"按照原样"提供.
这些内容并不构成TI技术规范,并且不一定反映TI的观点;请参阅TI的《使用条款》.
TIE2E在在线线社社区区TI的的工工程程师师对对工工程程师师(E2E)社社区区.
.
此社区的创建目的在于促进工程师之间的协作.
在e2e.
ti.
com中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题.
设设计计支支持持TI参参考考设设计计支支持持可帮助您快速查找有帮助的E2E论坛、设计支持工具以及技术支持的联系信息.
12.
3商商标标E2EisatrademarkofTexasInstruments.
Allothertrademarksarethepropertyoftheirrespectiveowners.
12.
4静静电电放放电电警警告告这些装置包含有限的内置ESD保护.
存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止MOS门极遭受静电损伤.
12.
5术术语语表表SLYZ022—TI术语表.
这份术语表列出并解释术语、缩写和定义.
13机机械械、、封封装装和和可可订订购购信信息息以下页面包含机械、封装和可订购信息.
这些信息是指定器件的最新可用数据.
数据如有变更,恕不另行通知,且不会对此文档进行修订.
如需获取此产品说明书的浏览器版本,请参阅左侧的导航栏.
PACKAGEOPTIONADDENDUMwww.
ti.
com6-Feb-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesTCA8418RTWRACTIVEWQFNRTW243000Green(RoHS&noSb/Br)NIPDAULevel-2-260C-1YEAR-40to85PZ418(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantTCA8418RTWRWQFNRTW243000330.
012.
44.
254.
251.
158.
012.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com19-May-2019PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)TCA8418RTWRWQFNRTW243000367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com19-May-2019PackMaterials-Page2NOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
PACKAGEOUTLINE4219135/A11/2016www.
ti.
comWQFN-0.
8mmmaxheightPLASTICQUADFLATPACK-NOLEADRTW0024BA0.
08C0.
1CAB0.
05CBSYMMSYMM4.
13.
94.
13.
9PIN1INDEXAREA0.
8MAX0.
050.
00CSEATINGPLANEPIN1ID(OPTIONAL)2X2.
520X0.
52X2.
516181371224192.
45±0.
124X0.
340.
2424X0.
50.
3(0.
2)TYP25EXPOSEDTHERMALPADNOTES:(continued)3.
Formoreinformation,seeTexasInstrumentsliteraturenumberSLUA271(www.
ti.
com/lit/slua271).
EXAMPLEBOARDLAYOUT4219135/A11/2016www.
ti.
comWQFN-0.
8mmmaxheightRTW0024BPLASTICQUADFLATPACK-NOLEADSYMMSYMMLANDPATTERNEXAMPLESCALE:20X(2.
45)24X(0.
6)24X(0.
24)1671213181924(3.
8)(0.
97)(3.
8)(0.
97)25(R0.
05)TYP20X(0.
5)(0.
2)TYPVIA0.
07MAXALLAROUND0.
07MINALLAROUNDMETALSOLDERMASKOPENINGSOLDERMASKOPENINGMETALUNDERSOLDERMASKSOLDERMASKDETAILSNONSOLDERMASKDEFINED(PREFERRED)SOLDERMASKDEFINEDNOTES:(continued)4.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
EXAMPLESTENCILDESIGN4219135/A11/2016www.
ti.
comWQFN-0.
8mmmaxheightRTW0024BPLASTICQUADFLATPACK-NOLEADSYMMSYMMSOLDERPASTEEXAMPLEBASEDON0.
125mmTHICKSTENCILEXPOSEDPAD25:78%PRINTEDCOVERAGEBYAREAUNDERPACKAGESCALE:20X(3.
8)(0.
64)TYP167121318192425(0.
64)TYP4X(1.
08)(R0.
05)TYP(3.
8)20X(0.
5)24X(0.
24)24X(0.
6)METALTYP重重要要声声明明和和免免责责声声明明TI均以"原样"提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示担保.
所述资源可供专业开发人员应用TI产品进行设计使用.
您将对以下行为独自承担全部责任:(1)针对您的应用选择合适的TI产品;(2)设计、验证并测试您的应用;(3)确保您的应用满足相应标准以及任何其他安全、安保或其他要求.
所述资源如有变更,恕不另行通知.
TI对您使用所述资源的授权仅限于开发资源所涉及TI产品的相关应用.
除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权许可.
如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI及其代表造成的损害.
TI所提供产品均受TI的销售条款(http://www.
ti.
com.
cn/zh-cn/legal/termsofsale.
html)以及ti.
com.
cn上或随附TI产品提供的其他可适用条款的约束.
TI提供所述资源并不扩展或以其他方式更改TI针对TI产品所发布的可适用的担保范围或担保免责声明.
IMPORTANTNOTICE邮寄地址:上海市浦东新区世纪大道1568号中建大厦32楼,邮政编码:200122Copyright2020德州仪器半导体技术(上海)有限公司