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AStudyontheHfindependenceofIntrinsicgatedelayinFinFETDaeyounYun,J.
Jang,H.
Y.
Bae,J.
S.
Shin,J.
Lee,H.
Jang,Y.
Hong,W.
H.
Lee,M.
Uhm,H.
Seo,D.
H.
Kim,andD.
M.
KimSchoolofElectricalEngineering,KookminUniversity,Seoul,136-702,KoreaAbstractAcomparativestudyonthetrade-offbetweenthedrivecurrent(ION)andthetotalgatecapacitance(Ctotal)in3-DFinFETsisperformedbyusinga3-Ddevicesimulation.
Astheresult,theintrinsicgatedelay(τ)hastheoptimumpoint(thevalueofτ=252fsatHfin=60nm,Tmask=2nm)withtheincreasingfinheight(Hfin).
ItmeansthattheFinFEThasION-dominantregimeratherthantheCtota-dominantregimeasHfinincreases.
WhentheHfinincreases,ION/HfindecreaseswhileCtotal/Hfinhasaconstantrateandthisisexpectedtobethemaincauseforhavingtheoptimumpointforthegatedelay.
I.
IntroductionInplanarmetal-oxide-semiconductorfield-effecttransistors(MOSFETs),shortchanneleffects(SCEs)havebeenverychallengingtobeefficientlycontrolled.
Ontheotherhand,non-planarthree-dimensional(3-D)MOSFETshavebecomeattractivefortheirgoodcontrolofSCEs,idealsubthresholdslope,andhighdrivecurrent[1,2].
Innano-scaledigitalVLSIcircuits,itisworthwhiletoelaboratelycontroltheintrinsicgatedealy(τ)betweentheinputandtheoutputinordertoestimatetheinfluenceonthecircuitperformance[3,4].
Inthiswork,tosuggestadesignguideforthetopoxidethickness(Tmask)andthefinheight(Hfin)forthegatedelayτ,acomparativestudyonthetrade-offbetweenthedrivecurrent(ION)andthetotalgatecapacitance(Ctotal)in3-Dfin-typeMOSFETs(FinFETs)isperformedbyusingaTCAD3-Ddevicesimulation[5,6].
II.
FundamentalSimulationFrameworkThedevicestructureandgeometricparametersoftheFinFETunderstudyareshowninFig.
1.
Therelationbetweenthegatelength(Lg)andfinwidth(Wfin)isfixedatLG=1.
5*Wfinasthewell-knowncriteriaforidealSCEsinFETs.
ParametersinthedevicesimulationincludeTmask(2~12nm),Hfin(20~120nm)andotherparametersassummarizedinTableI.
IDS-VGSandC-VGScharacteristicsofFinFETsareshowninFig.
2asafunctionofHfinforLG=30nm,Tmask=2nm,Wfin=20nm,andsidewalloxide(Tox)=2nm.
ItisclearthatbothIONandCtotaloftheFinFETwithhighHfinarelargerthanthoseofFinFETwithlowHfin.
III.
SimulationResultsandDiscussionInthissection,theestablishmentofdesignforFinFETsispursuedbyanalyzingthestructuraldependenceofCtotal,ION,andτatasupplyvoltageVDD=1V.
τisestimatedfromthesimulationresultsofCtotalandIONforthegatedelay/totalDDONCVIτ=*definedasafigureofmeritforthisstudy.
TheHfinandTmaskdependenceofτforaFinFETisshowninFig.
3.
WhenHfinincreases,τhasanoptimumpointatHfin=60~80nm.
And,forspecificLgandWfin,thegatedelayτisimprovedasTmaskdecreases.
ThisisbecausethecontributionofIONisdifferentfromthatofCtotalinthedelayasHfinincreases.
Fig.
4showscapacitancecomponentsintheFinFET.
Ctotalconsistsoftheintrinsiccapacitance(Cint)andparasiticcapacitance(Cpar).
Then,CtotalcanbeobtainedfromtotalintparC=C+C(1)'2'intgfinTmaskgfinToxCLWCLHC2)2'2'4'4'parpolyfinTfrovfinTovpolyfinSfrovfinSovCTWCLWCLHCLHC.
(3)withCj'definedasthecapacitanceofCjperunitarea.
Asexpected,CtotalincreaseswiththeincreasesofHfin.
ION/HfinandCtotal/HfinofFinFETsisshowninFig.
5asafunctionofHfinandTmask.
ItshowsthatCtotal/HfinisconstantovertheHfin.
Ontheotherhand,ION/HfindecreaseswithHfin.
ThereasonfortheCtotalisproportionaltoHfin,thereducedION/Hfinistoincreasetheparasiticresistance.
WhentheHfinincrease,chargesfromthebottomofthefinneedtopassthroughthelongdistancetoreachcontactandthenspreadingresistanceincreasesresultinginreducedcurrentdriving[7].
IV.
ConclusionInthiswork,acomparativestudyonthetrade-offbetweenIONandCtotalin3-DFinFETsisreportedbyusinga3-Ddevicesimulation.
Asaresult,τwithHfinhasanoptimumpointforthegatedelay.
ItisobservedthatFinFEThasION-dominantregimeratherandtheCtota-dominantregimeasHfinincreases.
WhentheHfinincreases,ION/HfindecreaseswhileCtotal/Hfinisconstant.
Thisisexpectedtobethemaincauseofhavinganoptimumpointfortheintrinsicgatedelay.
AcknowledgementsThisworkwassupportedbytheNationalResearchFoundation(NRF)grantfundedbytheKoreagovernment(MEST)(No.
2010-0013883and2009–0080344)andtheCADsoftwaresweresupportedbyICDesignEducationCenter(IDEC).
References[1]Leland.
Chang,etal,Proc.
IEEE,vol.
91,no.
11,pp.
1860-1873,Nov.
2003.
[2]C.
R.
Manoj,etal,IEEETrans.
ElectronDevices,vol.
55,no.
2,pp.
609-615,Feb.
2008.
[3]K.
Y.
Kim,etal.
JSTS,vol.
10,no.
2,pp.
1385-1388,June.
2010.
[4]W.
WuandM.
Chan,IEEETrans.
ElectronDevices,vol.
54,no.
4,pp.
242-250,Apr.
2007[5]SynopsysSentaurusStructureEditorUserGuide,2010,Synopsys,MountainView,CA.
[6]SynopsysSentaurusDeviceUserGuide,2010,Synopsys,MountainView,CA.
[7]H.
Kawasaki,etal,inTech.
Dig.
IEDM,pp.
289-292,Baltimore,Dec.
2009Fig.
1.
Thedevicestructureandgeometricparametersofthesingle-finFET.
TherelationbetweenLGandWfinLisfixedatG=1.
5*Wfin-0.
50.
00.
51.
00200400600DrainCurrent,ID[A]GateVoltage,VG[V]Hfin=20nmHfin=40nmHfin=60nmHfin=80nmHfin=100nmHfin=120nmWfin=20nmLG=30nmNA=5*1018cm-3Tox=2nmTmask=2nmVDS=1V(a)asthewell-knowncriteriaforidealSCEsinFETs.
-0.
50.
00.
51.
0306090120150180TotalCapacitance,C[aF]GateVoltage,VG[V]Hfin=20nmHfin=40nmHfin=60nmHfin=80nmHfin=100nmHfin=120nmWfin=20nmLg=30nmTmask=2nm(b)Fig.
2.
IDS-VGSandC-VGScharacteristicsofFinFETsasafunctionofHfinforLG=30nm,Wfin=20nm,Tmask=2nm,andTox=2nm.
20406080100120255270285300315330345Tmask=2nmTmask=5nmTmask=10nmTmask=12nmWfin=20nm,LG=30nmNA=5*1018cm-3,VDD=1VTox=2nmIntrinsicgatedelay(Ctotal*VDD/ION),τ[fs]Hfin[nm]Fig.
3.
TheHfin-andTmask-dependenceofτforaFinFET.
WhenHfinSourceDrainGateGateCSfrCToxCSovCSfrCSfrCSfrTboxSourceDrainGateCTfrCTmaskCTovCTfrincreases,τhastheoptimumpointatgatedelay.
Fig.
4.
CapacitancecomponentsforthetotalcapacitanceCtotal.
WhileCTmaskandCToxcorrespondtoCint's,CTfr,CSfr,CTov,andCSovdoCpar4060801001203.
54.
04.
55.
05.
56.
04060801001200.
00.
51.
01.
52.
02.
5Hfin[nm]ION/Hfin[A/nm]Tmask=2nmTmask=5nmTmask=10nmTmask=12nmWfin=20nm,LG=30nmNA=5*1018cm-3,VDD=1VTox=2nmCtotal/Hfin[aF/nm]Hfin[nm]'s.
Fig.
5.
ION/HfinandCtotal/HfinofFinFETsasafunctionofHfin.
AsHfinincreases,ION/HfindecreaseswhileCtotal/Hfinisconstant.
TableI.
VariableparametersinthedevicesimulationLG[nm]Wfin[nm]Tox[nm]Tmask[nm]Hfin[nm]Tpoly[nm]Lpoly[nm]020225101220406080100120Hfin+Tmask20
Jang,H.
Y.
Bae,J.
S.
Shin,J.
Lee,H.
Jang,Y.
Hong,W.
H.
Lee,M.
Uhm,H.
Seo,D.
H.
Kim,andD.
M.
KimSchoolofElectricalEngineering,KookminUniversity,Seoul,136-702,KoreaAbstractAcomparativestudyonthetrade-offbetweenthedrivecurrent(ION)andthetotalgatecapacitance(Ctotal)in3-DFinFETsisperformedbyusinga3-Ddevicesimulation.
Astheresult,theintrinsicgatedelay(τ)hastheoptimumpoint(thevalueofτ=252fsatHfin=60nm,Tmask=2nm)withtheincreasingfinheight(Hfin).
ItmeansthattheFinFEThasION-dominantregimeratherthantheCtota-dominantregimeasHfinincreases.
WhentheHfinincreases,ION/HfindecreaseswhileCtotal/Hfinhasaconstantrateandthisisexpectedtobethemaincauseforhavingtheoptimumpointforthegatedelay.
I.
IntroductionInplanarmetal-oxide-semiconductorfield-effecttransistors(MOSFETs),shortchanneleffects(SCEs)havebeenverychallengingtobeefficientlycontrolled.
Ontheotherhand,non-planarthree-dimensional(3-D)MOSFETshavebecomeattractivefortheirgoodcontrolofSCEs,idealsubthresholdslope,andhighdrivecurrent[1,2].
Innano-scaledigitalVLSIcircuits,itisworthwhiletoelaboratelycontroltheintrinsicgatedealy(τ)betweentheinputandtheoutputinordertoestimatetheinfluenceonthecircuitperformance[3,4].
Inthiswork,tosuggestadesignguideforthetopoxidethickness(Tmask)andthefinheight(Hfin)forthegatedelayτ,acomparativestudyonthetrade-offbetweenthedrivecurrent(ION)andthetotalgatecapacitance(Ctotal)in3-Dfin-typeMOSFETs(FinFETs)isperformedbyusingaTCAD3-Ddevicesimulation[5,6].
II.
FundamentalSimulationFrameworkThedevicestructureandgeometricparametersoftheFinFETunderstudyareshowninFig.
1.
Therelationbetweenthegatelength(Lg)andfinwidth(Wfin)isfixedatLG=1.
5*Wfinasthewell-knowncriteriaforidealSCEsinFETs.
ParametersinthedevicesimulationincludeTmask(2~12nm),Hfin(20~120nm)andotherparametersassummarizedinTableI.
IDS-VGSandC-VGScharacteristicsofFinFETsareshowninFig.
2asafunctionofHfinforLG=30nm,Tmask=2nm,Wfin=20nm,andsidewalloxide(Tox)=2nm.
ItisclearthatbothIONandCtotaloftheFinFETwithhighHfinarelargerthanthoseofFinFETwithlowHfin.
III.
SimulationResultsandDiscussionInthissection,theestablishmentofdesignforFinFETsispursuedbyanalyzingthestructuraldependenceofCtotal,ION,andτatasupplyvoltageVDD=1V.
τisestimatedfromthesimulationresultsofCtotalandIONforthegatedelay/totalDDONCVIτ=*definedasafigureofmeritforthisstudy.
TheHfinandTmaskdependenceofτforaFinFETisshowninFig.
3.
WhenHfinincreases,τhasanoptimumpointatHfin=60~80nm.
And,forspecificLgandWfin,thegatedelayτisimprovedasTmaskdecreases.
ThisisbecausethecontributionofIONisdifferentfromthatofCtotalinthedelayasHfinincreases.
Fig.
4showscapacitancecomponentsintheFinFET.
Ctotalconsistsoftheintrinsiccapacitance(Cint)andparasiticcapacitance(Cpar).
Then,CtotalcanbeobtainedfromtotalintparC=C+C(1)'2'intgfinTmaskgfinToxCLWCLHC2)2'2'4'4'parpolyfinTfrovfinTovpolyfinSfrovfinSovCTWCLWCLHCLHC.
(3)withCj'definedasthecapacitanceofCjperunitarea.
Asexpected,CtotalincreaseswiththeincreasesofHfin.
ION/HfinandCtotal/HfinofFinFETsisshowninFig.
5asafunctionofHfinandTmask.
ItshowsthatCtotal/HfinisconstantovertheHfin.
Ontheotherhand,ION/HfindecreaseswithHfin.
ThereasonfortheCtotalisproportionaltoHfin,thereducedION/Hfinistoincreasetheparasiticresistance.
WhentheHfinincrease,chargesfromthebottomofthefinneedtopassthroughthelongdistancetoreachcontactandthenspreadingresistanceincreasesresultinginreducedcurrentdriving[7].
IV.
ConclusionInthiswork,acomparativestudyonthetrade-offbetweenIONandCtotalin3-DFinFETsisreportedbyusinga3-Ddevicesimulation.
Asaresult,τwithHfinhasanoptimumpointforthegatedelay.
ItisobservedthatFinFEThasION-dominantregimeratherandtheCtota-dominantregimeasHfinincreases.
WhentheHfinincreases,ION/HfindecreaseswhileCtotal/Hfinisconstant.
Thisisexpectedtobethemaincauseofhavinganoptimumpointfortheintrinsicgatedelay.
AcknowledgementsThisworkwassupportedbytheNationalResearchFoundation(NRF)grantfundedbytheKoreagovernment(MEST)(No.
2010-0013883and2009–0080344)andtheCADsoftwaresweresupportedbyICDesignEducationCenter(IDEC).
References[1]Leland.
Chang,etal,Proc.
IEEE,vol.
91,no.
11,pp.
1860-1873,Nov.
2003.
[2]C.
R.
Manoj,etal,IEEETrans.
ElectronDevices,vol.
55,no.
2,pp.
609-615,Feb.
2008.
[3]K.
Y.
Kim,etal.
JSTS,vol.
10,no.
2,pp.
1385-1388,June.
2010.
[4]W.
WuandM.
Chan,IEEETrans.
ElectronDevices,vol.
54,no.
4,pp.
242-250,Apr.
2007[5]SynopsysSentaurusStructureEditorUserGuide,2010,Synopsys,MountainView,CA.
[6]SynopsysSentaurusDeviceUserGuide,2010,Synopsys,MountainView,CA.
[7]H.
Kawasaki,etal,inTech.
Dig.
IEDM,pp.
289-292,Baltimore,Dec.
2009Fig.
1.
Thedevicestructureandgeometricparametersofthesingle-finFET.
TherelationbetweenLGandWfinLisfixedatG=1.
5*Wfin-0.
50.
00.
51.
00200400600DrainCurrent,ID[A]GateVoltage,VG[V]Hfin=20nmHfin=40nmHfin=60nmHfin=80nmHfin=100nmHfin=120nmWfin=20nmLG=30nmNA=5*1018cm-3Tox=2nmTmask=2nmVDS=1V(a)asthewell-knowncriteriaforidealSCEsinFETs.
-0.
50.
00.
51.
0306090120150180TotalCapacitance,C[aF]GateVoltage,VG[V]Hfin=20nmHfin=40nmHfin=60nmHfin=80nmHfin=100nmHfin=120nmWfin=20nmLg=30nmTmask=2nm(b)Fig.
2.
IDS-VGSandC-VGScharacteristicsofFinFETsasafunctionofHfinforLG=30nm,Wfin=20nm,Tmask=2nm,andTox=2nm.
20406080100120255270285300315330345Tmask=2nmTmask=5nmTmask=10nmTmask=12nmWfin=20nm,LG=30nmNA=5*1018cm-3,VDD=1VTox=2nmIntrinsicgatedelay(Ctotal*VDD/ION),τ[fs]Hfin[nm]Fig.
3.
TheHfin-andTmask-dependenceofτforaFinFET.
WhenHfinSourceDrainGateGateCSfrCToxCSovCSfrCSfrCSfrTboxSourceDrainGateCTfrCTmaskCTovCTfrincreases,τhastheoptimumpointatgatedelay.
Fig.
4.
CapacitancecomponentsforthetotalcapacitanceCtotal.
WhileCTmaskandCToxcorrespondtoCint's,CTfr,CSfr,CTov,andCSovdoCpar4060801001203.
54.
04.
55.
05.
56.
04060801001200.
00.
51.
01.
52.
02.
5Hfin[nm]ION/Hfin[A/nm]Tmask=2nmTmask=5nmTmask=10nmTmask=12nmWfin=20nm,LG=30nmNA=5*1018cm-3,VDD=1VTox=2nmCtotal/Hfin[aF/nm]Hfin[nm]'s.
Fig.
5.
ION/HfinandCtotal/HfinofFinFETsasafunctionofHfin.
AsHfinincreases,ION/HfindecreaseswhileCtotal/Hfinisconstant.
TableI.
VariableparametersinthedevicesimulationLG[nm]Wfin[nm]Tox[nm]Tmask[nm]Hfin[nm]Tpoly[nm]Lpoly[nm]020225101220406080100120Hfin+Tmask20
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