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EnglishDataSheet:SBAS940DAC8742HZHCSJ40–DECEMBER2018DAC8742HHART和和FOUNDATION现现场场总总线线/PROFIBUSPA调调制制解解调调器器11特特性性1兼容HART的物理层调制解调器–1200/2200HzHARTFSK正弦波–TX信号振幅的寄存器编程控制(仅适用于DAC8741H/DAC8742H)–集成式RX解调器和带通滤波器,具有极少的外部组件兼容FOUNDATION现场总线的H1控制器和介质连接单元(MAU)–基于曼彻斯特编码总线供电(MBP)的31.
25kbit/s通信–集成曼彻斯特编码器和解码器–与PROFIBUSPA兼容低静态电流:最大值180uA,典型工业工作温度范围(-40°C至85°C)集成1.
5V电压基准灵活的时钟选项–内部振荡器–外部晶体振荡器–外部CMOS时钟数字接口–DAC8742H:UART和SPI可靠性:CRC位错校验、看门狗计时器宽工作温度范围:-55°C至125°C5mmx5mmTQFP封装2应应用用工业过程控制和自动化PLC或DCSI/O模块现场和传感器发送器3说说明明DAC8742H是一款HART、FOUNDATION现场总线和PROFIBUSPA兼容的低功耗调制解调器,适用于工业过程控制和工业自动化数据隔离.
在HART模式下,DAC8742H集成所有必需电路,以作为一个半双工HART物理层调制解调器,在从配置或主配置中使用最少的外部过滤组件运行.
在FOUNDATION现场总线模式下,DAC8742H集成所有必需电路,以作为兼容FOUNDATION现场总线的半双工H1控制器和MAU运行.
在HART、FOUNDATION现场总线或PROFIBUSPA模式下,可通过UART接口或SPI接口接入的集成式FIFO传输来自微控制器的数据流.
SPI接口包括一个支持菊链的SDO引脚、各种中断以及其他扩展特性.
器器件件信信息息(1)器器件件型型号号封封装装封封装装尺尺寸寸((标标称称值值))DAC8742HTQFP(32)5mm*5mm(1)如需了解所有可用封装,请参阅数据表末尾的可订购产品附录.
空白空白简简化化原原理理图图2DAC8742HZHCSJ40–DECEMBER2018www.
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cnCopyright2018,TexasInstrumentsIncorporated目目录录1特特性性.
12应应用用.
13说说明明.
14修修订订历历史史记记录录25PinConfigurationandFunctions.
36Specifications.
56.
1AbsoluteMaximumRatings56.
2ESDRatings.
56.
3RecommendedOperatingConditions.
56.
4ThermalInformation.
66.
5ElectricalCharacteristics.
66.
6TimingRequirements.
96.
7TypicalCharacteristics.
107DetailedDescription147.
1Overview147.
2FunctionalBlockDiagram147.
3FeatureDescription.
147.
4DeviceFunctionalModes.
177.
5RegisterMaps.
218ApplicationandImplementation288.
1ApplicationInformation.
288.
2TypicalApplication309PowerSupplyRecommendations.
3410Layout.
3510.
1LayoutGuidelines3510.
2LayoutExample3511器器件件和和文文档档支支持持3711.
1文档支持3711.
2接收文档更新通知3711.
3社区资源.
3711.
4商标.
3711.
5静电放电警告.
3711.
6术语表3712机机械械、、封封装装和和可可订订购购信信息息.
374修修订订历历史史记记录录日日期期修修订订版版本本说说明明2018年12月*DAC8742H独立数据表的初始发行版.
3DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018Copyright2018,TexasInstrumentsIncorporated5PinConfigurationandFunctionsPBSPackage32-PinTQFPTopViewPinFunctionsPINI/ODESCRIPTIONNAMENO.
XEN2DigitalInputCrystalOscillatorEnable.
Logiclowonthispinenablesthecrystaloscillatorcircuit;inthismodeanexternalcrystalisrequired.
Logichighonthispindisablestheinternalcrystaloscillatorcircuit;inthismodeanexternalCMOSclockortheinternaloscillatorarerequired.
Nodigitalinputpinshouldbeleftfloating.
CLKO3DigitalOutputClockOutput.
Ifusingtheinternaloscillatororanexternalcrystal,thispincanbeconfiguredasaclockoutput.
CLK_CFG04DigitalInputClockConfigurationPin.
Thispinisusedtoconfiguretheinput/outputclockingscheme.
Nodigitalinputpinshouldbeleftfloating.
CLK_CFG15DigitalInputClockConfigurationPin.
Thispinisusedtoconfiguretheinput/outputclockingscheme.
Nodigitalinputpinshouldbeleftfloating.
RST6DigitalInputReset.
LogiclowonthispinplacestheDAC8742Hintopower-downmodeandresetsthedevice.
Logichighreturnsthedevicetonormaloperation.
Nodigitalinputpinshouldbeleftfloating.
4DAC8742HZHCSJ40–DECEMBER2018www.
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cnCopyright2018,TexasInstrumentsIncorporatedPinFunctions(continued)PINI/ODESCRIPTIONNAMENO.
CD/IRQ7DigitalOutputUARTModeHARTModeCarrierdetect.
Alogichighonthispinindicatesavalidcarrierispresent.
FF/PAModeWhilenottransmitting,alogichighonthispinindicatesavalidcarrierispresent.
Whiletransmitting,alogichighonthispinindicatesthatthejabberinhibitorhastriggered.
SPIModeDigitalInterrupt.
Theinterruptcanbeconfiguredasedgesensitiveorlevelsensitivewithpositiveornegativepolarity,assetbytheCONTROLregister.
EventsthattriggeraninterruptarecontrolledbytheModemIRQMaskregister.
IF_SEL9DigitalInputInterfaceselect.
AlogichighonthispinconfiguresthedeviceforSPImode.
AlogiclowonthispinconfiguresthedeviceforUARTmode.
Aninternalpull-downresistorisincluded.
Nodigitalinputpinshouldbeleftfloating.
UART_IN/CS10DigitalInputUARTModeUARTdatainput.
SPIModeSPIchip-select.
DatabitsareclockedintotheserialshiftregisterwhenCSislow.
WhenCSishigh,SDOisinahigh-impedancestateanddataonSDIareignored.
Nodigitalinputpinshouldbeleftfloating.
Nodigitalinputpinshouldbeleftfloating.
UART_RTS/SCLK11DigitalInput,DigitalOutputUARTModeHARTModeRequesttosendalogichighonthispinenablesthedemodulatoranddisablesthemodulator.
Alogiclowonthispinenablesthemodulatoranddisablesthedemodulator.
Nodigitalinputpinshouldbeleftfloating.
FF/PAModeThispinreportstransmitFIFOthresholdinformationasprogrammedbythepacketinitiationcode.
SPIModeSPIclock.
Datacanbetransferredatratesupto12.
5MHz.
Schmitt-Triggerlogicinput.
DUPLEX/SDI12DigitalOutputUARTModeDigitalinput.
Logichighenablesfull-duplex,orinternalloop-back,testmode.
SPIModeSPIdatainput.
Dataisclockedintothe24-bitinputshiftregisteronthefallingedgeoftheserialclockinput.
Schmitt-Triggerlogicinput.
UART_OUT/SDO13DigitalOutputUARTModeUARTdataoutput.
SPIModeSPIdataoutput.
DataisvalidonthefallingedgeofSCLK.
IOVDD14SupplyInterfacesupply.
Supplyvoltagefordigitalinputandoutputcircuitry.
Thisvoltagesetsthelogicalthresholdsforthedigitalinterface.
GND15SupplyDigitalground.
Groundreferencevoltageforalldigitalcircuitryofthedevice.
REG_CAP18AnalogOutputCapacitorforinternalregulator.
MOD_OUT19AnalogOutputModemoutput.
FSKoutputsinusoidinHARTmodeorManchestercodeddatastreaminFOUNDATIONFieldbusandPROFIBUSPAmodes.
Requiresparallelcapacitanceof5-22nFinHARTmodeor0-100pFinFOUNDATIONFieldbusandPROFIBUSPAmodeforstability.
REF20AnalogInputorOutputWhentheinternalreferenceisenabledthispinoutputstheinternalreferencevoltage.
Whentheinternalreferenceisdisabled,thisistheexternal2.
5Vreferenceinput.
MOD_IN21AnalogInputHARTFSKinputorFOUNDATIONFieldbusandPROFIBUSPAManchestercodeddatastreaminput.
Ifanexternalfilterisused,donotconnectthispin.
MOD_INF22AnalogInputIfusingtheinternalband-passfilter,connect680pFtothispinor120pFinFOUNDATIONFieldbusandPROFIBUSPAmodes.
Ifusinganexternalfilter,connecttheoutputofthatfiltertothispin.
AVDD23SupplyPowersupply.
GND26SupplyAnalogground.
Groundreferencevoltageforpowersupplyinput.
X227AnalogInputCrystalstimulus.
X128AnalogInputCrystal/Clockinput.
GND29SupplyDigitalground.
Groundreferencevoltageforalldigitalcircuitryofthedevice.
REF_EN30DigitalInputReferenceenable.
Logichighenablestheinternal1.
5Vreference.
Nodigitalinputpinshouldbeleftfloating.
5DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018Copyright2018,TexasInstrumentsIncorporatedPinFunctions(continued)PINI/ODESCRIPTIONNAMENO.
BPF_EN31DigitalInputFilterenable.
Alogichighenablestheinternalband-passfilter.
Nodigitalinputpinshouldbeleftfloating.
NC1,8,16,17,24,25,32–Donotconnectthesepins.
(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditions.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
6Specifications6.
1AbsoluteMaximumRatingsOveroperatingfree-airtemperaturerange(unlessotherwisenoted)(1)MINMAXUNITInputvoltageAVDDtoGND-0.
36VIOVDDtoGND-0.
36AnalogoutputvoltagetoGND-0.
3AVDD+0.
3DigitaloutputvoltagetoGND-0.
3IOVDD+0.
3OutputvoltageAnalogoutputpintoGND-0.
3AVDD+0.
3VDigitaloutputpintoGND-0.
3IOVDD+0.
3InputCurrentInputcurrenttoanypinexceptsupplypins-1010mAOperatingjunctiontemperature,TJ-55125°CJunctiontemperaturerange(TJmax)150Storagetemperature,Tstg-60150(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2)JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
6.
2ESDRatingsVALUEUNITV(ESD)ElectrostaticdischargeHumanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1)±8000VChargeddevicemodel(CDM),perJEDECspecificationJESD22-C101,allpins(2)±15006.
3RecommendedOperatingConditionsOveroperatingfree-airtemperaturerange(unlessotherwisenoted)MINNOMMAXUNITPOWERSUPPLYAVDD2.
75.
5VIOVDD1.
715.
5VANALOGINPUTSExternalReferenceInputVoltage2.
3752.
52.
625VDIGITALINPUTSExternalClockSourceFrequency(HARTMode)3.
6864MHzClock3.
64693.
68643.
7232MHz1.
2288MHzClock1.
21651.
22881.
2411MHz6DAC8742HZHCSJ40–DECEMBER2018www.
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cnCopyright2018,TexasInstrumentsIncorporatedRecommendedOperatingConditions(continued)Overoperatingfree-airtemperaturerange(unlessotherwisenoted)MINNOMMAXUNITExternalClockSourceFrequency(FF/PAModes)3.
9644.
04MHz(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplicationreport,SPRA953.
6.
4ThermalInformationTHERMALMETRIC(1)DAC8742HUNITPBS(TQFP)32PINRθJAJunction-to-ambientthermalresistance79.
7°C/WRθJC(top)Junction-to-case(top)thermalresistance19.
3°C/WRθJBJunction-to-boardthermalresistance33.
2°C/WΨJTJunction-to-topcharacterizationparameter0.
5°C/WΨJBJunction-to-boardcharacterizationparameter32.
9°C/WRθJC(bot)Junction-to-case(bottom)thermalresistancen/a°C/W6.
5ElectricalCharacteristicsAllspecificationsover-40°Cto+125°Cambientoperatingtemperature,2.
7V≤AVDD≤5.
5V,1.
71V≤IOVDD≤5.
5V,InternalReference,InternalFilter,unlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITPOWERREQUIREMENTSIOVDD1.
715.
5VAVDD2.
75.
5VAVDDandIOVDDSupplyCurrent(HARTMode)DemodulatoractiveExternalClock,-40°Cto85°C110150AExternalClock,-55°Cto125°C220AExternalClock,-40°Cto85°C,ExternalReference100140AExternalClock,-55°Cto125°C,ExternalReference210AModulatoractiveExternalClock,-40°Cto85°C160180AExternalClock,-55°Cto125°C250AExternalClock,-40°Cto85°C,ExternalReference150170AExternalClock,-55°Cto125°C,ExternalReference240ACrystalOscillatorExternalCrystal,16pFatXTAL1andXTAL24065AExternalCrystal,36pFatXTAL1andXTAL24065AInternalOscillatorExternalReference105180ASPIInterfaceAdditionalquiescentcurrentrequiredwheninterfacingviaSPI5AAVDDandIOVDDSupplyCurrent(FF/PAMode)DecoderactiveExternalClock,-40°Cto85°C160220AExternalClock,-55°Cto125°C330AExternalClock,-40°Cto85°C,ExternalReference175200AExternalClock,-55°Cto125°C,ExternalReference320AEncoderactiveExternalClock,-40°Cto85°C175250AExternalClock,-55°Cto125°C360AExternalClock,-40°Cto85°C,ExternalReference165235AExternalClock,-55°Cto125°C,ExternalReference350A7DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018Copyright2018,TexasInstrumentsIncorporatedElectricalCharacteristics(continued)Allspecificationsover-40°Cto+125°Cambientoperatingtemperature,2.
7V≤AVDD≤5.
5V,1.
71V≤IOVDD≤5.
5V,InternalReference,InternalFilter,unlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITCrystalOscillatorExternalCrystal,16pFatXTAL1andXTAL24065AExternalCrystal,36pFatXTAL1andXTAL24065ASPIInterfaceAdditionalquiescentcurrentrequiredwheninterfacingviaSPI5AAVDDandIOVDDSupplyCurrent(AllModes)Power-DownModeInternalreferencedisabled,-40°Cto85°C,noactiveclockinput3060AInternalreferencedisabled,-55°Cto125°C,noactiveclockinput182ACLOCKREQUIREMENTSEXTERNALCLOCK(HARTMODE)ExternalClockSourceFrequency3.
6864MHzClock3.
64693.
68643.
7232MHz1.
2288MHzClock1.
21651.
22881.
2411MHzEXTERNALCLOCK(FF/PAMODE)ExternalClockSourceFrequency4MHzClock3.
9644.
04MHzINTERNALOSCILLATORFrequency-40°Cto125°C1.
21651.
22881.
2411MHzVOLTAGEREFERENCEINTERNALREFERENCEVOLTAGEInternalReferenceVoltage1.
471.
51.
53VLoadRegulation1.
3V/mACapacitiveLoadGuaranteedbydesign1FOPTIONALEXTERNALREFERENCEVOLTAGEExternalReferenceInputVoltage2.
3752.
52.
625VExternalReferenceInputCurrentDemodulator4.
5AModulator4.
5AInternalOscillator4.
5APower-Down4.
5AHARTMODEMMOD_ININPUT(HARTMODE)InputVoltageRangeExternalReferenceSource,guaranteedbydesign.
SignalappliedattheinputtotheDCblockingcapacitor.
01.
5Vp-pInternalReferenceSource,guaranteedbydesign.
SignalappliedattheinputtotheDCblockingcapacitor.
01.
5Vp-pReceiverSensitivityThresholdforsuccessfulcarrierdetectionanddemodulation,assumingidealsinusoidalinputFSKsignalswithvalidpreambleusinginternalfilter.
80100120mVp-pMOD_OUTOUTPUT(HARTMODE)OutputVoltageAC-coupled(2.
2F),measuredatMOD_OUTpinwith160Ωload450460480mVp-pMarkFrequencyInternalOscillator1200HzSpaceFrequencyInternalOscillator2200HzFrequencyErrorInternalOscillator,-40°Cto125°C-11%PhaseContinuityErrorGuaranteedbydesign0Degrees8DAC8742HZHCSJ40–DECEMBER2018www.
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cnCopyright2018,TexasInstrumentsIncorporatedElectricalCharacteristics(continued)Allspecificationsover-40°Cto+125°Cambientoperatingtemperature,2.
7V≤AVDD≤5.
5V,1.
71V≤IOVDD≤5.
5V,InternalReference,InternalFilter,unlessotherwisenoted.
PARAMETERTESTCONDITIONSMINTYPMAXUNITMinimumResistiveLoad160Ω,ACcoupledwith2.
2F,guaranteedbydesign160ΩTransmitImpedanceRTSlow,measuredattheMOD_OUTpin,1mAmeasurementcurrent13ΩRTShigh,measuredattheMOD_OUTpin,±200nAmeasurementcurrent250kΩFF/PAMODEMMOD_ININPUT(FF/PAMODE)InputVoltageRangeExternalReferenceSource,specifiedbydesign.
SignalappliedattheinputtotheDCblockingcapacitor.
01Vp-pInternalReferenceenabled,specifiedbydesign.
SignalappliedattheinputtotheDCblockingcapacitor.
01Vp-pReceiverJitterToleranceEdge-to-edgemeasurementofManchesterEncodedwaveforms-3.
23.
2sReceiverSensitivityThresholdforsuccessfulcarrierdetectionanddecoding,assumingidealManchesterEncodedinputtrapezoidalsignalswith6srisetime,validpreamblebyte(s)andstartdelimiterbyte,usinginternalfilter.
75mVp-pMOD_OUTOUTPUT(FF/PAMODE)OutputVoltage800mVp-pMaximumAmplitudeDifferenceMaximumdifferenceinpositiveandnegativeamplitudesignals-5050mVTransmitBitRate31.
187531.
2531.
3125kbit/sTransmitJitterMeasuredwithrespecttoidealcrossingofhightimeandlowtime-0.
80.
8sOutputSignalDistortionMeasuredpeaktotroughdistortionforpositiveandnegativeamplitudevoltageoutputs-1010%RiseandFallTime10%to90%ofpeaktopeaksignal8sSlewRate10%to90%ofpeaktopeaksignal0.
2V/sDIGITALREQUIREMENTSDIGITALINPUTSVIH,InputHighVoltage0.
7xIOVDDVVIL,InputLowVoltage0.
3xIOVDDVCLK_CFG0,InputHighVoltageGuaranteedbydesign0.
8xIOVDDVCLK_CFG0,InputMid-ScaleVoltageGuaranteedbydesign0.
4xIOVDD0.
55xIOVDDVCLK_CFG0,InputLowVoltageGuaranteedbydesign0.
15xIOVDDInputCurrent-11AInputCapcitance5pFDIGITALOUTPUTSVOH,OutputHighVoltage200Asource/sinkIOVDD-0.
5VVOL,OutputLowVoltage200Asource/sink0.
4V9DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporated(1)TimebetweentwoconsecutiveCSrisingedgesmustbe≥3.
06s6.
6TimingRequirementsAlltimingconditionsguaranteedbydesignPARAMETERMINNOMMAXUNITtcSCLKCycleTime80nstw1SCLKHighTime32nstw2SCLKLowTime32nstsu/CStoSCLKFallingEdgeSetupTime32nstsu1DataSetupTime5nsth1DataHoldTime5nstd1SCLKFallingEdgeto/CSRisingEdge32nstw3Minimum/CSHighTime(1)1ustvSCLKRisingEdgetoSDOValid32nstrstResetlowtime100nsHARTModeTimingtcstartCarrierstarttime.
TimefromRTSfallingedgetotransmitcarrierreachingitsfirstpeak.
5Bit-TimestcstopCarrierstoptime.
TimefromRTSrisingedgetotransmitcarrieramplitudefallingbelowthereceiveamplitude3Bit-TimestcdecayCarrierdecaytime.
TimefromRTSridingedgetocarrieramplitudedroppingtozero.
6Bit-TimestcdetonCarrierdetecton.
TimefromvalidcarrieronreceivepathtoCDrisingedge.
6Bit-Timestcdetoff1Carrierdetectoff.
TimefromvalidcarrierremovedonreceivepathtoCDfallingedge.
3mstcdetoff2Carrierdetectonwhentransitioningfromtransmitmodetoreceivemodeinthepresenceofaconstantvalidreceivecarrier.
2.
1mstcos1Crystaloscillatorpower-uptimefromenablingtheoscillatorviaclockconfigurationpinswith16pFloadcapacitors.
25mstcos2Crystaloscillatorpower-uptimefromenablingtheoscillatorviaclockconfigurationpinswith36pFloadcapacitors.
25mstrefReferencepower-uptimefromenablingviahardwarepin.
10mstpowTransitiontimefrompower-downmodetonormaloperatingmodewithexternalclockandexternalreference.
30s图图1.
SPITimingDiagram10DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporated6.
7TypicalCharacteristics图图2.
HARTModeExternalBand-PassFilterResponse图图3.
HARTModeInternalBand-PassFilterResponse图图4.
FF/PAModeExternalBand-PassFilterResponse图图5.
FF/PAModeInternalBand-PassFilterResponse图图6.
InternalReferenceVoltageversusAVDD图图7.
InternalReferenceVoltageversusTemperature11DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporatedTypicalCharacteristics(接接下下页页)图图8.
HARTTXCarrierStartTime图图9.
HARTTXCarrierStop/DecayTime图图10.
HARTRXCarrierDetectOffTiming图图11.
HARTRXCarrierDetectOnTiming图图12.
HARTModeIOVDDSupplyCurrentversusVoltagewithExternalReference图图13.
HARTModeAVDDSupplyCurrentversusVoltagewithExternalReference12DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporatedTypicalCharacteristics(接接下下页页)图图14.
HARTModeIOVDDSupplyCurrentversusVoltagewithInternalReference图图15.
HARTModeAVDDSupplyCurrentversusVoltagewithInternalReference图图16.
FF/PAModeIOVDDSupplyCurrentversusVoltagewithExternalReference图图17.
FF/PAModeAVDDSupplyCurrentversusVoltagewithExternalReference图图18.
FF/PAModeIOVDDSupplyCurrentversusVoltagewithInternalReference图图19.
FF/PAModeAVDDSupplyCurrentversusVoltagewithInternalReference13DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporatedTypicalCharacteristics(接接下下页页)图图20.
TypicalManchesterEncodedTrapezoid,NoFilter图图21.
TypicalManchesterEncodedTrapezoid,withSuggestedFilterResponse图图22.
MOD_OUTVoltageversusRLOAD14DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporated7DetailedDescription7.
1OverviewTheDAC8742HisaHARTcompliantandFOUNDATIONFieldbusorPROFIBUSPAcompatiblelowpowermodemdesignedforindustrialprocesscontrolandindustrialautomationapplications.
InHARTmode,theDAC8742Hintegratesalloftherequiredcircuitrytooperateashalf-duplexHARTphysicallayermodems,ineitherslaveormasterconfigurationswithminimalexternalcomponentsforfiltering.
InFOUNDATIONFieldbusmode,theDAC8742Hintegratealloftherequiredcircuitrytooperateashalf-duplexFOUNDATIONFieldbuscompliantH1Controllers&MAUs.
TheHART,FOUNDATIONFieldbus,orPROFIBUSPA,datastreamcanbetransferredfromthemicrocontrollerthrougheitheraUARTinterfaceoranintegratedFIFOaccessedbyaSPIinterface.
TheSPIinterfaceincludesanSDOpinfordaisy-chainsupport,variousinterrupts,andotherextendedfeatures.
7.
2FunctionalBlockDiagram7.
3FeatureDescription7.
3.
1HARTModulatorInSPImode,HARTdataisloadedintoatransmitFIFOviatheSPIserialinterface.
InUARTmode,theUARTBAUDratematchestheHARTBAUDrateandthereforetheFIFOisbypassed.
Inbothcasestheinputdataistranslatedintothemarkandspace,1200Hzand2200Hzrespectively,frequencyshiftkeyed(FSK)analogsignalsusedinHARTcommunicationthroughaninternalHARTmodulator.
TheHARTmodulatorimplementsalook-uptablecontaining326-bitsignedvalueswhichrepresentasinglephasecontinuoussinusoidalcycle.
AcounterisimplementedthatincrementallyloadsthetablevaluestoaDigital-to-AnalogConverter(DAC),ataclockfrequencydeterminedbythebinaryvalueoftheinputdata,inordertocreatethemarkandspaceanalogoutputsignalsusedtorepresentHARTdata.
Themodemoperatesinhalf-duplexmode,unlessplacedinfull-duplexmode,wherethemodulatoranddemodulatorarenotactivesimultaneously.
Themodemarbitratesoverwhichcomponentisactive.
TorequestthatthemodulatorisactivatedUARTdevicestoggletheRTSpinlow,SPIdevicestoggletheRTSbitintheMODEMCONTROLregister.
ThesemechanicsareexplainedinmoredetailintherespectivesectionsofDeviceFunctionalModes.
InHARTmodetheMOD_OUTpinrequiresparallelcapacitanceof5-22nFor0-100pFinFOUNDATIONFieldbusandPROFIBUSPAmodeforstability.
15DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporatedFeatureDescription(接接下下页页)7.
3.
2HARTDemodulatorTheHARTdemodulatorconvertstheHARTFSKinputsignalsappliedattheMOD_INorMOD_INFpins,dependingonwhetheranexternalfilterisimplemented,tobinarydatathatisloadedintoareceiveFIFOinSPImode.
DatainthereceiveFIFOcanthenbereadbythehostcontrollerviaSPIserialinterface.
InUARTmodereceiveddataisdirectlyfedthroughtotheUARTinterface.
WhenavalidcarrierisdetectedondevicesusingtheUARTinterfaces,theCDpinwilltogglehigh.
FordevicesusingtheSPIinterface,theIRQpinwilltoggleindicatinganalarmcondition.
TheMODEMSTATUSregistercanthenbereadtodeterminethesourceoftheinterrupt,whichincludesabitforcarrierdetectioninDB1.
Hysteresisisimplementedwiththecarrierdetectfeatureinordertopreventerroneouscarrierdetectionsignals.
MoredetailsareexplainedintherespectiveDeviceFunctionalModessections.
7.
3.
3FOUNDATIONFIELDBUS/PROFIBUSPAManchesterEncoderFOUNDATIONFIELDBUSorPROFIBUSPAdataisloadedintoatransmitFIFOviaUARTorSPIinterfaceswhichistranslatedintotheManchesterencodedbinaryanalogsignalsusedinbothFOUNDATIONFIELDBUSandPROFIBUSPAbusprotocolsthroughaninternalManchesterencoder.
TheManchesterencoderinteractswiththeDACtotransmitpositiveandnegativeamplitudesignals,withrespecttoapositivecommonmodevoltage,tocreatetheManchesterencodedanalogoutputsat31.
25kHzBAUD.
Abinary0isrepresentedbyalow-to-hightransitionandabinary1isrepresentedbyahigh-to-lowtransition.
InbothUARTandSPIinterfaceddevice,theencoderisactivatedanytimethereisdataavailableinthetransmitFIFOandthedecoderisnotreceivingdata.
InordertopreventFIFObufferoverflow,forUARTmodetheCDpinactsasaninterrupttoindicatewhentheFIFOlevelhasexceedaprogrammedthresholdinthepacketinitiationcode.
InSPImodethetransmitFIFOthresholdprogrammedintheFIFOLEVELSETregistercantriggeraninterruptontheIRQpin.
OncetheIRQinterruptsistriggered,theMODEMSTATUSregistercanthenbereadtodeterminethesourceoftheinterrupt,whichincludesabitfortheFIFOlevelinDB4.
MoredetailsareexplainedintherespectiveDeviceFunctionalModessections.
7.
3.
4FOUNDATIONFIELDBUS/PROFIBUSPAManchesterDecoderTheFOUNDATIONFIELDBUSandPROFIBUSPAdecoderconvertstheManchesterencodeddataappliedattheMOD_INorMOD_INFpins,dependingonwhetheranexternalfilterisimplemented,tobinarydatathatisloadedintoareceiveFIFO.
DatainthereceiveFIFOcanthenbereadbythehostcontrollerviaUARTorSPIserialinterfaces.
Whenvaliddataisprovidedtothedecoder,binarydataisreadoutseriallyontheUARTinterface.
ForSPIdevices,thereceiveFIFOisloadeduntilthethresholdprogrammedinFIFOLEVELSETismetwhichwilltriggeraninterruptontheIRQpin.
TheMODEMSTATUSregistercanthenbereadtodeterminethesourceoftheinterrupt,whichincludesabitfortheFIFOlevelinDB7,indicatingthatdataisreadytobereadontheSPIbus.
MoredetailsareexplainedintherespectiveDeviceFunctionalModessections.
7.
3.
5InternalReferenceAninternalreferenceisincludedintheDAC8742H.
TheREF_ENpinisusedtoenableordisabletheinternalreference,whentheinternalreferenceisdisabledanexternalreferencemustbeprovidedattheREFpin.
InSPImode,thePDVREFbitintheCONTROLregistercanbeusedtoenableordisabletheinternalreferenceviasoftware.
IftheREF_ENpinissethigh,theregistercontentsofthePDVREFbitisignored.
INTERFACEPDVREFREF_ENREFERENCEMODEUART1(Default)0ExternalReferenceUART1(Default)1InternalReferenceSPI1(Default)1InternalReferenceSPI01InternalReferenceSPI1(Default)0ExternalReferenceSPI00ExternalReference16DAC8742HZHCSJ40–DECEMBER2018www.
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3.
6ClockConfigurationAllofthedevicesintheDAC8742HfamilysupportavarietyofclockingoptionsinordertoprovidesystemflexibilityandreduceoverallcurrentconsumptioninHARTapplications.
Theclockingoptionsinclude:aninternaloscillator(HARTmodeonly),anexternalcrystaloscillator,oranexternalCMOSclock.
TheselectionoftheclockingschemeiscontrolledbytheXEN,CLK_CFG1,andCLK_CFG0pinsasdescribedinthetablebelow.
Theinternaloscillatortakesapproximately50mstostartoscillatingfromwhenitisenabled.
Duringthistimeperiodthedeviceisunabletoperformmodulationordemodulationactivities.
表表1.
ClockConfigurationTableXENCLK_CFG1CLK_CFG0CLKODESCRIPTIONMODE100NoOutput3.
6864MHzCMOSclockconnectedatXTAL1HART101NoOutput1.
2288MHzCMOSclockconnectedatXTAL1110NoOutputInternaloscillatorenabled1111.
2288MHzOutputInternaloscillatorenabled,CLKOenabled000NoOutputCrystaloscillatorenabled0013.
6864MHzOutput3.
6864MHzcrystaloscillator,CLKOenabled0101.
8432MHzOutput3.
6864MHzcrystaloscillator,CLKOenabled0111.
2288MHzOutput3.
6864MHzcrystaloscillator,CLKOenabled100.
5NoOutput4MHzCMOSclockconnectedatXTAL1FOUNDATIONFIELDBUS&PROFIBUSPA110.
5NoOutput2MHzCMOSclockconnectedatXTAL1000.
5NoOutput4MHzcrystaloscillator010.
54MHzOutput4MHzcrystaloscillator,CLKOenabled7.
3.
7ResetandPower-DownTheRSTpinfunctionsasbothahardwareresetandapower-down.
Whenthepinisbroughtlowaresetisissued,restoringalldevicecomponentstotheirdefaultstate.
Whilethepiniskeptlow,thedeviceisinapower-downstatewheretheinternalreferenceisdisabled,themodulatoranddemodulatororencoderanddecoderaredisabled,serialdataoutputlinesarehigh-impedance,MOD_OUTimpedanceissetto70k,andtheclockoutputisdisabled.
Ifanexternalcrystaloscillatorisused,thecrystaloscillatorcircuitremainsactivetoreducestart-uptimewhenexitingthepower-downstate.
Clockconfigurationpinsremainactiveinpower-downallowingthecrystaloscillatortobedisabledifdesired.
7.
3.
8Full-DuplexModeInfull-duplexmodethemodulatoranddemodulator(HARTmode)orencoderanddecoder(FOUNDATIONFIELDBUSorPROFIBUSPAmode)aresimultaneouslyenabled.
Thisallowsaself-testfeaturetoverifyfunctionalityofthetransmitandreceivesignalchainstoimprovesystemdiagnostics.
7.
3.
9I/OSelectionTheDAC8742HimplementsbothSPIandUARTinterfaces.
OnlyoneinterfaceisactiveatatimefortheDAC8742H.
TheinterfacemodeisselectedbytheIF_SELpin:alogichighonthispinsetsthedevicetoSPImodeandalogiclowsetsthedevicetoUARTmode.
Aninternalpull-downresistorisincludedtoensurepower-upinaknownstate,bydefaultthepull-downsetstheinterfacetoUARTmode.
IfchangingI/Omodesafterpower-up,aresetcommandshouldbeissuedonRST.
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3.
10JabberInhibitorTheDAC8742HimplementsaJabberInhibitorfeatureinFOUNDATIONFIELDBUSorPROFIBUSPAmodeswhichpreventstheencoderfromcontinuouslytransmittingdataonthebusforlongerthanaprogrammedthresholdcontrolledbytheUARTorSPIinterface.
InSPImodethisthresholdisprogrammedbythePAFF_JABBERregister,inUARTmodethisthresholdisprogrammedbythefourbyteinitializationsequencebeforeeachtransmission.
ThisisdescribedinfurtherdetailintheDeviceFunctionalModesandRegisterMapsections.
7.
4DeviceFunctionalModes7.
4.
1UARTInterfacedHARTWheninterfacingtheHARTmodemviatheUARTinterface,thedevicecanbethoughtofasasimpleUART-to-HARTorHART-to-UARTdirectfeedthroughconverter.
TheUARTdataistransmittedandreceivedat1200BAUD,whichismatchedtotheHARTFSKinputandoutputsignals.
TheHARTcommunicationprotocolisahalf-duplexprotocolwhichmeansthateitherthemodulatorordemodulatorisactive,andneversimultaneouslyenabled.
ThedevicearbitratesoverwhichcomponentofthemodemisactiveatalltimesbasedonactivityontheHARTbus.
BusactivityisinterfacedtothehostcontrollerthroughtheCDandRTSpins.
BydefaultwhenRTSishighthedemodulatorisactiveandthemodulatorisinactive.
Whenavalidcarrierisdetectedanddataisbeingreceivedbythemodem,theCDpinistoggledhighandbinaryUARTdataisprovidedattheoutput.
IfarequesttosendisissuedbytogglingtheRTSpinlowwhileCDishigh,thedemodulatorremainsatpriorityandanydataprovidedattheUARTinputisignored.
WhenCDislownovalidcarrierispresentandwhenRTSisbroughtlowthemodulatorisactivatedandUARTinputdataislatchedintothemodulatorandplacedontotheHARTbus.
7.
4.
2UARTInterfacedFOUNDATIONFIELDBUS/PROFIBUSPAFOUNDATIONFIELDBUSandPROFIBUSPAarehalf-duplexcommunicationprotocolswhereonlytheencoderordecoderareactiveatanytimeandtheDAC8742Harbitratesoverwhichpathisactive.
WheninterfacingtheFOUNDATIONFIELDBUSorPROFIBUSPAmodemviatheUARTinterface,dataplacedinthetransmitFIFOisautomaticallyplacedontheFF/PAbusuntiltheFIFOisemptyanytimethedeviceisnotreceivingdata,assumingcorrectdataformat.
Whenreceivingdatathedecoderwillexpectapreamblebyte(s)andastartdelimiterbyte.
Thesebytes,aswellasthestopbyte,willbestrippedfromtheUARTcommunicationandonlythefirstdatabytewillbetransmittedtostartthedatapacket.
Thehostcontrollermustuseatimertodetecttheendofthepacket.
EachbytetransmittedontheUARTwillbeat57.
6kHzBAUDandbytespacingof256us.
Ifanewbytehasnotbeenstartedwithin512usitcanbeassumedthattheincomingpackethasended.
Thedeviceexpectstoseeafourbytesequencetoinitiatetransmission:0xEAfollowedby0x80-0x9F,wherebits4:3ofthesecondbyteconfigureaninterruptthresholdforthetransmitFIFOlevelandbits2:0setthenumberofpreamblebytestobetransmitted.
ThethirdbytecontainstheinformationtoconfiguretheJabberInhibitorfollowedbythefinalbyteof0xAE.
TosendinvertedManchesterencodeddatathefirstbyte,0xEA,isinvertedto0x15andthefirstthreebitsofthesecondbyteareinvertedsuchthattherangeofvaluesforthesecondbytearefrom0x60-0x7F.
Thefunctionalityofbits4:3and2:0andtheJabberInhibitorbyteremainthesameandthefinalbyteisinvertedto0x51.
Thedetailsconcerningthisfourbytesequenceareexplainedinthetablesbelow.
B3B2ModeD7:D0D7D6D5D4D3D2D1D0Non-inverted11101010100D2M_LEVELPRE_BYTESInverted00010101011D2M_LEVELPRE_BYTES18DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporatedB1B0ModeD7:D0D7D6D5D4D3D2D1D0Non-invertedJABBER_TIMEOUT10101110InvertedJABBER_TIMEOUT01010001CONTROLBITSDESCRIPTIOND2M_LEVEL00AlarmonUART_RTSwhentransmitFIFOhaslessthan2bytesloaded01AlarmonUART_RTSwhentransmitFIFOhaslessthan4bytesloaded10AlarmonUART_RTSwhentransmitFIFOhaslessthan6bytesloaded11AlarmonUART_RTSwhentransmitFIFOhaslessthan8bytesloadedPRE_BYTESNumberofpreamblebytesisequivalenttothestraightbinarydecimalvalueinthisregisterplusoneTheJABBER_TIMEOUTbitscontrolthetimeoutperiodfortheJabberInhibitor.
Ifavalueof0x0isprogrammedtheJabberInhibitorisdisabled.
Otherwisethetimerwillbeprogrammedin2.
048msincrementssuchthatthetimeoutcanbecalculatedasshownbelow.
IftheJabberInhibitortriggerstheCDpinwillbetakenhigh.
TheCDpinwillbereturnedtologiclowwhenthesilenceperiodof3secondshasended.
TimeOut=JABBER_TIMEOUTx2.
048ms(1)Theencoderwillbegintransmittingdataoncethefollowingconditionsaremet:avalidfour-bytetransmissioninitiationsequencehasbeensenttothedevice,theFIFOisnotempty,andthedeviceisnotreceivingdata.
Transmissionwillbeginbysendingthepreamblebyte(s)followedbyastartdelimiter.
Then,theencoderwillbegintoremovedatafromtheFIFO–thiscreatesatleastafive-bytelagoftheencoderwithrespecttotheUART.
DuringtransmissionofapackettheUARTmusttakecaretoensurethattheFIFOdoesnotbecomeemptybeforethepacketiscomplete.
TheencodertransmitsataBAUDrateof31.
25kHzor256sperbyteintheFIFOsotheUARTmustkeepupwiththisrate.
Thefour-bytesequencethatinitiatesatransmissionincludessettingatransmitFIFOthresholdinbits4:3.
WhentheFIFOlevelislessthanorequaltothisthresholdtheUART_RTSpinwillbetakenhigh,thiscanbeleveragedtoensuretheFIFOisnotprematurelyempty.
OncetheFIFOisemptyastopdelimiterisplacedonthebus.
OncetheFIFOisemptyanewpacketcanbeinitiatedwithanewfour-bytetransmissioninitiationsequence.
ThedeviceexpectsUARTBAUDrateof57.
6kHz.
ThisBAUDrateisfasterthanthe31.
25kHzBAUDratespecifiedbyFOUNDATIONFIELDBUSandPROFIBUSPA,thereforeFIFOoverflowispossible.
InordertopreventFIFOoverflow,theUART_RTSpinFIFOthresholdalarmcanbeleveragedbyneveraddingmoredatatotheFIFOthanitcancontainbasedontheprogrammedalarmthreshold.
7.
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3SPIInterfacedHARTWheninterfacingtheHARTmodemviatheSPIinterface,thedeviceutilizestransmitandreceiveFIFOsthatare9-bitswideand16locationsdeeptobufferallHARTdata.
TheHARTcommunicationprotocolishalf-duplexprotocolwhichmeansthateitherthemodulatorordemodulatorisactive,andneversimultaneouslyenabled.
ThedevicearbitratesoverwhichcomponentofthemodemisactiveatalltimesbasedonactivityontheHARTbus.
BusactivityisinterfacedtothehostcontrollerthroughtheIRQpinandMODEMSTATUSregister.
Bydefaultthedemodulatorisactiveandthemodulatorisinactive.
Whenavalidcarrierisdetectedanddataisbeingreceivedbythemodem,theCDbit(bit1)intheMODEMSTATUSregisterissethigh.
IftheCDbit(bit1)intheMODEMIRQMASKregisterissetto0,thiswillalsocausetheIRQpintotoggleasprogrammedinthestatusCONTROLregister.
TheIRQpinmaybeprogrammedtobeedgesensitiveorlevelsensitive,thepolarityofthesignalisalsoprogrammable.
WhentheIRQpintoggles,theMODEMSTATUSregistershouldbereadtodeterminethesourceoftheinterrupt.
ReceivedatacanbereadfromtheRECEIVEFIFObyissuinganSPIreadcommand.
19DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporatedAlternatively,theCDpincanbeignoredbysettingtheCDbit(bit1)intheMODEMIRQMASKregistertoa1.
InthismodetheIRQpinwillnottogglewhentheCDbitintheMODEMSTATUSregisterisa1.
Instead,aRECEIVEFIFOreadeventcanbetriggeredbytheRECEIVEFIFOlevelthreshold.
ThisisachievedbyprogrammingtheFIFOLEVELSETregister(bits7:4)tothedesiredthresholdvaluefrom1-15,ifafullFIFO(level16threshold)isdesiredtheM2DFIFOFULLalarmcanbeusedinstead.
IftheM2DFIFOLEVELbit(bit7)intheMODEMIRQMASKregisterissetto0,theIRQpinwilltoggleandtheMODEMSTATUSregistershouldbereadtodeterminethesourceoftheinterrupt.
ReceivedatacanthenbereadfromtheRECEIVEFIFObyissuinganSPIreadcommand.
IfdataisplacedinthetransmitFIFOwhilethedemodulatorisactiveandtheCDbitishigh,thedataremainsintheFIFOuntilthemodulatorisactivated.
TorequestthatthemodulatorisactivatedandthedemodulatorisdeactivatedtheRTSbit(bit0)intheMODEMCONTROLregistershouldbesethigh.
Whenthemodulatorisactivatedandthedemodulatorisdeactivatedthecleartosend,orCTS,bit(bit0)intheMODEMSTATUSregisterissethigh.
IftheCTSbit(bit0)intheMODEMIRQMASKregisterissettoa0thiswillcausetheIRQpintotoggle,indicatingthattransmitFIFOdatawillbegintobeplacedonthebus.
ThelevelofthetransmitFIFOmaybemonitoredinordertoavoidbufferoverflow.
Thiscanbedoneeitherbywatchingforabufferfullorbufferthresholdevent.
TomonitorbyaFIFOlevelthresholdtheFIFOLEVELSETregister(bits3:0)canbeprogrammedtothedesiredthresholdvaluefrom1-15.
IftheD2MFIFOLEVELbit(bit4)intheMODEMIRQMASKregisterissettoa0,thiswillcausetheIRQpintotoggle.
SimilarlyanalarmcanbetriggeredbasedontheD2MFIFOFULLbitintheMODEMSTATUSregister.
7.
4.
4SPIInterfacedFOUNDATIONFIELDBUS/PROFIBUSPAFOUNDATIONFIELDBUSandPROFIBUSPAarehalf-duplexcommunicationprotocolswhereonlytheencoderordecoderareactiveatanytimeandtheDAC8742Harbitratesoverwhichpathisactive.
WheninterfacingtheFOUNDATIONFIELDBUSorPROFIBUSPAencoderviaSPIinterface,dataisplacedintransmitandreceiveFIFOsthatareeach16-bytesdeeptobufferalldata.
Whenreceivingdatathedecoderwillexpectapreamblebyte(s)andastartdelimiterbyte,followedbythedatabytesforthepacket,andconcludedwithastopdelimiterbyte.
AllofthesebytesareplacedintotheRECEIVEFIFOwherebits7:0representthedataandbit8isusedasaspecialbittoindicatethestartofapacket,withdata0x014D,theendofapacket,withdata0x0126,orahalf-bitslip,withdata0x0100.
Ifahalf-bitslipoccursitisrecommendedtodiscardthepacket.
AtimerisnotnecessarytodetecttheendofreceivingapacketinSPImodebecausethestopdelimiterisincludedintheRECEIVEFIFOdata.
InordertopreventRECEIVEFIFOoverflow,alarmsareavailabletowatchathresholdoftheFIFOorwhentheFIFOisfull.
IftheFIFOisfullitispossiblefordatatobelost.
ThisisachievedbyprogrammingtheFIFOLEVELSETregister(bits7:4)tothedesiredthresholdvaluefrom1-15,ifafullFIFO(level16threshold)isdesiredtheM2DFIFOFULLalarmcanbeusedinstead.
IftheM2DFIFOLEVELbit(bit7)intheMODEMIRQMASKregisterissetto0,theIRQpinwilltoggleandtheMODEMSTATUSregistershouldbereadtodeterminethesourceoftheinterrupt.
ReceivedatacanthenbereadfromtheRECEIVEFIFObyissuinganSPIreadcommand.
Theencoderwillbegintosenddatabysendingthepreamblebyte(s)followedbyastartdelimiterwhentheTRANSMITFIFOisnotemptyandthedeviceisnotreceivingdata.
ThenumberofpreamblebytesusedinthepacketiscontrolledbythePAFFPREAMBLEbits(bits14:12)intheMODEMCONTROLREGISTER.
ThepolarityoftheManchesterencodeddatacanalsobeprogrammedbythePAFFPOLARITYbit(bit15)intheMODEMCONTROLREGISTER.
Aftertransmittingthepreamblebyte(s)andstartdelimitertheencoderwillbegintakingdatafromtheTRANSMITFIFO.
DuringtransmissiontheSPIcontrollermusttakecaretoensurethattheTRANSMITFIFOdoesnotbecomeemptybeforethepacketiscomplete.
WhentheTRANSMITFIFOisemptyastopdelimiterisplacedonthebus.
ThelevelofthetransmitFIFOmaybemonitoredinordertoavoidbufferoverflow.
Thiscanbedoneeitherbywatchingforabufferfullorbufferthresholdevent.
TomonitorbyaFIFOlevelthresholdtheFIFOLEVELSETregister(bits3:0)canbeprogrammedtothedesiredthresholdvaluefrom1-15.
IftheD2MFIFOLEVELbit(bit4)intheMODEMIRQMASKregisterissettoa0,thiswillcausetheIRQpintotoggle.
SimilarlyanalarmcanbetriggeredbasedontheD2MFIFOFULLbitintheMODEMSTATUSregister.
20DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporatedTheJabberInhibitorthresholdcanbeprogrammedbythePAFF_JABBERregister(address0x27).
The8-bitvalueprogrammedinthisregistercanbeusedtocalculatethethresholdusingtheequationbelow.
WhenthetimeouttriggerstheJAB_ONbitintheSTATUSregisterwillbetakenhighandtransmissionwillbeblockedforthe3secondtimeoutperiod.
TheJAB_OFFbitwillgohighwhenthetimeoutperiodhasexpired.
BothJAB_ONandJAB_OFFbitstriggerandIRQevent,meaningtheIRQpinwillbetriggeredforbothevents.
TimeOut=JABBER_TIMEOUTx2.
048ms(2)7.
4.
5Interface7.
4.
5.
1UARTThebehavioroftheUARTinterfacechangesbasedonwhetherthedeviceisoperatinginHARTmodeorinFOUNDATIONFIELDBUSandPROFIBUSPAmode.
InHARTmode,thedeviceexpects1startbit,8databits,1oddparitybit,and1stopbitoran8O1UARTcharacterformat.
ThetransmitpathofthedeviceactsasadirectfeedthroughoftheUARTinputtotheHARTFSKoutput,thereforetheUARTBAUDratefromthehostcontrollermustbe1200Hz±1%asrequiredbytheHARTstandard.
Thereceivepathofthedevicewillalsooperateat1200Hz±1%.
InFOUNDATIONFIELDBUSandPROFIBUSPAmodetheUARTinterfaceexpects1startbit,8databits,noparitybit,and1stopbitoran8N1UARTcharacterformat.
InthismodetheUARTinterfacestransmitandreceiveFIFOssotheBAUDrateisnotrequiredtomatchthe31.
25kHzBAUDusedbyFOUNDATIONFIELDBUSandPROFIBUSPA.
InthismodetheexpectedtransmitandreceiveUARTBAUDis57.
6Hz±2.
5%.
7.
4.
5.
1.
1UARTCarrierDetectThebehaviorofthecarrierdetectorCDpinchangesdependingonwhetherthedeviceisinHARTmodeorFOUNDATIONFIELDBUSandPROFIBUSPAmode.
InHARTmodethepinoperatesasacarrierdetectpin.
WhenavalidcarrierisdetectedandthemodemisreceivingdatatheCDpinistakenhigh.
WhentheCDpinishigh,UARTdatasenttothedeviceandtherequesttosend,orRTS,pinwillbeignoreduntilthecarrierisnolongerpresent.
InFOUNDATIONFIELDBUSandPROFIBUSPAtheCDpinoperatesasacarrierdetectpinwhennotintransmitmode.
WhentheCDpinishigh,UARTdatasenttothedevicewillbeignoreduntilthecarrierisnolongerpresent.
WhenintransmitmodetheCDpinfunctionsasanalarmindicatorthatthejabberinhibitorhastriggeredandfurtherUARTtransmissiondatawillbeignored.
IngeneraliftheCDpinishighthehostcontrollershouldnotbesendingtransmitdatatothedevice.
7.
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5.
2SPITheSPIinterfacecanoperateonSCLKspeedsupto12.
5MHz,buttheframe-ratemustbegreaterthan2442nsinHARTmodeand3000nsinFOUNDATIONFIELDBUSandPROFIBUSPAmode.
Framesmustcontainatleast24-bitswithoutCRCenabledand32-bitswithCRCenabled.
Thedatawithintheframeisrightjustified,meaningthatupontherisingedgeofCStheright-most,orlast,24-bitsor32-bitswillbeevaluatedastheinputdataword.
TwomodesofSPIaresupportedbytheinterface:clockpolarity0andclockphase1orclockpolarity1andclockphase0.
TheSDOpinwilloutputdataontherisingedgeofSCLKorthefallingedgeofCS.
SDOwillalwaysprovideinformationfromthepreviousframe,ifthepreviousframewasareadthentheoutputdatawillbetherequesteddata.
Ifthepreviouswritewasacommandorregisterwrite,thatdatawillberepeated.
Thisallowsamethodfortheusertoverifywhatwaswrittentothedevice.
IfCRCisenabledandwritedataisbeingrepeatedonSDO,theCRCprovidedduringthepreviousframewillbeoutput–notanewlycalculatedCRC.
TheSPIframestructureisshowninthefigurebelow.
Theframeincludesaread/writebit,followedbya7-bitaddress,then16-bitwritedataforawriteframeordon'tcarebitsforareadframe.
IfCRCisenabled,anadditional8-bitsareplacedattheendoftheframecontainingtheCRCword.
R/WFRAMED23D22:16D15:0WriteFrame07-BitAddressWriteDataReadFrame17-BitAddressX21DAC8742Hwww.
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4.
5.
2.
1SPICyclicRedundancyCheckTheSPIinterfaceincludesanoptionalCRCmodetoenhancethereliabilityoftheinterfacebyblockingerroneouscommandssenttothedeviceduetonoiseorothererrorssources.
Whenwritingtoorreadingfromthedevicethelast8-bitsintheframecontaintheCRCwordwhichiscalculatedbasedonthepolynomialx8+x2+x+1.
IfabadCRCwordisincludedinawrite-frametothedevice,theframewillbeignored.
Whenreadingfromthedevice,thehostcontrollershouldchecktheCRCwordtovalidatetheframe.
ReadcommandswithabadCRCvaluewilloutput0x80000000and,inthecaseofareceiveFIFOread,preventdatafromleavingtheFIFOandsubsequentlybeinglost.
7.
4.
5.
2.
2SPIInterruptRequestSPIinterfaceddevicesincludeaninterruptrequest,orIRQ,pintocommunicatetheoccurrenceofavarietyofeventstothehostcontroller.
ThebehavioroftheIRQpiniscontrolledbytheCONTROLregisterandMODEMIRQMASKregister.
TheCONTROLregisterallowsthehostcontrollertoconfiguretheIRQpinaslevelsensitiveoredgesensitiveviatheIRQLEVELbit(bit2).
Forbothlevelsensitiveandedgesensitivemodes,thepolarityoftheIRQpincanbesetviatheIRQPOLARITYbit(bit3)intheCONTROLregister.
TheMODEMIRQMASKregisterallowsthecontrollertodecidewhicheventsareabletotriggertheIRQpintotoggle.
Ifalogic0iswrittentotherespectivebit,thateventisallowedtotoggletheIRQpin.
Ifalogic1iswrittentotherespectivebit,theeventismaskedfromtheIRQpin.
WhenaneventoccurstheIRQpinsignal,inthecaseoflevel-sensitiveconfigurations,islatchedandtheIRQpinvoltagestaysatlogichighuntilthestatushasbeenreset,orcleared,byreadingthecontentsoftheMODEM_STATUSregister.
Inthecaseofedge-sensitiveconfigurationsapulseisgeneratedanytimeaneweventisdetected.
7.
5RegisterMapsTable2liststhememory-mappedregistersfortheDAC8742H.
AllregisteroffsetaddressesnotlistedinTable2shouldbeconsideredasreservedlocationsandtheregistercontentsshouldnotbemodified.
Table2.
DAC8742HRegistersOffsetAcronymRegisterNameSection2hCONTROLCONTROLRegisterGo7hRESETRESETRegisterGo20hMODEM_STATUSMODEMSTATUSRegisterGo21hMODEM_IRQ_MASKMODEMIRQMASKRegisterGo22hMODEM_CONTROLMODEMCONTROLRegisterGo23hFIFO_D2MFIFOD2MRegisterGo24hFIFO_M2DFIFOM2DRegisterGo25hFIFO_LEVEL_SETFIFOLEVELSETRegisterGo27hPAFF_JABBERPAFFJABBERRegisterGoComplexbitaccesstypesareencodedtofitintosmalltablecells.
Table3showsthecodesthatareusedforaccesstypesinthissection.
Table3.
DAC8742HAccessTypeCodesAccessTypeCodeDescriptionReadTypeRRReadWriteTypeWWWriteResetorDefaultValue-nValueafterresetorthedefaultvalue22DAC8742HZHCSJ40–DECEMBER2018www.
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cnCopyright2018,TexasInstrumentsIncorporated7.
5.
1CONTROLRegister(Offset=2h)[reset=0x8042]ThisregistercontrolstheSPIwatch-dogtimer,internalreference,CRCmode,IRQpinbehavior,andSDOpinbehavior.
CONTROLisshowninFigure23anddescribedinTable4.
ReturntoSummaryTable.
Figure23.
CONTROLRegister15141312111098WDTOWDTRESERVEDR/WR/WR76543210RESERVEDPDVREFRESERVEDCRC_ENIRQ_POLIRQ_LEVELSDO_ZSDO_BRR/WRR/WR/WR/WR/WR/WTable4.
CONTROLRegisterFieldDescriptionsBitFieldTypeResetDescription15-13WDTOR/W100SPIWatch-dogTimer(basedon3.
6864MHzClock)D15D14D13TimeoutPeriod00050ms001100ms010500ms0111second1002seconds(default)1013seconds1104seconds1115seconds12WDTR/W00=SPIWatch-dogTimerDisabled(default)1=SPIWatch-dogTimerEnabled11-7RESERVEDR00000Reserved6PDVREFR/W1Thisbitisonlyfunctionalifthehardwarereferenceenabledisenabled.
0=Internalreferenceispowereddown1=Internalreferenceispoweredup(default)5RESERVEDR0Reserved4CRC_ENR/W00=NoCRC(default)1=CRCisenabled3IRQ_POLR/W00=IRQisactivelow(default)1=IRQisactivehigh2IRQ_LEVELR/W00=IRQcreatesapulseforedgesensitivity(default)1=IRQassertstoaleveluntilMODEMSTATUSisread1SDO_ZR/W10=SDOwillbedrivenduringwritesandreadrequests1=SDOwillbeHiZduringwritesrequests(default)0SDO_BR/W00=SDOwillremainfilledfromlastframe(default)1=SDOwillclearwiththebeginningofeachframe23DAC8742Hwww.
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5.
2RESETRegister(Offset=7h)[reset=0x0000]Writing0x0001tothisregisterwillresetallregisterstotheirdefaultvaluesandtheFIFOswillbeemptied.
RESETisshowninFigure24anddescribedinTable5.
ReturntoSummaryTable.
Figure24.
RESETRegister15141312111098RESERVEDR76543210RESERVEDRSTRR/WTable5.
RESETRegisterFieldDescriptionsBitFieldTypeResetDescription15-1RESERVEDR/W000000000000000Reserved0RSTW0Writinga1tothisbittriggersasoftwarereset.
7.
5.
3MODEM_STATUSRegister(Offset=20h)[reset=0x0000]Themodemstatusregisterisaread/writeregister.
Whenaneventoccurs,thecorrespondingbittoindicatethateventissettoalogic1inthisregister.
Thestatusbitsaresticky,meaningtheyarenotclearedunlessa1iswrittentothecorrespondingbitposition,exceptforcarrierdetect,orCD,whichrespondsbasedonthepresencesofacarrier,theFIFOlevelregisters,whichrespondbasedontheconditionsoftheFIFOs,andJAB_OFFandJAB_ONwhichrepresentthecurrentstatusofthejabberinibhior.
CTSwillassertafterRTSissetandnocarrierispresentifnotoperatinginfull-duplexmode.
MODEM_STATUSisshowninFigure25anddescribedinTable6.
ReturntoSummaryTable.
Figure25.
MODEM_STATUSRegister15141312111098RSTJAB_OFFJAB_ONGAPFRAMEPARITYWDTCRCR/WR/WR/WR/WR/WR/WR/WR/W76543210FIFO_M2DLEVELFIFO_M2DFULLFIFO_M2DEMPTYFIFO_D2MLEVELFIFO_D2MFULLFIFO_D2MEMPTYCDCTSR/WR/WR/WR/WR/WR/WRRTable6.
MODEM_STATUSRegisterFieldDescriptionsBitFieldTypeResetDescription15RSTR/W0Aresethasoccurred14JAB_OFFR/W0Thisbitgoeshighwhenthejabberinhibitortimeoutperiodhasexpired13JAB_ONR/W0Thisbitgoeshighwhenthejabberinhibitorhasbeentriggered12GAPR/W0AgaperrorinHARTmode11FRAMER/W0AframeerrorinHARTmodeora1/2bitslipinFF/PAmode10PARITYR/W0AParityerrorinHARTmode9WDTR/W0Thewatch-dogtimerhasexpired8CRCR/W0AnincorrectCRCwordwasprovidedinareadorwritecommand7FIFO_M2D_LEVELR/W0ThereceiveFIFOisattheprogrammedlevel6FIFO_M2D_FULLR/W0ThereceiveFIFOisfull5FIFO_M2D_EMPTYR/W0ThereceiveFIFOisempty24DAC8742HZHCSJ40–DECEMBER2018www.
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cnCopyright2018,TexasInstrumentsIncorporatedTable6.
MODEM_STATUSRegisterFieldDescriptions(continued)BitFieldTypeResetDescription4FIFO_D2M_LEVELR/W0ThetransmitFIFOisattheprogrammedlevel3FIFO_D2M_FULLR/W0ThetransmitFIFOisfull2FIFO_D2M_EMPTYR/W0ThetransmitFIFOisempty1CDR0InHARTmode,avalidcarrierhasbeendetected0CTSR0InHARTmode,themodemisclearedtosenddataandthemodulatorisactive7.
5.
4MODEM_IRQ_MASKRegister(Offset=21h)[reset=0x0024]ThisregistercontrolswhichMODEMSTATUSeventsareallowedtotriggeraninterruptontheIRQpin.
A0intherespectivebitpositionallowstheinterrupteventtotoggletheIRQpin.
A1intherespectivebitpositionblockstheinterrupteventfromtogglingtheIRQpin,buttheeventcanstillbedetectedbyreadingtheMODEMSTATUSregister.
MODEM_IRQ_MASKisshowninFigure26anddescribedinTable7.
ReturntoSummaryTable.
Figure26.
MODEM_IRQ_MASKRegister15141312111098RESERVEDJAB_OFFJAB_ONGAPFRAMEPARITYWDTCRCRR/WR/WR/WR/WR/WR/WR/W76543210FIFO_M2DLEVELFIFO_M2DFULLFIFO_M2DEMPTYFIFO_D2MLEVELFIFO_D2MFULLFIFO_D2MEMPTYCDCTSR/WR/WR/WR/WR/WR/WR/WR/WTable7.
MODEM_IRQ_MASKRegisterFieldDescriptionsBitFieldTypeResetDescription15RESERVEDR/W0Reserved14JAB_OFFR/W0Writinga1tothisbitblockstheJAB_OFFeventfromtriggeringtheIRQpin13JAB_ONR/W0Writinga1tothisbitblockstheJAB_ONeventfromtriggeringtheIRQpin12GAPR/W0Writinga1tothisbitblockstheGAPeventfromtriggeringtheIRQpin11FRAMER/W0Writinga1tothisbitblockstheFRAMEeventfromtriggeringtheIRQpin10PARITYR/W0Writinga1tothisbitblocksthePARITYeventfromtriggeringtheIRQpin9WDTR/W0Writinga1tothisbitblockstheWDTeventfromtriggeringtheIRQpin8CRCR/W0Writinga1tothisbitblockstheCRCeventfromtriggeringtheIRQpin7FIFO_M2D_LEVELR/W0Writinga1tothisbitblockstheFIFO_M2D_LEVELeventfromtriggeringtheIRQpin6FIFO_M2D_FULLR/W0Writinga1tothisbitblockstheFIFO_M2D_FULLeventfromtriggeringtheIRQpin5FIFO_M2D_EMPTYR/W1Writinga1tothisbitblockstheFIFO_M2D_EMPTYeventfromtriggeringtheIRQpin4FIFO_D2M_LEVELR/W0Writinga1tothisbitblockstheFIFO_D2M_LEVELeventfromtriggeringtheIRQpin3FIFO_D2M_FULLR/W0Writinga1tothisbitblockstheFIFO_D2M_FULLeventfromtriggeringtheIRQpin2FIFO_D2M_EMPTYR/W1Writinga1tothisbitblockstheFIFO_D2M_EMPTYeventfromtriggeringtheIRQpin25DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018Copyright2018,TexasInstrumentsIncorporatedTable7.
MODEM_IRQ_MASKRegisterFieldDescriptions(continued)BitFieldTypeResetDescription1CDR/W0Writinga1tothisbitblockstheCDeventfromtriggeringtheIRQpin0CTSR/W0Writinga1tothisbitblockstheCTSeventfromtriggeringtheIRQpin7.
5.
5MODEM_CONTROLRegister(Offset=22h)[reset=0x0048]Thisregistercontrolsvariousmodemfeaturesincluding:FF/PAManchesterdatapolarity,numberofFF/PApreamblebits,analogoutputamplitude,modemenable,duplexmode,andrequesttosend.
MODEM_CONTROLisshowninFigure27anddescribedinTable8.
ReturntoSummaryTable.
Figure27.
MODEM_CONTROLRegister15141312111098FFPA_POLFFPA_PREAMBLERESERVEDTX_AMPR/WR/WRR/W76543210TX_AMPMOD_ENDUP_ENRESERVEDRTSR/WR/WR/WRR/WTable8.
MODEM_CONTROLRegisterFieldDescriptionsBitFieldTypeResetDescription15FFPA_POLR/W0SetsthetransmittedpolarityoftheManchesterencodeddata0=Logical1istransmittedasatransitionfromhigh-to-low(default)1=Logical1istransmittedasatransitionfromlow-to-high14-12FFPA_PREAMBLER/W0Numberofpreamblebytessentisthevalueprogrammedinthisregisterplus111-9RESERVEDR0Reserved8-4TX_AMPR/W00100Unsignedbinaryvaluethatcontrolstheamplitude(HARTmodeonly)ofthetransmittedwaveformin25mVppsteps.
Defaultvalue00100for500mVppoutputamplitude.
Amplitudemayvaryfrom400mVppto800mVpp.
3MOD_ENR/W10=DisablesTX/RXofthemodem1=EnablesTX/RXofthemodem(default)2DUP_ENR/W00–TXFIFOisnotconnectedtoRXFIFO(default)1=ConnectsTXFIFOtoRXFIFO1RESERVEDR0Reserved0RTSR/W00=NoactiverequesttosendinHARTmode(default)1=ActiverequesttosendinHARTmode26DAC8742HZHCSJ40–DECEMBER2018www.
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cnCopyright2018,TexasInstrumentsIncorporated7.
5.
6FIFO_D2MRegister(Offset=23h)[reset=0x0200]ThisregisterinterfacestheFIFOthattransmitsdatafromthedigitalinterfacetothemodem.
FIFO_D2MisshowninFigure28anddescribedinTable9.
ReturntoSummaryTable.
Figure28.
FIFO_D2MRegister15141312111098FIFO_LEVELLEVEL_FLAGFULL_FLAGEMPTY_FLAGPARITY_BITRRRRW76543210DATAWTable9.
FIFO_D2MRegisterFieldDescriptionsBitFieldTypeResetDescription15-12FIFO_LEVELR0ReadsbackthecurrentleveloftheFIFO,readonly11LEVEL_FLAGR0Indicatestheprogrammedlevelhasbeenreached,readonly10FULL_FLAGR0IndicatestheFIFOisfull,readonly9EMPTY_FLAGR1IndicatestheFIFOisempty,readonly8PARITY_BITW0Oddparityfor8-bitdatareadonbus,writeonly7-0DATAW0Datatransmittedfromthedigitalinterfacetothemodem,writeonly7.
5.
7FIFO_M2DRegister(Offset=24h)[reset=0x0200]ThisregisterinterfacestheFIFOthatreceivesdatafromthemodemtothedigitalinterface.
ThisregisterisreadonlyFIFO_M2DisshowninFigure29anddescribedinTable10.
ReturntoSummaryTable.
Figure29.
FIFO_M2DRegister15141312111098FIFO_LEVELLEVEL_FLAGFULL_FLAGEMPTY_FLAGPARITY_BITRRRRR76543210DATARTable10.
FIFO_M2DRegisterFieldDescriptionsBitFieldTypeResetDescription15-12FIFO_LEVELR0ReadsbackthecurrentleveloftheFIFO,readonly11LEVEL_FLAGR0Indicatestheprogrammedlevelhasbeenreached,readonly10FULL_FLAGR0IndicatestheFIFOisfull,readonly9EMPTY_FLAGR1IndicatestheFIFOisempty,readonly8PARITY_BITR0Oddparityfor8-bitdatareadonbus,readonly7-0DATAR0Datatransmittedfromthemodemtothedigitalinterface,readonly27DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporated7.
5.
8FIFO_LEVEL_SETRegister(Offset=25h)[reset=0x0000]ThisregisterprogramsthealarmthresholdforbothtransmitandreceiveFIFOs.
EachbitfieldallowsfortheFIFOalarmthresholdtobeprogrammedtointegervaluesfrom1-15.
FIFO_LEVEL_SETisshowninFigure30anddescribedinTable11.
ReturntoSummaryTable.
Figure30.
FIFO_LEVEL_SETRegister15141312111098RESERVEDR76543210M2D_LEVELD2M_LEVELR/WR/WTable11.
FIFO_LEVEL_SETRegisterFieldDescriptionsBitFieldTypeResetDescription15-8RESERVEDR00000000Reserved7-4M2D_LEVELR/W0000ThebinaryvalueinthisregistersetsthemodulatorFIFOalarmthreshold3-0D2M_LEVELR/W0000ThebinaryvalueinthisregistersetsthedemodulatorFIFOalarmthreshold7.
5.
9PAFF_JABBERRegister(Offset=27h)[reset=0x0000]Thisregistercontrolsthejabberinhibitortime-outbehavior.
Thetime-outcanbecalculatedusingtheequationbelowwithPAFF_JABBERindecimalformat.
PAFF_JABBERisshowninFigure31anddescribedinTable12.
ReturntoSummaryTable.
Figure31.
PAFF_JABBERRegister15141312111098RESERVEDR76543210PAFF_JABBERR/WTable12.
PAFF_JABBERRegisterFieldDescriptionsBitFieldTypeResetDescription15-8RESERVEDR00000000Reserved7-0PAFF_JABBERR/W00000000TimeOut=JABBER_TIMEOUT*2.
048ms28DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporated8ApplicationandImplementation注注InformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.
TI'scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.
Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.
8.
1ApplicationInformationTheDAC8742HfamilyofdevicesintegratesmodemfunctionalityforseverallargelyusedIndustrialprotocols:HighwayAddressableRemoteTransducer(HART),FOUNDATIONFieldbus(FF),andPROFIBUS(PA).
ThedifferentmodesaresetviatheCLK_CFGxpinsofthedevicethatallowthedevicetoeitherenterHARTorPAFFmode.
InHARTmode,a1200-/2200-HzHARTFSKSignalismodulatedanddemodulated,whilethePAFFmodecommunicatesviaa31.
25Kbit/sManchestercoded/encodedsignal.
Thesmallpackagesizes,widetemperaturerangeandlowquiescentcurrentmakethisdeviceanidealcandidateforapplicationsinIndustrialProcessControlandAutomation.
8.
1.
1DesignRecommendationsLocalpowersupplydecouplingisrecommendedbyplacing10-FcapacitorsontheIOVDDandAVDDsupplylines,and0.
1-FcapacitorsclosetotheDAC8742Hsupplypins.
CeramiccapacitortypessuchasC0GorX7Rarerecommendedforitsoptimalperformanceacrosstemperature,andverylowdissipationfactor.
DCbiascharacteristicsofthecapacitorsshouldalsobeconsideredwhenselectingpassivecomponents,suchasthevoltageratingandequivalentseriesresistance(ESR).
8.
1.
2SelectingtheCrystal/ResonatorBothcommunicationmodes,HARTandPAFF,requiredifferentclockingfrequenciesforcorrectoperation:HART–1.
2288MHzor3.
686MHz,PAFF–4MHz.
Inadditiontoselectingthecommunicationmode,theCLK_CFGxandXENpinsalsoselectwhetheraninternaloscillatororexternalclocksourceisconfiguredfordeviceoperation.
Theconfigurationtableisexplainedin表1.
Accuracyovertheapplicationstemperaturerangeshouldbeconsideredwhenselectingtheexternalcrystalorresonator.
Furthermore,crystalswithalowdriftspecificationoverthedesiredapplicationtemperaturerangeshouldalsobeselectedwhenusingtheDAC8742HdevicesinHART,FOUNDATIONFieldbus,andPROFIBUSPAapplicationsascommunicationtimingiscritical.
Inordertoreducequiescentcurrentconsumption,theXTALnetsshouldbeoptimizedduringlayouttoreduceanylengththatmayincreasenetcapacitance.
Thisincreaseincapacitanceisdirectlyproportiontocurrentconsumption.
8.
1.
3IncludedFunctionsandFilterSelectionAsahighlyintegrateddevice,theDAC8742Hnotonlyincludesthemodulationanddemodulationcapabilitiesforthepreviouslydescribedindustrialprotocols,butalsoincludesaninternalreference,andintegratedreceivebandpassfilter,withotheraforementionedfunctions.
InHARTmode,aninternalamplifierprovideshighoutputdrivecapability,andcandriveawiderangeofpurelycapacitiveloads,rangingfrom5nFto22nF.
Thelowervaluespecifiedintheloadrangeistoensureoutputstability.
Twodifferentfilterconfigurations,externalandinternal,areachievablethroughtheBPF_ENdigitalinput--logichighonthispinenablestheinternalbandpassfilter.
Theexternalfilterconfigurationisshownin图32.
TheexampleprovideddisplaystheDAC8742Hdeviceconfiguredwithanexternalreferenceandexternalbandpassfilter.
29DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporatedApplicationInformation(接接下下页页)图图32.
HARTMode:DAC8742HPassiveSelectionForExternalBandpassFilterandExternalReferenceThesecondconfiguration,whichcanreducecostsassociatedwithPCBdevelopmentandBOMcomponentcounts,additionallyaidsintheoptimizationofboardspace.
Thisoptimizationgivestheuserflexibilityintoachievingindustrialapplicationswithsmallerformfactorsizes.
Theinternalfilterconfiguration,withcorrectMOD_IN,MOD_INF,andMOD_OUTconnections,isshownin图33.
图图33.
HARTMode:DAC8742HPassiveSelectionForInternalFilterDAC8742HZHCSJ40–DECEMBER2018www.
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cn30版权2018,TexasInstrumentsIncorporated8.
2TypicalApplicationTheapplicationschematicshownin图34isdescribedinthefollowingsections.
图图34.
2-WireTransmitterwithDAC8742HHARTModemDesignSchematic31DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporated8.
2.
1DesignRequirementsTheapplicationpresentedin图34representsaloop-powered,2-wire,smart4-mAto20-mAtransmitterthatcommonlyresidesinfactorycontrolandindustrialautomationsectors.
Inthisapplication,theDAC8742HenablesasmartinterfacebyprovidingHARTcommunication,whichisresponsibleformodulatingtwo-waydigitalinformationthatencapsulateawidevarietyofdata,includingdevice/sensorinformation,calibrationdata,andsystemdiagnosticinformation.
ThiscircuithasbeensuccessfullyHARTcertificationandregisteredwiththeFieldCommGroup.
8.
2.
2DetailedDesignProcedure8.
2.
2.
1DAC8742HHARTModemInthisdesigntheDAC8742Hinternalreferenceandbandpassfilterwaschosentooptimizeboardarea,consequentlyreducingformfactorandcost.
X7R,10%accurate,bypasscapacitancesof1-Fand0.
1-Fvalueswerechosenforthereferenceandsupplies,respectively.
TheDAC8742HdeviceinterfaceswiththeMSP430FR5969,orothersimilarhostcontroller,throughastandardUARTinterface.
TheDAC8742HdigitalpinsconnectedthroughthisinterfaceincludeUART_RTS,UART_OUT(TX),UART_IN(RX),andCD.
TheremainingportionoftheschematicincludesotherTIdevicesthataidintherealizationofahighlyaccurate4-mAto20-mA,2-wiretransmitter.
Thiscombinationofcircuitryisideallysuitedforremotesignalconditioningofawidevarietyofsensorsandtransducers,includingthermocouples,RTDs,thermistors,andstraingaugebridges.
Thetwo-wiretransmitterispoweredfromanexternalDCpowersupplythatisconnectedviathetwoBUSsupplylines.
Thetransmittercommunicatesbysourcinga4-mAto20-mAcurrentthroughtheconnectedbus,andbacktothecentralhost,whichistypicallyaPLCanaloginputmodule.
Thisexpressedrangeof4mAto20mAistypicallyemployedtoadheretoindustrystandard,andensuresthatthetransmitterreceivesaminimumof4mAforcorrectpoweredoperation.
图图35.
SimplifiedSchematicofthe2-WireCurrentLoop8.
2.
2.
22-WireCurrentLoopTheA2operationalamplifieremploysnegativefeedbacktoensurepotentialsatbothinputnodes,V+andV-,areequivalent.
ThisestablishesthesetofKCLequations(1)–assumingnoHARTcommunication,VHART=0V.
I1=VDAC/(25.
6k)+VREF/(102.
4k)(3)32DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporatedA2alsodrivesthebaseoftheNPNBJT,Q1,whichenablescurrenttoflowfromitscollectorthroughemitterpinsandthroughtheR8resistor,whilemaintaininganequivalentpotentialdropfromitsinputnodestothenetrepresentedbyTP4.
ThisensuresthatthecombinedvoltagedropacrossR9andR11isequivalenttothecombineddropofR10andR12.
Usingthisrelationship,alongwithcurrent公式3and公式4,IOUTiscalculatedasfollows:I2=I1*(1.
80k+180)/(10+10)=I1*(1.
980k/20)=I1*99(4)IOUT=I1+I2=[VDAC/(25.
6k)+VREF/(102.
4k)]+I1*99=[VDAC/(25.
6k)+VREF/(102.
4k)]*(100)(5)ForaVREFvalueof4.
096V,thezero-scaleportionofthetransferfunction,[VREF/(102.
4k)]*(100),translatesto4mA,whilethespan,[VDAC/(25.
6k)]*100,encompasses16mA.
Thisfinalproductisasystemcapableofsourcing4mAto20mA,whichisdependentonDACoutputvoltage.
ThevalueofR4isresponsibleforconvertingthe500-mVp-pHARTsignalintoa1-mAp-pfrequencyshiftkeyed(FSK)signalthatresidesontopofthe4-mAto20-mAanalogcurrentsignal.
8.
2.
2.
3RegulatorTheprimarysupplyforthetransmitteristheTPS7A4101device,whichisa50-Vinput,50-mASingleoutputlow-dropoutlinearregulatorwithverylowquiescentcurrent,25A.
Thedevicesuppliesawell-regulatedvoltagerail(1%accuracy),operatingwithinanextendedtemperaturerangeof–40°Cto125°C,andalsowithstandsandmaintainsregulationduringveryhighandfastvoltagetransients.
InthisdesigntheLDOconvertstheexternalsupplytoa5-VrailthatisusedbytheDAC8830,LM4132andOPA333/OPA335.
The200-ΩresistorthatseparatestheloopsupplyfromtheLDOactsasacurrentlimitingresistoratstartupandadditionallyimprovestheoverallreceiverimpedanceofthedesign.
Generally,seriesreferencesarepreferredovershuntreferencesbecauseoftheirlowerpowerconsumption;inthiscasetheLM4132exhibitsamaximumof60-Aquiescentcurrent.
Moreover,thedevicehasaninitialaccuracyof0.
05%withaspecifiedtemperaturecoefficientof10ppm/°Corless,andiscapableofoperatingwiththesemetricsatanextendedtemperaturerangeof–40°Cto125°C.
Inordertogeneratea3.
3-VsupplyfortheDAC8742H,theTPS7B6933-Q1,alow-dropoutlinearregulatorwithlowquiescentcurrent,isincorporatedintothedesign.
ThisLDOiscapableofoperatingoverawidetemperaturerangeof–40°Cto125°C,whileexhibitingamaximumquiescentvalueof25Aoverthistemperaturerange.
8.
2.
2.
4DACAftersufficientbypass,thisprecisionreferencevoltageisappliedtotheVREFpinoftheDAC8830device.
AnaccuratereferencealongwithanaccurateDACarelargelyresponsiblefortheoverallaccuracyofthecurrentloop,asanyaccuracyerrorsassociatedwiththeDACwillpropagatethroughtherestofthesignalchainanddecreasetheaccuracyofthesolution.
Inthiscase,theDAC8830,a16-bitvoltage-outputDACwithexcellentlinearity(1LSBINL),lowglitch,lownoise,andfastsettlingwaschosentosetthebaselineperformanceofthedesign.
8.
2.
2.
5AmplifiersNext,thevoltageoutputisbufferedwiththeOPA333CMOSoperationamplifier,whichfeaturesnear-zerodriftovertimeandtemperature,lowquiescentcurrent(17A),andsinglesupplyoperationwithrail-to-railoutputthatswingswithin50mVofthesupplyrail.
AswiththeOPA333,theOPA335waschosenduetoitsexcellentDCaccuracyspecifications.
Theseparametersincludelowinputbiascurrent,lowoffsetvoltage,andhighCMRR/PSRR.
InadditiontotheseDCspecifications,theOPA335featuresanoperatingbandwidthofupto2MHz,whichprovidesamplemarginforHARTcommunication.
8.
2.
2.
6DiodesFortransientvoltageprotection,a40-Vbidirectionaltransientvoltagesuppressor(TVS)diodeisplacedacrosstheBUSlinesofthedesign.
Certaincriteriashouldbeconsideredwhenmakingthisdiodeselection,suchasthediode'sworkingvoltage,breakdownvoltage,leakagecurrentandpowerrating.
Inadditiontotheseparameters,leakagecurrentshouldalsobefactoredintothedesignasitwillimpacttheaccuracyoftheanalogcurrentloop.
33DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporated2-wirepolarityprotectionisalsoemployedbyusingtheDSRHD10asadiodebridgerectifier.
Theplacementofthiscomponentensuresthatthecurrentloopwillalwayscorrectlyoperateregardlessofthearrangementofinputconnections.
Aswithotherelements,leakageandbiasingvoltageshouldbeconsideredasitwillaffectsystemaccuracyandcompliancevoltage.
8.
2.
2.
7PassivesAmongthepassivesincludedinthedesign,thegainsettingresistorsshouldbechosentoexhibittighttolerancesinordertoachievehighaccuracy.
Theseresistors--R4,R5,R6,R9,R11,R10,andR12--areprimarilyresponsibleforsettingthegainofthecurrentloop,alongwithprimarypathoftheoutputcurrentflow.
Sincethebiasedtransistor,Q1,isresponsibleforsourcingmostoftheoutputcurrent,componentsinthepathofthiscurrentflowshouldbechosenwithappropriatepowerratings.
InthiscaseR8isa0.
25-Wresistor.
8.
2.
3ApplicationCurvesFivehundreddatapointsweretakenonfivedifferentboards,producingthe4to20-mAtransferfunctionbelowin图36.
Thetotalunadjustederror(TUE)ofthetransmittersisdisplayedin图37.
图图36.
4-20mATransferFunction图图37.
TotalUnadjustedErrorGraphofApplicationCircuit34DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporated9PowerSupplyRecommendationsTheDAC8742Hcanoperatewithanalogsuppliesfrom2.
7Vto5.
5Vanddigitalsuppliesfrom1.
71Vto5.
5V,enablinginterfacinghostcontrollerplatformswithlowvoltagedigitallogic.
Forapplicationsthatareparticularlyfocusedonreducingpowerdissipationinthemodem,itissuggestedtousethelowestsupplyvoltageavailableforbothanaloganddigitalsupplies.
35DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporated10Layout10.
1LayoutGuidelinesPrecisiondesignsrequirecarefullayout,thelistbelowprovidessomeinsightintogoodlayoutpractices.
AllPowerSupplypinsshouldbebypassedtogroundwithalowESRceramicbypasscapacitor.
Thetypicalrecommendedbypasscapacitanceis0.
1to1FceramicwithaX7RorNP0dielectric.
PowersupplyandReferencebypasscapacitorsshouldbeplacedclosetoterminalstominimizeinductanceandoptimizeperformance.
Ahigh-qualityceramictypeNP0orX7Risrecommendedforitsoptimalperformanceacrosstemperature,andverylowdissipationfactor.
Thedigitalandanalogsectionsshouldhaveproperplacementwithrespecttothedigitalandanalogcomponents.
Theseparationofanaloganddigitalcircuitrywillallowforbetterdesignandpracticeasitwillensurelesscouplingintoneighboringblocks,andwillminimizetheinteractionbetweenanaloganddigitalreturncurrents.
10.
2LayoutExample图图38.
DAC8742HBasicLayoutExample36DAC8742HZHCSJ40–DECEMBER2018www.
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cn版权2018,TexasInstrumentsIncorporatedLayoutExample(接接下下页页)图图39.
2-WireTransmitterwithDAC8742HHARTModemLayout-TopLayer图图40.
2-WireTransmitterwithDAC8742HHARTModemLayout-BottomLayer37DAC8742Hwww.
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cnZHCSJ40–DECEMBER2018版权2018,TexasInstrumentsIncorporated11器器件件和和文文档档支支持持11.
1文文档档支支持持11.
1.
1相相关关文文档档请参阅如下相关文档:《DAC8742H评估模块用户指南》(SLAU700)11.
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11.
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11.
4商商标标E2EisatrademarkofTexasInstruments.
FOUNDATION现场总线isatrademarkofFieldCommGroup.
HARTisaregisteredtrademarkofFieldCommGroup.
Allothertrademarksarethepropertyoftheirrespectiveowners.
11.
5静静电电放放电电警警告告ESD可能会损坏该集成电路.
德州仪器(TI)建议通过适当的预防措施处理所有集成电路.
如果不遵守正确的处理措施和安装程序,可能会损坏集成电路.
ESD的损坏小至导致微小的性能降级,大至整个器件故障.
精密的集成电路可能更容易受到损坏,这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符.
11.
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重重要要声声明明和和免免责责声声明明TI均以"原样"提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示担保.
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您将对以下行为独自承担全部责任:(1)针对您的应用选择合适的TI产品;(2)设计、验证并测试您的应用;(3)确保您的应用满足相应标准以及任何其他安全、安保或其他要求.
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除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权许可.
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TI所提供产品均受TI的销售条款(http://www.
ti.
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cn/zh-cn/legal/termsofsale.
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com.
cn上或随附TI产品提供的其他可适用条款的约束.
TI提供所述资源并不扩展或以其他方式更改TI针对TI产品所发布的可适用的担保范围或担保免责声明.
IMPORTANTNOTICE邮寄地址:上海市浦东新区世纪大道1568号中建大厦32楼,邮政编码:200122Copyright2019德州仪器半导体技术(上海)有限公司PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDAC8742HPBSACTIVETQFPPBS32250RoHS&GreenNIPDAULevel-3-260C-168HR-55to1258742HDAC8742HPBSRACTIVETQFPPBS321000RoHS&GreenNIPDAULevel-3-260C-168HR-55to1258742H(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page2TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDAC8742HPBSRTQFPPBS321000330.
016.
47.
27.
21.
512.
016.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com26-Feb-2019PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DAC8742HPBSRTQFPPBS321000350.
0350.
043.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com26-Feb-2019PackMaterials-Page2重重要要声声明明和和免免责责声声明明TI均以"原样"提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示担保.
所述资源可供专业开发人员应用TI产品进行设计使用.
您将对以下行为独自承担全部责任:(1)针对您的应用选择合适的TI产品;(2)设计、验证并测试您的应用;(3)确保您的应用满足相应标准以及任何其他安全、安保或其他要求.
所述资源如有变更,恕不另行通知.
TI对您使用所述资源的授权仅限于开发资源所涉及TI产品的相关应用.
除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权许可.
如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI及其代表造成的损害.
TI所提供产品均受TI的销售条款(http://www.
ti.
com.
cn/zh-cn/legal/termsofsale.
html)以及ti.
com.
cn上或随附TI产品提供的其他可适用条款的约束.
TI提供所述资源并不扩展或以其他方式更改TI针对TI产品所发布的可适用的担保范围或担保免责声明.
IMPORTANTNOTICE邮寄地址:上海市浦东新区世纪大道1568号中建大厦32楼,邮政编码:200122Copyright2020德州仪器半导体技术(上海)有限公司