unitsphysicalmemory

022-0045Rev.
Cwww.
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com1TN202RabbitMemoryManagementInaNutshellTheRabbitCPUhasaMemoryManagementUnit(MMU)thatcontrolshowlogicalmemoryaddressesmapintophysicaladdresses,andaMemoryInterfaceUnitthatcontrolshowphysicaladdressesmapintoactualhardware.
TheDynamicCcompilerandlibrariesgenerallyhandlememorymappingdetailssothatmostDynamicCusersdon'thavetoconcernthemselveswithit,butsomeadvancedapplicationsmayneedtomanipulatetheMMUand/ortheMIU.
Forfurtherdetailsonmemorymanagement,seetheRabbitmicroprocessoruser'smanualforyourRabbitchip.
DefinitionsPhysical(orLinear)Addresses-20-bitaddressesrepresentingthe1Maddressspacethatlogicaladdressesmapinto.
Thehighest20-bitaddressis0xFFFFF.
ThedefaultaddressesintheDynamicCdevelopmentsystemflashstartatphysicaladdress0x00000andinRAMstartatphysicaladdress0x80000.
LogicalAddresses-16-bitaddressesrepresentinga64Kaddressspace.
Thehighest16-bitaddressis0x0FFFF.
MostRabbitinstructionsuselogicaladdresses.
ThelocationinphysicalmemorywheretheseaddressesmapintoiscompletelycontrollablebytheprogrammerviatheMMU.
Segment-Ablockoflogicalmemory;theblocksizesaremultiplesof4K(0x01000)Bank-A256KblockofPM,ona256Kboundary(0x40000).
TherearefourbanksavailablewithintheRabbitphysicaladdressspace.
Thestartingaddressofeachbankis0x00000,0x40000,0x80000,and0xC0000.
2www.
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comTN202MemoryMappingUnitTheMMUtranslatesa16-bitlogicaladdresstoa20-bitphysicaladdress.
Thelogicaladdressspaceisdividedintofoursegments:xmem,stack,data,andbase.
ThexmemsegmentalwaysoccupiesE000h–FFFFh.
Theothersegmentsarelocatedfrom0000htoDFFFh,andareadjustableinsizetoanywherefrom0bytestoE000hbytes.
ThetotalsizeofallthreeisalwaysE000h.
ThestacksegmentstartsabovethedatasegmentandalwaysendsatDFFFh.
Thedatasegmentisalwaysabovethebasesegment.
Theboundariesbetweenthebasesegmentandthedatasegment,andbetweenthedataseg-mentandthestacksegmentaresetbyanMMUregister,SEGSIZE.
TheuppernibbleofSEGSIZErepre-sentsthestack-databoundary(in1000hbyteunits),andthelowernibblerepresentsthedata-baseboundary(in1000hbyteunits).
Eachoftheupperthreesegmentshasanassociatedsegmentregisterusedtomaplogicaladdressesthatfallwithinthesegmenttothephysicaladdressspace.
Fromtoptobottom,theyare:XPCSTACKSEGDATASEG.
Ineachcase,thephysicaladdressiscomputedbyshiftingthesegmentregisterleft12bits(multiplyingby1000h)andaddingittothel6-bitlogicaladdress.
Hereisthealgorithmforconvertinglogicaladdressestophysicaladdresses.
AbbreviationsLetSEGSIZE=XYhwhereXisthehighnibbleandYisthelownibble.
IfLA>=E000hPA=LA+(XPCx1000h)ElseIfLA>=X000hPA=LA+(STACKSEGx1000h)ElseIfLA>=Y000hPA=LA+(DATASEGx1000h)ElsePA=LAAnyofthesegmentregisterscanbeloadedwithanewvalidvalueatanytime,butthishastobedonewithgreatcare.
Forexample,ifcodeisexecutinginthexmemsegmentandtheXPCischanged,thenexecutionwillnotcontinueatthenextinstruction,butinsteadwillcontinueatthelocationinphysicalmemorywherethelogicaladdressofthenextinstructionmapsto.
ThisisbecausethePC(programcounter)registerholdsalogicaladdress.
LM-LogicalMemoryPM-PhysicalMemoryLA-LogicalAddress-addresswithintheLMPA-PhysicalAddress-addresswithinthePMTN202www.
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com3ExampleTheMMUregistersaresetasfollows:XPC=0xF8SEGSIZE=0xD6STACKSEG=0x92DATASEG=0x7AThephysicaladdressofthebottomofthexmemsegmentisgivenby:0xF8000+0x0E000=0x06000(bit20,the21storcarrybit,isignored)Thephysicaladdressofthebottomofthestacksegmentisgivenby:0x92000+0x0D000=0x9F000Thephysicaladdressofthebottomofthedatasegmentisgivenby:0x7A000+0x06000=0x80000Notethatthedatasegmentstartsatthebeginningofthe"normal"RAMspaceand,fora128KRAM,thestacksegmentisallocated4K.
TherearespecialDynamicCfunctionstoaccessdataataspecificPA:root2xmem()andxmem2root().
Therearealsoseveralassemblylanguageinstructions:LDPformemoryaccessLCALLandLJPforbranchingNotethattheLDPinstructionsbypasstheMMUandgodirectlytotheMIU(seethenextsection).
Thefollowingdiagramillustratesthememorymappingdiscussedaboveusingthesamplecalculationswitha128Kflashanda128KRAM.
4www.
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MemoryMappingBetweenLogicalAddressandPhysicalAddressMemoryInterfaceUnitTheMIUcontrolsmemoryaccessaftertheMMUdeterminesthephysicaladdress.
TherearefiveregistersassociatedwiththeMIU:MMIDRMB0CRMB1CRMB2CRMB3CRTheprimaryfunctionoftheMMIDRregisteristoallowthesystemtopermanentlyenable/CS1.
ThiscouldallowfasteraccesstotheRAMbykeepingthechipalwaysselected.
However,youwillneedtoinsurethatthe/OEand/or/WEsignalsarenotsharedwithanotherdevice.
EachofthefourMemoryBankControlRegistersMB0CR,MB1CR,MB2CRandMB3CR.
controlsone256Kquadrantofthe1Mphysicaladdressspace.
Theseregisterscontrolwaitstates,CS/WE/OElineusageandwriteprotection.
TheMBxCRregistersalsocanbesetuptoinvertaddresslinesA18andA19.
Ifbit4ofoneoftheseregis-tersisset,theMIUinvertsA18afterthelogicaltophysicalconversionisdonebytheMMU.
Ifbit5ofoneoftheseregistersisset,theMIUinvertsA19afterthelogicaltophysicalconversionisdonebytheMMU.
unusedunusedRAMFlashLogicalAddressSpaceXMEMStackDataBase0xFFFF0xE0000xD0000x60000x0000PhysicalAddressSpace0xFFFFF0xC00000xA00000x800000x400000x200000x000000x9F0000x06000TN202www.
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com5Fora256Korsmallerdevice,addresslineinversionhasnoeffectsincethehighestaddresslineneededtoaddress256kisA17,butfora512Kdevice,thismeansthatwehaveaccesstothewhole512Kviaone256Kquadrantofphysicalmemory.
BecausewecancontrolA19aswell,each256Kquadrantofphysicaladdressescanactuallyaddressawhole1M.
This,incombinationwithdifferentCS/WE/OEcombinationscontrollablebythesameregisters,givestheRabbitaccessto6Mofmemorywithnoexternalgluelogic.
ExampleMB2CRissettomaptoCS1/WE1/OE1,andtheselinesgointoa512KRAM.
Thereforephysicaladdresses80000h-BFFFFh(quadrant2of0-3)maptooffsetsinthechipof00000h-3FFFFh(thelower256Kofthechip)usinglinesA0-A17withA18notasserted.
Nowwesetbit4ofMB2CRtoinvertA18.
Physicaladdresses80000h-BFFFFhnowmaptooffsetsinthechipof40000h-7FFFFh(theupper256Kofthechip.
)usinglinesA0-A17withA18asserted.
MMU/MIURegistersSegmentandMemoryBankRegistersTable1liststhedetailsaboutthesegmentregisters.
Table2liststhedetailsaboutthememorybankcontrolregisters.
Table1.
SegmentRegistersRegisterNameMnemonicI/OAddressR/WPostResetMMUInstruction/DataRegisterMMIDR10hR/Wxxx00000StackSegmentRegisterSTACKSEG11hR/W00000000LocatesstacksegmentinphysicalmemoryDataSegmentRegisterDATASEG12hR/W00000000LocatesdatasegmentinphysicalmemorySegmentSizeRegisterSEGSIZE13hR/W11111111Bits7.
.
4–boundaryaddressstacksegmentBits3.
.
0–boundaryaddressdatasegmentTable2.
MemoryBankControlRegistersRegisterNameMnemonicI/OAddressR/WPostResetMemoryBank0ControlRegisterMB0CR14hW00000000MemoryBank1ControlRegisterMB1CR15hWxxxxxxxxMemoryBank2ControlRegisterMB2CR16hWxxxxxxxxMemoryBank3ControlRegisterMB3CR17hWxxxxxxxx6www.
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comTN202MemoryBankControlRegisterFunctionsThistabledetailsthefunctionalityofthememorybankcontrolregistersandthenecessarybitvalues.
Table3describestheoperationofthefourmemorybankcontrolregisters.
Theregistersarewrite-only.
Eachregistercontrolsonequadrantinthe1Maddressspace.
Bits7,6—Thenumberofwaitstatesusedinaccesstothisquadrant.
Withoutwaitstates,readrequires2clocksandwriterequires3clocks.
Thewaitstateaddstothesenumbers.
Bits5,4—Thesebitsallowtheupperaddresslinestobeinverted.
Thisinversionoccursafterthelogicthatselectsthebankregister,sosettingtheselineshasnoeffectonwhichbankregisterisused.
Theinversionmaybeusedtoinstalla1Mmemorychipinthespacenormallyallocatedtoa256Kchip.
Thelargermemorycanthenbeaccessedas4pagesof256Keach.
Thereisnoeffectoutsidethequadrantthatthememorybankcontrolregisteriscontrolling.
Bit3—Inhibitsthewritepulsetomemoryaccessedinthisquadrant.
Usefulforprotectingflashmemoryfromaninadvertentwritepulse,whichwillnotactuallywritetotheflashbecauseitispro-tectedbylockcodes,butwilltemporarilydisabletheflashmemoryandcrashthesystemifthememoryisusedforcode.
Bit2—Selectswhichsetofthetwolines/OExand/WExwillbedrivenformemoryaccessesinthisquadrant.
Bits1,0—Determineswhichofthethreechipselectlineswillbedrivenformemoryaccessestothisquadrant.
Allbitsofthecontrolregisterareinitializedtozeroonreset.
Table3.
MemoryBankControlRegisterx(MBxCR=14h+x)Bit(s)ValueDescription7:6004waitstates012waitstates101waitstates110waitstates51InvertaddressA1941InvertaddressA1831Write-protectmemorythisquadrant20Use/OE0,/WE01Use/OE1,/WE11:000Use/CS001Use/CS11xUse/CS2