unitsphysicalmemory
physicalmemory 时间:2021-05-19 阅读:()
022-0045Rev.
Cwww.
rabbit.
com1TN202RabbitMemoryManagementInaNutshellTheRabbitCPUhasaMemoryManagementUnit(MMU)thatcontrolshowlogicalmemoryaddressesmapintophysicaladdresses,andaMemoryInterfaceUnitthatcontrolshowphysicaladdressesmapintoactualhardware.
TheDynamicCcompilerandlibrariesgenerallyhandlememorymappingdetailssothatmostDynamicCusersdon'thavetoconcernthemselveswithit,butsomeadvancedapplicationsmayneedtomanipulatetheMMUand/ortheMIU.
Forfurtherdetailsonmemorymanagement,seetheRabbitmicroprocessoruser'smanualforyourRabbitchip.
DefinitionsPhysical(orLinear)Addresses-20-bitaddressesrepresentingthe1Maddressspacethatlogicaladdressesmapinto.
Thehighest20-bitaddressis0xFFFFF.
ThedefaultaddressesintheDynamicCdevelopmentsystemflashstartatphysicaladdress0x00000andinRAMstartatphysicaladdress0x80000.
LogicalAddresses-16-bitaddressesrepresentinga64Kaddressspace.
Thehighest16-bitaddressis0x0FFFF.
MostRabbitinstructionsuselogicaladdresses.
ThelocationinphysicalmemorywheretheseaddressesmapintoiscompletelycontrollablebytheprogrammerviatheMMU.
Segment-Ablockoflogicalmemory;theblocksizesaremultiplesof4K(0x01000)Bank-A256KblockofPM,ona256Kboundary(0x40000).
TherearefourbanksavailablewithintheRabbitphysicaladdressspace.
Thestartingaddressofeachbankis0x00000,0x40000,0x80000,and0xC0000.
2www.
rabbit.
comTN202MemoryMappingUnitTheMMUtranslatesa16-bitlogicaladdresstoa20-bitphysicaladdress.
Thelogicaladdressspaceisdividedintofoursegments:xmem,stack,data,andbase.
ThexmemsegmentalwaysoccupiesE000h–FFFFh.
Theothersegmentsarelocatedfrom0000htoDFFFh,andareadjustableinsizetoanywherefrom0bytestoE000hbytes.
ThetotalsizeofallthreeisalwaysE000h.
ThestacksegmentstartsabovethedatasegmentandalwaysendsatDFFFh.
Thedatasegmentisalwaysabovethebasesegment.
Theboundariesbetweenthebasesegmentandthedatasegment,andbetweenthedataseg-mentandthestacksegmentaresetbyanMMUregister,SEGSIZE.
TheuppernibbleofSEGSIZErepre-sentsthestack-databoundary(in1000hbyteunits),andthelowernibblerepresentsthedata-baseboundary(in1000hbyteunits).
Eachoftheupperthreesegmentshasanassociatedsegmentregisterusedtomaplogicaladdressesthatfallwithinthesegmenttothephysicaladdressspace.
Fromtoptobottom,theyare:XPCSTACKSEGDATASEG.
Ineachcase,thephysicaladdressiscomputedbyshiftingthesegmentregisterleft12bits(multiplyingby1000h)andaddingittothel6-bitlogicaladdress.
Hereisthealgorithmforconvertinglogicaladdressestophysicaladdresses.
AbbreviationsLetSEGSIZE=XYhwhereXisthehighnibbleandYisthelownibble.
IfLA>=E000hPA=LA+(XPCx1000h)ElseIfLA>=X000hPA=LA+(STACKSEGx1000h)ElseIfLA>=Y000hPA=LA+(DATASEGx1000h)ElsePA=LAAnyofthesegmentregisterscanbeloadedwithanewvalidvalueatanytime,butthishastobedonewithgreatcare.
Forexample,ifcodeisexecutinginthexmemsegmentandtheXPCischanged,thenexecutionwillnotcontinueatthenextinstruction,butinsteadwillcontinueatthelocationinphysicalmemorywherethelogicaladdressofthenextinstructionmapsto.
ThisisbecausethePC(programcounter)registerholdsalogicaladdress.
LM-LogicalMemoryPM-PhysicalMemoryLA-LogicalAddress-addresswithintheLMPA-PhysicalAddress-addresswithinthePMTN202www.
rabbit.
com3ExampleTheMMUregistersaresetasfollows:XPC=0xF8SEGSIZE=0xD6STACKSEG=0x92DATASEG=0x7AThephysicaladdressofthebottomofthexmemsegmentisgivenby:0xF8000+0x0E000=0x06000(bit20,the21storcarrybit,isignored)Thephysicaladdressofthebottomofthestacksegmentisgivenby:0x92000+0x0D000=0x9F000Thephysicaladdressofthebottomofthedatasegmentisgivenby:0x7A000+0x06000=0x80000Notethatthedatasegmentstartsatthebeginningofthe"normal"RAMspaceand,fora128KRAM,thestacksegmentisallocated4K.
TherearespecialDynamicCfunctionstoaccessdataataspecificPA:root2xmem()andxmem2root().
Therearealsoseveralassemblylanguageinstructions:LDPformemoryaccessLCALLandLJPforbranchingNotethattheLDPinstructionsbypasstheMMUandgodirectlytotheMIU(seethenextsection).
Thefollowingdiagramillustratesthememorymappingdiscussedaboveusingthesamplecalculationswitha128Kflashanda128KRAM.
4www.
rabbit.
comTN202Figure1.
MemoryMappingBetweenLogicalAddressandPhysicalAddressMemoryInterfaceUnitTheMIUcontrolsmemoryaccessaftertheMMUdeterminesthephysicaladdress.
TherearefiveregistersassociatedwiththeMIU:MMIDRMB0CRMB1CRMB2CRMB3CRTheprimaryfunctionoftheMMIDRregisteristoallowthesystemtopermanentlyenable/CS1.
ThiscouldallowfasteraccesstotheRAMbykeepingthechipalwaysselected.
However,youwillneedtoinsurethatthe/OEand/or/WEsignalsarenotsharedwithanotherdevice.
EachofthefourMemoryBankControlRegistersMB0CR,MB1CR,MB2CRandMB3CR.
controlsone256Kquadrantofthe1Mphysicaladdressspace.
Theseregisterscontrolwaitstates,CS/WE/OElineusageandwriteprotection.
TheMBxCRregistersalsocanbesetuptoinvertaddresslinesA18andA19.
Ifbit4ofoneoftheseregis-tersisset,theMIUinvertsA18afterthelogicaltophysicalconversionisdonebytheMMU.
Ifbit5ofoneoftheseregistersisset,theMIUinvertsA19afterthelogicaltophysicalconversionisdonebytheMMU.
unusedunusedRAMFlashLogicalAddressSpaceXMEMStackDataBase0xFFFF0xE0000xD0000x60000x0000PhysicalAddressSpace0xFFFFF0xC00000xA00000x800000x400000x200000x000000x9F0000x06000TN202www.
rabbit.
com5Fora256Korsmallerdevice,addresslineinversionhasnoeffectsincethehighestaddresslineneededtoaddress256kisA17,butfora512Kdevice,thismeansthatwehaveaccesstothewhole512Kviaone256Kquadrantofphysicalmemory.
BecausewecancontrolA19aswell,each256Kquadrantofphysicaladdressescanactuallyaddressawhole1M.
This,incombinationwithdifferentCS/WE/OEcombinationscontrollablebythesameregisters,givestheRabbitaccessto6Mofmemorywithnoexternalgluelogic.
ExampleMB2CRissettomaptoCS1/WE1/OE1,andtheselinesgointoa512KRAM.
Thereforephysicaladdresses80000h-BFFFFh(quadrant2of0-3)maptooffsetsinthechipof00000h-3FFFFh(thelower256Kofthechip)usinglinesA0-A17withA18notasserted.
Nowwesetbit4ofMB2CRtoinvertA18.
Physicaladdresses80000h-BFFFFhnowmaptooffsetsinthechipof40000h-7FFFFh(theupper256Kofthechip.
)usinglinesA0-A17withA18asserted.
MMU/MIURegistersSegmentandMemoryBankRegistersTable1liststhedetailsaboutthesegmentregisters.
Table2liststhedetailsaboutthememorybankcontrolregisters.
Table1.
SegmentRegistersRegisterNameMnemonicI/OAddressR/WPostResetMMUInstruction/DataRegisterMMIDR10hR/Wxxx00000StackSegmentRegisterSTACKSEG11hR/W00000000LocatesstacksegmentinphysicalmemoryDataSegmentRegisterDATASEG12hR/W00000000LocatesdatasegmentinphysicalmemorySegmentSizeRegisterSEGSIZE13hR/W11111111Bits7.
.
4–boundaryaddressstacksegmentBits3.
.
0–boundaryaddressdatasegmentTable2.
MemoryBankControlRegistersRegisterNameMnemonicI/OAddressR/WPostResetMemoryBank0ControlRegisterMB0CR14hW00000000MemoryBank1ControlRegisterMB1CR15hWxxxxxxxxMemoryBank2ControlRegisterMB2CR16hWxxxxxxxxMemoryBank3ControlRegisterMB3CR17hWxxxxxxxx6www.
rabbit.
comTN202MemoryBankControlRegisterFunctionsThistabledetailsthefunctionalityofthememorybankcontrolregistersandthenecessarybitvalues.
Table3describestheoperationofthefourmemorybankcontrolregisters.
Theregistersarewrite-only.
Eachregistercontrolsonequadrantinthe1Maddressspace.
Bits7,6—Thenumberofwaitstatesusedinaccesstothisquadrant.
Withoutwaitstates,readrequires2clocksandwriterequires3clocks.
Thewaitstateaddstothesenumbers.
Bits5,4—Thesebitsallowtheupperaddresslinestobeinverted.
Thisinversionoccursafterthelogicthatselectsthebankregister,sosettingtheselineshasnoeffectonwhichbankregisterisused.
Theinversionmaybeusedtoinstalla1Mmemorychipinthespacenormallyallocatedtoa256Kchip.
Thelargermemorycanthenbeaccessedas4pagesof256Keach.
Thereisnoeffectoutsidethequadrantthatthememorybankcontrolregisteriscontrolling.
Bit3—Inhibitsthewritepulsetomemoryaccessedinthisquadrant.
Usefulforprotectingflashmemoryfromaninadvertentwritepulse,whichwillnotactuallywritetotheflashbecauseitispro-tectedbylockcodes,butwilltemporarilydisabletheflashmemoryandcrashthesystemifthememoryisusedforcode.
Bit2—Selectswhichsetofthetwolines/OExand/WExwillbedrivenformemoryaccessesinthisquadrant.
Bits1,0—Determineswhichofthethreechipselectlineswillbedrivenformemoryaccessestothisquadrant.
Allbitsofthecontrolregisterareinitializedtozeroonreset.
Table3.
MemoryBankControlRegisterx(MBxCR=14h+x)Bit(s)ValueDescription7:6004waitstates012waitstates101waitstates110waitstates51InvertaddressA1941InvertaddressA1831Write-protectmemorythisquadrant20Use/OE0,/WE01Use/OE1,/WE11:000Use/CS001Use/CS11xUse/CS2
Cwww.
rabbit.
com1TN202RabbitMemoryManagementInaNutshellTheRabbitCPUhasaMemoryManagementUnit(MMU)thatcontrolshowlogicalmemoryaddressesmapintophysicaladdresses,andaMemoryInterfaceUnitthatcontrolshowphysicaladdressesmapintoactualhardware.
TheDynamicCcompilerandlibrariesgenerallyhandlememorymappingdetailssothatmostDynamicCusersdon'thavetoconcernthemselveswithit,butsomeadvancedapplicationsmayneedtomanipulatetheMMUand/ortheMIU.
Forfurtherdetailsonmemorymanagement,seetheRabbitmicroprocessoruser'smanualforyourRabbitchip.
DefinitionsPhysical(orLinear)Addresses-20-bitaddressesrepresentingthe1Maddressspacethatlogicaladdressesmapinto.
Thehighest20-bitaddressis0xFFFFF.
ThedefaultaddressesintheDynamicCdevelopmentsystemflashstartatphysicaladdress0x00000andinRAMstartatphysicaladdress0x80000.
LogicalAddresses-16-bitaddressesrepresentinga64Kaddressspace.
Thehighest16-bitaddressis0x0FFFF.
MostRabbitinstructionsuselogicaladdresses.
ThelocationinphysicalmemorywheretheseaddressesmapintoiscompletelycontrollablebytheprogrammerviatheMMU.
Segment-Ablockoflogicalmemory;theblocksizesaremultiplesof4K(0x01000)Bank-A256KblockofPM,ona256Kboundary(0x40000).
TherearefourbanksavailablewithintheRabbitphysicaladdressspace.
Thestartingaddressofeachbankis0x00000,0x40000,0x80000,and0xC0000.
2www.
rabbit.
comTN202MemoryMappingUnitTheMMUtranslatesa16-bitlogicaladdresstoa20-bitphysicaladdress.
Thelogicaladdressspaceisdividedintofoursegments:xmem,stack,data,andbase.
ThexmemsegmentalwaysoccupiesE000h–FFFFh.
Theothersegmentsarelocatedfrom0000htoDFFFh,andareadjustableinsizetoanywherefrom0bytestoE000hbytes.
ThetotalsizeofallthreeisalwaysE000h.
ThestacksegmentstartsabovethedatasegmentandalwaysendsatDFFFh.
Thedatasegmentisalwaysabovethebasesegment.
Theboundariesbetweenthebasesegmentandthedatasegment,andbetweenthedataseg-mentandthestacksegmentaresetbyanMMUregister,SEGSIZE.
TheuppernibbleofSEGSIZErepre-sentsthestack-databoundary(in1000hbyteunits),andthelowernibblerepresentsthedata-baseboundary(in1000hbyteunits).
Eachoftheupperthreesegmentshasanassociatedsegmentregisterusedtomaplogicaladdressesthatfallwithinthesegmenttothephysicaladdressspace.
Fromtoptobottom,theyare:XPCSTACKSEGDATASEG.
Ineachcase,thephysicaladdressiscomputedbyshiftingthesegmentregisterleft12bits(multiplyingby1000h)andaddingittothel6-bitlogicaladdress.
Hereisthealgorithmforconvertinglogicaladdressestophysicaladdresses.
AbbreviationsLetSEGSIZE=XYhwhereXisthehighnibbleandYisthelownibble.
IfLA>=E000hPA=LA+(XPCx1000h)ElseIfLA>=X000hPA=LA+(STACKSEGx1000h)ElseIfLA>=Y000hPA=LA+(DATASEGx1000h)ElsePA=LAAnyofthesegmentregisterscanbeloadedwithanewvalidvalueatanytime,butthishastobedonewithgreatcare.
Forexample,ifcodeisexecutinginthexmemsegmentandtheXPCischanged,thenexecutionwillnotcontinueatthenextinstruction,butinsteadwillcontinueatthelocationinphysicalmemorywherethelogicaladdressofthenextinstructionmapsto.
ThisisbecausethePC(programcounter)registerholdsalogicaladdress.
LM-LogicalMemoryPM-PhysicalMemoryLA-LogicalAddress-addresswithintheLMPA-PhysicalAddress-addresswithinthePMTN202www.
rabbit.
com3ExampleTheMMUregistersaresetasfollows:XPC=0xF8SEGSIZE=0xD6STACKSEG=0x92DATASEG=0x7AThephysicaladdressofthebottomofthexmemsegmentisgivenby:0xF8000+0x0E000=0x06000(bit20,the21storcarrybit,isignored)Thephysicaladdressofthebottomofthestacksegmentisgivenby:0x92000+0x0D000=0x9F000Thephysicaladdressofthebottomofthedatasegmentisgivenby:0x7A000+0x06000=0x80000Notethatthedatasegmentstartsatthebeginningofthe"normal"RAMspaceand,fora128KRAM,thestacksegmentisallocated4K.
TherearespecialDynamicCfunctionstoaccessdataataspecificPA:root2xmem()andxmem2root().
Therearealsoseveralassemblylanguageinstructions:LDPformemoryaccessLCALLandLJPforbranchingNotethattheLDPinstructionsbypasstheMMUandgodirectlytotheMIU(seethenextsection).
Thefollowingdiagramillustratesthememorymappingdiscussedaboveusingthesamplecalculationswitha128Kflashanda128KRAM.
4www.
rabbit.
comTN202Figure1.
MemoryMappingBetweenLogicalAddressandPhysicalAddressMemoryInterfaceUnitTheMIUcontrolsmemoryaccessaftertheMMUdeterminesthephysicaladdress.
TherearefiveregistersassociatedwiththeMIU:MMIDRMB0CRMB1CRMB2CRMB3CRTheprimaryfunctionoftheMMIDRregisteristoallowthesystemtopermanentlyenable/CS1.
ThiscouldallowfasteraccesstotheRAMbykeepingthechipalwaysselected.
However,youwillneedtoinsurethatthe/OEand/or/WEsignalsarenotsharedwithanotherdevice.
EachofthefourMemoryBankControlRegistersMB0CR,MB1CR,MB2CRandMB3CR.
controlsone256Kquadrantofthe1Mphysicaladdressspace.
Theseregisterscontrolwaitstates,CS/WE/OElineusageandwriteprotection.
TheMBxCRregistersalsocanbesetuptoinvertaddresslinesA18andA19.
Ifbit4ofoneoftheseregis-tersisset,theMIUinvertsA18afterthelogicaltophysicalconversionisdonebytheMMU.
Ifbit5ofoneoftheseregistersisset,theMIUinvertsA19afterthelogicaltophysicalconversionisdonebytheMMU.
unusedunusedRAMFlashLogicalAddressSpaceXMEMStackDataBase0xFFFF0xE0000xD0000x60000x0000PhysicalAddressSpace0xFFFFF0xC00000xA00000x800000x400000x200000x000000x9F0000x06000TN202www.
rabbit.
com5Fora256Korsmallerdevice,addresslineinversionhasnoeffectsincethehighestaddresslineneededtoaddress256kisA17,butfora512Kdevice,thismeansthatwehaveaccesstothewhole512Kviaone256Kquadrantofphysicalmemory.
BecausewecancontrolA19aswell,each256Kquadrantofphysicaladdressescanactuallyaddressawhole1M.
This,incombinationwithdifferentCS/WE/OEcombinationscontrollablebythesameregisters,givestheRabbitaccessto6Mofmemorywithnoexternalgluelogic.
ExampleMB2CRissettomaptoCS1/WE1/OE1,andtheselinesgointoa512KRAM.
Thereforephysicaladdresses80000h-BFFFFh(quadrant2of0-3)maptooffsetsinthechipof00000h-3FFFFh(thelower256Kofthechip)usinglinesA0-A17withA18notasserted.
Nowwesetbit4ofMB2CRtoinvertA18.
Physicaladdresses80000h-BFFFFhnowmaptooffsetsinthechipof40000h-7FFFFh(theupper256Kofthechip.
)usinglinesA0-A17withA18asserted.
MMU/MIURegistersSegmentandMemoryBankRegistersTable1liststhedetailsaboutthesegmentregisters.
Table2liststhedetailsaboutthememorybankcontrolregisters.
Table1.
SegmentRegistersRegisterNameMnemonicI/OAddressR/WPostResetMMUInstruction/DataRegisterMMIDR10hR/Wxxx00000StackSegmentRegisterSTACKSEG11hR/W00000000LocatesstacksegmentinphysicalmemoryDataSegmentRegisterDATASEG12hR/W00000000LocatesdatasegmentinphysicalmemorySegmentSizeRegisterSEGSIZE13hR/W11111111Bits7.
.
4–boundaryaddressstacksegmentBits3.
.
0–boundaryaddressdatasegmentTable2.
MemoryBankControlRegistersRegisterNameMnemonicI/OAddressR/WPostResetMemoryBank0ControlRegisterMB0CR14hW00000000MemoryBank1ControlRegisterMB1CR15hWxxxxxxxxMemoryBank2ControlRegisterMB2CR16hWxxxxxxxxMemoryBank3ControlRegisterMB3CR17hWxxxxxxxx6www.
rabbit.
comTN202MemoryBankControlRegisterFunctionsThistabledetailsthefunctionalityofthememorybankcontrolregistersandthenecessarybitvalues.
Table3describestheoperationofthefourmemorybankcontrolregisters.
Theregistersarewrite-only.
Eachregistercontrolsonequadrantinthe1Maddressspace.
Bits7,6—Thenumberofwaitstatesusedinaccesstothisquadrant.
Withoutwaitstates,readrequires2clocksandwriterequires3clocks.
Thewaitstateaddstothesenumbers.
Bits5,4—Thesebitsallowtheupperaddresslinestobeinverted.
Thisinversionoccursafterthelogicthatselectsthebankregister,sosettingtheselineshasnoeffectonwhichbankregisterisused.
Theinversionmaybeusedtoinstalla1Mmemorychipinthespacenormallyallocatedtoa256Kchip.
Thelargermemorycanthenbeaccessedas4pagesof256Keach.
Thereisnoeffectoutsidethequadrantthatthememorybankcontrolregisteriscontrolling.
Bit3—Inhibitsthewritepulsetomemoryaccessedinthisquadrant.
Usefulforprotectingflashmemoryfromaninadvertentwritepulse,whichwillnotactuallywritetotheflashbecauseitispro-tectedbylockcodes,butwilltemporarilydisabletheflashmemoryandcrashthesystemifthememoryisusedforcode.
Bit2—Selectswhichsetofthetwolines/OExand/WExwillbedrivenformemoryaccessesinthisquadrant.
Bits1,0—Determineswhichofthethreechipselectlineswillbedrivenformemoryaccessestothisquadrant.
Allbitsofthecontrolregisterareinitializedtozeroonreset.
Table3.
MemoryBankControlRegisterx(MBxCR=14h+x)Bit(s)ValueDescription7:6004waitstates012waitstates101waitstates110waitstates51InvertaddressA1941InvertaddressA1831Write-protectmemorythisquadrant20Use/OE0,/WE01Use/OE1,/WE11:000Use/CS001Use/CS11xUse/CS2
- unitsphysicalmemory相关文档
- eventphysicalmemory
- bringphysicalmemory
- maintainsphysicalmemory
- reasonsphysicalmemory
- enabledphysicalmemory
- specificphysicalmemory
提速啦（69元起）香港大带宽CN2+BGP独享云服务器
香港大带宽服务器香港大带宽云服务器目前市场上可以选择的商家十分少，这次给大家推荐的是我们的老便宜提速啦的香港大带宽云服务器，默认通用BGP线路（即CN2+BGP）是由三网直连线路 中国电信骨干网以及HGC、NTT、PCCW等国际线路混合而成的高品质带宽（精品带宽）线路，可有效覆盖全球200多个国家和地区。（适用于绝大部分应用场景，适合国内外访客访问，域名无需备案）提速啦官网链接：点击进入香港Cer...
3元/首月香港便宜vps究竟是什么货。
便宜的香港vps多少钱?现在国外VPS主机的价格已经很便宜了，美国VPS主机最低一个月只要十几元，但同样免备案的香港VPS价格贵不贵呢?或者说便宜的香港VPS多少钱?香港vps主机价格要比美国机房的贵一些，但比国内的又便宜不少，所以目前情况是同等配置下，美国VPS比香港的便宜，香港VPS比国内(指大陆地区)的便宜。目前，最便宜香港vps低至3元/首月、18元/月起，今天云服务器网(www.yunt...
DogYun春节优惠：动态云7折,经典云8折,独立服务器月省100元,充100送10元
传统农历新年将至，国人主机商DogYun(狗云)发来了虎年春节优惠活动，1月31日-2月6日活动期间使用优惠码新开动态云7折，经典云8折，新开独立服务器可立减100元/月；使用优惠码新开香港独立服务器优惠100元，并次月免费；活动期间单笔充值每满100元赠送10元，还可以参与幸运大转盘每日抽取5折码，流量，余额等奖品；商家限量推出一款年付特价套餐，共100台，每个用户限1台，香港VPS年付199元...
physicalmemory为你推荐
-
恶意win7支持ipad支持ipad城乡居民社会养老保险人脸识别生存认证ipad连不上wifiiPad 连不上Wifi，显示无互联网连接重庆电信网速测试电信100M下载速度多少M，为什么我家里电信100M下载速度最快5M美妙，是不是严重缩水fusionchartsfusioncharts怎么生成图片至excel谷歌sbgoogle一下"SB"，虽然显示的是baidu排第一，链接的不是baidu.icloudiphone苹果6显示已停用请连接itunes什么意思如何用itunes备份如何使用iTunes最新版进行备份？急！！