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IDT8T49N008ANLGIREVISIONAFEBRUARY13,201412014IntegratedDeviceTechnology,Inc.
DATASHEETProgrammableFemtoClockNGLVPECL/LVDSClockGeneratorwith8-OutputsIDT8T49N008IGeneralDescriptionTheIDT8T49N008IisaneightoutputClockSynthesizerwithselectableLVDSorLVPECLoutputs.
TheIDT8T49N008Icansynthesizeanyoneoffourfrequenciesfromasinglecrystalorreferenceclock.
ThefourfrequenciesareselectedfromtheFrequencySelectionTable(Table3A)andareprogrammedviaI2Cinterface.
Thefourpredefinedfrequenciesareselectedintheuserapplicationbytwofrequencyselectionpins.
NotethedesiredprogrammedfrequenciesmustbeusedwiththecorrespondingcrystalorclockfrequencyasindicatedinTable3A.
ExcellentphasenoiseperformanceismaintainedwithIDT'sFourthGenerationFemtoClockNGPLLtechnology,whichdeliverssub-400fsRMSphasejitter.
FeaturesFourthGenerationFemtoClockNGPLLtechnologyEightselectableLVPECLorLVDSoutputsCLK,nCLKinputpaircanacceptthefollowingdifferentialinputlevels:LVPECL,LVDS,HCSLFemtoClockNGVCORange:1.
91GHz-2.
5GHzRMSphasejitterat156.
25MHz(12kHz-20MHz):228fs(typical)RMSphasejitterat156.
25MHz(10kHz-1MHz):175fs(typical)Full2.
5Vor3.
3VpowersupplyI2CprogramminginterfacePCIExpress(2.
5Gb/S),Gen2(5Gb/s)andGen3(8Gb/s)jittercompliant-40°Cto85°CambientoperatingtemperatureLead-free(RoHS6)packagingPinAssignmentIDT8T49N008I40-LeadVFQFN6mmx6mmx0.
925mmpackagebody4.
65mmx4.
65mmE-PadNLPackage12345678910313233343536373839402019181716151413121130292827262524232221Q0nQ0Q1nQ1VCCOQ2nQ2Q3nQ3VEEQ4nQ4Q5nQ5VCCOQ6nQ6Q7nQ7VEEFSEL1VCCVEEADDR_SELFSEL0nCLKCLKVEEXTAL_OUTXTAL_INVEESCLKSDATAVEEVCCALOCKVEEVCCCLK_SELVEEIDT8T49N008ANLGIREVISIONAFEBRUARY13,201422014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSBlockDiagramCLKSELXTAL_INXTAL_OUTXtalOscFemtoClockNGVCODivider,OutputType&OutputEnableSelection÷P[1:0]01OUTPUTENABLEOUTPUTSTYLE88PhaseDetector+ChargePumpPSPulldownPulldownPullupPullupPulldownPulldownPU/PDPulldownVPP/FSEL0G_CLK/FSEL1SCLKSDATAADDR_SELCLKnCLK÷M[8:1]10LOCKQ0nQ0Q1nQ1Q2nQ2Q3nQ3Q4nQ4Q5nQ5Q6nQ6Q7nQ7÷N[6:0]IDT8T49N008ANLGIREVISIONAFEBRUARY13,201432014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSPinDescriptionandPinCharacteristicTablesTable1.
PinDescriptionsNOTE:PullupandPulldownrefertointernalinputresistors.
SeeTable2,PinCharacteristics,fortypicalvalues.
Table2.
PinCharacteristicsNumberNameTypeDescription1,2Q0,nQ0OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
3,4Q1,nQ1OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
5,26VCCOPowerOutputsupplypins.
6,7Q2,nQ2OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
8,9Q3,nQ3OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
10,13,18,21,31,34,37,40VEEPowerNegativesupplypins.
11,12XTAL_INXTAL_OUTInputCrystaloscillatorinterface.
XTAL_INistheinput,XTAL_OUTistheoutput.
CrystalfrequencyisselectedfromTable3A.
14CLKInputPulldownNon-invertingdifferentialclockinput.
15nCLKInputPullup/PulldownInvertingdifferentialclockinput.
InternalresistorbiastoVCC/2.
16,20FSEL0,FSEL1InputPulldownFrequencyandconfiguration.
Selectsbetweenoneoffourfactoryprogrammablepower-updefaultconfigurations.
ThefourconfigurationscanhavedifferentPLLstates,outputfrequencies,outputstylesandoutputstates.
Thesedefaultconfigurationscanbeoverwrittenafterpower-upviaI2C.
LVCMOS/LVTTLinterfacelevels.
00=Configuration0(default)01=Configuration110=Configuration211=Configuration317ADDR_SELInputPulldownI2CAddressselectpin.
LVCMOS/LVTTLinterfacelevels.
19,38VCCPowerCoresupplypins.
22,23nQ7,Q7OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
24,25nQ6,Q6OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
27,28nQ5,Q5OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
29,30nQ4,Q4OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
32SCLKInputPullupI2CClockInput.
LVCMOS/LVTTLinterfacelevels.
33SDATAInput/OutputPullupI2CDataInput.
Input:LVCMOS/LVTTLinterfacelevels.
Output:OpenDrain.
35VCCAPowerAnalogsupplypin.
36LOCKOutputPLLLockIndicator.
LVCMOS/LVTTLinterfacelevels.
39CLK_SELInputPulldownInputsourcecontrolpin.
LVCMOS/LVTTLinterfacelevels.
0=XTAL(default)1=CLK,nCLKSymbolParameterTestConditionsMinimumTypicalMaximumUnitsCINInputCapacitance3.
5pFRPULLDOWNInputPulldownResistor51kRPULLUPInputPullupResistor51kIDT8T49N008ANLGIREVISIONAFEBRUARY13,201442014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSFrequencyConfigurationTable3A.
FrequencyConfigurationExamplesNOTE:Eachdevicesupports4outputfrequencies(withrelatedinputorcrystalvalue)asselectedfromthistableRegisterSettings.
NOTE:XTALoperation:fOUT=fREF*PS*M/N;CLK,nCLKinputoperation:fOUT=(fREF/P)*PS*M/N.
OutputFrequencies(MHz)InputFrequencyorCrystalFrequency(MHz)InputClockDividerPInputClockPrescalerPSFeedbackDividerMOutputDividerNVCOFrequency(MHz)30.
7230.
721x232641966.
0861.
4430.
721x232321966.
0862.
5251x24032200076.
830.
721x240322457.
678.
125251x250322500100251x240202000106.
2526.
56251x240202125122.
830.
721x232161966.
08125251x240162000133.
33251x248182400148.
5271x244162376150251x242142100153.
630.
721x240162457.
6155.
5219.
441x264162488.
32156.
25251x2501625001002x1501625001255x250162500159.
37526.
56251x236121912.
5160201x248121920166.
66251x240122000184.
3230.
721x236122211.
8461.
441x136122211.
84187.
5251x190122250200251x240102000212.
526.
56251x240102125250251x24082000300251x24882400311.
0419.
441x26482488.
3277.
761x13282488.
32155.
522x13282488.
32312.
5251x250825001252x14082500156.
255x24082500318.
7526.
56251x23661912.
5322.
26562525.
781252x115061933.
59375375251x19062250400251x2405200042526.
56251x24052125491.
5230.
721x23241966.
08614.
430.
721x24042457.
6122.
882x14042457.
6153.
65x24042457.
6622.
0819.
441x26442488.
32625251x250425001228.
8830.
721x24022457.
6IDT8T49N008ANLGIREVISIONAFEBRUARY13,201452014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3B.
I2CRegisterMapRegisterBinaryRegisterAddressRegisterBitD7D6D5D4D3D2D1D0000000M0[8]M0[7]M0[6]M0[5]M0[4]M0[3]M0[2]M0[1]100001M1[8]M1[7]M1[6]M1[5]M1[4]M1[3]M1[2]M1[1]200010M2[8]M2[7]M2[6]M2[5]M2[4]M2[3]M2[2]M2[1]300011M3[8]M3[7]M3[6]M3[5]M3[4]M3[3]M3[2]M3[1]400100unusedN0[6]N0[5]N0[4]N0[3]N0[2]N0[1]N0[0]500101unusedN1[6]N1[5]N1[4]N1[3]N1[2]N1[1]N1[0]600110unusedN2[6]N2[5]N2[4]N2[3]N2[2]N2[1]N2[0]700111unusedN3[6]N3[5]N3[4]N3[3]N3[2]N3[1]N3[0]801000unusedBYPASS0PS0[1]PS0[0]P0[1]P0[0]CP0[1]CP0[0]901001unusedBYPASS1PS1[1]PS1[0]P1[1]P1[0]CP1[1]CP1[0]1001010unusedBYPASS2PS2[1]PS2[0]P2[1]P2[0]CP2[1]CP2[0]1101011unusedBYPASS3PS3[1]PS3[0]P3[1]P3[0]CP3[1]CP3[0]1201100LVDS_SEL0[Q7]LVDS_SEL0[Q6]LVDS_SEL0[Q5]LVDS_SEL0[Q4]LVDS_SEL0[Q3]LVDS_SEL0[Q2]LVDS_SEL0[Q1]LVDS_SEL0[Q0]1301101LVDS_SEL1[Q7]LVDS_SEL1[Q6]LVDS_SEL1[Q5]LVDS_SEL1[Q4]LVDS_SEL1[Q3]LVDS_SEL1[Q2]LVDS_SEL1[Q1]LVDS_SEL1[Q0]1401110LVDS_SEL2[Q7]LVDS_SEL2[Q6]LVDS_SEL2[Q5]LVDS_SEL2[Q4]LVDS_SEL2[Q3]LVDS_SEL2[Q2]LVDS_SEL2[Q1]LVDS_SEL2[Q0]1501111LVDS_SEL3[Q7]LVDS_SEL3[Q6]LVDS_SEL3[Q5]LVDS_SEL3[Q4]LVDS_SEL3[Q3]LVDS_SEL3[Q2]LVDS_SEL3[Q1]LVDS_SEL3[Q0]1610000OE0[Q7]OE0[Q6]OE0[Q5]OE0[Q4]OE0[Q3]OE0[Q2]OE0[Q1]OE0[Q0]1710001OE1[Q7]OE1[Q6]OE1[Q5]OE1[Q4]OE1[Q3]OE1[Q2]OE1[Q1]OE1[Q0]1810010OE2[Q7]OE2[Q6]OE2[Q5]OE2[Q4]OE2[Q3]OE2[Q2]OE2[Q1]OE2[Q0]1910011OE3[Q7]OE3[Q6]OE3[Q5]OE3[Q4]OE3[Q3]OE3[Q2]OE3[Q1]OE3[Q0]2010100reservedreservedreservedreservedreservedreservedunusedunused2110101unusedunusedunusedunusedunusedunusedunusedunused2210110unusedunusedunusedunusedunusedunusedunusedunused2310111unusedunusedunusedunusedunusedunusedunusedunusedIDT8T49N008ANLGIREVISIONAFEBRUARY13,201462014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3C.
I2CFunctionDescriptionsBitsNameFunctionPn[1:0]InputClockDividerRegistern(n=0.
.
.
3)SetsthePLLinputclockdivider.
Thedividervaluehastherangeof1,2,4and5.
SeeTable3F.
Pn[1:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
PSn(1:0)InputPrescalerRegistern(n=0.
.
.
3)SetsthePLLinputclockprescalervalue.
Validprescalervaluesarex0.
5,x1orx2.
SeeTable3F.
Setprescalertox2foroptimumphasenoiseperformance.
PSn[1:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
Mn[8:1]IntegerFeedbackDividerRegistern(n=0.
.
.
3)Setstheintegerfeedbackdividervalue.
BasedontheFemtoClockNGVCOrange,theapplicablefeedbackdividerssettingsare16thru250.
Pleasenotetheregistervaluepresentsbits[8:1]ofMn,theLSBofMnisnotintheregister.
Mn[8:1]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
Nn[6:0]OutputDividerRegistern(n=0.
.
.
3)Setstheoutputdivider.
Theoutputdividervaluecanrangefrom2,3,4,5,6and8,10,12to126(step:2).
SeeTable3Gfortheoutputdividercoding.
Nn[6:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
CPn[1:0]PLLBandwidthRegistern(n=0.
.
.
3)SetstheFemtoClockNGPLLbandwidthbycontrollingthechargepumpcurrent.
SeeTable3H.
CPn[1:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
BYPASSnPLLBypassRegistern(n=0.
.
.
3)BypassesPLL.
OutputoftheprescalerisroutedthroughtheoutputdividerNtotheoutputfanoutbuffer.
Programminga1tothisbitbypassesthePLL.
Programminga0tothisbitroutestheoutputoftheprescalerthroughthePLL.
BYPASSnbitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
OEn[Q0]OEn[Q1]OEn[Q2]OEn[Q3]OEn[Q4]OEn[Q5]OEn[Q6]OEn[Q7]OutputEnableRegistern(n=0.
.
.
3)SetstheoutputstoActiveorHighImpedance.
Programminga0tothisbitsetstheoutputstoHighImpedance.
Programminga1setstheoutputstoactivestatus.
OEn[Q0],OEn[Q1],OEn[Q2],OEn[Q3],OEn[Q4],OEn[Q5],OEn[Q6],OEn[Q7]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
LVDS_SELn[Q0]LVDS_SELn[Q1]LVDS_SELn[Q2]LVDS_SELn[Q3]LVDS_SELn[Q4]LVDS_SELn[Q5]LVDS_SELn[Q6]LVDS_SELn[Q7]OutputStyleRegistern(n=0.
.
.
3)SetsthedifferentialoutputstyletoeitherLVDSorLVPECLinterfacelevels.
Programminga1tothisbitsetstheoutputstylestoLVDSlevels.
Programminga0tothisbitsetstheoutputstylestoLVPECLlevels.
LVDS_SELn[Q0],LVDS_SELn[Q1],LVDS_SELn[Q2],LVDS_SELn[Q3]LVDS_SELn[Q4],LVDS_SELn[Q5],LVDS_SELn[Q6],LVDS_SELn[Q7]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
IDT8T49N008ANLGIREVISIONAFEBRUARY13,201472014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3D.
FeedbackDividerMnCodingNote:Mnisalwaysanevenvalue.
TheMn[0]bitsarenotimplemented.
Table3E.
PLLPre-ScalerPCodingRegisterBitFeedbackDividerMnMn[8:1]DoNotUse1thru15000010001600001001180000101020000010112200001100thru0001111124thru6200100000640010000166001000106800100011700010010072.
.
.
Mn00110010100001100111020011010010400110101106.
.
.
Mn01111010244011110112460111110024801111101250CLK_SELInputP[1:0]PS[1:0]InputClockDividerPInputClockPrescalerPSInputFrequency(MHz)MinimumMaximum0XTALxx001x11040011x0.
520401x1x25401CLK00001x110120011x0.
5202401x1x256001002x120240012x0.
5404801x2x21012010004x140480014x0.
5808001x4x22024011005x150600015x0.
51008001x5x225300IDT8T49N008ANLGIREVISIONAFEBRUARY13,201482014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3F.
PLLPostDividerNCodingNOTE:Xdenotes"don'tcare".
Table3G.
FemtoClockNGPLLBandwidthCodingNOTE:FemtoClockNGPLLstabilityisonlyguaranteedoverthefeedbackdividerrangeslistedisTable3G.
RegisterBitOutputDividerNOutputFrequencyRangeNn[6:0]fOUT_MIN(MHz)fOUT_MAX(MHz)000000X2DoNotUse00000102955125000000113636.
67833.
3300001004477.
562500001015382500000011X6318.
33416.
67000100X8238.
75312.
5000101X10191250000110X12159.
1667208.
33000111X14136.
4286178.
57001000X16119.
375156.
25.
.
.
N(eveninteger)(1910÷N)(2500÷N)111101X12415.
4020.
16111111X12615.
1619.
84RegisterBitFeedbackDividerValueRangeCPn1CPn0MinimumMaximum00164801481001010025011192250IDT8T49N008ANLGIREVISIONAFEBRUARY13,201492014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSPower-upDefaultConfigurationDescriptionTheIDT8T49N008Isupportsavarietyofoptionssuchasdifferentoutputstyles,numberofprogrammeddefaultfrequencies,outputen-ableandoperatingtemperaturerange.
Thedeviceoptionsandde-faultfrequenciesmustbespecifiedatthetimeoforderandareprogrammedbyIDTpriortoshipment.
Thedocument,Programma-bleFemtoClockNGProductOrderingGuidespecifiestheavailableordercodes,includingthedeviceoptionsanddefaultfrequencycon-figurations.
Examplepartnumber:8T49N004A-007NLGI,specifiesaquadfrequencyclockgeneratorwithdefaultfrequenciesof106.
25MHz,133.
333MHz,156.
25MHzand156.
25MHz,withfourLVDSoutputsthatareenabledafterpower-up,specifiedoverthein-dustrialtemperaturerangeandhousedinalead-free(6/6RoHS)VFQFNpackage.
OtherordercodeswithrespectiveprogrammedfrequenciesareavailablefromIDTuponrequest.
Afterpower-upchangestotheoutputfrequenciesarecontrolledbyFSEL[1:0]ortheI2Cinterface.
Changestotheoutputstylesandstatesofoutputs(enabledordisabled)canalsobecontrolledwiththeI2Cinterfaceafterpowerup.
Table3H.
Power-upDefaultSettingsSerialInterfaceConfigurationDescriptionTheIDT8T49N008IhasanI2C-compatibleconfigurationinterfacetoaccessanyoftheinternalregisters(Table3B)forfrequencyandPLLparameterprogramming.
TheIDT849N008IactsasaslavedeviceontheI2Cbusandhastheaddress0b110111x,wherexissetbythevalueontheADDR_SELinput(seeTables3Iand3J).
Theinterfaceacceptsbyte-orientedblockwriteandblockreadoperations.
Anaddressbyte(P)specifiestheregisteraddress(Table3B)asthebytepositionofthefirstregistertowriteorread.
Databytes(registers)areaccessedinsequentialorderfromthelowesttothehighestbyte(mostsignificantbitfirst,seeTable3K,3L).
Readandwriteblocktransferscanbestoppedafteranycompletebytetransfer.
ItisrecommendedtoterminatetheI2Creadorwritetransferafteraccessingbyte#23bysendingastopcommand.
ForfullelectricalI2Ccompliance,itisrecommendedtouseexternalpull-upresistorsforSDATAandSCLK.
Theinternalpull-upresistorshaveasizeof50ktypical.
Table3I.
I2CDeviceSlaveAddressADDR_SEL=0(default)Table3J.
I2CDeviceSlaveAddressADDR_SEL=1Table3K.
BlockWriteOperationTable3L.
BlockReadOperationFSEL1FSEL0FrequencyPLLState(OnorBypass)OutputState(ActiveorHighImpedance)OutputStyle(LVDSorLVPECL)0(default)0(default)Frequency0PLLState0OutputState0OutputStyle001Frequency1PLLState1OutputState1OutputStyle110Frequency2PLLState2OutputState2OutputStyle211Frequency3PLLState3OutputState3OutputStyle31101110R/W1101111R/WBit12:891011:181920:272829-3637DescriptionSTARTSlaveAddressW(0)ACKAddressBytePACKDataByte(P)ACKDataByte(P+1)ACKDataByte.
.
.
ACKSTOPLength(bits)1711818181811Bit12:891011:18192021:27282930:373839-4647DescriptionSTARTSlaveAddressW(0)ACKAddressbytePACKRepeatedSTARTSlaveaddressR(1)ACKDataByte(P)ACKDataByte(P+1)ACKDataByte.
.
.
ACKSTOPLength(bits)17118117118181811IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014102014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSAbsoluteMaximumRatingsNOTE:StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Theseratingsarestressspecificationsonly.
FunctionaloperationofproductattheseconditionsoranyconditionsbeyondthoselistedintheDCCharacteristicsorACCharacteristicsisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectproductreliability.
DCElectricalCharacteristicsTable4A.
PowerSupplyDCCharacteristics,VCC=VCCO=3.
3V±5%,VEE=0V,TA=-40°Cto85°CTable4B.
PowerSupplyDCCharacteristics,VCC=VCCO=2.
5V±5%,VEE=0V,TA=-40°Cto85°CItemRatingSupplyVoltage,VCC3.
63VInputs,VIXTAL_INOtherInput0Vto2V-0.
5VtoVCC+0.
5VOutputs,IO(LVPECL)ContinuousCurrentSurgeCurrentOutputs,IO(SDATA)Outputs,IO(LVDS)ContinuousCurrentSurgeCurrent50mA100mA10mA10mA15mAPackageThermalImpedance,JA32.
4C/W(0mps)StorageTemperature,TSTG-65Cto150CSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVCCCoreSupplyVoltage3.
1353.
33.
465VVCCAAnalogSupplyVoltageVCC–0.
323.
3VCCVVCCOOutputSupplyVoltage3.
1353.
33.
465VICCAAnalogSupplyCurrent32mAIEEPowerSupplyCurrentLVPECL225mAICCPowerSupplyCurrentLVDS125mAICCOOutputSupplyCurrentLVDS162mASymbolParameterTestConditionsMinimumTypicalMaximumUnitsVCCCoreSupplyVoltage2.
3752.
52.
625VVCCAAnalogSupplyVoltageVCC–0.
282.
5VCCVVCCOOutputSupplyVoltage2.
3752.
52.
625VICCAAnalogSupplyCurrent28mAIEEPowerSupplyCurrentLVPECL216mAICCPowerSupplyCurrentLVDS122mAICCOOutputSupplyCurrentLVDS160mAIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014112014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable4C.
LVCMOS/LVTTLDCCharacteristics,VCC=VCCO=3.
3V±5%or2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Outputterminatedwith50toVCCO/2.
SeeParameterMeasurementInformation,OutputLoadTestCircuitdiagrams.
Table4D.
DifferentialDCCharacteristics,VCC=VCCO=3.
3V±5%or2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Commonmodeinputvoltageisatthecrosspoint.
Table4E.
LVPECLDCCharacteristics,VCC=VCCO=3.
3V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Outputsterminationwith50toVCC–2V.
SymbolParameterTestConditionsMinimumTypicalMaximumUnitsVIHInputHighVoltageSCLK,SDATA,FSEL[1:0],CLK_SEL,ADDR_SELVCC=3.
3V2VCC+0.
3VVCC=2.
5V1.
7VCC+0.
3VVILInputLowVoltageSCLK,SDATA,CLK_SEL,ADDR_SELVCC=3.
3V-0.
30.
8VVCC=2.
5V-0.
30.
7VFSEL[1:0],VCC=3.
3Vor2.
5V0.
5VIIHInputHighCurrentSCLK,SDATAVCC=VIN=3.
465Vor2.
625V5AFSEL[1:0],CLK_SEL,ADDR_SELVCC=VIN=3.
465Vor2.
625V150AIILInputLowCurrentSCLK,SDATAVCC=3.
465Vor2.
625V,VIN=0V-150AFSEL[1:0],CLK_SEL,ADDR_SELVCC=3.
465Vor2.
625V,VIN=0V-5AVOHOutputHighVoltage;NOTE1LOCKVCC=3.
465V2.
6VLOCKVCC=2.
625V1.
8VVOLOutputLowVoltage;NOTE1LOCKVCC=3.
465Vor2.
625V0.
5VSymbolParameterTestConditionsMinimumTypicalMaximumUnitsIIHInputHighCurrentCLK,nCLKVCC=VIN=3.
465Vor2.
625V150AIILInputLowCurrentnCLKVCC=3.
465Vor2.
625V,VIN=0V-150ACLKVCC=3.
465Vor2.
625V,VIN=0V-5AVPPPeak-to-PeakVoltage0.
151.
3VVCMRCommonModeInputVoltage;NOTE1VEEVCC–0.
85VSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVOHOutputHighVoltage;NOTE1VCC–1.
1VCCO–0.
75VVOLOutputLowVoltage;NOTE1VCC–2.
0VCCO–1.
6VVSWINGPeak-to-PeakOutputVoltageSwing0.
61.
0VIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014122014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable4F.
LVPECLDCCharacteristics,VCC=VCCO=2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Outputsterminationwith50toVCC–2V.
Table4G.
LVDSDCCharacteristics,VCC=VCCO=3.
3V±5%,VEE=0V,TA=-40°Cto85°CTable4H.
LVDSDCCharacteristics,VCC=VCCO=2.
5V±5%,VEE=0V,TA=-40°Cto85°CTable5.
CrystalCharacteristicsSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVOHOutputHighVoltage;NOTE1VCC–1.
2VCCO–0.
75VVOLOutputLowVoltage;NOTE1VCC–2.
0VCC–1.
5VVSWINGPeak-to-PeakOutputVoltageSwing0.
51.
0VSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVODDifferentialOutputVoltage247345454mVVODVODMagnitudeChange50mVVOSOffsetVoltage1.
151.
251.
375VVOSVOSMagnitudeChange50mVSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVODDifferentialOutputVoltage230340454mVVODVODMagnitudeChange50mVVOSOffsetVoltage1.
151.
251.
375VVOSVOSMagnitudeChange50mVParameterTestConditionsMinimumTypicalMaximumUnitsModeofOscillationFundamentalFrequency1040MHzLoadCapacitance(CL)1018pFEquivalentSeriesResistance(ESR)50IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014132014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSACElectricalCharacteristicsTable6A.
PCIExpressJitterSpecifications,VCC=VCCO=3.
3V±5%or2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE:Electricalparametersareguaranteedoverthespecifiedambientoperatingtemperaturerange,whichisestablishedwhenthedeviceismountedinatestsocketwithmaintainedtransverseairflowgreaterthan500lfpm.
Thedevicewillmeetspecificationsafterthermalequilibriumhasbeenreachedundertheseconditions.
Foradditionalinformation,refertothePCIExpressApplicationNotesectioninthedatasheet.
NOTE1:Peak-to-PeakjitterafterapplyingsystemtransferfunctionfortheCommonClockArchitecture.
MaximumlimitforPCIExpressGen1is86pspeak-to-peakforasamplesizeof106clockperiods.
NOTE2:RMSjitterafterapplyingthetwoevaluationbandstothetwotransferfunctionsdefinedintheCommonClockArchitectureandreportingtheworstcaseresultsforeachevaluationband.
MaximumlimitforPCIExpressGeneration2is3.
1psRMSfortREFCLK_HF_RMS(HighBand)and3.
0psRMSfortREFCLK_LF_RMS(LowBand).
NOTE3:RMSjitterafterapplyingsystemtransferfunctionforthecommonclockarchitecture.
ThisspecificationisbasedonthePCIExpressBaseSpecificationRevision0.
7,October2009andissubjecttochangependingthefinalreleaseversionofthespecification.
NOTE4:Thisparameterisguaranteedbycharacterization.
Nottestedinproduction.
SymbolParameterTestConditionsMinimumTypicalMaximumPCIeIndustrySpecificationUnitstj(PCIeGen1)PhaseJitterPeak-to-Peak;NOTE1,4=100MHz,25MHzCrystalInputEvaluationBand:0Hz-Nyquist(clockfrequency/2)8.
313.
286pstREFCLK_HF_RMS(PCIeGen2)PhaseJitterRMS;NOTE2,4=100MHz,25MHzCrystalInputHighBand:1.
5MHz-Nyquist(clockfrequency/2)0.
781.
353.
1pstREFCLK_LF_RMS(PCIeGen2)PhaseJitterRMS;NOTE2,4=100MHz,25MHzCrystalInputLowBand:10kHz-1.
5MHz0.
050.
103.
0pstREFCLK_RMS(PCIeGen3)PhaseJitterRMS;NOTE3,4=100MHz,25MHzCrystalInputEvaluationBand:0Hz-Nyquist(clockfrequency/2)0.
1750.
340.
8psIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014142014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable6B.
ACCharacteristics,VCC=VCCO=3.
3V±5%or2.
5V±5%VEE=0V,TA=-40°Cto85°CNOTE:Electricalparametersareguaranteedoverthespecifiedambientoperatingtemperaturerange,whichisestablishedwhenthedeviceismountedinatestsocketwithmaintainedtransverseairflowgreaterthan500lfpm.
Thedevicewillmeetspecificationsafterthermalequilibriumhasbeenreachedundertheseconditions.
NOTE1:RefertoPhaseNoisePlots.
NOTE2:Definedasskewbetweenoutputsatthesamesupplyvoltageandwithequalloadconditions.
Measuredatthedifferentialcrosspoints.
NOTE3:Theseparametersareguaranteedbycharacterization.
Nottestedinproduction.
NOTE4:RefertotLOCKandtTRANSITIONinParameterMeasurementInformation.
SymbolParameterTestConditionsMinimumTypicalMaximumUnitsfDIFF_INDifferentialInputFrequency10312.
5MHzfVCOVCOFrequency19102500MHztjit()RMSPhaseJitter,Random;NOTE125MHzCrystal,fOUT=100MHz,IntegrationRange:12kHz–20MHz258332fs25MHzCrystal,fOUT=125MHz,IntegrationRange:12kHz–20MHz220291fs25MHzCrystal,fOUT=125MHz,IntegrationRange:10kHz–1MHz164232fs25MHzCrystal,fOUT=156.
25MHz,IntegrationRange:12kHz–20MHz228306fs25MHzCrystal,fOUT=156.
25MHz,IntegrationRange:10kHz–1MHz175234fs25MHzCrystal,fOUT=250MHz,IntegrationRange:12kHz–20MHz212292fs30.
72MHzCrystal,fOUT=491.
52MHz,IntegrationRange:12kHz–20MHz213299fs19.
44MHzCrystal,fOUT=622.
08MHz,IntegrationRange:12kHz–20MHz280386fstsk(o)OutputSkew;NOTE2,3LVPECLOutputsLVDS_SEL=050psLVDSOutputsLVDS_SEL=150pstR/tFOutputRise/FallTimeLVPECLOutputs20%-80%,LVDS_SEL=0100400psLVDSOutputs20%-80%,LVDS_SEL=1100400psodcOutputDutyCycleN>3OutputDivider;LVDS_SEL=0or14753%N3OutputDivider;LVDS_SEL=0or14258%tLOCKPLLLockTime;NOTE3,4LOCKOutput20mstTRANSITIONTransitionTime;NOTE3,4LOCKOutput20msIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014152014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTypicalPhaseNoiseat100MHz(3.
3V)TypicalPhaseNoiseat125MHz(3.
3V)NoisePower(dBc/Hz)OffsetFrequency(Hz)NoisePower(dBc/Hz)OffsetFrequency(Hz)IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014162014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTypicalPhaseNoiseat156.
25MHz(3.
3V)NoisePower(dBc/Hz)OffsetFrequency(Hz)IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014172014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSParameterMeasurementInformation3.
3VLVPECLOutputLoadACTestCircuit3.
3VLVDSOutputLoadACTestCircuitDifferentialInputLevels2.
5VLVPECLOutputLoadACTestCircuit2.
5VLVDSOutputLoadACTestCircuitRMSPhaseJitterVCC,2V-1.
3V±0.
165V2VVCCAVCCO3.
3V±5%VCC,VCCOVCCAVCCVEEnCLKCLK-0.
5V±0.
125VVCC,2V2VVCCAVCCOSCOPEQxnQx2.
5V±5%POWERSUPPLY+–FloatGNDVCC,VCCOVCCAIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014182014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSParameterMeasurementInformation,continuedOutputSkewLVPECLOutputRise/FallTimeOffsetVoltageSetupOutputDutyCycle/PulseWidth/PeriodLVDSOutputRise/FallTimeDifferentialOutputVoltageSetupnQxQxnQyQynQ[0:7]Q[0:7]nQ[0:7]Q[0:7]20%80%80%20%tRtFVODnQ[0:7]Q[0:7]IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014192014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSParameterMeasurementInformation,continuedLockTime&TransitionTimeApplicationsInformationRecommendationsforUnusedInputandOutputPinsInputs:LVCMOSControlPinsAllcontrolpinshaveinternalpullupsorpulldowns;additionalresistanceisnotrequiredbutcanbeaddedforadditionalprotection.
A1kresistorcanbeused.
CLK/nCLKInputsForapplicationsnotrequiringtheuseofthedifferentialinput,bothCLKandnCLKcanbeleftfloating.
Thoughnotrequired,butforadditionalprotection,a1kresistorcanbetiedfromCLKtoground.
CrystalInputsForapplicationsnotrequiringtheuseofthecrystaloscillatorinput,bothXTAL_INandXTAL_OUTcanbeleftfloating.
Thoughnotrequired,butforadditionalprotection,a1kresistorcanbetiedfromXTAL_INtoground.
Outputs:LVPECLOutputsAllunusedLVPECLoutputpairscanbeleftfloating.
Werecommendthatthereisnotraceattached.
Bothsidesofthedifferentialoutputpairshouldeitherbeleftfloatingorterminated.
LVDSOutputsAllunusedLVDSoutputpairscanbeeitherleftfloatingorterminatedwith100across.
Iftheyareleftfloating,thereshouldbenotraceattached.
IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014202014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSWiringtheDifferentialInputtoAcceptSingle-EndedLevelsFigure1showshowadifferentialinputcanbewiredtoacceptsingleendedlevels.
ThereferencevoltageV1=VCC/2isgeneratedbythebiasresistorsR1andR2.
Thebypasscapacitor(C1)isusedtohelpfilternoiseontheDCbias.
Thisbiascircuitshouldbelocatedasclosetotheinputpinaspossible.
TheratioofR1andR2mightneedtobeadjustedtopositiontheV1inthecenteroftheinputvoltageswing.
Forexample,iftheinputclockswingis2.
5VandVCC=3.
3V,R1andR2valueshouldbeadjustedtosetV1at1.
25V.
ThevaluesbelowareforwhenboththesingleendedswingandVCCareatthesamevoltage.
Thisconfigurationrequiresthatthesumoftheoutputimpedanceofthedriver(Ro)andtheseriesresistance(Rs)equalsthetransmissionlineimpedance.
Inaddition,matchedterminationattheinputwillattenuatethesignalinhalf.
Thiscanbedoneinoneoftwoways.
First,R3andR4inparallelshouldequalthetransmissionlineimpedance.
Formost50applications,R3andR4canbe100.
ThevaluesoftheresistorscanbeincreasedtoreducetheloadingforslowerandweakerLVCMOSdriver.
Whenusingsingle-endedsignaling,thenoiserejectionbenefitsofdifferentialsignalingarereduced.
EventhoughthedifferentialinputcanhandlefullrailLVCMOSsignaling,itisrecommendedthattheamplitudebereduced.
Thedatasheetspecifiesalowerdifferentialamplitude,howeverthisonlyappliestodifferentialsignals.
Forsingle-endedapplications,theswingcanbelarger,howeverVILcannotbelessthan-0.
3VandVIHcannotbemorethanVCC+0.
3V.
Thoughsomeoftherecommendedcomponentsmightnotbeused,thepadsshouldbeplacedinthelayout.
Theycanbeutilizedfordebuggingpurposes.
Thedatasheetspecificationsarecharacterizedandguaranteedbyusingadifferentialsignal.
Figure1.
RecommendedSchematicforWiringaDifferentialInputtoAcceptSingle-endedLevelsReceiver+-R4100R3100RSZo=50OhmRoDriverVCCVCCR21KR11KC10.
1uFRo+Rs=ZoV1VCCVCCIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014212014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSOverdrivingtheXTALInterfaceTheXTAL_INinputcanbeoverdrivenbyanLVCMOSdriverorbyonesideofadifferentialdriverthroughanACcouplingcapacitor.
TheXTAL_OUTpincanbeleftfloating.
Theamplitudeoftheinputsignalshouldbebetween500mVand1.
8Vandtheslewrateshouldnotbelessthan0.
2V/nS.
For3.
3VLVCMOSinputs,theamplitudemustbereducedfromfullswingtoatleasthalftheswinginordertopreventsignalinterferencewiththepowerrailandtoreduceinternalnoise.
Figure2Ashowsanexampleoftheinterfacediagramforahighspeed3.
3VLVCMOSdriver.
Thisconfigurationrequiresthatthesumoftheoutputimpedanceofthedriver(Ro)andtheseriesresistance(Rs)equalsthetransmissionlineimpedance.
Inaddition,matchedterminationatthecrystalinputwillattenuatethesignalinhalf.
Thiscanbedoneinoneoftwoways.
First,R1andR2inparallelshouldequalthetransmissionlineimpedance.
Formost50applications,R1andR2canbe100.
ThiscanalsobeaccomplishedbyremovingR1andchangingR2to50.
ThevaluesoftheresistorscanbeincreasedtoreducetheloadingforaslowerandweakerLVCMOSdriver.
Figure2BshowsanexampleoftheinterfacediagramforanLVPECLdriver.
ThisisastandardLVPECLterminationwithonesideofthedriverfeedingtheXTAL_INinput.
Itisrecommendedthatallcomponentsintheschematicsbeplacedinthelayout.
Thoughsomecomponentsmightnotbeused,theycanbeutilizedfordebuggingpurposes.
Thedatasheetspecificationsarecharacterizedandguaranteedbyusingaquartzcrystalastheinput.
Figure2A.
GeneralDiagramforLVCMOSDrivertoXTALInputInterfaceFigure2B.
GeneralDiagramforLVPECLDrivertoXTALInputInterfaceVCCXTAL_OUTXTAL_INR1100R2100Zo=50ohmsRsRoZo=Ro+RsC1.
1ufLVCMOSDriverXTAL_OUTXTAL_INZo=50ohmsC2.
1ufLVPECLDriverZo=50ohmsR150R250R350IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014222014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS3.
3VDifferentialClockInputInterfaceTheCLK/nCLKacceptsLVDS,LVPECL,HCSLandotherdifferentialsignals.
BothVSWINGandVOHmustmeettheVPPandVCMRinputrequirements.
Figures3Ato3DshowinterfaceexamplesfortheCLK/nCLKinputdrivenbythemostcommondrivertypes.
Theinputinterfacessuggestedhereareexamplesonly.
Ifthedriverisfromanothervendor,usetheirterminationrecommendation.
Pleaseconsultwiththevendorofthedrivercomponenttoconfirmthedriverterminationrequirements.
Figure3A.
CLK/nCLKInputDrivenbya3.
3VLVPECLDriverFigure3C.
CLK/nCLKInputDrivenbya3.
3VHCSLDriverFigure3B.
CLK/nCLKInputDrivenbya3.
3VLVPECLDriverFigure3D.
CLK/nCLKInputDrivenbya3.
3VLVDSDriver3.
3VCLKnCLK3.
3V3.
3VLVPECLDifferentialInputHCSL*R3*R4CLKnCLK3.
3V3.
3VDifferentialInputCLKnCLKDifferentialInputLVPECL3.
3VZo=50ΩZo=50Ω3.
3VR150ΩR250ΩR250Ω3.
3VR1100ΩLVDSCLKnCLK3.
3VReceiverZo=50ΩZo=50ΩIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014232014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS2.
5VDifferentialClockInputInterfaceTheCLK/nCLKacceptsLVDS,LVPECL,HCSLandotherdifferentialsignals.
BothVSWINGandVOHmustmeettheVPPandVCMRinputrequirements.
Figures4Ato4DshowinterfaceexamplesfortheCLK/nCLKinputdrivenbythemostcommondrivertypes.
Theinputinterfacessuggestedhereareexamplesonly.
Ifthedriverisfromanothervendor,usetheirterminationrecommendation.
Pleaseconsultwiththevendorofthedrivercomponenttoconfirmthedriverterminationrequirements.
Figure4A.
CLK/nCLKInputDrivenbya2.
5VLVPECLDriverFigure4C.
CLK/nCLKInputDrivenbya2.
5VHCSLDriverFigure4B.
CLK/nCLKInputDrivenbya2.
5VLVPECLDriverFigure4D.
CLK/nCLKInputDrivenbya2.
5VLVDSDriverR3250R4250R162.
5R262.
52.
5VZo=50Zo=50CLKnCLK2.
5V2.
5VLVPECLDifferentialInputHCSL*R333*R433CLKnCLK2.
5V2.
5VZo=50Zo=50DifferentialInputR150R250*Optional–R3andR4canbe0CLKnCLKDifferentialInputLVPECL2.
5VZo=50Zo=502.
5VR150R250R3182.
5VR1100LVDSCLKnCLK2.
5VDifferentialInputZo=50Zo=50IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014242014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSLVDSDriverTerminationForageneralLVDSinterface,therecommendedvaluefortheterminationimpedance(ZT)isbetween90and132.
Theactualvalueshouldbeselectedtomatchthedifferentialimpedance(Z0)ofyourtransmissionline.
Atypicalpoint-to-pointLVDSdesignusesa100parallelresistoratthereceiveranda100differentialtransmission-lineenvironment.
Inordertoavoidanytransmission-linereflectionissues,thecomponentsshouldbesurfacemountedandmustbeplacedasclosetothereceiveraspossible.
IDToffersafulllineofLVDScompliantdeviceswithtwotypesofoutputstructures:currentsourceandvoltagesource.
ThestandardterminationschematicasshowninFigure5Acanbeusedwitheithertypeofoutputstructure.
Figure5B,whichcanalsobeusedwithbothoutputtypes,isanoptionalterminationwithcentertapcapacitancetohelpfiltercommonmodenoise.
Thecapacitorvalueshouldbeapproximately50pF.
Ifusinganon-standardtermination,itisrecommendedtocontactIDTandconfirmiftheoutputstructureiscurrentsourceorvoltagesourcetype.
Inaddition,sincetheseoutputsareLVDScompatible,theinputreceiver'samplitudeandcommon-modeinputrangeshouldbeverifiedforcompatibilitywiththeoutput.
Terminationfor3.
3VLVPECLOutputsTheclocklayouttopologyshownbelowisatypicalterminationforLVPECLoutputs.
Thetwodifferentlayoutsmentionedarerecommendedonlyasguidelines.
ThedifferentialoutputsarelowimpedancefolloweroutputsthatgenerateECL/LVPECLcompatibleoutputs.
Therefore,terminatingresistors(DCcurrentpathtoground)orcurrentsourcesmustbeusedforfunctionality.
Theseoutputsaredesignedtodrive50transmissionlines.
Matchedimpedancetechniquesshouldbeusedtomaximizeoperatingfrequencyandminimizesignaldistortion.
Figures6Aand6Bshowtwodifferentlayoutswhicharerecommendedonlyasguidelines.
Othersuitableclocklayoutsmayexistanditwouldberecommendedthattheboarddesignerssimulatetoguaranteecompatibilityacrossallprintedcircuitandclockcomponentprocessvariations.
Figure6A.
3.
3VLVPECLOutputTerminationFigure6B.
3.
3VLVPECLOutputTerminationLVDSDriverLVDSDriverLVDSReceiverLVDSReceiverZTCZOZTZOZTZT2ZT2Figure5A.
StandardTerminationFigure5B.
OptionalTerminationR184R2843.
3VR3125R4125Zo=50Zo=50LVPECLInput3.
3V3.
3V+_IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014252014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTerminationfor2.
5VLVPECLOutputsFigure7AandFigure7Bshowexamplesofterminationfor2.
5VLVPECLdriver.
Theseterminationsareequivalenttoterminating50toVCCO–2V.
ForVCCO=2.
5V,theVCCO–2Visveryclosetogroundlevel.
TheR3inFigure7BcanbeeliminatedandtheterminationisshowninFigure7C.
Figure7A.
2.
5VLVPECLDriverTerminationExampleFigure7C.
2.
5VLVPECLDriverTerminationExampleFigure7B.
2.
5VLVPECLDriverTerminationExample2.
5VLVPECLDriverVCCO=2.
5V2.
5V2.
5V5050R1250R3250R262.
5R462.
5+–2.
5VLVPECLDriverVCCO=2.
5V2.
5V5050R150R250+–2.
5VLVPECLDriverVCCO=2.
5V2.
5V5050R150R250R318+–IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014262014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSVFQFNEPADThermalReleasePathInordertomaximizeboththeremovalofheatfromthepackageandtheelectricalperformance,alandpatternmustbeincorporatedonthePrintedCircuitBoard(PCB)withinthefootprintofthepackagecorrespondingtotheexposedmetalpadorexposedheatslugonthepackage,asshowninFigure8.
ThesolderableareaonthePCB,asdefinedbythesoldermask,shouldbeatleastthesamesize/shapeastheexposedpad/slugareaonthepackagetomaximizethethermal/electricalperformance.
SufficientclearanceshouldbedesignedonthePCBbetweentheouteredgesofthelandpatternandtheinneredgesofpadpatternfortheleadstoavoidanyshorts.
WhilethelandpatternonthePCBprovidesameansofheattransferandelectricalgroundingfromthepackagetotheboardthroughasolderjoint,thermalviasarenecessarytoeffectivelyconductfromthesurfaceofthePCBtothegroundplane(s).
Thelandpatternmustbeconnectedtogroundthroughthesevias.
Theviasactas"heatpipes".
Thenumberofvias(i.
e.
"heatpipes")areapplicationspecificanddependentuponthepackagepowerdissipationaswellaselectricalconductivityrequirements.
Thus,thermalandelectricalanalysisand/ortestingarerecommendedtodeterminetheminimumnumberneeded.
Maximumthermalandelectricalperformanceisachievedwhenanarrayofviasisincorporatedinthelandpattern.
Itisrecommendedtouseasmanyviasconnectedtogroundaspossible.
Itisalsorecommendedthattheviadiametershouldbe12to13mils(0.
30to0.
33mm)with1ozcopperviabarrelplating.
Thisisdesirabletoavoidanysolderwickinginsidetheviaduringthesolderingprocesswhichmayresultinvoidsinsolderbetweentheexposedpad/slugandthethermalland.
Precautionsshouldbetakentoeliminateanysoldervoidsbetweentheexposedheatslugandthelandpattern.
Note:Theserecommendationsaretobeusedasaguidelineonly.
Forfurtherinformation,pleaserefertotheApplicationNoteontheSurfaceMountAssemblyofAmkor'sThermally/ElectricallyEnhanceLeadframeBasePackage,AmkorTechnology.
Figure8.
P.
C.
AssemblyforExposedPadThermalReleasePath–SideView(drawingnottoscale)SOLDERSOLDERPINPINEXPOSEDHEATSLUGPINPADPINPADGROUNDPLANELANDPATTERN(GROUNDPAD)THERMALVIAIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014272014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSSchematicLayoutFigure9(nextpage)showsanexampleofIDT8T49N008Iapplicationschematic.
Theschematicfocusesonfunctionalconnectionsandisnotconfigurationspecific.
Refertothepindescriptionandfunctionaltablesinthedatasheettoensurethatthelogiccontrolinputsareproperlyset.
InthisexamplethedeviceisoperatedatVCC=VCCO=VCCA=3.
3Vratherthan2.
5V.
TheCLK,nCLKinputsareprovidedbya3.
3VLVPECLdriveranddepictedwithaY-terminationratherthanthestandardfourresistorVCC-2VThevininterminationforreasonsofminimumterminationpowerandlayoutsimplicity.
ThreeexamplesofPECLterminationsareshownfortheoutputstodemonstratemixingofPECLterminationdesignoptions.
Aswithanyhighspeedanalogcircuitry,thepowersupplypinsarevulnerabletonoise.
Toachieveoptimumjitterperformance,powersupplyisolationisrequired.
TheIDT8T49N006IprovidesseparatepowersuppliestoisolatefromcouplingintotheinternalPLL.
Inordertoachievethebestpossiblefiltering,itisrecommendedthattheplacementofthefiltercomponentsbeonthedevicesideofthePCBasclosetothepowerpinsaspossible.
Ifspaceislimited,the0.
1uFcapacitorineachpowerpinfiltershouldbeplacedonthedevicesideofthePCBandtheothercomponentscanbeplacedontheoppositeside.
Powersupplyfilterrecommendationsareageneralguidelinetobeusedforreducingexternalnoisefromcouplingintothedevices.
TheVCCandVCCOfiltersstarttoattenuatenoiseatapproximately10kHz.
Ifaspecificfrequencynoisecomponentisknown,suchasswitchingpowersuppliesfrequencies,itisrecommendedthatcomponentvaluesbeadjustedandifrequired,additionalfilteringbeadded.
Additionally,goodgeneraldesignpracticesforpowerplanevoltagestabilitysuggestsaddingbulkcapacitanceinthelocalareaofalldevices.
IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014282014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSFigure9.
IDT8T49N008IApplicationSchematicC90.
1uFC170.
1uFVCCOC70.
1uFVCC_38VCCAQ2_NQ2_PQ3_NQ3_PQ4_PQ4_NQ5_PQ5_NQ6_PQ6_NZo=50OhmR982.
5R1450R1550Zo=50Ohm+-Zo=50OhmR1350OptionalFourResistorThevininTerminationRU2NotInstallRU11KRD21KVCCRD1NotInstallVCCC60.
1uFC100.
1uF3.
3VC1410uFFB1BLM18BB221SN112C1610uF3.
3VFB2BLM18BB221SN112C190.
1uFToLogicInputpinsLogicControlInputExamplesSetLogicInputto'1'SetLogicInputto'0'SCLKSDATA3.
3VC2110uF3.
3VFB3BLM18BB221SN112C220.
1uFVCCOVCC_19VCC_38Zo=50OhmR450R550Zo=50OhmR350Q7_NC810uFR1610Q7_PR14.
7KR24.
7K3.
3VR6330Q1_NQ0_NQ0_PQ1_PC150.
1uFR1082.
5R8133R7133+-Zo=50OhmC239pFC189pFX125MHz(12pf)U1VEE37VCC38CLK_SEL39VEE40Q01nQ02nQ14Q13VCCO5Q26nQ27Q38nQ39VEE10XTAL_IN11XTAL_OUT12nQ624Q723nQ722VEE21FSEL120VCC19VEE18ADDR_SEL17FSEL016nCLK15CLK14VEE13LOCK36VCCA35VEE34SDATA33SCLK32VEE31Q430nQ429Q528nQ527VCCO26Q625epad41VCC_19PECLDriverToLogicInputpinsVCCACLK_SELFSEL0FSEL1ADDR_SELForACterminationoptionsconsulttheIDTApplicationsNote"Termination-3.
3VLVPECL"LOCKIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014292014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSPCIExpressApplicationNotePCIExpressjitteranalysismethodologymodelsthesystemresponsetoreferenceclockjitter.
TheblockdiagrambelowshowsthemostfrequentlyusedCommonClockArchitectureinwhichacopyofthereferenceclockisprovidedtobothendsofthePCIExpressLink.
Inthejitteranalysis,thetransmit(Tx)andreceive(Rx)serdesPLLsaremodeledaswellasthephaseinterpolatorinthereceiver.
ThesetransferfunctionsarecalledH1,H2,andH3respectively.
Theoverallsystemtransferfunctionatthereceiveris:ThejitterspectrumseenbythereceiveristheresultofapplyingthissystemtransferfunctiontotheclockspectrumX(s)andis:Inordertogeneratetimedomainjitternumbers,aninverseFourierTransformisperformedonX(s)*H3(s)*[H1(s)-H2(s)].
PCIExpressCommonClockArchitectureForPCIExpressGen1,onetransferfunctionisdefinedandtheevaluationisperformedovertheentirespectrum:DCtoNyquist(e.
gfora100MHzreferenceclock:0Hz–50MHz)andthejitterresultisreportedinpeak-peak.
PCIeGen1MagnitudeofTransferFunctionForPCIExpressGen2,twotransferfunctionsaredefinedwith2evaluationrangesandthefinaljitternumberisreportedinRMS.
ThetwoevaluationrangesforPCIExpressGen2are10kHz–1.
5MHz(LowBand)and1.
5MHz–Nyquist(HighBand).
TheplotsshowtheindividualtransferfunctionsaswellastheoveralltransferfunctionHt.
PCIeGen2AMagnitudeofTransferFunctionPCIeGen2BMagnitudeofTransferFunctionForPCIExpressGen3,onetransferfunctionisdefinedandtheevaluationisperformedovertheentirespectrum.
ThetransferfunctionparametersaredifferentfromGen1andthejitterresultisreportedinRMS.
PCIeGen3MagnitudeofTransferFunctionForamorethoroughoverviewofPCIExpressjitteranalysismethodology,pleaserefertoIDTApplicationNotePCIExpressReferenceClockRequirements.
HtsH3sH1sH2s–=YsXsH3sH1sH2s–=IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014302014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSLVPECLPowerConsiderationsThissectionprovidesinformationonpowerdissipationandjunctiontemperaturefortheIDT8T49N008I.
Equationsandexamplecalculationsarealsoprovided.
1.
PowerDissipation.
ThetotalpowerdissipationfortheIDT8T49N008Iisthesumofthecorepowerplusthepowerdissipatedintheload(s).
ThefollowingisthepowerdissipationforVCC=3.
465V,whichgivesworstcaseresults.
NOTE:PleaserefertoSection3fordetailsoncalculatingpowerdissipatedintheload.
Power(core)MAX=VCC_MAX*IEE_MAX=3.
465V*225mA=779.
625mWPower(outputs)MAX=31.
55mW/LoadedOutputpairIfalloutputsareloaded,thetotalpoweris8*31.
55mW=252.
4mWTotalPower_MAX(3.
465V,withalloutputsswitching)=779.
625W+252.
4mW=1032.
025W2.
JunctionTemperature.
Junctiontemperature,Tj,isthetemperatureatthejunctionofthebondwireandbondpaddirectlyaffectsthereliabilityofthedevice.
Themaximumrecommendedjunctiontemperatureis125°C.
Limitingtheinternaltransistorjunctiontemperature,Tj,to125°Censuresthatthebondwireandbondpadtemperatureremainsbelow125°C.
TheequationforTjisasfollows:Tj=JA*Pd_total+TATj=JunctionTemperatureJA=Junction-to-AmbientThermalResistancePd_total=TotalDevicePowerDissipation(examplecalculationisinsection1above)TA=AmbientTemperatureInordertocalculatejunctiontemperature,theappropriatejunction-to-ambientthermalresistanceJAmustbeused.
Assumingnoairflowandamulti-layerboard,theappropriatevalueis32.
4°C/WperTable7below.
Therefore,Tjforanambienttemperatureof85°Cwithalloutputsswitchingis:85°C+1.
032W*32.
4°C/W=118.
4°C.
Thisisbelowthelimitof125°C.
Thiscalculationisonlyanexample.
Tjwillobviouslyvarydependingonthenumberofloadedoutputs,supplyvoltage,airflowandthetypeofboard(multi-layer).
Table7.
ThermalResistanceJAfor40-LeadVFQFN,ForcedConvectionJAbyVelocityMetersperSecond013Multi-LayerPCB,JEDECStandardTestBoards32.
4°C/W25.
7°C/W23.
4°C/WIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014312014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS3.
CalculationsandEquations.
ThepurposeofthissectionistocalculatethepowerdissipationfortheLVPECLoutputpair.
LVPECLoutputdrivercircuitandterminationareshowninFigure10.
Figure10.
LVPECLDriverCircuitandTerminationTocalculateworstcasepowerdissipationintotheload,usethefollowingequationswhichassumea50load,andaterminationvoltageofVCCO–2V.
Forlogichigh,VOUT=VOH_MAX=VCCO_MAX–0.
75V(VCCO_MAX–VOH_MAX)=0.
75VForlogiclow,VOUT=VOL_MAX=VCCO_MAX–1.
6V(VCCO_MAX–VOL_MAX)=1.
6VPd_Hispowerdissipationwhentheoutputdriveshigh.
Pd_Listhepowerdissipationwhentheoutputdriveslow.
Pd_H=[(VOH_MAX–(VCCO_MAX–2V))/RL]*(VCCO_MAX–VOH_MAX)=[(2V–(VCCO_MAX–VOH_MAX))/RL]*(VCCO_MAX–VOH_MAX)=[(2V–0.
75V)/50]*0.
75V=18.
75mWPd_L=[(VOL_MAX–(VCCO_MAX–2V))/RL]*(VCCO_MAX–VOL_MAX)=[(2V–(VCCO_MAX–VOL_MAX))/RL]*(VCCO_MAX–VOL_MAX)=[(2V–1.
6V)/50]*1.
6V=12.
80mWTotalPowerDissipationperoutputpair=Pd_H+Pd_L=31.
55mWVOUTVCCOVCCO-2VQ1RL50ΩIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014322014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSLVDSPowerConsiderationsThissectionprovidesinformationonpowerdissipationandjunctiontemperaturefortheIDT8T49N008I.
Equationsandexamplecalculationsarealsoprovided.
1.
PowerDissipation.
ThetotalpowerdissipationfortheIDT8T49N008Iisthesumofthecorepowerplustheanalogpowerplusthepowerdissipatedintheload(s).
ThefollowingisthepowerdissipationforVCC=3.
3V+5%=3.
465V,whichgivesworstcaseresults.
Power(core)MAX=VCC_MAX*(ICC_MAX+ICCA_MAX)=3.
465V*(125mA+32mA)=544.
005mWPower(outputs)MAX=VCCO_MAX*ICCO_MAX=3.
465V*162mA=561.
33mWTotalPower_MAX=544.
005mW+561.
33mW=1105.
335mW2.
JunctionTemperature.
Junctiontemperature,Tj,isthetemperatureatthejunctionofthebondwireandbondpaddirectlyaffectsthereliabilityofthedevice.
Themaximumrecommendedjunctiontemperatureis125°C.
Limitingtheinternaltransistorjunctiontemperature,Tj,to125°Censuresthatthebondwireandbondpadtemperatureremainsbelow125°C.
TheequationforTjisasfollows:Tj=JA*Pd_total+TATj=JunctionTemperatureJA=Junction-to-AmbientThermalResistancePd_total=TotalDevicePowerDissipation(examplecalculationisinsection1above)TA=AmbientTemperatureInordertocalculatejunctiontemperature,theappropriatejunction-to-ambientthermalresistanceJAmustbeused.
Assumingnoairflowandamulti-layerboard,theappropriatevalueis32.
4°C/WperTable8below.
Therefore,Tjforanambienttemperatureof85°Cwithalloutputsswitchingis:85°C+1.
105W*32.
4°C/W=120.
8°C.
Thisisbelowthelimitof125°C.
Thiscalculationisonlyanexample.
Tjwillobviouslyvarydependingonthenumberofloadedoutputs,supplyvoltage,airflowandthetypeofboard(multi-layer).
Table8.
ThermalResistanceJAfor40-LeadVFQFN,ForcedConvectionJAbyVelocityMetersperSecond012.
5Multi-LayerPCB,JEDECStandardTestBoards32.
4°C/W25.
7°C/W23.
4°C/WIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014332014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSReliabilityInformationTable9.
JAvs.
AirFlowTablefora40-LeadVFQFNTransistorCountThetransistorcountforIDT8T49N008Iis:26,856JAvs.
AirFlowMetersperSecond012.
5Multi-LayerPCB,JEDECStandardTestBoards32.
4°C/W25.
7°C/W23.
4°C/WIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014342014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS40-LeadVFQFNPackageOutlineandPackageDimensionsIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014352014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS40-LeadVFQFNPackageOutlineandPackageDimensions,continued40-LeadVFQFN,D2/E2EPADDimensions:4.
65mmx4.
65mmIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014362014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSOrderingInformationTable10.
OrderingInformationNOTE:Forthespecific-dddordercodes,refertotheProgrammableFemtoClockNGProductOrderingGuidedocument.
Part/OrderNumberMarkingPackageShippingPackagingTemperature8T49N008A-dddNLGIIDT8T49N008A-dddNLGI"Lead-Free"40-LeadVFQFNTray-40Cto85C8T49N008A-dddNLGI8IDT8T49N008A-dddNLGI"Lead-Free"40-LeadVFQFNTape&Reel-40Cto85CIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014372014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSRevisionHistorySheetRevTablePageDescriptionofChangeDateA1PinAssignment-repositionedpinnumbers(11-20).
4/18/12AT1036Changedfooterpart/ordernumberfromIDT8T49N008BNLGItoIDT8T49N008ANLGI.
OrderingInformationTable-changedShippingPackagingfrom1000Tape&Reelto5000Tape&Reel.
4/23/12AT1011,3838ChangednameoftheIDT8T49N00xIProgrammableFemtoClockNGProductOrderingInformationdocumenttoProgrammableFemtoClockOrderingProductInformationDeletedquantityfromTape&Reel,DeletedLeadFreenote.
8/21/13AT1011138ChangedtitletoProgrammableFemtoClockNGLVPECL/LVDSClockGeneratorwith8-Outputs.
Changedtextfrom'ProgrammableFemtoClockOrderingProductInformation'to'ProgrammableFemtoClockNGProductOrderingGuide'.
ChangedNotefrom'ProgrammableFemtoClockOrderingProductInformation'to'ProgrammableFemtoClockNGProductOrderingGuide'.
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DATASHEETProgrammableFemtoClockNGLVPECL/LVDSClockGeneratorwith8-OutputsIDT8T49N008IGeneralDescriptionTheIDT8T49N008IisaneightoutputClockSynthesizerwithselectableLVDSorLVPECLoutputs.
TheIDT8T49N008Icansynthesizeanyoneoffourfrequenciesfromasinglecrystalorreferenceclock.
ThefourfrequenciesareselectedfromtheFrequencySelectionTable(Table3A)andareprogrammedviaI2Cinterface.
Thefourpredefinedfrequenciesareselectedintheuserapplicationbytwofrequencyselectionpins.
NotethedesiredprogrammedfrequenciesmustbeusedwiththecorrespondingcrystalorclockfrequencyasindicatedinTable3A.
ExcellentphasenoiseperformanceismaintainedwithIDT'sFourthGenerationFemtoClockNGPLLtechnology,whichdeliverssub-400fsRMSphasejitter.
FeaturesFourthGenerationFemtoClockNGPLLtechnologyEightselectableLVPECLorLVDSoutputsCLK,nCLKinputpaircanacceptthefollowingdifferentialinputlevels:LVPECL,LVDS,HCSLFemtoClockNGVCORange:1.
91GHz-2.
5GHzRMSphasejitterat156.
25MHz(12kHz-20MHz):228fs(typical)RMSphasejitterat156.
25MHz(10kHz-1MHz):175fs(typical)Full2.
5Vor3.
3VpowersupplyI2CprogramminginterfacePCIExpress(2.
5Gb/S),Gen2(5Gb/s)andGen3(8Gb/s)jittercompliant-40°Cto85°CambientoperatingtemperatureLead-free(RoHS6)packagingPinAssignmentIDT8T49N008I40-LeadVFQFN6mmx6mmx0.
925mmpackagebody4.
65mmx4.
65mmE-PadNLPackage12345678910313233343536373839402019181716151413121130292827262524232221Q0nQ0Q1nQ1VCCOQ2nQ2Q3nQ3VEEQ4nQ4Q5nQ5VCCOQ6nQ6Q7nQ7VEEFSEL1VCCVEEADDR_SELFSEL0nCLKCLKVEEXTAL_OUTXTAL_INVEESCLKSDATAVEEVCCALOCKVEEVCCCLK_SELVEEIDT8T49N008ANLGIREVISIONAFEBRUARY13,201422014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSBlockDiagramCLKSELXTAL_INXTAL_OUTXtalOscFemtoClockNGVCODivider,OutputType&OutputEnableSelection÷P[1:0]01OUTPUTENABLEOUTPUTSTYLE88PhaseDetector+ChargePumpPSPulldownPulldownPullupPullupPulldownPulldownPU/PDPulldownVPP/FSEL0G_CLK/FSEL1SCLKSDATAADDR_SELCLKnCLK÷M[8:1]10LOCKQ0nQ0Q1nQ1Q2nQ2Q3nQ3Q4nQ4Q5nQ5Q6nQ6Q7nQ7÷N[6:0]IDT8T49N008ANLGIREVISIONAFEBRUARY13,201432014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSPinDescriptionandPinCharacteristicTablesTable1.
PinDescriptionsNOTE:PullupandPulldownrefertointernalinputresistors.
SeeTable2,PinCharacteristics,fortypicalvalues.
Table2.
PinCharacteristicsNumberNameTypeDescription1,2Q0,nQ0OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
3,4Q1,nQ1OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
5,26VCCOPowerOutputsupplypins.
6,7Q2,nQ2OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
8,9Q3,nQ3OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
10,13,18,21,31,34,37,40VEEPowerNegativesupplypins.
11,12XTAL_INXTAL_OUTInputCrystaloscillatorinterface.
XTAL_INistheinput,XTAL_OUTistheoutput.
CrystalfrequencyisselectedfromTable3A.
14CLKInputPulldownNon-invertingdifferentialclockinput.
15nCLKInputPullup/PulldownInvertingdifferentialclockinput.
InternalresistorbiastoVCC/2.
16,20FSEL0,FSEL1InputPulldownFrequencyandconfiguration.
Selectsbetweenoneoffourfactoryprogrammablepower-updefaultconfigurations.
ThefourconfigurationscanhavedifferentPLLstates,outputfrequencies,outputstylesandoutputstates.
Thesedefaultconfigurationscanbeoverwrittenafterpower-upviaI2C.
LVCMOS/LVTTLinterfacelevels.
00=Configuration0(default)01=Configuration110=Configuration211=Configuration317ADDR_SELInputPulldownI2CAddressselectpin.
LVCMOS/LVTTLinterfacelevels.
19,38VCCPowerCoresupplypins.
22,23nQ7,Q7OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
24,25nQ6,Q6OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
27,28nQ5,Q5OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
29,30nQ4,Q4OutputDifferentialoutputpair.
LVPECLorLVDSinterfacelevels.
32SCLKInputPullupI2CClockInput.
LVCMOS/LVTTLinterfacelevels.
33SDATAInput/OutputPullupI2CDataInput.
Input:LVCMOS/LVTTLinterfacelevels.
Output:OpenDrain.
35VCCAPowerAnalogsupplypin.
36LOCKOutputPLLLockIndicator.
LVCMOS/LVTTLinterfacelevels.
39CLK_SELInputPulldownInputsourcecontrolpin.
LVCMOS/LVTTLinterfacelevels.
0=XTAL(default)1=CLK,nCLKSymbolParameterTestConditionsMinimumTypicalMaximumUnitsCINInputCapacitance3.
5pFRPULLDOWNInputPulldownResistor51kRPULLUPInputPullupResistor51kIDT8T49N008ANLGIREVISIONAFEBRUARY13,201442014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSFrequencyConfigurationTable3A.
FrequencyConfigurationExamplesNOTE:Eachdevicesupports4outputfrequencies(withrelatedinputorcrystalvalue)asselectedfromthistableRegisterSettings.
NOTE:XTALoperation:fOUT=fREF*PS*M/N;CLK,nCLKinputoperation:fOUT=(fREF/P)*PS*M/N.
OutputFrequencies(MHz)InputFrequencyorCrystalFrequency(MHz)InputClockDividerPInputClockPrescalerPSFeedbackDividerMOutputDividerNVCOFrequency(MHz)30.
7230.
721x232641966.
0861.
4430.
721x232321966.
0862.
5251x24032200076.
830.
721x240322457.
678.
125251x250322500100251x240202000106.
2526.
56251x240202125122.
830.
721x232161966.
08125251x240162000133.
33251x248182400148.
5271x244162376150251x242142100153.
630.
721x240162457.
6155.
5219.
441x264162488.
32156.
25251x2501625001002x1501625001255x250162500159.
37526.
56251x236121912.
5160201x248121920166.
66251x240122000184.
3230.
721x236122211.
8461.
441x136122211.
84187.
5251x190122250200251x240102000212.
526.
56251x240102125250251x24082000300251x24882400311.
0419.
441x26482488.
3277.
761x13282488.
32155.
522x13282488.
32312.
5251x250825001252x14082500156.
255x24082500318.
7526.
56251x23661912.
5322.
26562525.
781252x115061933.
59375375251x19062250400251x2405200042526.
56251x24052125491.
5230.
721x23241966.
08614.
430.
721x24042457.
6122.
882x14042457.
6153.
65x24042457.
6622.
0819.
441x26442488.
32625251x250425001228.
8830.
721x24022457.
6IDT8T49N008ANLGIREVISIONAFEBRUARY13,201452014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3B.
I2CRegisterMapRegisterBinaryRegisterAddressRegisterBitD7D6D5D4D3D2D1D0000000M0[8]M0[7]M0[6]M0[5]M0[4]M0[3]M0[2]M0[1]100001M1[8]M1[7]M1[6]M1[5]M1[4]M1[3]M1[2]M1[1]200010M2[8]M2[7]M2[6]M2[5]M2[4]M2[3]M2[2]M2[1]300011M3[8]M3[7]M3[6]M3[5]M3[4]M3[3]M3[2]M3[1]400100unusedN0[6]N0[5]N0[4]N0[3]N0[2]N0[1]N0[0]500101unusedN1[6]N1[5]N1[4]N1[3]N1[2]N1[1]N1[0]600110unusedN2[6]N2[5]N2[4]N2[3]N2[2]N2[1]N2[0]700111unusedN3[6]N3[5]N3[4]N3[3]N3[2]N3[1]N3[0]801000unusedBYPASS0PS0[1]PS0[0]P0[1]P0[0]CP0[1]CP0[0]901001unusedBYPASS1PS1[1]PS1[0]P1[1]P1[0]CP1[1]CP1[0]1001010unusedBYPASS2PS2[1]PS2[0]P2[1]P2[0]CP2[1]CP2[0]1101011unusedBYPASS3PS3[1]PS3[0]P3[1]P3[0]CP3[1]CP3[0]1201100LVDS_SEL0[Q7]LVDS_SEL0[Q6]LVDS_SEL0[Q5]LVDS_SEL0[Q4]LVDS_SEL0[Q3]LVDS_SEL0[Q2]LVDS_SEL0[Q1]LVDS_SEL0[Q0]1301101LVDS_SEL1[Q7]LVDS_SEL1[Q6]LVDS_SEL1[Q5]LVDS_SEL1[Q4]LVDS_SEL1[Q3]LVDS_SEL1[Q2]LVDS_SEL1[Q1]LVDS_SEL1[Q0]1401110LVDS_SEL2[Q7]LVDS_SEL2[Q6]LVDS_SEL2[Q5]LVDS_SEL2[Q4]LVDS_SEL2[Q3]LVDS_SEL2[Q2]LVDS_SEL2[Q1]LVDS_SEL2[Q0]1501111LVDS_SEL3[Q7]LVDS_SEL3[Q6]LVDS_SEL3[Q5]LVDS_SEL3[Q4]LVDS_SEL3[Q3]LVDS_SEL3[Q2]LVDS_SEL3[Q1]LVDS_SEL3[Q0]1610000OE0[Q7]OE0[Q6]OE0[Q5]OE0[Q4]OE0[Q3]OE0[Q2]OE0[Q1]OE0[Q0]1710001OE1[Q7]OE1[Q6]OE1[Q5]OE1[Q4]OE1[Q3]OE1[Q2]OE1[Q1]OE1[Q0]1810010OE2[Q7]OE2[Q6]OE2[Q5]OE2[Q4]OE2[Q3]OE2[Q2]OE2[Q1]OE2[Q0]1910011OE3[Q7]OE3[Q6]OE3[Q5]OE3[Q4]OE3[Q3]OE3[Q2]OE3[Q1]OE3[Q0]2010100reservedreservedreservedreservedreservedreservedunusedunused2110101unusedunusedunusedunusedunusedunusedunusedunused2210110unusedunusedunusedunusedunusedunusedunusedunused2310111unusedunusedunusedunusedunusedunusedunusedunusedIDT8T49N008ANLGIREVISIONAFEBRUARY13,201462014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3C.
I2CFunctionDescriptionsBitsNameFunctionPn[1:0]InputClockDividerRegistern(n=0.
.
.
3)SetsthePLLinputclockdivider.
Thedividervaluehastherangeof1,2,4and5.
SeeTable3F.
Pn[1:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
PSn(1:0)InputPrescalerRegistern(n=0.
.
.
3)SetsthePLLinputclockprescalervalue.
Validprescalervaluesarex0.
5,x1orx2.
SeeTable3F.
Setprescalertox2foroptimumphasenoiseperformance.
PSn[1:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
Mn[8:1]IntegerFeedbackDividerRegistern(n=0.
.
.
3)Setstheintegerfeedbackdividervalue.
BasedontheFemtoClockNGVCOrange,theapplicablefeedbackdividerssettingsare16thru250.
Pleasenotetheregistervaluepresentsbits[8:1]ofMn,theLSBofMnisnotintheregister.
Mn[8:1]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
Nn[6:0]OutputDividerRegistern(n=0.
.
.
3)Setstheoutputdivider.
Theoutputdividervaluecanrangefrom2,3,4,5,6and8,10,12to126(step:2).
SeeTable3Gfortheoutputdividercoding.
Nn[6:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
CPn[1:0]PLLBandwidthRegistern(n=0.
.
.
3)SetstheFemtoClockNGPLLbandwidthbycontrollingthechargepumpcurrent.
SeeTable3H.
CPn[1:0]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
BYPASSnPLLBypassRegistern(n=0.
.
.
3)BypassesPLL.
OutputoftheprescalerisroutedthroughtheoutputdividerNtotheoutputfanoutbuffer.
Programminga1tothisbitbypassesthePLL.
Programminga0tothisbitroutestheoutputoftheprescalerthroughthePLL.
BYPASSnbitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
OEn[Q0]OEn[Q1]OEn[Q2]OEn[Q3]OEn[Q4]OEn[Q5]OEn[Q6]OEn[Q7]OutputEnableRegistern(n=0.
.
.
3)SetstheoutputstoActiveorHighImpedance.
Programminga0tothisbitsetstheoutputstoHighImpedance.
Programminga1setstheoutputstoactivestatus.
OEn[Q0],OEn[Q1],OEn[Q2],OEn[Q3],OEn[Q4],OEn[Q5],OEn[Q6],OEn[Q7]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
LVDS_SELn[Q0]LVDS_SELn[Q1]LVDS_SELn[Q2]LVDS_SELn[Q3]LVDS_SELn[Q4]LVDS_SELn[Q5]LVDS_SELn[Q6]LVDS_SELn[Q7]OutputStyleRegistern(n=0.
.
.
3)SetsthedifferentialoutputstyletoeitherLVDSorLVPECLinterfacelevels.
Programminga1tothisbitsetstheoutputstylestoLVDSlevels.
Programminga0tothisbitsetstheoutputstylestoLVPECLlevels.
LVDS_SELn[Q0],LVDS_SELn[Q1],LVDS_SELn[Q2],LVDS_SELn[Q3]LVDS_SELn[Q4],LVDS_SELn[Q5],LVDS_SELn[Q6],LVDS_SELn[Q7]bitsareprogrammedwithvaluestosupportdefaultconfigurationsettingsforFSEL[1:0].
IDT8T49N008ANLGIREVISIONAFEBRUARY13,201472014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3D.
FeedbackDividerMnCodingNote:Mnisalwaysanevenvalue.
TheMn[0]bitsarenotimplemented.
Table3E.
PLLPre-ScalerPCodingRegisterBitFeedbackDividerMnMn[8:1]DoNotUse1thru15000010001600001001180000101020000010112200001100thru0001111124thru6200100000640010000166001000106800100011700010010072.
.
.
Mn00110010100001100111020011010010400110101106.
.
.
Mn01111010244011110112460111110024801111101250CLK_SELInputP[1:0]PS[1:0]InputClockDividerPInputClockPrescalerPSInputFrequency(MHz)MinimumMaximum0XTALxx001x11040011x0.
520401x1x25401CLK00001x110120011x0.
5202401x1x256001002x120240012x0.
5404801x2x21012010004x140480014x0.
5808001x4x22024011005x150600015x0.
51008001x5x225300IDT8T49N008ANLGIREVISIONAFEBRUARY13,201482014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable3F.
PLLPostDividerNCodingNOTE:Xdenotes"don'tcare".
Table3G.
FemtoClockNGPLLBandwidthCodingNOTE:FemtoClockNGPLLstabilityisonlyguaranteedoverthefeedbackdividerrangeslistedisTable3G.
RegisterBitOutputDividerNOutputFrequencyRangeNn[6:0]fOUT_MIN(MHz)fOUT_MAX(MHz)000000X2DoNotUse00000102955125000000113636.
67833.
3300001004477.
562500001015382500000011X6318.
33416.
67000100X8238.
75312.
5000101X10191250000110X12159.
1667208.
33000111X14136.
4286178.
57001000X16119.
375156.
25.
.
.
N(eveninteger)(1910÷N)(2500÷N)111101X12415.
4020.
16111111X12615.
1619.
84RegisterBitFeedbackDividerValueRangeCPn1CPn0MinimumMaximum00164801481001010025011192250IDT8T49N008ANLGIREVISIONAFEBRUARY13,201492014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSPower-upDefaultConfigurationDescriptionTheIDT8T49N008Isupportsavarietyofoptionssuchasdifferentoutputstyles,numberofprogrammeddefaultfrequencies,outputen-ableandoperatingtemperaturerange.
Thedeviceoptionsandde-faultfrequenciesmustbespecifiedatthetimeoforderandareprogrammedbyIDTpriortoshipment.
Thedocument,Programma-bleFemtoClockNGProductOrderingGuidespecifiestheavailableordercodes,includingthedeviceoptionsanddefaultfrequencycon-figurations.
Examplepartnumber:8T49N004A-007NLGI,specifiesaquadfrequencyclockgeneratorwithdefaultfrequenciesof106.
25MHz,133.
333MHz,156.
25MHzand156.
25MHz,withfourLVDSoutputsthatareenabledafterpower-up,specifiedoverthein-dustrialtemperaturerangeandhousedinalead-free(6/6RoHS)VFQFNpackage.
OtherordercodeswithrespectiveprogrammedfrequenciesareavailablefromIDTuponrequest.
Afterpower-upchangestotheoutputfrequenciesarecontrolledbyFSEL[1:0]ortheI2Cinterface.
Changestotheoutputstylesandstatesofoutputs(enabledordisabled)canalsobecontrolledwiththeI2Cinterfaceafterpowerup.
Table3H.
Power-upDefaultSettingsSerialInterfaceConfigurationDescriptionTheIDT8T49N008IhasanI2C-compatibleconfigurationinterfacetoaccessanyoftheinternalregisters(Table3B)forfrequencyandPLLparameterprogramming.
TheIDT849N008IactsasaslavedeviceontheI2Cbusandhastheaddress0b110111x,wherexissetbythevalueontheADDR_SELinput(seeTables3Iand3J).
Theinterfaceacceptsbyte-orientedblockwriteandblockreadoperations.
Anaddressbyte(P)specifiestheregisteraddress(Table3B)asthebytepositionofthefirstregistertowriteorread.
Databytes(registers)areaccessedinsequentialorderfromthelowesttothehighestbyte(mostsignificantbitfirst,seeTable3K,3L).
Readandwriteblocktransferscanbestoppedafteranycompletebytetransfer.
ItisrecommendedtoterminatetheI2Creadorwritetransferafteraccessingbyte#23bysendingastopcommand.
ForfullelectricalI2Ccompliance,itisrecommendedtouseexternalpull-upresistorsforSDATAandSCLK.
Theinternalpull-upresistorshaveasizeof50ktypical.
Table3I.
I2CDeviceSlaveAddressADDR_SEL=0(default)Table3J.
I2CDeviceSlaveAddressADDR_SEL=1Table3K.
BlockWriteOperationTable3L.
BlockReadOperationFSEL1FSEL0FrequencyPLLState(OnorBypass)OutputState(ActiveorHighImpedance)OutputStyle(LVDSorLVPECL)0(default)0(default)Frequency0PLLState0OutputState0OutputStyle001Frequency1PLLState1OutputState1OutputStyle110Frequency2PLLState2OutputState2OutputStyle211Frequency3PLLState3OutputState3OutputStyle31101110R/W1101111R/WBit12:891011:181920:272829-3637DescriptionSTARTSlaveAddressW(0)ACKAddressBytePACKDataByte(P)ACKDataByte(P+1)ACKDataByte.
.
.
ACKSTOPLength(bits)1711818181811Bit12:891011:18192021:27282930:373839-4647DescriptionSTARTSlaveAddressW(0)ACKAddressbytePACKRepeatedSTARTSlaveaddressR(1)ACKDataByte(P)ACKDataByte(P+1)ACKDataByte.
.
.
ACKSTOPLength(bits)17118117118181811IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014102014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSAbsoluteMaximumRatingsNOTE:StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Theseratingsarestressspecificationsonly.
FunctionaloperationofproductattheseconditionsoranyconditionsbeyondthoselistedintheDCCharacteristicsorACCharacteristicsisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectproductreliability.
DCElectricalCharacteristicsTable4A.
PowerSupplyDCCharacteristics,VCC=VCCO=3.
3V±5%,VEE=0V,TA=-40°Cto85°CTable4B.
PowerSupplyDCCharacteristics,VCC=VCCO=2.
5V±5%,VEE=0V,TA=-40°Cto85°CItemRatingSupplyVoltage,VCC3.
63VInputs,VIXTAL_INOtherInput0Vto2V-0.
5VtoVCC+0.
5VOutputs,IO(LVPECL)ContinuousCurrentSurgeCurrentOutputs,IO(SDATA)Outputs,IO(LVDS)ContinuousCurrentSurgeCurrent50mA100mA10mA10mA15mAPackageThermalImpedance,JA32.
4C/W(0mps)StorageTemperature,TSTG-65Cto150CSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVCCCoreSupplyVoltage3.
1353.
33.
465VVCCAAnalogSupplyVoltageVCC–0.
323.
3VCCVVCCOOutputSupplyVoltage3.
1353.
33.
465VICCAAnalogSupplyCurrent32mAIEEPowerSupplyCurrentLVPECL225mAICCPowerSupplyCurrentLVDS125mAICCOOutputSupplyCurrentLVDS162mASymbolParameterTestConditionsMinimumTypicalMaximumUnitsVCCCoreSupplyVoltage2.
3752.
52.
625VVCCAAnalogSupplyVoltageVCC–0.
282.
5VCCVVCCOOutputSupplyVoltage2.
3752.
52.
625VICCAAnalogSupplyCurrent28mAIEEPowerSupplyCurrentLVPECL216mAICCPowerSupplyCurrentLVDS122mAICCOOutputSupplyCurrentLVDS160mAIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014112014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable4C.
LVCMOS/LVTTLDCCharacteristics,VCC=VCCO=3.
3V±5%or2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Outputterminatedwith50toVCCO/2.
SeeParameterMeasurementInformation,OutputLoadTestCircuitdiagrams.
Table4D.
DifferentialDCCharacteristics,VCC=VCCO=3.
3V±5%or2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Commonmodeinputvoltageisatthecrosspoint.
Table4E.
LVPECLDCCharacteristics,VCC=VCCO=3.
3V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Outputsterminationwith50toVCC–2V.
SymbolParameterTestConditionsMinimumTypicalMaximumUnitsVIHInputHighVoltageSCLK,SDATA,FSEL[1:0],CLK_SEL,ADDR_SELVCC=3.
3V2VCC+0.
3VVCC=2.
5V1.
7VCC+0.
3VVILInputLowVoltageSCLK,SDATA,CLK_SEL,ADDR_SELVCC=3.
3V-0.
30.
8VVCC=2.
5V-0.
30.
7VFSEL[1:0],VCC=3.
3Vor2.
5V0.
5VIIHInputHighCurrentSCLK,SDATAVCC=VIN=3.
465Vor2.
625V5AFSEL[1:0],CLK_SEL,ADDR_SELVCC=VIN=3.
465Vor2.
625V150AIILInputLowCurrentSCLK,SDATAVCC=3.
465Vor2.
625V,VIN=0V-150AFSEL[1:0],CLK_SEL,ADDR_SELVCC=3.
465Vor2.
625V,VIN=0V-5AVOHOutputHighVoltage;NOTE1LOCKVCC=3.
465V2.
6VLOCKVCC=2.
625V1.
8VVOLOutputLowVoltage;NOTE1LOCKVCC=3.
465Vor2.
625V0.
5VSymbolParameterTestConditionsMinimumTypicalMaximumUnitsIIHInputHighCurrentCLK,nCLKVCC=VIN=3.
465Vor2.
625V150AIILInputLowCurrentnCLKVCC=3.
465Vor2.
625V,VIN=0V-150ACLKVCC=3.
465Vor2.
625V,VIN=0V-5AVPPPeak-to-PeakVoltage0.
151.
3VVCMRCommonModeInputVoltage;NOTE1VEEVCC–0.
85VSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVOHOutputHighVoltage;NOTE1VCC–1.
1VCCO–0.
75VVOLOutputLowVoltage;NOTE1VCC–2.
0VCCO–1.
6VVSWINGPeak-to-PeakOutputVoltageSwing0.
61.
0VIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014122014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable4F.
LVPECLDCCharacteristics,VCC=VCCO=2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE1:Outputsterminationwith50toVCC–2V.
Table4G.
LVDSDCCharacteristics,VCC=VCCO=3.
3V±5%,VEE=0V,TA=-40°Cto85°CTable4H.
LVDSDCCharacteristics,VCC=VCCO=2.
5V±5%,VEE=0V,TA=-40°Cto85°CTable5.
CrystalCharacteristicsSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVOHOutputHighVoltage;NOTE1VCC–1.
2VCCO–0.
75VVOLOutputLowVoltage;NOTE1VCC–2.
0VCC–1.
5VVSWINGPeak-to-PeakOutputVoltageSwing0.
51.
0VSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVODDifferentialOutputVoltage247345454mVVODVODMagnitudeChange50mVVOSOffsetVoltage1.
151.
251.
375VVOSVOSMagnitudeChange50mVSymbolParameterTestConditionsMinimumTypicalMaximumUnitsVODDifferentialOutputVoltage230340454mVVODVODMagnitudeChange50mVVOSOffsetVoltage1.
151.
251.
375VVOSVOSMagnitudeChange50mVParameterTestConditionsMinimumTypicalMaximumUnitsModeofOscillationFundamentalFrequency1040MHzLoadCapacitance(CL)1018pFEquivalentSeriesResistance(ESR)50IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014132014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSACElectricalCharacteristicsTable6A.
PCIExpressJitterSpecifications,VCC=VCCO=3.
3V±5%or2.
5V±5%,VEE=0V,TA=-40°Cto85°CNOTE:Electricalparametersareguaranteedoverthespecifiedambientoperatingtemperaturerange,whichisestablishedwhenthedeviceismountedinatestsocketwithmaintainedtransverseairflowgreaterthan500lfpm.
Thedevicewillmeetspecificationsafterthermalequilibriumhasbeenreachedundertheseconditions.
Foradditionalinformation,refertothePCIExpressApplicationNotesectioninthedatasheet.
NOTE1:Peak-to-PeakjitterafterapplyingsystemtransferfunctionfortheCommonClockArchitecture.
MaximumlimitforPCIExpressGen1is86pspeak-to-peakforasamplesizeof106clockperiods.
NOTE2:RMSjitterafterapplyingthetwoevaluationbandstothetwotransferfunctionsdefinedintheCommonClockArchitectureandreportingtheworstcaseresultsforeachevaluationband.
MaximumlimitforPCIExpressGeneration2is3.
1psRMSfortREFCLK_HF_RMS(HighBand)and3.
0psRMSfortREFCLK_LF_RMS(LowBand).
NOTE3:RMSjitterafterapplyingsystemtransferfunctionforthecommonclockarchitecture.
ThisspecificationisbasedonthePCIExpressBaseSpecificationRevision0.
7,October2009andissubjecttochangependingthefinalreleaseversionofthespecification.
NOTE4:Thisparameterisguaranteedbycharacterization.
Nottestedinproduction.
SymbolParameterTestConditionsMinimumTypicalMaximumPCIeIndustrySpecificationUnitstj(PCIeGen1)PhaseJitterPeak-to-Peak;NOTE1,4=100MHz,25MHzCrystalInputEvaluationBand:0Hz-Nyquist(clockfrequency/2)8.
313.
286pstREFCLK_HF_RMS(PCIeGen2)PhaseJitterRMS;NOTE2,4=100MHz,25MHzCrystalInputHighBand:1.
5MHz-Nyquist(clockfrequency/2)0.
781.
353.
1pstREFCLK_LF_RMS(PCIeGen2)PhaseJitterRMS;NOTE2,4=100MHz,25MHzCrystalInputLowBand:10kHz-1.
5MHz0.
050.
103.
0pstREFCLK_RMS(PCIeGen3)PhaseJitterRMS;NOTE3,4=100MHz,25MHzCrystalInputEvaluationBand:0Hz-Nyquist(clockfrequency/2)0.
1750.
340.
8psIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014142014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTable6B.
ACCharacteristics,VCC=VCCO=3.
3V±5%or2.
5V±5%VEE=0V,TA=-40°Cto85°CNOTE:Electricalparametersareguaranteedoverthespecifiedambientoperatingtemperaturerange,whichisestablishedwhenthedeviceismountedinatestsocketwithmaintainedtransverseairflowgreaterthan500lfpm.
Thedevicewillmeetspecificationsafterthermalequilibriumhasbeenreachedundertheseconditions.
NOTE1:RefertoPhaseNoisePlots.
NOTE2:Definedasskewbetweenoutputsatthesamesupplyvoltageandwithequalloadconditions.
Measuredatthedifferentialcrosspoints.
NOTE3:Theseparametersareguaranteedbycharacterization.
Nottestedinproduction.
NOTE4:RefertotLOCKandtTRANSITIONinParameterMeasurementInformation.
SymbolParameterTestConditionsMinimumTypicalMaximumUnitsfDIFF_INDifferentialInputFrequency10312.
5MHzfVCOVCOFrequency19102500MHztjit()RMSPhaseJitter,Random;NOTE125MHzCrystal,fOUT=100MHz,IntegrationRange:12kHz–20MHz258332fs25MHzCrystal,fOUT=125MHz,IntegrationRange:12kHz–20MHz220291fs25MHzCrystal,fOUT=125MHz,IntegrationRange:10kHz–1MHz164232fs25MHzCrystal,fOUT=156.
25MHz,IntegrationRange:12kHz–20MHz228306fs25MHzCrystal,fOUT=156.
25MHz,IntegrationRange:10kHz–1MHz175234fs25MHzCrystal,fOUT=250MHz,IntegrationRange:12kHz–20MHz212292fs30.
72MHzCrystal,fOUT=491.
52MHz,IntegrationRange:12kHz–20MHz213299fs19.
44MHzCrystal,fOUT=622.
08MHz,IntegrationRange:12kHz–20MHz280386fstsk(o)OutputSkew;NOTE2,3LVPECLOutputsLVDS_SEL=050psLVDSOutputsLVDS_SEL=150pstR/tFOutputRise/FallTimeLVPECLOutputs20%-80%,LVDS_SEL=0100400psLVDSOutputs20%-80%,LVDS_SEL=1100400psodcOutputDutyCycleN>3OutputDivider;LVDS_SEL=0or14753%N3OutputDivider;LVDS_SEL=0or14258%tLOCKPLLLockTime;NOTE3,4LOCKOutput20mstTRANSITIONTransitionTime;NOTE3,4LOCKOutput20msIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014152014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTypicalPhaseNoiseat100MHz(3.
3V)TypicalPhaseNoiseat125MHz(3.
3V)NoisePower(dBc/Hz)OffsetFrequency(Hz)NoisePower(dBc/Hz)OffsetFrequency(Hz)IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014162014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTypicalPhaseNoiseat156.
25MHz(3.
3V)NoisePower(dBc/Hz)OffsetFrequency(Hz)IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014172014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSParameterMeasurementInformation3.
3VLVPECLOutputLoadACTestCircuit3.
3VLVDSOutputLoadACTestCircuitDifferentialInputLevels2.
5VLVPECLOutputLoadACTestCircuit2.
5VLVDSOutputLoadACTestCircuitRMSPhaseJitterVCC,2V-1.
3V±0.
165V2VVCCAVCCO3.
3V±5%VCC,VCCOVCCAVCCVEEnCLKCLK-0.
5V±0.
125VVCC,2V2VVCCAVCCOSCOPEQxnQx2.
5V±5%POWERSUPPLY+–FloatGNDVCC,VCCOVCCAIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014182014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSParameterMeasurementInformation,continuedOutputSkewLVPECLOutputRise/FallTimeOffsetVoltageSetupOutputDutyCycle/PulseWidth/PeriodLVDSOutputRise/FallTimeDifferentialOutputVoltageSetupnQxQxnQyQynQ[0:7]Q[0:7]nQ[0:7]Q[0:7]20%80%80%20%tRtFVODnQ[0:7]Q[0:7]IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014192014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSParameterMeasurementInformation,continuedLockTime&TransitionTimeApplicationsInformationRecommendationsforUnusedInputandOutputPinsInputs:LVCMOSControlPinsAllcontrolpinshaveinternalpullupsorpulldowns;additionalresistanceisnotrequiredbutcanbeaddedforadditionalprotection.
A1kresistorcanbeused.
CLK/nCLKInputsForapplicationsnotrequiringtheuseofthedifferentialinput,bothCLKandnCLKcanbeleftfloating.
Thoughnotrequired,butforadditionalprotection,a1kresistorcanbetiedfromCLKtoground.
CrystalInputsForapplicationsnotrequiringtheuseofthecrystaloscillatorinput,bothXTAL_INandXTAL_OUTcanbeleftfloating.
Thoughnotrequired,butforadditionalprotection,a1kresistorcanbetiedfromXTAL_INtoground.
Outputs:LVPECLOutputsAllunusedLVPECLoutputpairscanbeleftfloating.
Werecommendthatthereisnotraceattached.
Bothsidesofthedifferentialoutputpairshouldeitherbeleftfloatingorterminated.
LVDSOutputsAllunusedLVDSoutputpairscanbeeitherleftfloatingorterminatedwith100across.
Iftheyareleftfloating,thereshouldbenotraceattached.
IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014202014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSWiringtheDifferentialInputtoAcceptSingle-EndedLevelsFigure1showshowadifferentialinputcanbewiredtoacceptsingleendedlevels.
ThereferencevoltageV1=VCC/2isgeneratedbythebiasresistorsR1andR2.
Thebypasscapacitor(C1)isusedtohelpfilternoiseontheDCbias.
Thisbiascircuitshouldbelocatedasclosetotheinputpinaspossible.
TheratioofR1andR2mightneedtobeadjustedtopositiontheV1inthecenteroftheinputvoltageswing.
Forexample,iftheinputclockswingis2.
5VandVCC=3.
3V,R1andR2valueshouldbeadjustedtosetV1at1.
25V.
ThevaluesbelowareforwhenboththesingleendedswingandVCCareatthesamevoltage.
Thisconfigurationrequiresthatthesumoftheoutputimpedanceofthedriver(Ro)andtheseriesresistance(Rs)equalsthetransmissionlineimpedance.
Inaddition,matchedterminationattheinputwillattenuatethesignalinhalf.
Thiscanbedoneinoneoftwoways.
First,R3andR4inparallelshouldequalthetransmissionlineimpedance.
Formost50applications,R3andR4canbe100.
ThevaluesoftheresistorscanbeincreasedtoreducetheloadingforslowerandweakerLVCMOSdriver.
Whenusingsingle-endedsignaling,thenoiserejectionbenefitsofdifferentialsignalingarereduced.
EventhoughthedifferentialinputcanhandlefullrailLVCMOSsignaling,itisrecommendedthattheamplitudebereduced.
Thedatasheetspecifiesalowerdifferentialamplitude,howeverthisonlyappliestodifferentialsignals.
Forsingle-endedapplications,theswingcanbelarger,howeverVILcannotbelessthan-0.
3VandVIHcannotbemorethanVCC+0.
3V.
Thoughsomeoftherecommendedcomponentsmightnotbeused,thepadsshouldbeplacedinthelayout.
Theycanbeutilizedfordebuggingpurposes.
Thedatasheetspecificationsarecharacterizedandguaranteedbyusingadifferentialsignal.
Figure1.
RecommendedSchematicforWiringaDifferentialInputtoAcceptSingle-endedLevelsReceiver+-R4100R3100RSZo=50OhmRoDriverVCCVCCR21KR11KC10.
1uFRo+Rs=ZoV1VCCVCCIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014212014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSOverdrivingtheXTALInterfaceTheXTAL_INinputcanbeoverdrivenbyanLVCMOSdriverorbyonesideofadifferentialdriverthroughanACcouplingcapacitor.
TheXTAL_OUTpincanbeleftfloating.
Theamplitudeoftheinputsignalshouldbebetween500mVand1.
8Vandtheslewrateshouldnotbelessthan0.
2V/nS.
For3.
3VLVCMOSinputs,theamplitudemustbereducedfromfullswingtoatleasthalftheswinginordertopreventsignalinterferencewiththepowerrailandtoreduceinternalnoise.
Figure2Ashowsanexampleoftheinterfacediagramforahighspeed3.
3VLVCMOSdriver.
Thisconfigurationrequiresthatthesumoftheoutputimpedanceofthedriver(Ro)andtheseriesresistance(Rs)equalsthetransmissionlineimpedance.
Inaddition,matchedterminationatthecrystalinputwillattenuatethesignalinhalf.
Thiscanbedoneinoneoftwoways.
First,R1andR2inparallelshouldequalthetransmissionlineimpedance.
Formost50applications,R1andR2canbe100.
ThiscanalsobeaccomplishedbyremovingR1andchangingR2to50.
ThevaluesoftheresistorscanbeincreasedtoreducetheloadingforaslowerandweakerLVCMOSdriver.
Figure2BshowsanexampleoftheinterfacediagramforanLVPECLdriver.
ThisisastandardLVPECLterminationwithonesideofthedriverfeedingtheXTAL_INinput.
Itisrecommendedthatallcomponentsintheschematicsbeplacedinthelayout.
Thoughsomecomponentsmightnotbeused,theycanbeutilizedfordebuggingpurposes.
Thedatasheetspecificationsarecharacterizedandguaranteedbyusingaquartzcrystalastheinput.
Figure2A.
GeneralDiagramforLVCMOSDrivertoXTALInputInterfaceFigure2B.
GeneralDiagramforLVPECLDrivertoXTALInputInterfaceVCCXTAL_OUTXTAL_INR1100R2100Zo=50ohmsRsRoZo=Ro+RsC1.
1ufLVCMOSDriverXTAL_OUTXTAL_INZo=50ohmsC2.
1ufLVPECLDriverZo=50ohmsR150R250R350IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014222014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS3.
3VDifferentialClockInputInterfaceTheCLK/nCLKacceptsLVDS,LVPECL,HCSLandotherdifferentialsignals.
BothVSWINGandVOHmustmeettheVPPandVCMRinputrequirements.
Figures3Ato3DshowinterfaceexamplesfortheCLK/nCLKinputdrivenbythemostcommondrivertypes.
Theinputinterfacessuggestedhereareexamplesonly.
Ifthedriverisfromanothervendor,usetheirterminationrecommendation.
Pleaseconsultwiththevendorofthedrivercomponenttoconfirmthedriverterminationrequirements.
Figure3A.
CLK/nCLKInputDrivenbya3.
3VLVPECLDriverFigure3C.
CLK/nCLKInputDrivenbya3.
3VHCSLDriverFigure3B.
CLK/nCLKInputDrivenbya3.
3VLVPECLDriverFigure3D.
CLK/nCLKInputDrivenbya3.
3VLVDSDriver3.
3VCLKnCLK3.
3V3.
3VLVPECLDifferentialInputHCSL*R3*R4CLKnCLK3.
3V3.
3VDifferentialInputCLKnCLKDifferentialInputLVPECL3.
3VZo=50ΩZo=50Ω3.
3VR150ΩR250ΩR250Ω3.
3VR1100ΩLVDSCLKnCLK3.
3VReceiverZo=50ΩZo=50ΩIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014232014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS2.
5VDifferentialClockInputInterfaceTheCLK/nCLKacceptsLVDS,LVPECL,HCSLandotherdifferentialsignals.
BothVSWINGandVOHmustmeettheVPPandVCMRinputrequirements.
Figures4Ato4DshowinterfaceexamplesfortheCLK/nCLKinputdrivenbythemostcommondrivertypes.
Theinputinterfacessuggestedhereareexamplesonly.
Ifthedriverisfromanothervendor,usetheirterminationrecommendation.
Pleaseconsultwiththevendorofthedrivercomponenttoconfirmthedriverterminationrequirements.
Figure4A.
CLK/nCLKInputDrivenbya2.
5VLVPECLDriverFigure4C.
CLK/nCLKInputDrivenbya2.
5VHCSLDriverFigure4B.
CLK/nCLKInputDrivenbya2.
5VLVPECLDriverFigure4D.
CLK/nCLKInputDrivenbya2.
5VLVDSDriverR3250R4250R162.
5R262.
52.
5VZo=50Zo=50CLKnCLK2.
5V2.
5VLVPECLDifferentialInputHCSL*R333*R433CLKnCLK2.
5V2.
5VZo=50Zo=50DifferentialInputR150R250*Optional–R3andR4canbe0CLKnCLKDifferentialInputLVPECL2.
5VZo=50Zo=502.
5VR150R250R3182.
5VR1100LVDSCLKnCLK2.
5VDifferentialInputZo=50Zo=50IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014242014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSLVDSDriverTerminationForageneralLVDSinterface,therecommendedvaluefortheterminationimpedance(ZT)isbetween90and132.
Theactualvalueshouldbeselectedtomatchthedifferentialimpedance(Z0)ofyourtransmissionline.
Atypicalpoint-to-pointLVDSdesignusesa100parallelresistoratthereceiveranda100differentialtransmission-lineenvironment.
Inordertoavoidanytransmission-linereflectionissues,thecomponentsshouldbesurfacemountedandmustbeplacedasclosetothereceiveraspossible.
IDToffersafulllineofLVDScompliantdeviceswithtwotypesofoutputstructures:currentsourceandvoltagesource.
ThestandardterminationschematicasshowninFigure5Acanbeusedwitheithertypeofoutputstructure.
Figure5B,whichcanalsobeusedwithbothoutputtypes,isanoptionalterminationwithcentertapcapacitancetohelpfiltercommonmodenoise.
Thecapacitorvalueshouldbeapproximately50pF.
Ifusinganon-standardtermination,itisrecommendedtocontactIDTandconfirmiftheoutputstructureiscurrentsourceorvoltagesourcetype.
Inaddition,sincetheseoutputsareLVDScompatible,theinputreceiver'samplitudeandcommon-modeinputrangeshouldbeverifiedforcompatibilitywiththeoutput.
Terminationfor3.
3VLVPECLOutputsTheclocklayouttopologyshownbelowisatypicalterminationforLVPECLoutputs.
Thetwodifferentlayoutsmentionedarerecommendedonlyasguidelines.
ThedifferentialoutputsarelowimpedancefolloweroutputsthatgenerateECL/LVPECLcompatibleoutputs.
Therefore,terminatingresistors(DCcurrentpathtoground)orcurrentsourcesmustbeusedforfunctionality.
Theseoutputsaredesignedtodrive50transmissionlines.
Matchedimpedancetechniquesshouldbeusedtomaximizeoperatingfrequencyandminimizesignaldistortion.
Figures6Aand6Bshowtwodifferentlayoutswhicharerecommendedonlyasguidelines.
Othersuitableclocklayoutsmayexistanditwouldberecommendedthattheboarddesignerssimulatetoguaranteecompatibilityacrossallprintedcircuitandclockcomponentprocessvariations.
Figure6A.
3.
3VLVPECLOutputTerminationFigure6B.
3.
3VLVPECLOutputTerminationLVDSDriverLVDSDriverLVDSReceiverLVDSReceiverZTCZOZTZOZTZT2ZT2Figure5A.
StandardTerminationFigure5B.
OptionalTerminationR184R2843.
3VR3125R4125Zo=50Zo=50LVPECLInput3.
3V3.
3V+_IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014252014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSTerminationfor2.
5VLVPECLOutputsFigure7AandFigure7Bshowexamplesofterminationfor2.
5VLVPECLdriver.
Theseterminationsareequivalenttoterminating50toVCCO–2V.
ForVCCO=2.
5V,theVCCO–2Visveryclosetogroundlevel.
TheR3inFigure7BcanbeeliminatedandtheterminationisshowninFigure7C.
Figure7A.
2.
5VLVPECLDriverTerminationExampleFigure7C.
2.
5VLVPECLDriverTerminationExampleFigure7B.
2.
5VLVPECLDriverTerminationExample2.
5VLVPECLDriverVCCO=2.
5V2.
5V2.
5V5050R1250R3250R262.
5R462.
5+–2.
5VLVPECLDriverVCCO=2.
5V2.
5V5050R150R250+–2.
5VLVPECLDriverVCCO=2.
5V2.
5V5050R150R250R318+–IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014262014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSVFQFNEPADThermalReleasePathInordertomaximizeboththeremovalofheatfromthepackageandtheelectricalperformance,alandpatternmustbeincorporatedonthePrintedCircuitBoard(PCB)withinthefootprintofthepackagecorrespondingtotheexposedmetalpadorexposedheatslugonthepackage,asshowninFigure8.
ThesolderableareaonthePCB,asdefinedbythesoldermask,shouldbeatleastthesamesize/shapeastheexposedpad/slugareaonthepackagetomaximizethethermal/electricalperformance.
SufficientclearanceshouldbedesignedonthePCBbetweentheouteredgesofthelandpatternandtheinneredgesofpadpatternfortheleadstoavoidanyshorts.
WhilethelandpatternonthePCBprovidesameansofheattransferandelectricalgroundingfromthepackagetotheboardthroughasolderjoint,thermalviasarenecessarytoeffectivelyconductfromthesurfaceofthePCBtothegroundplane(s).
Thelandpatternmustbeconnectedtogroundthroughthesevias.
Theviasactas"heatpipes".
Thenumberofvias(i.
e.
"heatpipes")areapplicationspecificanddependentuponthepackagepowerdissipationaswellaselectricalconductivityrequirements.
Thus,thermalandelectricalanalysisand/ortestingarerecommendedtodeterminetheminimumnumberneeded.
Maximumthermalandelectricalperformanceisachievedwhenanarrayofviasisincorporatedinthelandpattern.
Itisrecommendedtouseasmanyviasconnectedtogroundaspossible.
Itisalsorecommendedthattheviadiametershouldbe12to13mils(0.
30to0.
33mm)with1ozcopperviabarrelplating.
Thisisdesirabletoavoidanysolderwickinginsidetheviaduringthesolderingprocesswhichmayresultinvoidsinsolderbetweentheexposedpad/slugandthethermalland.
Precautionsshouldbetakentoeliminateanysoldervoidsbetweentheexposedheatslugandthelandpattern.
Note:Theserecommendationsaretobeusedasaguidelineonly.
Forfurtherinformation,pleaserefertotheApplicationNoteontheSurfaceMountAssemblyofAmkor'sThermally/ElectricallyEnhanceLeadframeBasePackage,AmkorTechnology.
Figure8.
P.
C.
AssemblyforExposedPadThermalReleasePath–SideView(drawingnottoscale)SOLDERSOLDERPINPINEXPOSEDHEATSLUGPINPADPINPADGROUNDPLANELANDPATTERN(GROUNDPAD)THERMALVIAIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014272014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSSchematicLayoutFigure9(nextpage)showsanexampleofIDT8T49N008Iapplicationschematic.
Theschematicfocusesonfunctionalconnectionsandisnotconfigurationspecific.
Refertothepindescriptionandfunctionaltablesinthedatasheettoensurethatthelogiccontrolinputsareproperlyset.
InthisexamplethedeviceisoperatedatVCC=VCCO=VCCA=3.
3Vratherthan2.
5V.
TheCLK,nCLKinputsareprovidedbya3.
3VLVPECLdriveranddepictedwithaY-terminationratherthanthestandardfourresistorVCC-2VThevininterminationforreasonsofminimumterminationpowerandlayoutsimplicity.
ThreeexamplesofPECLterminationsareshownfortheoutputstodemonstratemixingofPECLterminationdesignoptions.
Aswithanyhighspeedanalogcircuitry,thepowersupplypinsarevulnerabletonoise.
Toachieveoptimumjitterperformance,powersupplyisolationisrequired.
TheIDT8T49N006IprovidesseparatepowersuppliestoisolatefromcouplingintotheinternalPLL.
Inordertoachievethebestpossiblefiltering,itisrecommendedthattheplacementofthefiltercomponentsbeonthedevicesideofthePCBasclosetothepowerpinsaspossible.
Ifspaceislimited,the0.
1uFcapacitorineachpowerpinfiltershouldbeplacedonthedevicesideofthePCBandtheothercomponentscanbeplacedontheoppositeside.
Powersupplyfilterrecommendationsareageneralguidelinetobeusedforreducingexternalnoisefromcouplingintothedevices.
TheVCCandVCCOfiltersstarttoattenuatenoiseatapproximately10kHz.
Ifaspecificfrequencynoisecomponentisknown,suchasswitchingpowersuppliesfrequencies,itisrecommendedthatcomponentvaluesbeadjustedandifrequired,additionalfilteringbeadded.
Additionally,goodgeneraldesignpracticesforpowerplanevoltagestabilitysuggestsaddingbulkcapacitanceinthelocalareaofalldevices.
IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014282014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSFigure9.
IDT8T49N008IApplicationSchematicC90.
1uFC170.
1uFVCCOC70.
1uFVCC_38VCCAQ2_NQ2_PQ3_NQ3_PQ4_PQ4_NQ5_PQ5_NQ6_PQ6_NZo=50OhmR982.
5R1450R1550Zo=50Ohm+-Zo=50OhmR1350OptionalFourResistorThevininTerminationRU2NotInstallRU11KRD21KVCCRD1NotInstallVCCC60.
1uFC100.
1uF3.
3VC1410uFFB1BLM18BB221SN112C1610uF3.
3VFB2BLM18BB221SN112C190.
1uFToLogicInputpinsLogicControlInputExamplesSetLogicInputto'1'SetLogicInputto'0'SCLKSDATA3.
3VC2110uF3.
3VFB3BLM18BB221SN112C220.
1uFVCCOVCC_19VCC_38Zo=50OhmR450R550Zo=50OhmR350Q7_NC810uFR1610Q7_PR14.
7KR24.
7K3.
3VR6330Q1_NQ0_NQ0_PQ1_PC150.
1uFR1082.
5R8133R7133+-Zo=50OhmC239pFC189pFX125MHz(12pf)U1VEE37VCC38CLK_SEL39VEE40Q01nQ02nQ14Q13VCCO5Q26nQ27Q38nQ39VEE10XTAL_IN11XTAL_OUT12nQ624Q723nQ722VEE21FSEL120VCC19VEE18ADDR_SEL17FSEL016nCLK15CLK14VEE13LOCK36VCCA35VEE34SDATA33SCLK32VEE31Q430nQ429Q528nQ527VCCO26Q625epad41VCC_19PECLDriverToLogicInputpinsVCCACLK_SELFSEL0FSEL1ADDR_SELForACterminationoptionsconsulttheIDTApplicationsNote"Termination-3.
3VLVPECL"LOCKIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014292014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSPCIExpressApplicationNotePCIExpressjitteranalysismethodologymodelsthesystemresponsetoreferenceclockjitter.
TheblockdiagrambelowshowsthemostfrequentlyusedCommonClockArchitectureinwhichacopyofthereferenceclockisprovidedtobothendsofthePCIExpressLink.
Inthejitteranalysis,thetransmit(Tx)andreceive(Rx)serdesPLLsaremodeledaswellasthephaseinterpolatorinthereceiver.
ThesetransferfunctionsarecalledH1,H2,andH3respectively.
Theoverallsystemtransferfunctionatthereceiveris:ThejitterspectrumseenbythereceiveristheresultofapplyingthissystemtransferfunctiontotheclockspectrumX(s)andis:Inordertogeneratetimedomainjitternumbers,aninverseFourierTransformisperformedonX(s)*H3(s)*[H1(s)-H2(s)].
PCIExpressCommonClockArchitectureForPCIExpressGen1,onetransferfunctionisdefinedandtheevaluationisperformedovertheentirespectrum:DCtoNyquist(e.
gfora100MHzreferenceclock:0Hz–50MHz)andthejitterresultisreportedinpeak-peak.
PCIeGen1MagnitudeofTransferFunctionForPCIExpressGen2,twotransferfunctionsaredefinedwith2evaluationrangesandthefinaljitternumberisreportedinRMS.
ThetwoevaluationrangesforPCIExpressGen2are10kHz–1.
5MHz(LowBand)and1.
5MHz–Nyquist(HighBand).
TheplotsshowtheindividualtransferfunctionsaswellastheoveralltransferfunctionHt.
PCIeGen2AMagnitudeofTransferFunctionPCIeGen2BMagnitudeofTransferFunctionForPCIExpressGen3,onetransferfunctionisdefinedandtheevaluationisperformedovertheentirespectrum.
ThetransferfunctionparametersaredifferentfromGen1andthejitterresultisreportedinRMS.
PCIeGen3MagnitudeofTransferFunctionForamorethoroughoverviewofPCIExpressjitteranalysismethodology,pleaserefertoIDTApplicationNotePCIExpressReferenceClockRequirements.
HtsH3sH1sH2s–=YsXsH3sH1sH2s–=IDT8T49N008ANLGIREVISIONAFEBRUARY13,2014302014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSLVPECLPowerConsiderationsThissectionprovidesinformationonpowerdissipationandjunctiontemperaturefortheIDT8T49N008I.
Equationsandexamplecalculationsarealsoprovided.
1.
PowerDissipation.
ThetotalpowerdissipationfortheIDT8T49N008Iisthesumofthecorepowerplusthepowerdissipatedintheload(s).
ThefollowingisthepowerdissipationforVCC=3.
465V,whichgivesworstcaseresults.
NOTE:PleaserefertoSection3fordetailsoncalculatingpowerdissipatedintheload.
Power(core)MAX=VCC_MAX*IEE_MAX=3.
465V*225mA=779.
625mWPower(outputs)MAX=31.
55mW/LoadedOutputpairIfalloutputsareloaded,thetotalpoweris8*31.
55mW=252.
4mWTotalPower_MAX(3.
465V,withalloutputsswitching)=779.
625W+252.
4mW=1032.
025W2.
JunctionTemperature.
Junctiontemperature,Tj,isthetemperatureatthejunctionofthebondwireandbondpaddirectlyaffectsthereliabilityofthedevice.
Themaximumrecommendedjunctiontemperatureis125°C.
Limitingtheinternaltransistorjunctiontemperature,Tj,to125°Censuresthatthebondwireandbondpadtemperatureremainsbelow125°C.
TheequationforTjisasfollows:Tj=JA*Pd_total+TATj=JunctionTemperatureJA=Junction-to-AmbientThermalResistancePd_total=TotalDevicePowerDissipation(examplecalculationisinsection1above)TA=AmbientTemperatureInordertocalculatejunctiontemperature,theappropriatejunction-to-ambientthermalresistanceJAmustbeused.
Assumingnoairflowandamulti-layerboard,theappropriatevalueis32.
4°C/WperTable7below.
Therefore,Tjforanambienttemperatureof85°Cwithalloutputsswitchingis:85°C+1.
032W*32.
4°C/W=118.
4°C.
Thisisbelowthelimitof125°C.
Thiscalculationisonlyanexample.
Tjwillobviouslyvarydependingonthenumberofloadedoutputs,supplyvoltage,airflowandthetypeofboard(multi-layer).
Table7.
ThermalResistanceJAfor40-LeadVFQFN,ForcedConvectionJAbyVelocityMetersperSecond013Multi-LayerPCB,JEDECStandardTestBoards32.
4°C/W25.
7°C/W23.
4°C/WIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014312014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS3.
CalculationsandEquations.
ThepurposeofthissectionistocalculatethepowerdissipationfortheLVPECLoutputpair.
LVPECLoutputdrivercircuitandterminationareshowninFigure10.
Figure10.
LVPECLDriverCircuitandTerminationTocalculateworstcasepowerdissipationintotheload,usethefollowingequationswhichassumea50load,andaterminationvoltageofVCCO–2V.
Forlogichigh,VOUT=VOH_MAX=VCCO_MAX–0.
75V(VCCO_MAX–VOH_MAX)=0.
75VForlogiclow,VOUT=VOL_MAX=VCCO_MAX–1.
6V(VCCO_MAX–VOL_MAX)=1.
6VPd_Hispowerdissipationwhentheoutputdriveshigh.
Pd_Listhepowerdissipationwhentheoutputdriveslow.
Pd_H=[(VOH_MAX–(VCCO_MAX–2V))/RL]*(VCCO_MAX–VOH_MAX)=[(2V–(VCCO_MAX–VOH_MAX))/RL]*(VCCO_MAX–VOH_MAX)=[(2V–0.
75V)/50]*0.
75V=18.
75mWPd_L=[(VOL_MAX–(VCCO_MAX–2V))/RL]*(VCCO_MAX–VOL_MAX)=[(2V–(VCCO_MAX–VOL_MAX))/RL]*(VCCO_MAX–VOL_MAX)=[(2V–1.
6V)/50]*1.
6V=12.
80mWTotalPowerDissipationperoutputpair=Pd_H+Pd_L=31.
55mWVOUTVCCOVCCO-2VQ1RL50ΩIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014322014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSLVDSPowerConsiderationsThissectionprovidesinformationonpowerdissipationandjunctiontemperaturefortheIDT8T49N008I.
Equationsandexamplecalculationsarealsoprovided.
1.
PowerDissipation.
ThetotalpowerdissipationfortheIDT8T49N008Iisthesumofthecorepowerplustheanalogpowerplusthepowerdissipatedintheload(s).
ThefollowingisthepowerdissipationforVCC=3.
3V+5%=3.
465V,whichgivesworstcaseresults.
Power(core)MAX=VCC_MAX*(ICC_MAX+ICCA_MAX)=3.
465V*(125mA+32mA)=544.
005mWPower(outputs)MAX=VCCO_MAX*ICCO_MAX=3.
465V*162mA=561.
33mWTotalPower_MAX=544.
005mW+561.
33mW=1105.
335mW2.
JunctionTemperature.
Junctiontemperature,Tj,isthetemperatureatthejunctionofthebondwireandbondpaddirectlyaffectsthereliabilityofthedevice.
Themaximumrecommendedjunctiontemperatureis125°C.
Limitingtheinternaltransistorjunctiontemperature,Tj,to125°Censuresthatthebondwireandbondpadtemperatureremainsbelow125°C.
TheequationforTjisasfollows:Tj=JA*Pd_total+TATj=JunctionTemperatureJA=Junction-to-AmbientThermalResistancePd_total=TotalDevicePowerDissipation(examplecalculationisinsection1above)TA=AmbientTemperatureInordertocalculatejunctiontemperature,theappropriatejunction-to-ambientthermalresistanceJAmustbeused.
Assumingnoairflowandamulti-layerboard,theappropriatevalueis32.
4°C/WperTable8below.
Therefore,Tjforanambienttemperatureof85°Cwithalloutputsswitchingis:85°C+1.
105W*32.
4°C/W=120.
8°C.
Thisisbelowthelimitof125°C.
Thiscalculationisonlyanexample.
Tjwillobviouslyvarydependingonthenumberofloadedoutputs,supplyvoltage,airflowandthetypeofboard(multi-layer).
Table8.
ThermalResistanceJAfor40-LeadVFQFN,ForcedConvectionJAbyVelocityMetersperSecond012.
5Multi-LayerPCB,JEDECStandardTestBoards32.
4°C/W25.
7°C/W23.
4°C/WIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014332014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSReliabilityInformationTable9.
JAvs.
AirFlowTablefora40-LeadVFQFNTransistorCountThetransistorcountforIDT8T49N008Iis:26,856JAvs.
AirFlowMetersperSecond012.
5Multi-LayerPCB,JEDECStandardTestBoards32.
4°C/W25.
7°C/W23.
4°C/WIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014342014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS40-LeadVFQFNPackageOutlineandPackageDimensionsIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014352014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTS40-LeadVFQFNPackageOutlineandPackageDimensions,continued40-LeadVFQFN,D2/E2EPADDimensions:4.
65mmx4.
65mmIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014362014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSOrderingInformationTable10.
OrderingInformationNOTE:Forthespecific-dddordercodes,refertotheProgrammableFemtoClockNGProductOrderingGuidedocument.
Part/OrderNumberMarkingPackageShippingPackagingTemperature8T49N008A-dddNLGIIDT8T49N008A-dddNLGI"Lead-Free"40-LeadVFQFNTray-40Cto85C8T49N008A-dddNLGI8IDT8T49N008A-dddNLGI"Lead-Free"40-LeadVFQFNTape&Reel-40Cto85CIDT8T49N008ANLGIREVISIONAFEBRUARY13,2014372014IntegratedDeviceTechnology,Inc.
IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSRevisionHistorySheetRevTablePageDescriptionofChangeDateA1PinAssignment-repositionedpinnumbers(11-20).
4/18/12AT1036Changedfooterpart/ordernumberfromIDT8T49N008BNLGItoIDT8T49N008ANLGI.
OrderingInformationTable-changedShippingPackagingfrom1000Tape&Reelto5000Tape&Reel.
4/23/12AT1011,3838ChangednameoftheIDT8T49N00xIProgrammableFemtoClockNGProductOrderingInformationdocumenttoProgrammableFemtoClockOrderingProductInformationDeletedquantityfromTape&Reel,DeletedLeadFreenote.
8/21/13AT1011138ChangedtitletoProgrammableFemtoClockNGLVPECL/LVDSClockGeneratorwith8-Outputs.
Changedtextfrom'ProgrammableFemtoClockOrderingProductInformation'to'ProgrammableFemtoClockNGProductOrderingGuide'.
ChangedNotefrom'ProgrammableFemtoClockOrderingProductInformation'to'ProgrammableFemtoClockNGProductOrderingGuide'.
9/26/13AT514Changedtheminloadcapacitancefrom12pFto10pF10/15/13ACorrectedpartnumberinthefooterpagesfromIDT8T49N00BNLGItoIDT8T49N00ANLGI2/13/14IDT8T49N008IDataSheetPROGRAMMABLEFEMTOCLOCKNGLVPECL/LVDSCLOCKGENERATORWITH8-OUTPUTSDISCLAIMERIntegratedDeviceTechnology,Inc.
(IDT)anditssubsidiariesreservetherighttomodifytheproductsand/orspecificationsdescribedhereinatanytimeandatIDT'ssolediscretion.
Allinformationinthisdocument,includingdescriptionsofproductfeaturesandperformance,issubjecttochangewithoutnotice.
Performancespecificationsandtheoperatingparametersofthedescribedproductsaredeterminedintheindependentstateandarenotguaranteedtoperformthesamewaywheninstalledincustomerproducts.
Theinformationcontainedhereinisprovidedwithoutrepresentationorwarrantyofanykind,whetherexpressorimplied,including,butnotlimitedto,thesuitabilityofIDT'sproductsforanyparticularpurpose,animpliedwarrantyofmerchantability,ornon-infringementoftheintellectualpropertyrightsofothers.
ThisdocumentispresentedonlyasaguideanddoesnotconveyanylicenseunderintellectualpropertyrightsofIDToranythirdparties.
IDT'sproductsarenotintendedforuseinapplicationsinvolvingextremeenvironmentalconditionsorinlifesupportsystemsorsimilardeviceswherethefailureormalfunctionofanIDTproductcanbereasonablyexpectedtosignifi-cantlyaffectthehealthorsafetyofusers.
AnyoneusinganIDTproductinsuchamannerdoessoattheirownrisk,absentanexpress,writtenagreementbyIDT.
IntegratedDeviceTechnology,IDTandtheIDTlogoareregisteredtrademarksofIDT.
Othertrademarksandservicemarksusedherein,includingprotectednames,logosanddesigns,arethepropertyofIDTortheirrespectivethirdpartyowners.
Copyright2014.
Allrightsreserved.
6024SilverCreekValleyRoadSanJose,California95138Sales800-345-7015(insideUSA)+408-284-8200(outsideUSA)Fax:408-284-2775www.
IDT.
com/go/contactIDTTechnicalSupportSalesnetcom@idt.
com+480-763-2056We'veGotYourTimingSolutionCorporateHeadquartersTOYOSUFORESIA,3-2-24Toyosu,Koto-ku,Tokyo135-0061,Japanwww.
renesas.
comContactInformationForfurtherinformationonaproduct,technology,themostup-to-dateversionofadocument,oryournearestsalesoffice,pleasevisit:www.
renesas.
com/contact/TrademarksRenesasandtheRenesaslogoaretrademarksofRenesasElectronicsCorporation.
Alltrademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
IMPORTANTNOTICEANDDISCLAIMERRENESASELECTRONICSCORPORATIONANDITSSUBSIDIARIES("RENESAS")PROVIDESTECHNICALSPECIFICATIONSANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSORIMPLIED,INCLUDING,WITHOUTLIMITATION,ANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
TheseresourcesareintendedfordevelopersskilledintheartdesigningwithRenesasproducts.
Youaresolelyresponsiblefor(1)selectingtheappropriateproductsforyourapplication,(2)designing,validating,andtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicablestandards,andanyothersafety,security,orotherrequirements.
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