JTwww.147ttt.com

AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,intellectualpropertymattersandotherimportantdisclaimers.
PRODUCTIONDATA.
DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016DS92LV042x10-MHzto-75MHzChannelLinkIISerializerandDeserializerWithLVDSParallelInterface11Features15-Channel(4Data+1Clock)ChannelLinkLVDSParallelInterfaceSupports24-BitData3-BitControlat10to75MHzAC-CoupledSTPInterconnectUpto10mIntegratedTerminationsonSerializerandDeserializerAt-SpeedLinkBISTModeandReportingPinOptionalI2C-CompatibleSerialControlBusPower-DownModeMinimizesPowerDissipation1.
8-Vor3.
3-VCompatibleLVCMOSI/OInterface>8-kVHBM–40°to85°CTemperatureRangeSerializer(DS92LV0421)–DataScramblerforReducedEMI–DC–BalanceEncoderforACCoupling–SelectableOutputVODandAdjustableDe-EmphasisDeserializer(DS92LV0422)–FastRandomDataLock;NoReferenceClockRequired–AdjustableInputReceiverEqualization–EMIMinimizationonOutputParallelBus(SSCGandLVDSVODSelect)2ApplicationsEmbeddedVideoandDisplaysMedicalImagingandFactoryAutomationOfficeAutomation(PrintersandScanners)SecurityandVideoSurveillanceGeneral-PurposeDataCommunication3DescriptionTheDS92LV042xchipsettranslatesaChannelLinkLVDSvideointerface(4LVDSData+LVDSClock)intoahigh-speedserializedinterfaceoverasingleCMLpair.
TheDS92LV042xenablesapplicationscurrentlyusingpopularChannelLinkorOpenLDILVDSstyledevicestoupgradeseamlesslytoanembeddedclockinterface.
Thisserialbusschemereducesinterconnectcostandeasesdesignchallenges.
TheparallelOpenLDILVDSinterfacealsoreducesFPGAI/Opins,boardtracecount,andalleviatesEMIissueswhencomparedtotraditionalsingle-endedwidebusinterfaces.
Programmabletransmitde-emphasis,receiveequalization,on-chipscrambling,andDC-balancingenableslongerdistancetransmissionoverlossycablesandbackplanes.
TheDS92LV0422automaticallylockstoincomingdatawithoutanexternalreferenceclockorspecialsyncpatterns,providingeasyplug-and-gooperation.
TheDS92LV042xchipsetisprogrammablethroughanI2Cinterfaceaswellasthroughpins.
Abuilt-in,at-speedBISTfeaturevalidateslinkintegrityandmaybeusedforsystemdiagnostics.
TheDS92LV0421andDS92LV0422canbeusedinterchangeablywiththeDS92LV2421orDS92LV2422.
Thisallowsdesignerstheflexibilitytoconnecttothehostdeviceandreceivingdeviceswithdifferentinterfacetypes:LVDSorLVCMOS.
DeviceInformation(1)PARTNUMBERPACKAGEBODYSIZE(NOM)DS92LV0421WQFN(36)6.
00mm*6.
00mmDS92LV0422WQFN(48)7.
00mm*7.
00mm(1)Forallavailablepackages,seetheorderableaddendumattheendofthedatasheet.
TypicalApplicationBlockDiagram2DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedTableofContents1Features.
12Applications13Description14RevisionHistory.
25PinConfigurationandFunctions.
46Specifications.
96.
1AbsoluteMaximumRatings96.
2ESDRatings.
96.
3RecommendedOperatingConditions.
96.
4ThermalInformation.
106.
5ElectricalCharacteristics:SerializerDC106.
6ElectricalCharacteristics:DeserializerDC116.
7ElectricalCharacteristics:DCandACSerialControlBus.
136.
8TimingRequirements:SerialControlBus.
136.
9SwitchingCharacteristics:Serializer.
146.
10SwitchingCharacteristics:Deserializer.
156.
11TypicalCharacteristics.
227DetailedDescription237.
1Overview237.
2FunctionalBlockDiagrams237.
3FeatureDescription.
247.
4DeviceFunctionalModes.
367.
5RegisterMaps.
378ApplicationandImplementation408.
1ApplicationInformation.
408.
2TypicalApplication439PowerSupplyRecommendations.
4610Layout.
4710.
1LayoutGuidelines4710.
2LayoutExample4911DeviceandDocumentationSupport5011.
1DeviceSupport.
5011.
2DocumentationSupport5011.
3RelatedLinks5011.
4ReceivingNotificationofDocumentationUpdates5011.
5CommunityResources.
5011.
6Trademarks.
5011.
7ElectrostaticDischargeCaution.
5111.
8Glossary.
5112Mechanical,Packaging,andOrderableInformation514RevisionHistoryNOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionC(April2013)toRevisionDPageAddedDeviceInformationtable,PinConfigurationandFunctionssection,Specificationssection,ESDRatingstable,ThermalInformationtable,TypicalCharacteristicssection,DetailedDescriptionsection,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection.
1AddedOpenLDILVDSasanacceptableparallelinterfacetotheDS92LV024xchipset.
1ChangedRXINandRXCLKINtoTXOUTandTXCLKOUTtocorrectpinnametypos6ChangedoutputstateofdeserializerwhenPDB=1tobeTRI-STATE,notlogichigh.
6DeletedPowerdissipationrowsfromtheAbsoluteMaximumRatingstable9ChangedJunction-to-ambient,RθJA,valuesinThermalInformationtableFrom:27.
4°C/WTo:33.
8°C/W(NJK)andFrom:27.
7°C/Wto:28.
8°C/W(RHS)10ChangedJunction-to-case,RθJC(top),valuesinThermalInformationtableFrom:4.
5°C/WTo:15.
8°C/W(NJK)andFrom:3.
0°C/WTo:9.
3°C/W(RHS)10DeletednoteinElectricalCharacteristics:SerializerDCtablestatingthatconditionsareverifiedbycharacterizationordesignandnottestedinproduction,asthisnoteonlyappliestoasubsetoftestedparameters10ChangedminimumandmaximumvalueofserializerIINforLVDSreceiverDCspecification10Changedde-emphasistestconditionforserializerIDDsupplycurrent11ChangedIOLconditionforserialbusVOLparameterfrom3mAto0.
5mA13ChangedRPU=10kΩconditionfortheSerialControlBusCharacteristicsoftRandtF13ChangedtPLDfootnotetoincludetDDLTparameter.
14ChangednotationforserialbitstreamUIfootnotetoclarify1UI=1/(28xCLK)14ChangedfootnotefordeserializerLVDSoutputunitstoclarifythatparallelinterfaceUIreferstoChannelLinkformat(1UI=1/[7*CLK])insteadofChannelLinkIIformat(1UI=1/[28*CLK]15ChangedDS92LV0422LVDSTransmitterPulsePositionsimagetocorrectdiagramlabeling.
18ChangedparallelinterfacedescriptionofdeserializerFrom:wideparalleloutputbusTo:ChannelLinkLVDSclock3DS92LV0421,DS92LV0422www.
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28Deletedsupportforoutputdataandclockslewratecontrol28ChangedCMFcaprecommendationfrom0.
1Fto4.
7F28ChangedSSCGConfiguration(LFMODE=L)tableandSSCGConfiguration(LFMODE=H)tabletoclarifycorrectSSC[2:0]behavior.
29ChangedPDB,OEN,andOSS_SELConfigurationtabletoclarifycorrectbehaviorwithPDB,OEN,andOSS_SELpins31ChangedBISTENdetailinBISTWaveformsimagesothatserializeranddeserializeraregeneric33ChangeddescriptionofSerializerVODSELfromReg0x00[4]toReg0x00[5]37ChangedSerializerReg0x00[3:2]descriptionfromReservedtoReverse-CompatibilityModebits37ChangedDeserializerReg0x00[3:2]descriptionfromReservedtoReverse-CompatibilityModebits38ChangesfromRevisionB(April2013)toRevisionCPageChangedlayoutofNationalSemiconductorDataSheettoTIformat14DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated(1)G=Ground,I=Input,O=Output,andP=Power(2)1=HIGH,0=LOW5PinConfigurationandFunctionsNJKPackage36-PinWQFNTopViewPinFunctions:DS92LV0421PINTYPE(1)DESCRIPTION(2)NAMENO.
CHANNELLINKPARALLELINPUTINTERFACERXCLKIN+35ITrueLVDSClockInputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
RXCLKIN–34IInvertingLVDSClockInputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
RXIN[3:0]+2,33,31,29ITrueLVDSDataInputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
RXIN[3:0]–1,32,30,28IInvertingLVDSDataInputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
CHANNELLINKIISERIALOUTPUTINTERFACEDOUT+16OTrueOutput,CMLTheoutputmustbeAC-coupledwitha0.
1-Fcapacitor.
DOUT–15OInvertingOutput,CMLTheoutputmustbeAC-coupledwitha0.
1-Fcapacitor.
5DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedPinFunctions:DS92LV0421(continued)PINTYPE(1)DESCRIPTION(2)NAMENO.
(3)TheVDD(VDDnandVDDIO)supplyrampmustbefasterthan1.
5mswithamonotonicrise.
Ifslowerthan1.
5ms,acapacitoronthePDBpinisrequiredtoensurePDBarrivesafteralltheVDDsupplieshavesettledtotherecommendedoperatingvoltage.
CONTROLANDCONFIGURATIONCONFIG[1:0]10,9IOperatingModes:PinorRegisterControl,LVCMOSwithpulldown.
Determinesthedeviceoperatingmodeandinterfacingdevice(seeTable10).
CONFIG[1:0]=00:InterfacingtoDS92LV2422orDS92LV0422,ControlSignalFilterDISABLEDCONFIG[1:0]=01:InterfacingtoDS92LV2422orDS92LV0422,ControlSignalFilterENABLEDCONFIG[1:0]=10:InterfacingtoDS90UR124,DS99R124Q-Q1CONFIG[1:0]=11:InterfacingtoDS90C124DE-EMPH19IDe-emphasisControl:PinorRegisterControl,Analogwithpullup.
De-emphasis=Open(float)-disabledToenableDe-emphasis,tiearesistorfromthispintoGroundorcontrolthroughregister(seeTable2).
MAPSEL26IChannelLinkMapSelect:PinorRegisterControl,LVCMOSwithpulldown.
MAPSEL=1,MSBonRXIN3±(seeFigure23).
MAPSEL=0,LSBonRXIN3±(seeFigure24).
PDB23IPower-downModeinput,LVCMOSwithpulldown.
PDB=1,serializerisenabled(normaloperation).
SeePowerSupplyRecommendationsformoreinformation.
PDB=0,serializerispowereddownWhentheserializerisinthepower-downstate,thedriveroutputs(DOUT±)arebothlogichigh,thePLLisshutdown,andIDDisminimized.
ControlRegistersareRESET.
RES[7:0]25,3,36,27,18,13,12,8IReserved(tielow),LVCMOSwithpulldown.
VODSEL20IDifferentialDriverOutputVoltageSelect:PinorRegisterControl,LVCMOSwithpulldown.
VODSEL=1,CMLVODis±450mV,900mVp-p(typical):longcableorde-emphasisapplicationsVODSEL=0,CMLVODis±300mV,600mVp-p(typical):shortcable(node-emphasis),lowpowermodeOPTIONALBISTMODEBISTEN21IBISTMode:Optional,LVCMOSwithpulldown.
BISTEN=1,BISTisenabledBISTEN=0,BISTisdisabled(normaloperation)OPTIONALSERIALBUSCONTROLID[X]4ISerialControlBusDeviceIDAddressSelect:Optional,AnalogResistortoGroundand10-kΩpullupto1.
8-Vrail(seeTable8).
SCL6ISerialControlBusClockInput:Optional,LVCMOS(open-drain)SCLrequiresanexternalpullupresistortoVDDIO.
SDA7I/OSerialControlBusDataInputorOutput:Optional,LVCMOS(open-drain)SDArequiresanexternalpullupresistorVDDIO.
POWERANDGROUND(3)DAPGNDGDAPisthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFNpackage.
Connecttothegroundplane(GND)withatleast9vias.
VDDHS14PTXhigh-speedlogicpower,1.
8V±5%VDDIO22PLVCMOSI/OpowerandChannelLinkI/Opower,1.
8V±5%or3.
3V±10%VDDL5PLogicpower,1.
8V±5%VDDP11PPLLpower,1.
8V±5%VDDRX24PRXpower,1.
8V±5%VDDTX17POutputdriverpower,1.
8V±5%6DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated(1)G=Ground,I=Input,O=Output,andP=Power(2)1=HIGH,0=LOWRHSPackage48-PinWQFNTopViewPinFunctions:DS92LV0422PINTYPE(1)DESCRIPTION(2)NAMENO.
CHANNELLINKIISERIALINPUTINTERFACECMF42ICommon-modefilter,AnalogVCMcenter-tapisavirtualGroundwhichmaybeAC-coupledtoGroundtoincreasereceivercommonmodenoiseimmunity.
Recommendedvalueis4.
7Forhigher.
RIN+40ITrueInput,CMLTheoutputmustbeAC-coupledwitha0.
1-Fcapacitor.
RIN–41IInvertingInput,CMLTheoutputmustbeAC-coupledwitha0.
1-Fcapacitor.
CHANNELLINKPARALLELOUTPUTINTERFACETXCLKOUT+17OTrueLVDSClockOutputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
TXCLKOUT–18OInvertingLVDSClockOutputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
TXOUT[3:0]+15,19,21,23OTrueLVDSDataOutputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
TXOUT[3:0]–16,20,22,24OInvertingLVDSDataOutputThispairmusthavea100-ΩterminationforstandardLVDSlevels.
7DS92LV0421,DS92LV0422www.
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LVCMOSOUTPUTSLOCK27OLOCKStatusOutput,LVCMOSLOCK=1,PLLislocked,outputstateddeterminedbyOEN.
LOCK=0,PLLisunlocked,outputstatesdeterminedbyOSS_SELandOEN.
SeeTable7.
CONTROLANDCONFIGURATIONCONFIG[1:0]11,10IOperatingModes:PinorLimitedRegisterControl,LVCMOSwithpulldown.
Determinethedeviceoperatingmodeandinterfacingdevice.
(seeTable10).
CONFIG[1:0]=00:InterfacingtoDS92LV2421orDS92LV0421,ControlSignalFilterDISABLEDCONFIG[1:0]=01:InterfacingtoDS92LV2421orDS92LV0421,ControlSignalFilterENABLEDCONFIG[1:0]=10:InterfacingtoDS90UR241,DS99R421CONFIG[1:0]=11:InterfacingtoDS90C124LFMODE36ISSCGLowFrequencyMode:PinorRegisterControl,LVCMOSwithpulldown.
LFMODE=1,lowfrequencymode(TXCLKOUT=10–20MHz)LFMODE=0,highfrequencymode(TXCLKOUT=20–65MHz)SSCGnotavailableabove65MHz.
MAPSEL34IChannelLinkMapSelect:PinorRegisterControl,LVCMOSwithpulldown.
MAPSEL=1,MSBonTXOUT3±(seeFigure23).
MAPSEL=0,LSBonTXOUT3±(seeFigure24).
OEN30IOutputEnable,LVCMOSwithpulldown.
SeeTable7fordetails.
OSS_SEL35IOutputSleepStateSelectInput,LVCMOSwithpulldown.
SeeTable7fordetails.
PDB1IPower-downModeInput,LVCMOSwithpulldown.
PDB=1,deserializerisenabled(normaloperation).
SeePowerSupplyRecommendationsformoreinformation.
PDB=0,deserializerispowereddown.
Whenthedeserializerisinthepower-downstate,thedriveroutputs(TXOUT±)areinTRI-STATE.
ControlRegistersareRESET.
RES37IReserved(tielow),LVCMOSwithpulldown.
SSC[2:0]7,3,2ISpreadSpectrumClockGeneration(SSCG)RangeSelect,LVCMOSwithpulldown.
SeeTable5andTable6.
VODSEL33IParallelLVDSDriverOutputVoltageSelect:PinorRegisterControl,LVCMOSwithpulldown.
VODSEL=1,LVDSVODis±400mV,800mVp-p(typical)VODSEL=0,LVDSVODis±250mV,500mVp-p(typical)CONTROLANDCONFIGURATION—STRAPPINEQ28[PASS]IEQGainControlofChannelLinkIISerialInput,STRAP,LVCMOSwithpulldownEQ=1,EQgainisenabled(~13dB)EQ=0,EQgainisdisabled(~1.
625dB)OPTIONALBISTMODEBISTEN29IBISTMode:Optional,LVCMOSwithpulldown.
BISTEN=1,BISTisenabledBISTEN=0,BISTisdisabledPASS28OPASSOutput(BISTMode):Optional,LVCMOSPASS=1,noerrorsdetectedPASS=0,errorsdetectedLeaveopenifunused.
Routetoatestpoint(pad)recommended.
OPTIONALSERIALBUSCONTROLID[X]12ISerialControlBusDeviceIDAddressSelect:Optional,AnalogResistortoGroundand10-kΩpullupto1.
8-Vrail(seeTable8).
SCL5ISerialControlBusClockInput:Optional,LVCMOS(opendrain)SCLrequiresanexternalpullupresistorto3.
3V.
SDA4I/OSerialControlBusDataInputorOutput:Optional,LVCMOS(opendrain)SDArequiresanexternalpullupresistor3.
3V.
8DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedPinFunctions:DS92LV0422(continued)PINTYPE(1)DESCRIPTION(2)NAMENO.
(3)TheVDD(VDDnandVDDIO)supplyrampmustbefasterthan1.
5mswithamonotonicrise.
Ifslowerthan1.
5ms,acapacitoronthePDBpinisrequiredtoensurePDBarrivesafteralltheVDDsupplieshavesettledtotherecommendedoperatingvoltage.
POWERANDGROUND(3)DAPDAPGDAPisthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFNpackage.
Connecttothegroundplane(GND)withatleast9vias.
GND9,14,26,32,39,44,45,48GGroundVDDA38,43PAnalogpower,1.
8V±5%VDDIO25PLVCMOSI/OpowerandChannelLinkI/Opower,1.
8V±5%or3.
3V±10%VDDL6,31PLogicpower,1.
8V±5%VDDP8PPLLpower,1.
8V±5%VDDSC46,47PSSCGpower,1.
8V±5%VDDTX13PChannelLinkLVDSparalleloutputpower,3.
3V±10%9DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditions.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
(3)Forsolderingspecifications,seeAbsoluteMaximumRatingsforSoldering(SNOA549).
6Specifications6.
1AbsoluteMaximumRatingsoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2)(3)MINMAXUNITSupplyvoltageVDDn(1.
8V)–0.
32.
5VVDDIO–0.
34Serializer,VDDTX–0.
32.
5Deserializer,VDDTX–0.
34LVCMOSI/Ovoltage–0.
3VDDIO+0.
3VSerializerLVDSinputvoltage–0.
3VDDIO+0.
3VDeserializerLVDSoutputvoltage–0.
3VDDTX+0.
3VSerializerCMLdriveroutputvoltage–0.
3VDDn+0.
3VDeserializerCMLreceiverinputvoltage–0.
3VDD+0.
3VJunctiontemperature,TJ150°CStoragetemperature,Tstg–65150°C(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2)JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
6.
2ESDRatingsVALUEUNITV(ESD)ElectrostaticdischargeHuman-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1)±8000VCharged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2)±1250MachineModel±250IEC61000-4-2,powered-uponlycontactdischargeRD=330Ω,CS=150pF(RIN+,RIN–)>±8000IEC61000-4-2,powered-uponlyair-gapdischargeRD=330Ω,CS=150pF(RIN+,RIN–)>±30000(1)SupplynoisetestingwasdonewithminimumcapacitorsonthePCB.
AsinusoidalsignalisAC-coupledtotheVDDn(1.
8V)supplywithamplitude=100mVp-pmeasuredatthedeviceVDDnpins.
Biterrorratetestingofinputtotheserializerandoutputofthedeserializerwith10metercableshowsnoerrorwhenthenoisefrequencyontheserializerislessthan750kHz.
Thedeserializer,ontheotherhand,showsnoerrorwhenthenoisefrequencyislessthan400kHz.
6.
3RecommendedOperatingConditionsoveroperatingfree-airtemperaturerange(unlessotherwisenoted)MINNOMMAXUNITVDDnSupplyvoltage1.
711.
81.
89VVDDTXSupplyvoltage(serializer)1.
711.
81.
89VVDDTXSupplyvoltage(deserializer)33.
33.
6VVDDIOLVCMOSsupplyvoltage(1.
8-Vnominal)1.
711.
81.
89VVDDIOLVCMOSsupplyvoltage(3.
3-Vnominal)33.
33.
6VClockfrequency1075MHzSupplynoise(1)100mVp-pTAOperatingfree-airtemperature402585°C10DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplicationreport.
(2)Basedonninethermalvias.
6.
4ThermalInformationoveroperatingfree-airtemperaturerange(unlessotherwisenoted)THERMALMETRIC(1)DS92LV0421DS92LV0422UNITNJK(WQFN)RHS(WQFN)36PINS48PINSRθJAJunction-to-ambientthermalresistance(2)33.
828.
8°C/WRθJC(top)Junction-to-case(top)thermalresistance(2)15.
89.
3°C/WRθJBJunction-to-boardthermalresistance7.
25.
7°C/WψJTJunction-to-topcharacterizationparameter0.
20.
1°C/WψJBJunction-to-boardcharacterizationparameter7.
15.
7°C/WRθJC(bot)Junction-to-case(bottom)thermalresistance2.
61.
6°C/W(1)TypicalvaluesrepresentmostlikelyparametricnormsatVDD=3.
3V,TA=+25°C,andattheRecommendedOperationConditionsatthetimeofproductcharacterizationandarenotverified.
(2)Currentintodevicepinsisdefinedaspositive.
Currentoutofadevicepinisdefinedasnegative.
VoltagesarereferencedtogroundexceptVOD,ΔVOD,VTH,andVTL,whicharedifferentialvoltages.
6.
5ElectricalCharacteristics:SerializerDCoverrecommendedoperatingsupplyandtemperatureranges(unlessotherwisenoted)(1)(2)PARAMETERTESTCONDITIONSMINTYPMAXUNITLVCMOSINPUTDCSPECIFICATIONSVIHHigh-levelinputvoltageVDDIO=3Vto3.
6V(PDB,VODSEL,MAPSEL,CONFIG[1:0],BISTENpins)2VDDIOVVDDIO=1.
71Vto1.
89V(PDB,VODSEL,MAPSEL,CONFIG[1:0],BISTENpins)0.
65*VDDIOVDDIOVILLow-levelinputvoltageVDDIO=3Vto3.
6V(PDB,VODSEL,MAPSEL,CONFIG[1:0],BISTENpins)GND0.
8VVDDIO=1.
71Vto1.
89V(PDB,VODSEL,MAPSEL,CONFIG[1:0],BISTENpins)GND0.
35*VDDIOIINInputcurrentVIN=0VorVDDIO(PDB,VODSEL,MAPSEL,CONFIG[1:0],BISTENpins)VDDIO=3Vto3.
6V15±115AVDDIO=1.
7Vto1.
89V15±115CHANNELLINKPARALLELLVDSRECEIVERDCSPECIFICATIONSVTHDifferentialthreshold,highvoltageVCM=1.
2V(seeFigure1),RXIN[3:0]±andRXCLKIN±pins100mVVTLDifferentialthreshold,lowvoltageVCM=1.
2V(seeFigure1),RXIN[3:0]±andRXCLKIN±pins100mV|VID|DifferentialinputvoltageswingVCM=1.
2V(seeFigure1),RXIN[3:0]±andRXCLKIN±pins200600mVVCMCommon-modevoltageVDDIO=3.
3V(RXIN[3:0]±andRXCLKIN±pins)01.
22.
4VVDDIO=1.
8V(RXIN[3:0]±andRXCLKIN±pins)01.
21.
7IINInputcurrentRXIN[3:0]±andRXCLKIN±pins15±115ACHANNELLINKIISERIALCMLDRIVERDCSPECIFICATIONSVODDifferentialoutputvoltageRL=100Ω,de-emphasis=disabled(seeFigure3),DOUT+andDOUT–pinsVODSEL=L±225±300±375mVVODSEL=H±350±450±550VODp-pDifferentialoutputvoltage(DOUT+)–(DOUT–)RL=100Ω,de-emphasis=disabled(seeFigure3),DOUT+andDOUT–pinsVODSEL=L600mVp-pVODSEL=H900ΔVODOutputvoltageunbalanceRL=100Ω,de-emphasis=disabled,VODSEL=L(DOUT+andDOUT–pins)150mV11DS92LV0421,DS92LV0422www.
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65VVODSEL=H1.
575ΔVOSOffsetvoltageunbalance(single-ended)AtTPAandB(seeFigure2),RL=100Ω,de-emphasis=disabled(DOUT+andDOUT–pins)1mVIOSOutputshort-circuitcurrentDOUT±=0V,de-emphasis=disabled,VODSEL=0(DOUT+andDOUT–pins)36mARTOInternaloutputterminationresistorDOUT+andDOUT–pins80120ΩSERIALIZERSUPPLYCURRENTIDDT1Serializersupplycurrent(includesloadcurrent)RL=100Ω,f=75MHz,checkerboardpattern(seeFigure15),de-emphasis=3kΩ,VODSEL=H,VDD=1.
89V(AllVDDpins)84100mAIDDIOT1Serializersupplycurrent(includesloadcurrent)RL=100Ω,f=75MHzde-emphasis=3kΩ,VODSEL=H,checkerboardpattern(seeFigure15)VDDIO=1.
89V(VDDIOpin)35mAVDDIO=3.
6V(VDDIOpin)1013IDDT2Serializersupplycurrent(includesloadcurrent)RL=100Ω,f=75MHz,checkerboardpattern(seeFigure15),de-emphasis=6kΩ,VODSEL=L,VDD=1.
89V(AllVDDpins)7790mAIDDIOT2Serializersupplycurrent(includesloadcurrent)RL=100Ω,f=75MHzde-emphasis=6kΩ,VODSEL=L,checkerboardpattern(seeFigure15)VDDIO=1.
89V(VDDIOpin)35mAVDDIO=3.
6V(VDDIOpin)1013IDDZSerializersupplycurrentpower-downPDB=0V,allotherLVCMOSinputs=0V,VDD=1.
89V(AllVDDpins)1001000AIDDIOZSerializersupplycurrentpower-downPDB=0V,allotherLVCMOSinputs=0VVDDIO=1.
89V(VDDIOpin)0.
510AVDDIO=3.
6V(VDDIOpin)130(1)TypicalvaluesrepresentmostlikelyparametricnormsatVDD=3.
3V,TA=+25°C,andattheRecommendedOperationConditionsatthetimeofproductcharacterizationandarenotverified.
(2)Currentintodevicepinsisdefinedaspositive.
Currentoutofadevicepinisdefinedasnegative.
VoltagesarereferencedtogroundexceptVOD,ΔVOD,VTH,andVTL,whicharedifferentialvoltages.
6.
6ElectricalCharacteristics:DeserializerDCoverrecommendedoperatingsupplyandtemperatureranges(unlessotherwisenoted)(1)(2)PARAMETERTESTCONDITIONSMINTYPMAXUNIT3.
3-VLVCMOSI/ODCSPECIFICATIONS(VDDIO=3Vto3.
6V)VIHHighlevelinputvoltagePDB,VODSEL,OEN,MAPSEL,LFMODE,SSC[2:0],andBISTENpins2VDDIOVVILLowlevelinputvoltagePDB,VODSEL,OEN,MAPSEL,LFMODE,SSC[2:0],andBISTENpinsGND0.
8VIINInputcurrentVIN=0VorVDDIO(PDB,VODSEL,OEN,MAPSEL,LFMODE,SSC[2:0],andBISTENpins)15±115AVOHHighleveloutputvoltageIOH=–0.
5mA(LOCKandPASSpins)VDDIO–0.
2VDDIOVVOLLowleveloutputvoltageIOL=0.
5mA(LOCKandPASSpins)GND0.
2VIOSOutputshort-circuitcurrentVOUT=0V(LOCKandPASSpins)–10mAIOZTRI-STATEoutputcurrentPDB=0V,OSS_SEL=0V,VOUT=0VorVDDIO(LOCKandPASSpins)–1010A12DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedElectricalCharacteristics:DeserializerDC(continued)overrecommendedoperatingsupplyandtemperatureranges(unlessotherwisenoted)(1)(2)PARAMETERTESTCONDITIONSMINTYPMAXUNIT1.
8-VLVCMOSI/ODCSPECIFICATIONS(VDDIO=1.
71Vto1.
89V)VIHHighlevelinputvoltagePDB,VODSEL,OEN,MAPSEL,LFMODE,SSC[2:0],andBISTENpins0.
65*VDDIOVDDIOVVILLowlevelinputvoltagePDB,VODSEL,OEN,MAPSEL,LFMODE,SSC[2:0],andBISTENpinsGND0.
35*VDDIOVIINInputcurrentVIN=0VorVDDIO(PDB,VODSEL,OEN,MAPSEL,LFMODE,SSC[2:0],andBISTENpins)15±115AVOHHighleveloutputvoltageIOH=–0.
5mA(LOCKandPASSpins)VDDIO–0.
2VDDIOVVOLLowleveloutputvoltageIOL=0.
5mA(LOCKandPASSpins)GND0.
2VIOSOutputshort-circuitcurrentVOUT=0V(LOCKandPASSpins)–3mAIOZTRI-STATEoutputcurrentPDB=0V,OSS_SEL=0V,VOUT=0VorVDDIO(LOCKandPASSpins)–1515ACHANNELLINKPARALLELLVDSDRIVERDCSPECIFICATIONS|VOD|DifferentialoutputvoltageRL=100Ω(seeFigure3;TXOUT[3:0]±andTXCLKOUT±pins)VODSEL=L100250400mVVODSEL=H200400600VODp-pDifferentialoutputvoltageAtoBRL=100Ω(seeFigure3;TXOUT[3:0]±andTXCLKOUT±pins)VODSEL=L500mVp-pVODSEL=H800ΔVODOutputvoltageunbalanceRL=100Ω(seeFigure3;TXOUT[3:0]±andTXCLKOUT±pins)150mVVOSOffsetvoltage(single-ended)RL=100Ω(seeFigure3;TXOUT[3:0]±andTXCLKOUT±pins)VODSEL=L11.
21.
5VVODSEL=H1.
2ΔVOSOffsetvoltageunbalance(single-ended)RL=100Ω(seeFigure3;TXOUT[3:0]±andTXCLKOUT±pins)150mVIOSOutputshort-circuitcurrentRL=100Ω,VOUT=GND(TXOUT[3:0]±andTXCLKOUT±pins)–5mAIOZOutputTRI-STATEcurrentRL=100Ω,VOUT=VDDTXorGND(TXOUT[3:0]±andTXCLKOUT±pins)–1010ACHANNELLINKIISERIALCMLRECEIVERDCSPECIFICATIONSVTHDifferentialinputthresholdhighvoltageVCM=1.
2V(InternalVBIAS)(RIN+andRIN-pins)50mVVTLDifferentialinputthresholdlowvoltageVCM=1.
2V(InternalVBIAS)(RIN+andRIN-pins)–50mVVCMCommonmodevoltage,internalVBIASRIN+andRIN-pins1.
2VRTInputterminationRIN+andRIN-pins85100115ΩDESERIALIZERSUPPLYCURRENTIDD1Deserializersupplycurrent(Includesloadcurrent)75MHzclock,checkerboardpattern(seeFigure15),VODSEL=H,SSCG[2:0]=000'b,VDDn=1.
89V(AllVDD(1.
8)pins)88100mAIDDTX1Deserializersupplycurrent(Includesloadcurrent)75MHzclock,checkerboardpattern(seeFigure15),VODSEL=H,SSCG[2:0]=000'b,VDDTX=3.
6V(VDDTXpin)4050mAIDDIO1Deserializersupplycurrent(Includesloadcurrent)75MHzclock,checkerboardpattern(seeFigure15),VODSEL=H,SSCG[2:0]=000'bVDDIO=1.
89V(VDDIOpin)0.
30.
8mAVDDIO=3.
6V(VDDIOpin)0.
81.
5IDDZDeserializersupplycurrentpower-downPDB=0V,AllotherLVCMOSinputs=0V,VDDn=1.
89V(AllVDD(1.
8)pins)0.
152mAIDDTXZDeserializersupplycurrentpower-downPDB=0V,AllotherLVCMOSinputs=0V,VDDTX=3.
6V(VDDTXpin)0.
010.
1mA13DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedElectricalCharacteristics:DeserializerDC(continued)overrecommendedoperatingsupplyandtemperatureranges(unlessotherwisenoted)(1)(2)PARAMETERTESTCONDITIONSMINTYPMAXUNITIDDIOZDeserializersupplycurrentpower-downPDB=0V,allotherLVCMOSinputs=0VVDDIO=1.
89V(VDDIOpin)0.
010.
08mAVDDIO=3.
6V(VDDIOpin)0.
010.
086.
7ElectricalCharacteristics:DCandACSerialControlBusover3.
3-Vsupplyandtemperatureranges(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITVIHInputhigh-levelvoltageSDAandSCL0.
7*VDDIOVDDIOVVILInputlow-levelvoltageSDAandSCLGND0.
3*VDDIOVVHYInputhysteresis>50mVVOLOutputlow-levelvoltageSDA,IOL=0.
5mA00.
36VIINInputcurrentSDAorSCL,Vin=VDDIOorGND–1010AtRSDArisetime,READSDA,RPU=10kΩ,Cb≤400pF(seeFigure18)800nstFSDAfalltime,READSDA,RPU=10kΩ,Cb≤400pF(seeFigure18)50nstSU;DATSet-uptime,READSeeFigure18540nstHD;DATHoldtime,READSeeFigure18600nstSPInputfilter50nsCINInputcapacitanceSDAorSCL10MHz>0.
45UI(6)LVCMOSOUTPUTStCLHDeserializerlow-to-hightransitiontime(seeFigure4)CL=8pF(LOCKandPASSpins)1015nstCHLDeserializerhigh-to-lowtransitiontime(seeFigure4)CL=8pF(LOCKandPASSpins)1015nstPASSBISTPASSvalidtime,BISTEN=1(seeFigure17)10MHz(PASSpin)220230ns75MHz(PASSpin)406516DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedSwitchingCharacteristics:Deserializer(continued)overrecommendedoperatingsupplyandtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITSSCGMODEfDEVSpreadspectrumclockingdeviationfrequency(3)TXCLKOUT±=10to65MHz,SSCG=ON±0.
5%±2%fMODSpreadspectrumclockingmodulationfrequency(3)TXCLKOUT±=10to65MHz,SSCG=ON8100kHzFigure1.
ChannelLinkDCVTH/VTLDefinitionFigure2.
OutputTestCircuitFigure3.
CMLOutputWaveforms17DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedFigure4.
CMLOutputTransitionTimesFigure5.
DS92LV0421ChannelLinkReceiverStrobePositions18DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedFigure6.
DS92LV0422LVDSTransmitterPulsePositionsFigure7.
DS92LV0421LockTimeFigure8.
DS92LV0422LockTime19DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedFigure9.
DS92LV0421DisableTimeFigure10.
DS92LV0421LatencyDelayFigure11.
DS92LV0422LatencyDelayFigure12.
DS92LV0421OutputJitter20DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedFigure13.
DS92LV0422Power-DownDelayFigure14.
DS92LV0422EnableDelayFigure15.
CheckerboardDataPattern21DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedFigure16.
DS92LV0422ReceiverInputJitterToleranceFigure17.
BISTPASSWaveformFigure18.
SerialControlBusTimingDiagram22DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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11TypicalCharacteristicsFigure19.
TypicalIDDT(1.
8-VSupply)vsRXCLKINFigure20.
SerializerDOUTVoltagevsAmbientTemperature23DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated7DetailedDescription7.
1OverviewTheDS92LV042xchipsettransmitsandreceives24bitsofdataand3controlsignals,formattedasChannelLinkLVDSdata,overasingleserialCMLpairoperatingat280Mbpsto2.
1Gbps.
Theserialstreamcontainsanembeddedclock,videocontrolsignals,andtheDC-balanceinformationwhichenhancessignalqualityandsupportsACcoupling.
Thedeserializercanattainlocktoadatastreamwithouttheuseofaseparatereferenceclocksource,whichgreatlysimplifiessystemcomplexityandoverallcost.
Thedeserializeralsosynchronizestotheserializerregardlessofthedatapattern,deliveringtrueautomaticplugandlockperformance.
Itcanlocktotheincomingserialstreamwithouttherequirementofspecialtrainingpatternsorsynccharacters.
Thedeserializerrecoverstheclockanddatabyextractingtheembeddedclockinformation,validating,andthendeserializingtheincomingdatastream,providingaparallelChannelLinkLVDSbustothedisplay,ASIC,orFPGA.
TheDS92LV042xchipsetcanoperatewithupto24bitsofrawdatawiththreeslowerspeedcontrolbitsencodedwithintheserialdatastream.
Forapplicationsthatrequirelessthanthemaximum24rawdatabitsperclockcycle,theusermustensurethatallunusedbitspacesorparallelLVDSchannelsaresettovalidlogicstates,asallparallellanesand27bitspacesarealwayssampled.
7.
2FunctionalBlockDiagramsFigure21.
SerializerBlockDiagramFigure22.
DeserializerBlockDiagram24DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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3FeatureDescription7.
3.
1ParallelLVDSDataTransfer(ColorBitMappingSelect)TheDS92LV042xcanbeconfiguredtoacceptortransmit24-bitdatawithtwodifferentLVDSparallelinterfacemappingschemes:ThenormalChannelLinkLVDSformat(MSBsonLVDSChannel3)canbeselectedbyconfiguringtheMAPSELpintohigh.
SeeFigure23forthenormalChannelLinkLVDSmapping.
Analternatemappingschemeisavailable(LSBsonLVDSChannel3)byconfiguringtheMAPSELpintolow.
SeeFigure24forthealternateLVDSmapping.
Themappingschemescanalsobeselectedbyregistercontrol.
Thealternatemappingschemeisusefulinsomeapplicationswherethereceivingsystem,typicallyadisplay,requirestheLSBsforthe24-bitcolordatatobesentonLVDSChannel3.
NOTEWhiletheLVDSparallelinterfacehas28bitsdefined,only27bitsarerecoveredbytheserializerandsenttothedeserializer.
Thischipsetsupports24-bitRGBplusthethreevideocontrolsignals.
The28thbitisnotsampled,sent,orrecovered.
Figure23.
8–BitChannelLinkMapping:MSB'sonRXIN3Figure24.
8–BitChannelLinkMapping:LSB'sonRXIN325DS92LV0421,DS92LV0422www.
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3.
2SerialDataTransferTheDS92LV042xchipsettransmitsandreceivesapixelofdatainthefollowingformat:C1andC0representtheembeddedclockintheserialstream.
C1isalwayshighandC0isalwayslow.
Theb[23:0]containsthescrambledRGBdata.
DCBistheDC-Balancedcontrolbit.
DCBisusedtominimizetheshortandlong-termDCbiasonthesignallines.
Thisbitdeterminesifthedataisunmodifiedorinverted.
DCAisusedtovalidatedataintegrityintheembeddeddatastreamandcanalsocontainencodedcontrol(VS,HS,DE).
BothDCAandDCBcodingschemesaregeneratedbytheserializeranddecodedbythedeserializerautomatically.
Figure25illustratestheserialstreamperclockcycle.
NOTEFigure25onlyillustratesthebitsbutdoesnotactuallyrepresentthebitlocation,asthebitsarescrambledandbalancedcontinuously.
Figure25.
ChannelLinkIISerialStream(DS92LV042x)7.
3.
3VideoControlSignalFilterThethreecontrolbitscanbeusedtocommunicateanylowspeedsignal.
Themostcommonuseforthesebitsisinthedisplayormachinevisionapplications.
Inadisplayapplication,thesebitsaretypicallyassignedas:Bit26toDE,Bit24toHS,andBit25toVS.
Inthemachinevisionstandard,CameraLink,thesebitsaretypicallyassigned:Bit26toDVAL,Bit24toLVAL,andBit25toFVAL.
WhenoperatingthedevicesinNormalMode,thevideocontrolsignals(DE,HS,VS)havethefollowingrestrictions:NormalModewithControlSignalFilterEnabled:–DEandHS:Only2transitionsper130clockcyclesaretransmitted,thetransitionpulsemustbe3clockcyclesorlonger.
NormalModewithControlSignalFilterDisabled:–DEandHS:Only2transitionsper130clockcyclesaretransmitted,norestrictiononminimumtransitionpulse.
VS:Only1transitionper130clockcyclesaretransmitted,minimumpulsewidthis130clockcycles.
Glitchesofacontrolsignalcancauseavisualdisplayerror,andvideocontrolsignalsaredefinedaslowfrequencysignalswithlimitedtransitions.
Therefore,thevideocontrolsignalfilterfeatureallowsforthechipsettovalidateandfilteroutanyhighfrequencynoiseonthecontrolsignals(seeFigure26).
Figure26.
VideoControlSignalFilterWaveform26DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedFeatureDescription(continued)7.
3.
4SerializerFunctionalDescriptionTheserializerconvertsaChannelLinkLVDSclockanddatabustoasingleserialoutputdatastreamandalsoactsasasignalgeneratorforthechipsetBuilt-InSelfTest(BIST)mode.
Thedevicecanbeconfiguredthroughexternalpinsorthroughtheoptionalserialcontrolbus.
Theserializerfeaturesenhancedsignalqualityonthelinkbysupporting:aselectableVODlevel,aselectablede-emphasisforsignalconditioning,andChannelLinkIIdatacodingthatprovidesrandomization,scrambling,andDC-balancingofthedata.
TheserializerincludesmultiplefeaturestoreduceEMIassociatedwithdisplaydatatransmission.
Thisincludestherandomizationandscramblingoftheserialdataandsystemspreadspectrumclocksupport.
Theserializerincludespower-savingfeatureswithasleepmode,autostopclockfeature,andoptionalLVCMOS(1.
8Vor3.
3V)I/Ocompatibility(seealsoOptionalSerialBusControlandBuilt-InSelfTest(BIST)).
7.
3.
4.
1SignalQualityEnhancers7.
3.
4.
1.
1SerializerVODSelect(VODSEL)TheserializerdifferentialoutputvoltagemaybeincreasedbysettingtheVODSELpinhigh.
WhenVODSELislow,theDCVODisatthestandard(default)level.
WhenVODSELishigh,theVODisincreasedinlevel.
TheincreasedVODisusefulinextremelyhighnoiseenvironmentsandextralongcablelengthapplications.
Whenusingde-emphasis,TIrecommendssettingVODSEL=Htoavoidexcessivesignalattenuation,especiallywiththelargerde-emphasissettings.
Thisfeaturemaybecontrolledbyexternalpinorbyregister.
Table1.
SerializerDifferentialOutputVoltageINPUTEFFECTVODSELVOD(mV)VOD(mVp-p)L±300600H±4509007.
3.
4.
1.
2SerializerDe-Emphasis(DE-EMPH)Thede-emphasispincontrolstheamountofde-emphasisbeginningonefullbittimeafteralogictransitionthattheserializerdrives.
Thisisusefultocounteractloadingeffectsoflongorlossycables.
Thispinmustbeleftopenifusedforstandardswitchingcurrents(node-emphasis)orifusedunderregistercontrol.
De-emphasisisselectedbyconnectingaresistoronthispintoground,withtheRvaluebetween0.
5kΩand1MΩ,orbyregistersetting.
Whenusingde-emphasis,TIrecommendssettingVODSEL=H.
Table2.
De-EmphasisResistorValueRESISTORVALUE(kΩ)DE-EMPHASISSETTINGOpenDisabled0.
6–12dB1–9dB2–6dB5–3dB27DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedFigure27.
De-EmphasisvsRValue7.
3.
4.
2EMIReductionFeatures7.
3.
4.
2.
1DataRandomizationandScramblingChannelLinkIIserializersanddeserializersfeatureathree-stepencodingprocessthatenablestheuseofAC-coupledinterconnectsandalsohelpstomanageEMI.
Theserializerfirstpassestheparalleldatathroughascramblerwhichrandomizesthedata.
TherandomizeddataisthenDC-balanced.
TheDC-balancedandrandomizeddatathengoesthroughabit-shufflingcircuitandistransmittedoutontheserialline.
Thisencodingprocesshelpstopreventstaticdatapatternsontheserialstream.
TheresultingfrequencycontentoftheserialstreamrangesfromtheparallelclockfrequencytotheNyquistrate.
Forexample,iftheserializeranddeserializerchipsetisoperatingataparallelclockfrequencyof50MHz,theresultingfrequencycontentoftheserialstreamrangesfrom50MHzto700MHz(50MHz*28bits=1.
4GHz/2=700MHz).
7.
3.
4.
2.
2SerializerSpreadSpectrumCompatibilityTheserializerRXCLKINiscapableoftrackingspreadspectrumclocking(SSC)fromahostsource.
TheRXCLKINacceptsspreadspectrumtrackingupto35-kHzmodulationand±0.
5,±1,or±2%deviations(centerspread).
ThemaximumconditionsfortheRXCLKINinputare:amodulationfrequencyof35kHzandamplitudedeviationsof±2%(4%total).
7.
3.
4.
3Power-SavingFeatures7.
3.
4.
3.
1SerializerPower-DownFeature(PDB)TheserializerhasaPDBinputpintoenableorpowerdownthedevice.
Thispiniscontrolledbythehostandisusedtosavepower,disablingthelinkwhenthedisplayisnotrequired.
Inpower-downmode,thehigh-speeddriveroutputsarebothpulledtoVDDandpresenta0-VVODstate.
NOTEInpower-down,theoptionalserialbuscontrolregistersareRESET.
7.
3.
4.
3.
2SerializerStopClockFeatureTheserializerentersalowpowerSLEEPstatewhentheRXCLKINisstopped.
ASTOPconditionisdetectedwhentheinputclockfrequencyislessthan3MHz.
Theclockmustbeheldatastaticloworhighstate.
WhentheRXCLKINstartsagain,theserializerlockstothevalidinputclockandthentransmitstheserialdatatothedeserializer.
NOTEInSTOPCLOCKSLEEP,theoptionalserialbuscontrolregistersvaluesareRETAINED.
28DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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3.
4.
3.
3Serializer1.
8-Vor3.
3-VVDDIOOperationTheserializerparallelcontrolbuscanoperatewith1.
8-Vor3.
3-Vlevels(VDDIO)forhostcompatibility.
The1.
8-Vlevelsofferslowernoise(EMI)andalsosystempowersavings.
7.
3.
5DeserializerFunctionalDescriptionThedeserializerconvertsasingleinputserialdatastreamtoaChannelLinkLVDSclockanddatabusandalsoprovidesasignalcheckforthechipsetBuilt-InSelfTest(BIST)mode.
Thedevicecanbeconfiguredthroughexternalandstrappinsorthroughtheoptionalserialcontrolbus.
ThedeserializerfeaturesenhancedsignalqualityonthelinkbysupportinganintegratedequalizerontheserialinputandChannelLinkIIdataencodingwhichprovidesrandomization,scrambling,andDC-balancingofthedata.
ThedeserializerincludesmultiplefeaturestoreduceEMIassociatedwithdisplaydatatransmission.
Thisincludestherandomizationandscramblingofthedata,ChannelLinkLVDSoutputinterface,andoutputspreadspectrumclockgeneration(SSCG)support.
Thedeserializerincludespowersavingfeatureswithapower-downmodeandoptionalLVCMOS(1.
8-V)interfacecompatibility.
7.
3.
5.
1SignalQualityEnhancers7.
3.
5.
1.
1DeserializerInputEqualizerGain(EQ)Thedeserializercanenablereceiverinputequalizationoftheserialstreamtoincreasetheeyeopeningtothedeserializerinput.
NOTEThisfunctioncannotbeseenattheRXIN±input.
Theequalizationfeaturemaybecontrolledbytheexternalpinorbyregister.
Table3.
ReceiverEqualizationConfigurationEQ(STRAPOPTION)EFFECTL~1.
625dB(OFF)H~13dB7.
3.
5.
2EMIReductionFeatures7.
3.
5.
2.
1DeserializerVODSelect(VODSEL)ThedifferentialoutputvoltageoftheChannelLinkparallelinterfaceiscontrolledbytheVODSELinput.
Table4.
DeserializerDifferentialOutputVoltageINPUTEFFECTVODSELVOD(mV)VOD(mVp-p)L±250500H±4008007.
3.
5.
2.
2DeserializerCommon-ModeFilterPin(CMF)(Optional)Thedeserializerprovidesaccesstothecentertapoftheinternaltermination.
Acapacitormaybeplacedonthispinforadditionalcommon-modefilteringofthedifferentialpair.
Thiscanbeusefulinhigh-noiseenvironmentsforadditionalnoiserejectioncapability.
A4.
7-FcapacitormaybeconnectedfromthispintoGround.
7.
3.
5.
2.
3DeserializerSSCGGeneration(Optional)Thedeserializerprovidesaninternallygeneratedspreadspectrumclock(SSCG)tomodulateitsoutputs.
Bothclockanddataoutputsaremodulated.
ThisaidstolowersystemEMI.
OutputSSCGdeviationsof±2%(4%total)atupto100-kHzmodulationsareavailable(seeTable5).
Thisfeaturemaybecontrolledbyexternalpinsorbyregister.
29DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedNOTEThedeserializersupportstheSSCGfunctionwithTXCLKOUT=10MHzto65MHz.
WhentheTXCLKOUT=65MHzto75MHz,itisrequiredtodisabletheSSCGfunction(SSC[2:0]=000).
Figure28.
SSCGWaveformTable5.
SSCGConfiguration(LFMODE=L):DeserializerOutputSSC[2:0]INPUTSLFMODE=L(20TO65MHz)RESULTSSC2SSC1SSC0fdev(%)fmod(kHz)LLLOffOffLLH±0.
9CLK/2168LHL±1.
2LHH±1.
9HLL±2.
3HLH±0.
7CLK/1300HHL±1.
3HHH±1.
7Table6.
SSCGConfiguration(LFMODE=H):DeserializerOutputSSC[2:0]INPUTSLFMODE=H(10TO20MHz)RESULTSSC2SSC1SSC0fdev(%)fmod(kHz)LLLOffOffLLH±0.
7CLK/625LHL±1.
3LHH±1.
8HLL±2.
2HLH±0.
7CLK/385HHL±1.
2HHH±1.
730DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated7.
3.
5.
2.
4Power-SavingFeatures7.
3.
5.
2.
4.
1DeserializerPower-DownFeature(PDB)ThedeserializerhasaPDBinputpintoenableorpowerdownthedevice.
Thispincanbecontrolledbythesystemtosavepower,disablingthedeserializerwhenthedisplayisnotrequired.
Anauto-detectmodeisalsoavailable.
Inthismode,thePDBpinistiedhighandthedeserializerenterspower-downwhentheserialstreamstops.
Whentheserialstreamstartsupagain,thedeserializerlockstotheinputstream,assertstheLOCKpin,andoutputsvaliddata.
Inpower-downmode,theLVDSdataandclockoutputstatesaredeterminedbytheOSS_SELstatus.
NOTEInpower-down,theoptionalserialbuscontrolregistersareRESET.
7.
3.
5.
2.
4.
2DeserializerStopStreamSLEEPFeatureThedeserializerentersalowpowerSLEEPstatewhentheinputserialstreamisstopped.
ASTOPconditionisdetectedwhentheembeddedclockbitsarenotpresent.
Whentheserialstreamstartsagain,thedeserializerthenlockstotheincomingsignalandrecoversthedata.
NOTEInSTOPSTREAMSLEEP,theoptionalserialbuscontrolregistersvaluesareRETAINED.
7.
3.
5.
2.
4.
3Deserializer1.
8-Vor3.
3-VVDDIOOperationThedeserializerparallelcontrolbuscanoperatewith1.
8-Vor3.
3-Vlevels(VDDIO)fortarget(display)compatibility.
The1.
8-Vlevelsofferslowernoise(EMI)andalsosystempowersavings.
7.
3.
5.
3DeserializerClock-DataRecoveryStatusFlag(LOCK),OutputEnable(OEN),andOutputStateSelect(OSS_SEL)WhenPDBisdrivenhigh,theCDRPLLbeginslockingtotheserialinput,andLOCKgoesfromTRI-STATEtolow(dependingonthevalueoftheOSS_SELsetting).
AftertheDS92LV0422completesitslocksequencetotheinputserialdata,theLOCKoutputisdrivenhigh,indicatingvaliddataandclockrecoveredfromtheserialinputisavailableontheChannelLinkoutputs.
TheTXCLKOUToutputisheldatitscurrentstateatthechangefromOSC_CLK(ifthisisenabledthroughOSC_SEL)totherecoveredclock(orviceversa).
NOTETheChannelLinkoutputsmaybeheldinaninactivestate(TRI-STATE)throughtheuseoftheOutputEnablepin(OEN).
Ifthereisalossofclockfromtheinputserialstream,LOCKisdrivenlowandthestateoftheoutputsarebasedontheOSS_SELsetting(configurationpinorregister).
31DS92LV0421,DS92LV0422www.
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PDB,OEN,andOSS_SELConfiguration(DeserializerOutputs)INPUTSOUTPUTSSERIALINPUTPDBOENOSS_SELLOCKOTHEROUTPUTSXLXXXTXCLKOUTisTRI-STATETXOUT[3:0]areTRI-STATEPASSisTRI-STATEStaticHXLLTXCLKOUTisTRI-STATETXOUT[3:0]areTRI-STATEPASSisHIGHStaticHLHLTXCLKOUTisTRI-STATETXOUT[3:0]areTRI-STATEPASSisTRI-STATEStaticHHHLTXCLKOUTisTRI-STATEorOscillatorOutputthroughRegisterbitTXOUT[3:0]areTRI-STATEPASSisTRI-STATEActiveHLXHTXCLKOUTisTRI-STATETXOUT[3:0]areTRI-STATEPASSisActiveActiveHHXHTXCLKOUTisActiveTXOUT[3:0]areActivePASSisActive(Normaloperatingmode)7.
3.
5.
4DeserializerOscillatorOutput(Optional)Thedeserializerprovidesanoptionalclockoutputwhentheinputclock(serialstream)hasbeenlost.
Thisisbasedonaninternaloscillator.
Thefrequencyoftheoscillatormaybeselected.
Thisfeaturemaybecontrolledbyexternalpinorbyregister.
Figure29.
TXCLKOUTOutputOscillatorOptionEnabled32DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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3.
6Built-InSelfTest(BIST)Anoptionalat-speedBuilt-InSelfTest(BIST)featuresupportsthetestingofthehigh-speedseriallink.
Thisisusefulintheprototypestage,equipmentproduction,in-systemtest,andforsystemdiagnostics.
InBISTmode,onlyaninputclockisrequiredalongwithcontroltotheserializeranddeserializerBISTENinputpins.
Theserializeroutputsatestpattern(PRBS-7)anddrivesthelinkatspeed.
ThedeserializerdetectsthePRBS-7patternandmonitorsitforerrors.
APASSoutputpintogglestoflaganypayloadsthatarereceivedwith1to24errors.
Uponcompletionofthetest,theresultofthetestisheldonthePASSoutputuntilreset(newBISTtestorpower-down).
AhighonPASSindicatesNOERRORSweredetected.
AlowonPASSindicatesoneormoreerrorsweredetected.
ThedurationofthetestiscontrolledbythepulsewidthappliedtothedeserializerBISTENpin.
Inter-operabilityissupportedbetweenthisChannelLinkIIdeviceandallChannelLinkIIgenerations(Gen1/2/3);seerespectivedatasheetsfordetailsonenteringBISTmodeandcontrol.
7.
3.
6.
1SampleBISTSequenceSeeFigure30fortheBISTmodeflowdiagram.
Step1:PlacetheserializerinBISTModebysettingserializerBISTEN=H.
BISTModeisenabledthroughtheBISTENpin.
AnRXCLKINisrequiredforBIST.
WhenthedeserializerdetectstheBISTmodepatternandcommand(DCAandDCBcode),thedataandcontrolsignaloutputsareshutoff.
Step2:PlacethedeserializerinBISTmodebysettingtheBISTEN=H.
ThedeserializerisnowinBISTmodeandcheckstheincomingserialpayloadsforerrors.
Ifanerrorinthepayload(1to24)isdetected,thePASSpinswitcheslowforonehalfoftheclockperiod.
DuringtheBISTtest,thePASSoutputcanbemonitoredandcountedtodeterminethepayloaderrorrate.
Step3:TostopBISTmode,thedeserializerBISTENpinissetlow.
Thedeserializerstopscheckingthedata,andthefinaltestresultisheldonthePASSpin.
Ifthetestranerrorfree,thePASSoutputishigh.
Ifthereisoneormoreerrorsdetected,thePASSoutputislow.
ThePASSoutputstateishelduntilanewBISTisrun,thedeviceisRESET,orpowereddown.
TheBISTdurationisusercontrolledbythedurationoftheBISTENsignal.
Step4:Toreturnthelinktonormaloperation,theserializerBISTENinputissetlow.
Thelinkreturnstonormaloperation.
Figure31showsthewaveformdiagramofatypicalBISTtestfortwocases.
Case1iserror-free,andCase2showsonewithmultipleerrors.
Inmostcases,itisdifficulttogenerateerrorsduetotherobustnessofthelink(differentialdatatransmissionandsoforth),thustheymaybeintroducedbygreatlyextendingthecablelength,faultingtheinterconnect,orreducingsignalconditionenhancements(de-emphasis,VODSEL,orRxequalization).
Figure30.
BISTModeFlowDiagram33DS92LV0421,DS92LV0422www.
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BISTWaveforms7.
3.
6.
2BERCalculationsItispossibletocalculatetheapproximateBitErrorRate(BER).
Thefollowingisrequired:ClockFrequency(MHz)BISTDuration(seconds)BISTTestResult(PASS)TheBERislessthanorequaltooneovertheproductof24timestheRXCLKINratetimesthetestduration.
Ifweassumea65-MHzclock,a10-minute(600seconds)test,andaPASS,theBERis≤1.
07*10E-12.
BISTmoderunsacheckonthedatapayloadbits.
TheLOCKpinalsoprovidesalinkstatus.
IftherecoveryoftheC0andC1bitsdoesnotreconstructtheexpectedclocksignal,theLOCKpinswitcheslow.
ThecombinationoftheLOCKandat-speedBISTPASSpinprovidesapowerfultoolforsystemevaluationandperformancemonitoring.
7.
3.
7OptionalSerialBusControlTheserializeranddeserializermayalsobeconfiguredbytheuseofaserialcontrolbusthatisI2Cprotocol-compatible.
Bydefault,theI2CReg0x00=0x00,andallconfigurationissetbycontrolorstrappins.
WritingReg0x00=0x01enablesorallowsconfigurationbyregisters;thisoverridesthecontrolorstrappins.
Multipledevicesmaysharetheserialcontrolbus,becausemultipleaddressesaresupported(seeFigure32).
Theserialbusiscomprisedofthreepins.
TheSCLisaserialbusclockinput.
TheSDAistheserialbusdatainputoroutputsignal.
BothSCLandSDAsignalsrequireanexternalpullupresistortoVDDIO.
Formostapplications,a4.
7-kΩpullupresistortoVDDIOmaybeused.
Theresistorvaluemaybeadjustedforcapacitiveloadinganddataraterequirements.
Thesignalsareeitherpulledhighordrivenlow.
34DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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SerialControlBusConnectionThethirdpinistheID[X]pin.
Thispinsetsoneoffourpossibledeviceaddresses.
Twodifferentconnectionsarepossible:ThepinmaybepulledtoVDD(1.
8V,notVDDIO)witha10-kΩresistor.
ThepinmaybepulledtoVDD(1.
8V,notVDDIO)witha10-kΩresistorandpulleddowntogroundwitharecommendedvalueRIDresistor.
Thiscreatesavoltagedividerthatsetstheotherthreepossibleaddresses.
SeeTable8fortheserializerandTable9forthedeserializer.
DonottieID[X]directlytoVSS.
(1)RID≠0Ω.
DonotconnectdirectlytoVSS(GND).
Thisisnotavalidaddress.
Table8.
ID[X]ResistorValue:DS92LV0421(Serializer)RESISTORRIDkΩ(1)(5%TOL)ADDRESS7'bADDRESS8'b0APPENDED(WRITE)0.
477b'1101001(h'69)8b'11010010(h'D2)2.
77b'1101010(h'6A)8b'11010100(h'D4)8.
27b'1101011(h'6B)8b'11010110(h'D6)Open7b'1101110(h'6E)8b'11011100(h'DC)(1)RID≠0Ω.
DonotconnectdirectlytoVSS(GND).
Thisisnotavalidaddress.
Table9.
ID[X]ResistorValue–DS92LV0422(Deserializer)RESISTORRIDkΩ(1)(5%TOL)ADDRESS7'bADDRESS8'b0APPENDED(WRITE)0.
477b'1110001(h'71)8b'11100010(h'E2)2.
77b'1110010(h'72)8b'11100100(h'E4)8.
27b'1110011(h'73)8b'11100110(h'E6)Open7b'1110110(h'76)8b'11101100(h'EC)35DS92LV0421,DS92LV0422www.
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comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedTheserialbusprotocoliscontrolledbySTART,START-repeated,andSTOPphases.
ASTARToccurswhenSCLtransitionslowwhileSDAishigh.
ASTOPoccurswhenSDAtransitionshighwhileSCLisalsohigh(seeFigure33).
Figure33.
STARTandSTOPConditionsTocommunicatewitharemotedevice,thehostcontroller(master)sendstheslaveaddressandlistensforaresponsefromtheslave.
Thisresponseisreferredtoasanacknowledgebit(ACK).
Ifaslaveonthebusisaddressedcorrectly,itAcknowledges(ACKs)themasterbydrivingtheSDAbuslow.
Iftheaddressdoesn'tmatchtheslaveaddressofadevice,itNot-acknowledges(NACKs)themasterbylettingSDAbepulledhigh.
ACKsalsooccuronthebuswhendataisbeingtransmitted.
Whenthemasteriswritingdata,theslaveACKsaftereverydatabyteissuccessfullyreceived.
Whenthemasterisreadingdata,themasterACKsaftereverydatabyteisreceivedtolettheslaveknowitwantstoreceiveanotherdatabyte.
Whenthemasterwantstostopreading,itNACKsafterthelastdatabyteandcreatesastopconditiononthebus.
Allcommunicationonthebusbeginswitheitherastartconditionorarepeatedstartcondition.
Allcommunicationonthebusendswithastopcondition.
AREADisshowninFigure34andaWRITEisshowninFigure35.
NOTEDuringinitialpower-up,adelayof10msisrequiredbeforetheI2Cresponds.
Iftheserialbusisnotrequired,thethreepinsmaybeleftopen(NC).
Figure34.
SerialControlBus:READFigure35.
SerialControlBus:WRITE36DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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4DeviceFunctionalModes7.
4.
1SerializerandDeserializerOperatingModesandReverseCompatibility(CONFIG[1:0])TheDS92LV042xchipsetiscompatiblewithothersingleseriallaneChannelLinkIIorFPD-LinkIIdevices.
ConfigurationmodesareprovidedforreversecompatibilitywiththeDS90C241orDS90C124chipset(FPD-LinkIIGeneration1)andalsotheDS90UR241/DS90UR124chipset(FPD-LinkIIGeneration2)bysettingtherespectivemodewiththeCONFIG[1:0]pinsontheserializerordeserializerasshowninTable10andTable11.
Thisselectionalsodetermineswhetherthecontrolsignalfilterfeatureisenabledordisabledinthenormalmode.
Thisfeaturemaybecontrolledbyexternalpinorbyregister.
Table10.
DS92LV0421SerializerModesCONFIG1CONFIG0MODECOMPATIBLEDESERIALIZERDEVICELLNormalMode,ControlSignalFilterdisabledDS92LV0422,DS92LV0412,DS92LV2422,DS92LV2412LHNormalMode,ControlSignalFilterenabledDS92LV0422,DS92LV0412,DS92LV2422,DS92LV2412HLReverseCompatibilityMode(FPD-LinkII,GEN2)DS90UR124,DS99R124Q-Q1HHReverseCompatibilityMode(FPD-LinkII,GEN1)DS90C124Table11.
DS92LV0422DeserializerModesCONFIG1CONFIG0MODECOMPATIBLESERIALIZERDEVICELLNormalMode,ControlSignalFilterdisabledDS92LV0421,DS92LV0411,DS92LV2421,DS92LV2411LHNormalMode,ControlSignalFilterenabledDS92LV0421,DS92LV0411,DS92LV2421,DS92LV2411HLReverseCompatibilityMode(FPD-LinkII,GEN2)DS90UR241,DS99R421HHReverseCompatibilityMode(FPD-LinkII,GEN1)DS90C24137DS92LV0421,DS92LV0422www.
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5RegisterMapsTable12.
SERIALIZER:SerialBusControlRegistersADD(DEC)ADD(HEX)REGISTERNAMEBIT(S)R/WDEFAULT(BIN)FUNCTIONDESCRIPTION00SerializerConfig17R/W0ReservedReserved6R/W0MAPSEL0:LSBonRXIN31:MSBonRXIN35R/W0VODSEL0:Low1:High4R/W0ReservedReserved3:2R/W00CONFIG00:NormalMode,ControlSignalFilterDisabled01:NormalMode,ControlSignalFilterEnabled10:DS90UR124,DS99R124Q-Q1Reverse-CompatibilityMode(FPD-LinkII,GEN2)11:DS90C124Reverse-CompatibilityMode(FPD-LinkII,GEN1)1R/W0SLEEPNote–notthesamefunctionasPowerDown(PDB)0:NormalMode1:SleepMode–Registersettingsretained.
0R/W0REG0:Configurationssetfromcontrolpins1:Configurationsetfromregisters(exceptI2C_ID)11DeviceID7R/W0REGID0:AddressfromID[X]Pin1:AddressfromRegister6:0R/W1101000ID[X]SerialBusDeviceID,fourIDsare:7b'1101001(h'69)7b'1101010(h'6A)7b'1101011(h'6B)7b'1101110(h'6E)Allotheraddressesarereserved.
22De-EmphasisControl7:5R/W000De-EmphasisSetting000:setbyexternalresistor001:–1dB010:–2dB011:–3.
3dB100:–5dB101:–6.
7dB110:–9dB111:–12dB4R/W0De-EmphasisEN0:De-emphasisEnabled1:De-emphasisDisabled3:0R/W0000ReservedReserved38DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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DESERIALIZER:SerialBusControlRegistersADD(DEC)ADD(HEX)REGISTERNAMEBIT(S)R/WDEFAULT(BIN)FUNCTIONDESCRIPTION00DeserializerConfig17R/W0LFMODE0:20to65MHzSSCGOperation1:10to20MHzSSCGOperation6R/W0MAPSELChannelLinkMapSelect0:LSBonTXOUT3±1:MSBonTXOUT3±5R/W0ReservedReserved4R/W0ReservedReserved3:2R/W00CONFIG00:NormalMode,ControlSignalFilterDisabled01:NormalMode,ControlSignalFilterEnabled10:DS90UR241,DS99R421Reverse-CompatibilityMode(FPD-LinkII,GEN2)11:DS90C241Reverse-CompatibilityMode(FPD-LinkII,GEN1)1R/W0SLEEPNote–notthesamefunctionasPowerDown(PDB)0:NormalMode1:SleepMode–Registersettingsretained.
0R/W0REGControl0:Configurationssetfromcontrolorstrappins1:Configurationsetfromregisters(exceptI2C_ID)11DeviceID7R/W0REGID0:AddressfromID[X]Pin1:AddressfromRegister6:0R/W1110000ID[X]SerialBusDeviceID,fourIDsare:7b'1110001(h'71)7b'1110010(h'72)7b'1110011(h'73)7b'1110110(h'76)Allotheraddressesarereserved.
22DeserializerFeatures17R/W0OENOutputEnableInputSeeTable76R/W0OSS_SELOutputSleepStateSelectSeeTable75:4R/W00ReservedReserved3R/W0VODSELDifferentialLVDSDriverOutputVoltageSelect0:LVDSVODis±250mV,500mVp-p(typ)1:LVDSVODis±400mV,800mVp-p(typ)2:0R/W000OSC_SEL000:OFF001:Reserved010:25MHz±40%011:16.
7MHz±40%100:12.
5MHz±40%101:10MHz±40%110:8.
3MHz±40%111:6.
3MHz±40%39DS92LV0421,DS92LV0422www.
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DESERIALIZER:SerialBusControlRegisters(continued)ADD(DEC)ADD(HEX)REGISTERNAMEBIT(S)R/WDEFAULT(BIN)FUNCTIONDESCRIPTION33DeserializerFeatures27:5R/W000EQGain000:~1.
625dB001:~3.
25dB010:~4.
87dB011:~6.
5dB100:~8.
125dB101:~9.
75dB110:~11.
375dB111:~13dB4R/W0EQEnable0:EQ=disabled1:EQ=enabled3R/W0ReservedReserved2:0R/W000SSCIfLFMODE=0then:000:SSCGOFF001:fdev=±0.
9%,fmod=CLK/2168010:fdev=±1.
2%,fmod=CLK/2168011:fdev=±1.
9%,fmod=CLK/2168100:fdev=±2.
3%,fmod=CLK/2168101:fdev=±0.
7%,fmod=CLK/1300110:fdev=±1.
3%,fmod=CLK/1300111:fdev=±1.
7%,fmod=CLK/1300IfLFMODE=1,then:001:fdev=±0.
7%,fmod=CLK/625010:fdev=±1.
3%,fmod=CLK/625011:fdev=±1.
8%,fmod=CLK/625100:fdev=±2.
2%,fmod=CLK/625101:fdev=±0.
7%,fmod=CLK/385110:fdev=±1.
2%,fmod=CLK/385111:fdev=±1.
7%,fmod=CLK/38540DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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TI'scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.
Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.
8.
1ApplicationInformation8.
1.
1DisplayApplicationTheDS92LV042xchipsetisintendedforinterfacebetweenahost(graphicsprocessor)andadisplay.
Itsupportsa24-bitcolordepth(RGB888)andupto1024*768displayformats.
InaRGB888application,24colorbits(R[7:0],G[7:0],andB[7:0]),PixelClock(PCLK),andthreecontrolbits(VS,HS,andDE)aresupportedacrosstheseriallinkwithRXCLKINratesfrom10to75MHz.
Thechipsetmayalsobeusedin18-bitcolorapplications.
Inthisapplication,threetosixgeneral-purposesignalsmayalsobesentfromhosttodisplay.
8.
1.
2LiveLinkInsertionTheserializeranddeserializerdevicessupportlivelinkorcablehotplugapplications.
TheautomaticreceiverlocktorandomdataplugandgohotinsertioncapabilityallowstheDS92LV0422toattainlocktotheactivedatastreamduringaliveinsertionevent.
8.
1.
3AlternateColororDataMappingColor-mappeddatapinnamesareprovidedtospecifyarecommendedmappingfor24-bitand18-bitapplications.
Seven(7)isassumedtobetheMSB,andZero(0)isassumedtobetheLSB.
Whilethisisrecommended,itisnotrequired.
WhenconnectingtoearliergenerationsofFPD-LinkIIserializeranddeserializerdevices,acolormappingreviewisrecommendedtoensurethecorrectconnectivityisobtained.
Table14providesexamplesforinterfacingbetweenDS92LV0421anddifferentdeserializers.
Table15providesexamplesforinterfacingbetweenDS92LV0422anddifferentserializers.
Table14.
SerializerAlternateColororDataMappingCHANNELLINKBITNUMBERRGB(LSBEXAMPLE)DS92LV2422DS90UR124DS99R124Q-Q1DS90C124RXIN3Bit26B1B1N/AN/AN/ABit25B0B0Bit24G1G1Bit23G0G0Bit22R1R1Bit21R0R0RXIN2Bit20DEDEROUT20TXOUT2ROUT20Bit19VSVSROUT19ROUT19Bit18HSHSROUT18ROUT18Bit17B7B7ROUT17ROUT17Bit16B6B6ROUT16ROUT16Bit15B5B5ROUT15ROUT15Bit14B4B4ROUT14ROUT1441DS92LV0421,DS92LV0422www.
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SerializerAlternateColororDataMapping(continued)CHANNELLINKBITNUMBERRGB(LSBEXAMPLE)DS92LV2422DS90UR124DS99R124Q-Q1DS90C124(1)ThesebitsarenotsupportedbytheDS92LV0421.
RXIN1Bit13B3B3ROUT13TXOUT1ROUT13Bit12B2B2ROUT12ROUT12Bit11G7G7ROUT11ROUT11Bit10G6G6ROUT10ROUT10Bit9G5G5ROUT9ROUT9Bit8G4G4ROUT8ROUT8Bit7G3G3ROUT7ROUT7RXIN0Bit6G2G2ROUT6TXOUT0ROUT6Bit5R7R7ROUT5ROUT5Bit4R6R6ROUT4ROUT4Bit3R5R5ROUT3ROUT3Bit2R4R4ROUT2ROUT2Bit1R3R3ROUT1ROUT1Bit0R2R2ROUT0ROUT0N/AN/AN/AN/AROUT23(1)OS2(1)ROUT23(1)ROUT22(1)OS1(1)ROUT22(1)ROUT21(1)OS0(1)ROUT21(1)DS92LV0421SETTINGSMAPSEL=0CONFIG[1:0]=00CONFIG[1:0]=10CONFIG[1:0]=11Table15.
DeserializerAlternateColororDataMappingCHANNELLINKBITNUMBERRGB(LSBEXAMPLE)DS92LV2421DS90UR241DS99R421DS90C241TXOUT3Bit26B1B1N/AN/AN/ABit25B0B0Bit24G1G1Bit23G0G0Bit22R1R1Bit21R0R0TXOUT2Bit20DEDEDIN20RXIN2DIN20Bit19VSVSDIN19DIN19Bit18HSHSDIN18DIN18Bit17B7B7DIN17DIN17Bit16B6B6DIN16DIN16Bit15B5B5DIN15DIN15Bit14B4B4DIN14DIN14TXOUT1Bit13B3B3DIN13RXIN1DIN13Bit12B2B2DIN12DIN12Bit11G7G7DIN11DIN11Bit10G6G6DIN10DIN10Bit9G5G5DIN9DIN9Bit8G4G4DIN8DIN8Bit7G3G3DIN7DIN742DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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DeserializerAlternateColororDataMapping(continued)CHANNELLINKBITNUMBERRGB(LSBEXAMPLE)DS92LV2421DS90UR241DS99R421DS90C241(1)ThesebitsarenotsupportedbytheDS92LV0422.
TXOUT0Bit6G2G2DIN6RXIN0DIN6Bit5R7R7DIN5DIN5Bit4R6R6DIN4DIN4Bit3R5R5DIN3DIN3Bit2R4R4DIN2DIN2Bit1R3R3DIN1DIN1Bit0R2R2DIN0DIN0N/AN/AN/AN/ADIN23(1)OS2(1)DIN23(1)DIN22(1)OS1(1)DIN22(1)DIN21(1)OS0(1)DIN21(1)DS92LV0422SETTINGSMAPSEL=0CONFIG[1:0]=00CONFIG[1:0]=10CONFIG[1:0]=1143DS92LV0421,DS92LV0422www.
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2TypicalApplication8.
2.
1DS92LV0421TypicalConnectionFigure36showsatypicalapplicationoftheDS92LV0421serializerinpincontrolmodefora24-bitapplication.
TheLVDSinputsrequireexternal100-Ωdifferentialterminationresistors.
TheCMLoutputsrequire0.
1-F,AC-couplingcapacitorstotheline.
Thelinedriverincludesinternaltermination.
Bypasscapacitorsareplacednearthepowersupplypins.
Ataminimum,four0.
1-Fcapacitorsanda4.
7-Fcapacitormustbeusedforlocaldevicebypassing.
Ferritebeadsareplacedonthepowerlinesforeffectivenoisesuppression.
SystemGPO(GeneralPurposeOutput)signalscontrolthePDBandBISTENpins.
AdelaycapisplacedonthePDBsignaltodelaytheenablingofthedeviceuntilpowerisstable.
Theapplicationassumesconnectiontothecompaniondeserializer(DS92LV0422),andthereforetheconfigurationpinsCONFIG[1:0]arealsobothtiedlow.
Inthisexample,thecableislong,andthereforetheVODSELpinistiedhighandaDe-EmphasisvalueisselectedbytheresistorR1.
Theinterfacetothehostiswith1.
8-VLVCMOSlevels,thustheVDDIOpinisconnectedalsotothe1.
8-Vrail.
Theoptionalserialbuscontrolisnotusedinthisexample,thustheSCL,SDAandID[X]pinscanbeleftopen.
Figure36.
DS92LV0421TypicalConnectionDiagram44DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
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2.
1.
1DesignRequirementsForthisdesignexample,usetheparameterslistedinTable16astheinputparameters.
Table16.
DesignParametersPARAMETERVALUEVDDIO1.
8Vor3.
3VVDDL,VDDP,VDDHS,VDDTX,VDDRX1.
8VACCouplingCapacitorforDOUT±100nF8.
2.
1.
2DetailedDesignProcedureTheDOUT±outputsrequire100-nF,AC-couplingcapacitorstotheline.
Channel-Linkdatainputpairsrequireanexternal100-ΩterminationforstandardLVDSlevels.
Thepowersupplyfiltercapacitorsareplacednearthepowersupplypins.
Asmallercapacitancecapacitormustbeplacedclosertothepowersupplypins.
Addingaferritebeadisoptional,andifused,TIrecommendsusingaferritebeadwith1-kΩimpedanceandlowDCresistance(lessthan1Ω).
TheVODSELpinistiedtoVDDIOforlongcableapplications.
Thede-emphasispinmayconnectaresistortoGround(seeTable2).
ThePDBandBISTENpinsareassumedtobecontrolledbyamicroprocessor.
ThePDBmustremaininalowstateuntilallpowersupplyvoltagesreachthefinalvoltage.
TheCONFIG[1:0]pinsaresetdependingonoperatingmodesandbackwardcompatibility(seeTable10).
TheMAPSELpinsetsthemappingscheme(seeFigure23andFigure24).
TheSCL,SDA,andID[X]pinscanbeleftopenwhentheseserialbuscontrolpinsareunused.
TheRES[7:0]pinsandDAPmustbetiedtoGround.
8.
2.
1.
3ApplicationCurvesFigure37.
SerializerCMLOutputStream,RXCLKIN=65MHz,VODSEL=LFigure38.
SerializerCMLOutputStream,RXCLKIN=65MHz,VODSEL=H45DS92LV0421,DS92LV0422www.
ti.
comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated8.
2.
2DS92LV0422TypicalApplicationFigure39showsatypicalapplicationoftheDS92LV0422fora24-bitapplication.
TheCMLinputsrequire0.
1-F,AC-couplingcapacitorstotheline,andthereceiverprovidesinternaltermination.
Bypasscapacitorsareplacednearthepowersupplypins.
Ataminimum,four0.
1-Fcapacitorsanda4.
7-Fcapacitormustbeusedforlocaldevicebypassing.
Ferritebeadsareplacedonthepowerlinesforeffectivenoisesuppression.
SystemGPO(GeneralPurposeOutput)signalscontrolthePDBandBISTENpins.
AdelaycapisplacedonthePDBsignaltodelaytheenablingofthedeviceuntilpowerisstable.
Theapplicationassumesconnectiontothecompanionserializer(DS92LV0421),andthereforetheconfigurationpinsCONFIG[1:0]arealsobothtiedlow.
Theinterfacetothehostiswith1.
8-VLVCMOSlevels,thustheVDDIOpinisconnectedalsotothe1.
8-Vrail.
Theoptionalserialbuscontrolisnotusedinthisexample,thustheSCL,SDA,andID[X]pinscanbeleftopen.
Figure39.
DS92LV0422TypicalConnectionDiagram46DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
ti.
comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated8.
2.
2.
1DesignRequirementsForthisdesignexample,usetheparameterslistedinTable17astheinputparameters.
Table17.
DesignParametersPARAMETERVALUEVDDIO1.
8Vor3.
3VVDDL,VDDP,VDDSC,VDDA1.
8VVDDTX3.
3VACCouplingCapacitorforRIN±100nF8.
2.
2.
2DetailedDesignProcedureTheRIN±inputsrequire100-nF,AC-couplingcapacitorstotheline.
Thepowersupplyfiltercapacitorsareplacednearthepowersupplypins.
Asmallercapacitancecapacitormustbeplacedclosertothepowersupplypins.
Thedevicehasoneconfigurationpin(EQ)calledastrappin,whichispulleddownbydefault.
Forahighstate,usea10-kΩresistorpulluptoVDDIO.
ThePDBandBISTENpinsareassumedtobecontrolledbyamicroprocessor.
ThePDBmustremaininalowstateuntilallpowersupplyvoltagesreachthefinalvoltage.
TheSCL,SDA,andID[X]pinscanbeleftopenwhentheseserialbuscontrolpinsareunused.
TheRESpinandDAPmustbetiedtoGround.
8.
2.
2.
3ApplicationCurvesFigure40.
LVDSParallelOutputDataandClock,PRBS-7,TXCLKOUT=75MHz,VODSEL=LFigure41.
LVDSParallelOutputDataandClock,PRBS-7,TXCLKOUT=75MHz,VODSEL=H9PowerSupplyRecommendationsTheVDD(VDDnandVDDIO)supplyrampmustbefasterthan1.
5mswithamonotonicrise.
Ifslowerthan1.
5ms,acapacitoronthePDBpinisrequiredtoensurePDBarrivesafteralltheVDDsupplieshavesettledtotherecommendedoperatingvoltage.
WhenthePDBpinispulledtoVDDIO,TIrecommendsusinga10-kΩpullupanda22-FcaptoGroundtodelaythePDBinputsignal.
47DS92LV0421,DS92LV0422www.
ti.
comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated10Layout10.
1LayoutGuidelinesCircuitboardlayoutandstack-upfortheLVDSserializeranddeserializerdevicesmustbedesignedtoprovidelow-noisepowerfeedtothedevice.
Goodlayoutpracticealsoseparateshighfrequencyorhigh-levelinputsandoutputstominimizeunwantedstraynoisepickup,feedback,andinterference.
Powersystemperformancemaybegreatlyimprovedbyusingthindielectrics(2to4mils)forpowerorgroundsandwiches.
ThisarrangementprovidesplanecapacitanceforthePCBpowersystemwithlow-inductanceparasitics,whichhasprovenespeciallyeffectiveathighfrequenciesandmakesthevalueandplacementofexternalbypasscapacitorslesscritical.
ExternalbypasscapacitorsmustincludebothRFceramicandtantalumelectrolytictypes.
RFcapacitorsmayusevaluesintherangeof0.
01Fto0.
1F.
Tantalumcapacitorsmaybeinthe2.
2-Fto10-Frange.
Voltageratingofthetantalumcapacitorsmustbeatleast5xthepowersupplyvoltagebeingused.
Surface-mountcapacitorsarerecommendedduetotheirsmallerparasitics.
Whenusingmultiplecapacitorspersupplypin,placethesmallervalueclosertothepin.
Alargebulkcapacitorisrecommendedatthepointofpowerentry.
Thisistypicallyinthe50-Fto100-Frangeandsmoothslowfrequencyswitchingnoise.
TIrecommendsconnectingpowerandgroundpinsdirectlytothepowerandgroundplaneswithbypasscapacitorsconnectedtotheplane,withviasonbothendsofthecapacitor.
Connectingpowerorgroundpinstoanexternalbypasscapacitorincreasestheinductanceofthepath.
AsmallbodysizeX7Rchipcapacitor,suchas0603,isrecommendedforexternalbypass.
Itssmallbodysizereducestheparasiticinductanceofthecapacitor.
Theusermustpayattentiontotheresonancefrequencyoftheseexternalbypasscapacitors,usuallyintherangeof20to30MHz.
Toprovideeffectivebypassing,multiplecapacitorsareoftenusedtoachievelowimpedancebetweenthesupplyrailsoverthefrequencyofinterest.
Athighfrequency,itisalsoacommonpracticetousetwoviasfrompowerandgroundpinstotheplanes,reducingtheimpedanceathighfrequency.
Somedevicesprovideseparatepowerandgroundpinsfordifferentportionsofthecircuit.
Thisisdonetoisolateswitchingnoiseeffectsbetweendifferentsectionsofthecircuit.
SeparateplanesonthePCBaretypicallynotrequired.
Pindescriptiontablestypicallyprovideguidanceonwhichcircuitblocksareconnectedtowhichpowerpinpairs.
Insomecases,anexternalfiltermaybeusedtoprovidecleanpowertosensitivecircuitssuchasPLLs.
Useatleastafour-layerboardwithapowerandgroundplane.
PlaceLVCMOSsignalsawayfromtheCMLlinestopreventcouplingfromtheLVCMOSlinestotheCMLlines.
Closely-coupleddifferentiallinesof100ΩaretypicallyrecommendedforLVDSinterconnects.
Thecloselycoupledlineshelptoensurethatcouplednoiseappearsascommonmodeandthusisrejectedbythereceivers.
Thetightlycoupledlinesalsoradiateless.
10.
1.
1WQFN(LLP)StencilGuidelinesStencilparameterssuchasaperturearearatioandthefabricationprocesshaveasignificantimpactonpastedeposition.
InspectionofthestencilpriortoplacementoftheLLP(WQFN)packageishighlyrecommendedtoimproveboardassemblyyields.
Iftheviaandapertureopeningsarenotcarefullymonitored,thesoldermayflowunevenlythroughtheDAP.
StencilparametersforapertureopeningandvialocationsareshowninFigure42andFigure43.
Figure42.
NoPullbackLLP,SingleRowReferenceDiagram48DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
ti.
comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporatedLayoutGuidelines(continued)Table18.
NoPullbackLLPStencilApertureSummaryforDS92LV0421andDS92LV0422DEVICEPINCOUNTMKTDWGPCBI/OPADSIZE(mm)PCBPITCH(mm)PCBDAPSIZE(mm)STENCILI/OAPERTURE(mm)STENCILDAPAPERTURE(mm)NUMBEROFDAPAPERTUREOPENINGSGAPBETWEENDAPAPERTURE(DimAmm)DS92LV042136SQA36A0.
25*0.
60.
54.
6x4.
60.
25*0.
71.
0*1.
0160.
2DS92LV042248SQA48A0.
25*0.
60.
55.
1*5.
10.
25*0.
71.
1*1.
1160.
2Figure43.
48-PinWQFNStencilExampleofViaandOpeningPlacementInformationontheWQFNstylepackageisprovidedinLeadlessLeadframePackage(LLP)ApplicationReport(SNOA401).
10.
1.
2TransmissionMediaTheserializeranddeserializerchipsetisintendedtobeusedinapoint-to-pointconfigurationthroughaPCBtraceorthroughtwistedpaircable.
Theserializeranddeserializerprovideinternalterminationsforacleansignalingenvironment.
TheinterconnectforLVDSmustpresentadifferentialimpedanceof100Ω.
Usecablesandconnectorsthathavematcheddifferentialimpedancetominimizeimpedancediscontinuities.
Shieldedorun-shieldedcablesmaybeuseddependinguponthenoiseenvironmentandapplicationrequirements.
10.
1.
3LVDSInterconnectGuidelinesSeeAN-1108Channel-LinkPCBandInterconnectDesign-InGuidelines(SNLA008)andAN-905TransmissionLineRAPIDESIGNEROperationandApplicationsGuide(SNLA035)forfulldetails.
Use100-ΩcoupleddifferentialpairsUsetheS,2S,3Sruleinspacings–S=spacebetweenthepair–2S=spacebetweenpairs–3S=spacetoLVCMOSsignalMinimizethenumberofviasUsedifferentialconnectorswhenoperatingabove500-MbpslinespeedMaintainbalanceofthetracesMinimizeskewwithinthepairTerminateasclosetotheTxoutputsandRxinputsaspossibleAdditionalgeneralguidancecanbefoundintheLVDSOwner'sManual,availableinPDFformatfromtheTIwebsiteat:www.
ti.
com/lvds.
49DS92LV0421,DS92LV0422www.
ti.
comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated10.
2LayoutExampleThefollowingPCBlayoutexamplesarederivedfromthelayoutdesignoftheLV04EVK01EvaluationModule.
Thesegraphicsandadditionallayoutdescriptionareusedtodemonstratebothproperroutingandpropersoldertechniqueswhendesigningintheserializeranddeserializerpair.
Figure44.
DS92LV0421SerializerExampleLayoutFigure45.
DS92LV0422DeserializerExampleLayout50DS92LV0421,DS92LV0422SNLS325D–MAY2010–REVISEDDECEMBER2016www.
ti.
comProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated11DeviceandDocumentationSupport11.
1DeviceSupport11.
1.
1Third-PartyProductsDisclaimerTI'SPUBLICATIONOFINFORMATIONREGARDINGTHIRD-PARTYPRODUCTSORSERVICESDOESNOTCONSTITUTEANENDORSEMENTREGARDINGTHESUITABILITYOFSUCHPRODUCTSORSERVICESORAWARRANTY,REPRESENTATIONORENDORSEMENTOFSUCHPRODUCTSORSERVICES,EITHERALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE.
11.
1.
2DevelopmentSupportFordevelopmentalsupport,seethefollowing:OverviewforLVDS/M-LVDS/ECL/CML11.
2DocumentationSupport11.
2.
1RelatedDocumentationForrelateddocumentationseethefollowing:AbsoluteMaximumRatingsforSoldering(SNOA549)LeadlessLeadframePackage(LLP)ApplicationReport(SNOA401)AN-1108Channel-LinkPCBandInterconnectDesign-InGuidelines(SNLA008)AN-905TransmissionLineRAPIDESIGNEROperationandApplicationsGuide(SNLA035)11.
3RelatedLinksThetablebelowlistsquickaccesslinks.
Categoriesincludetechnicaldocuments,supportandcommunityresources,toolsandsoftware,andquickaccesstosampleorbuy.
Table19.
RelatedLinksPARTSPRODUCTFOLDERSAMPLE&BUYTECHNICALDOCUMENTSTOOLS&SOFTWARESUPPORT&COMMUNITYDS92LV0421ClickhereClickhereClickhereClickhereClickhereDS92LV0422ClickhereClickhereClickhereClickhereClickhere11.
4ReceivingNotificationofDocumentationUpdatesToreceivenotificationofdocumentationupdates,navigatetothedeviceproductfolderonti.
com.
Intheupperrightcorner,clickonAlertmetoregisterandreceiveaweeklydigestofanyproductinformationthathaschanged.
Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument.
11.
5CommunityResourcesThefollowinglinksconnecttoTIcommunityresources.
Linkedcontentsareprovided"ASIS"bytherespectivecontributors.
TheydonotconstituteTIspecificationsanddonotnecessarilyreflectTI'sviews;seeTI'sTermsofUse.
TIE2EOnlineCommunityTI'sEngineer-to-Engineer(E2E)Community.
Createdtofostercollaborationamongengineers.
Ate2e.
ti.
com,youcanaskquestions,shareknowledge,exploreideasandhelpsolveproblemswithfellowengineers.
DesignSupportTI'sDesignSupportQuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsandcontactinformationfortechnicalsupport.
11.
6TrademarksE2EisatrademarkofTexasInstruments.
Allothertrademarksarethepropertyoftheirrespectiveowners.
51DS92LV0421,DS92LV0422www.
ti.
comSNLS325D–MAY2010–REVISEDDECEMBER2016ProductFolderLinks:DS92LV0421DS92LV0422SubmitDocumentationFeedbackCopyright2010–2016,TexasInstrumentsIncorporated11.
7ElectrostaticDischargeCautionThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
11.
8GlossarySLYZ022—TIGlossary.
Thisglossarylistsandexplainsterms,acronyms,anddefinitions.
12Mechanical,Packaging,andOrderableInformationThefollowingpagesincludemechanical,packaging,andorderableinformation.
Thisinformationisthemostcurrentdataavailableforthedesignateddevices.
Thisdataissubjecttochangewithoutnoticeandrevisionofthisdocument.
Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation.
PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDS92LV0421SQ/NOPBACTIVEWQFNNJK361000RoHS&GreenSNLevel-3-260C-168HR-40to85LV0421DS92LV0421SQE/NOPBACTIVEWQFNNJK36250RoHS&GreenSNLevel-3-260C-168HR-40to85LV0421DS92LV0421SQX/NOPBACTIVEWQFNNJK362500RoHS&GreenSNLevel-3-260C-168HR-40to85LV0421DS92LV0422SQ/NOPBACTIVEWQFNRHS481000RoHS&GreenSNLevel-3-260C-168HR-40to85LV0422DS92LV0422SQE/NOPBACTIVEWQFNRHS48250RoHS&GreenSNLevel-3-260C-168HR-40to85LV0422DS92LV0422SQX/NOPBACTIVEWQFNRHS482500RoHS&GreenSNLevel-3-260C-168HR-40to85LV0422(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page2ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDS92LV0421SQ/NOPBWQFNNJK361000330.
016.
46.
36.
31.
512.
016.
0Q1DS92LV0421SQE/NOPBWQFNNJK36250178.
016.
46.
36.
31.
512.
016.
0Q1DS92LV0421SQX/NOPBWQFNNJK362500330.
016.
46.
36.
31.
512.
016.
0Q1DS92LV0422SQ/NOPBWQFNRHS481000330.
016.
47.
37.
31.
312.
016.
0Q1DS92LV0422SQE/NOPBWQFNRHS48250178.
016.
47.
37.
31.
312.
016.
0Q1DS92LV0422SQX/NOPBWQFNRHS482500330.
016.
47.
37.
31.
312.
016.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com20-Sep-2016PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DS92LV0421SQ/NOPBWQFNNJK361000367.
0367.
038.
0DS92LV0421SQE/NOPBWQFNNJK36250210.
0185.
035.
0DS92LV0421SQX/NOPBWQFNNJK362500367.
0367.
038.
0DS92LV0422SQ/NOPBWQFNRHS481000367.
0367.
038.
0DS92LV0422SQE/NOPBWQFNRHS48250210.
0185.
035.
0DS92LV0422SQX/NOPBWQFNRHS482500367.
0367.
038.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com20-Sep-2016PackMaterials-Page2www.
ti.
comPACKAGEOUTLINECSEETERMINALDETAIL48X0.
300.
185.
10.
148X0.
50.
30.
80.
7(A)TYP0.
050.
0044X0.
52X5.
52X5.
5A7.
156.
85B7.
156.
850.
300.
180.
50.
3(0.
2)WQFN-0.
8mmmaxheightRHS0048APLASTICQUADFLATPACK-NOLEAD4214990/B04/2018DIMAOPT1OPT2(0.
1)(0.
2)PIN1INDEXAREA0.
08CSEATINGPLANE112253613244837(OPTIONAL)PIN1ID0.
1CAB0.
05EXPOSEDTHERMALPAD49SYMMSYMMNOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
SCALE1.
800DETAILOPTIONALTERMINALTYPICALwww.
ti.
comEXAMPLEBOARDLAYOUT0.
07MINALLAROUND0.
07MAXALLAROUND48X(0.
25)48X(0.
6)(0.
2)TYPVIA44X(0.
5)(6.
8)(6.
8)(1.
25)TYP(5.
1)(R0.
05)TYP(1.
25)TYP(1.
05)TYP(1.
05)TYPWQFN-0.
8mmmaxheightRHS0048APLASTICQUADFLATPACK-NOLEAD4214990/B04/2018SYMM112132425363748SYMMLANDPATTERNEXAMPLEEXPOSEDMETALSHOWNSCALE:12XNOTES:(continued)4.
Thispackageisdesignedtobesolderedtoathermalpadontheboard.
Formoreinformation,seeTexasInstrumentsliteraturenumberSLUA271(www.
ti.
com/lit/slua271).
5.
Viasareoptionaldependingonapplication,refertodevicedatasheet.
Ifanyviasareimplemented,refertotheirlocationsshownonthisview.
Itisrecommendedthatviasunderpastebefilled,pluggedortented.
49SOLDERMASKOPENINGMETALUNDERSOLDERMASKSOLDERMASKDEFINEDEXPOSEDMETALMETALEDGESOLDERMASKOPENINGSOLDERMASKDETAILSNONSOLDERMASKDEFINED(PREFERRED)EXPOSEDMETALwww.
ti.
comEXAMPLESTENCILDESIGN48X(0.
6)48X(0.
25)44X(0.
5)(6.
8)(6.
8)16X(1.
05)(0.
625)TYP(R0.
05)TYP(1.
25)TYP(1.
25)TYP(0.
625)TYPWQFN-0.
8mmmaxheightRHS0048APLASTICQUADFLATPACK-NOLEAD4214990/B04/2018NOTES:(continued)6.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
49SYMMMETALTYPSOLDERPASTEEXAMPLEBASEDON0.
125mmTHICKSTENCILEXPOSEDPAD4968%PRINTEDSOLDERCOVERAGEBYAREAUNDERPACKAGESCALE:15XSYMM112132425363748MECHANICALDATANJK0036Awww.
ti.
comSQA36A(RevA)IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
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Youaresolelyresponsiblefor(1)selectingtheappropriateTIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicablestandards,andanyothersafety,security,orotherrequirements.
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