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3.
3V4K/8K/16K/32Kx8/9Dual-PortStaticRAMCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVCypressSemiconductorCorporation3901NorthFirstStreetSanJoseCA95134408-943-2600Document#:38-06051Rev.
*CRevisedJune6,2005FeaturesTrueDual-Portedmemorycellswhichallowsimultaneousaccessofthesamememorylocation4K/8K/16K/32Kx8organizations(CY7C0138AV/144AV/006AV/007AV)4K/8K/16K/32Kx9organizations(CY7C0139AV/145AV/016AV/017AV)0.
35-micronCMOSforoptimumspeed/powerHigh-speedaccess:20/25nsLowoperatingpower—Active:ICC=115mA(typical)—Standby:ISB3=10A(typical)FullyasynchronousoperationAutomaticpower-downExpandabledatabusto16/18bitsormoreusingMaster/SlavechipselectwhenusingmorethanonedeviceOn-chiparbitrationlogicSemaphoresincludedtopermitsoftwarehandshakingbetweenportsINTflagforport-to-portcommunicationPinselectforMasterorSlaveCommercialandIndustrialTemperatureRangesAvailablein68-pinPLCC(all)and64-pinTQFP(7C006AV&7C144AV)Pb-FreepackagesavailableForthemostrecentinformation,visittheCypresswebsiteatwww.
cypress.
comNotes:1.
I/O0–I/O7forx8devices;I/O0–I/O8forx9devices.
2.
A0–A11for4Kdevices;A0–A12for8Kdevices;A0–A13for16Kdevices;A0–A14for32Kdevices;3.
BUSYisanoutputinmastermodeandaninputinslavemode.
I/OControlAddressDecodeA0L–A11–14LCELOELR/WLBUSYLI/OControlInterruptSemaphoreArbitrationSEMLINTLM/SA0L–A11–14LTrueDual-PortedRAMArrayA0R–A11–14RCEROERR/WRBUSYRSEMRINTRAddressDecodeA0R–A11–14R[1][1][3][3]R/WLOELI/O0L–I/O7/8LCELR/WROERI/O0R–I/O7/8RCER12–158/912–158/912–1512–15[2][2][2][2]LogicBlockDiagramCY7C138AVCY7C139AVCY7C144AVCY7C145AVCY7C006AVCY7C016AVCY7C007AVCY7C017AV3.
3V4K/8K/16K/32Kx8/9Dual-PortStaticRAM[+]Feedbackwww.
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*CPage2of20PinConfigurationsNotes:4.
I/O8LontheCY7C139AV.
5.
I/O8RontheCY7C139AV.
6.
I/O8LontheCY7C145AV.
7.
I/O8RontheCY7C145AV.
10111213141516171819202122232467TopView68-PinPLCC60595857565554535251504948313233343536373839404142435432168666564636261AA4LA3LA2LA1LA0LINTLBUSYLGNDM/SBUSYRINTRA0RI/O2LI/O3LI/O4LI/O5LGNDI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RVCCA27282930987647464544A1RA2RA3RA4RI/O3RI/O4RI/O5RI/O6R25266L7LA8LA9LAA10L11LVCCNCNCCELSEMLR/WLOELNCI/OI/O1L0LAA6R7RA8RA9RA10RNCNCCERSEMRR/WROERI/O7RGNDA11RA5RA5LNCCY7C138AV(4Kx8)[5][4]NCNCCY7C139AV(4Kx9)10111213141516171819202122232467TopView68-PinPLCC60595857565554535251504948313233343536373839404142435432168666564636261AA4LA3LA2LA1LA0LINTLBUSYLGNDM/SBUSYRINTRA0RI/O2LI/O3LI/O4LI/O5LGNDI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RVCCA27282930987647464544A1RA2RA3RA4RI/O3RI/O4RI/O5RI/O6R25266L7LA8LA9LAA10L11LVCCNCNCCELSEMLR/WLOELNCI/OI/O1L0LAA6R7RA8RA9RA10RNCNCCERSEMRR/WROERI/O7RGNDA11RA5RA5LNCA12LA12RCY7C144AV(8Kx8)[7][6]CY7C145AV(8Kx9)[+]Feedbackwww.
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*CPage3of20Notes:8.
I/OforCY7C016AVandCY7C017AVonly.
NCforotherparts.
9.
AddresslineforCY7C007AVandCY7C017AVonly.
NCforotherparts.
PinConfigurations(continued)64-PinTQFPTopView12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916GNDOERI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RI/O6RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRI/O7RA5RA12RA11RA10RA9RA8RA7RA6RNCCERSEMRR/WRVCCOELI/O1LI/O0LA5LA12LA11LA10LA9LA8LA7LA6LNCCELSEMLR/WLCY7C144AV(8Kx8)TopView68-PinPLCCVCCOELI/O1LI/O0LA12LA11LA10LA9LA8LA7LA6LA13LCELSEMLR/WLI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRGNDOERI/O7RA5RA12RA11RA10RA9RA8RA7RA6RA13RCERSEMRR/WRA5LI/O8LI/O6RCY7C006AV(16Kx8)2425261011121314154847464544404127422843293031323368346735663665376438633962611659585756555453525150496098765432117181920212223[8]A14R[9]A14L[9]CY7C007AV(32Kx8)CY7C016AV(16Kx9)CY7C017AV(32Kx9)I/O8R[8][+]Feedbackwww.
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*CPage4of20PinConfigurations(continued)64-PinTQFPTopView12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916GNDOERI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RI/O6RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRI/O7RA5RA12RA11RA10RA9RA8RA7RA6RA13RCERSEMRR/WRVCCOELI/O1LI/O0LA5LA12LA11LA10LA9LA8LA7LA6LA13LCELSEMLR/WLCY7C006AV(16Kx8)SelectionGuideCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AV-20CY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AV-25MaximumAccessTime(ns)2025TypicalOperatingCurrent(mA)120115TypicalStandbyCurrentforISB1(mA)(BothPortsTTLlevel)3530TypicalStandbyCurrentforISB3(A)(BothPortsCMOSlevel)10A10A[+]Feedbackwww.
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*CPage5of20ArchitectureTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVconsistofanarrayof4K,8K,16K,and32Kwordsof8and9bitseachofdual-portRAMcells,I/Oandaddresslines,andcontrolsignals(CE,OE,R/W).
Thesecontrolpinspermitindependentaccessforreadsorwritestoanylocationinmemory.
Tohandlesimultaneouswrites/readstothesamelocation,aBUSYpinisprovidedoneachport.
Twointerrupt(INT)pinscanbeutilizedforport-to-portcommuni-cation.
Twosemaphore(SEM)controlpinsareusedforallocatingsharedresources.
WiththeM/Spin,thedevicecanfunctionasamaster(BUSYpinsareoutputs)orasaslave(BUSYpinsareinputs).
Thedevicealsohasanautomaticpower-downfeaturecontrolledbyCE.
Eachportisprovidedwithitsownoutputenablecontrol(OE),whichallowsdatatobereadfromthedevice.
FunctionalDescriptionTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVarelow-powerCMOS4K,8K,16K,and32Kx8/9dual-portstaticRAMs.
Variousarbitrationschemesareincludedonthedevicestohandlesituationswhenmultipleprocessorsaccessthesamepieceofdata.
Twoportsareprovided,permittingindependent,asynchronousaccessforreadsandwritestoanylocationinmemory.
Thedevicescanbeutilizedasstandalone8/9-bitdual-portstaticRAMsormultipledevicescanbecombinedinordertofunctionasa16/18-bitorwidermaster/slavedual-portstaticRAM.
AnM/Spinisprovidedforimplementing16/18-bitorwidermemoryapplicationswithouttheneedforseparatemasterandslavedevicesoradditionaldiscretelogic.
Applicationareasincludeinterprocessor/multiprocessordesigns,communicationsstatusbuffering,anddual-portvideo/graphicsmemory.
Eachporthasindependentcontrolpins:ChipEnable(CE),ReadorWriteEnable(R/W),andOutputEnable(OE).
Twoflagsareprovidedoneachport(BUSYandINT).
BUSYsignalsthattheportistryingtoaccessthesamelocationcurrentlybeingaccessedbytheotherport.
TheInterruptflag(INT)permitscommunicationbetweenportsorsystemsbymeansofamailbox.
Thesemaphoresareusedtopassaflag,ortoken,fromoneporttotheothertoindicatethatasharedresourceisinuse.
Thesemaphorelogiciscomprisedofeightsharedlatches.
Onlyonesidecancontrolthelatch(semaphore)atanytime.
Controlofasemaphoreindicatesthatasharedresourceisinuse.
Anautomaticpower-downfeatureiscontrolledindependentlyoneachportbyaChipSelect(CE)pin.
ReadandWriteOperationsWhenwritingdatamustbesetupforadurationoftSDbeforetherisingedgeofR/Winordertoguaranteeavalidwrite.
AwriteoperationiscontrolledbyeithertheR/Wpin(seeWriteCycleNo.
1waveform)ortheCEpin(seeWriteCycleNo.
2waveform).
Requiredinputsfornon-contentionoperationsaresummarizedinTable1.
Ifalocationisbeingwrittentobyoneportandtheoppositeportattemptstoreadthatlocation,aport-to-portflowthroughdelaymustoccurbeforethedataisreadontheoutput;otherwisethedatareadisnotdeterministic.
DatawillbevalidontheporttDDDafterthedataispresentedontheotherport.
Whenreadingthedevice,theusermustassertboththeOEandCEpins.
DatawillbeavailabletACEafterCEortDOEafterOEisasserted.
Iftheuserwishestoaccessasemaphoreflag,thentheSEMpinmustbeassertedinsteadoftheCEpinandOEmustalsobeasserted.
InterruptsTheuppertwomemorylocationsmaybeusedformessagepassing.
Thehighestmemorylocation(FFFfortheCY7C138AV/9AV,1FFFfortheCY7C144AV/5AV,3FFFfortheCY7C006AV/16AV,7FFFfortheCY7C007AV/17AV)isthemailboxfortherightportandthesecond-highestmemorylocation(FFEfortheCY7C138AV/9AV,1FFEfortheCY7C144AV/5AV,3FFEfortheCY7C006AV/16AV,7FFEfortheCY7C007AV/17AV)isthemailboxfortheleftport.
Whenoneportwritestotheotherport'smailbox,aninterruptisgeneratedtotheowner.
Theinterruptisresetwhentheownerreadsthecontentsofthemailbox.
Themessageisuserdefined.
Eachportcanreadtheotherport'smailboxwithoutresettingtheinterrupt.
Theactivestateofthebusysignal(toaport)PinDefinitionsLeftPortRightPortDescriptionCELCERChipEnableR/WLR/WRRead/WriteEnableOELOEROutputEnableA0L–A14LA0R–A14RAddress(A0–A11for4Kdevices;A0–A12for8Kdevices;A0–A13for16Kdevices;A0–A14for32K)I/O0L–I/O8LI/O0R–I/O8RDataBusInput/Output(I/O0–I/O7forx8devicesandI/O0–I/O8forx9)SEMLSEMRSemaphoreEnableINTLINTRInterruptFlagBUSYLBUSYRBusyFlagM/SMasterorSlaveSelectVCCPowerGNDGroundNCNoConnect[+]Feedbackwww.
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*CPage6of20preventstheportfromsettingtheinterrupttothewinningport.
Also,anactivebusytoaportpreventsthatportfromreadingitsownmailboxand,thus,resettingtheinterrupttoit.
Ifanapplicationdoesnotrequiremessagepassing,donotconnecttheinterruptpintotheprocessor'sinterruptrequestinputpin.
TheoperationoftheinterruptsandtheirinteractionwithBusyaresummarizedinTable2.
BusyTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVprovideon-chiparbitrationtoresolvesimultaneousmemorylocationaccess(contention).
Ifbothports'CEsareassertedandanaddressmatchoccurswithintPSofeachother,thebusylogicwilldeterminewhichporthasaccess.
IftPSisviolated,oneportwilldefinitelygainpermissiontothelocation,butitisnotpredictablewhichportwillgetthatpermission.
BUSYwillbeassertedtBLAafteranaddressmatchortBLCafterCEistakenLOW.
Master/SlaveAnM/Spinisprovidedinordertoexpandthewordwidthbyconfiguringthedeviceaseitheramasteroraslave.
TheBUSYoutputofthemasterisconnectedtotheBUSYinputoftheslave.
Thiswillallowthedevicetointerfacetoamasterdevicewithnoexternalcomponents.
WritingtoslavedevicesmustbedelayeduntilaftertheBUSYinputhassettled(tBLCortBLA),otherwise,theslavechipmaybeginawritecycleduringacontentionsituation.
WhentiedHIGH,theM/Spinallowsthedevicetobeusedasamasterand,therefore,theBUSYlineisanoutput.
BUSYcanthenbeusedtosendthearbitrationoutcometoaslave.
SemaphoreOperationTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVprovideeightsemaphorelatches,whichareseparatefromthedual-portmemorylocations.
Semaphoresareusedtoreserveresourcesthataresharedbetweenthetwoports.
Thestateofthesemaphoreindicatesthataresourceisinuse.
Forexample,iftheleftportwantstorequestagivenresource,itsetsalatchbywritingazerotoasemaphorelocation.
Theleftportthenverifiesitssuccessinsettingthelatchbyreadingit.
Afterwritingtothesemaphore,SEMorOEmustbedeassertedfortSOPbeforeattemptingtoreadthesemaphore.
ThesemaphorevaluewillbeavailabletSWRD+tDOEaftertherisingedgeofthesemaphorewrite.
Iftheleftportwassuccessful(readsazero),itassumescontrolofthesharedresource,otherwise(readsaone)itassumestherightporthascontrolandcontinuestopollthesemaphore.
Whentherightsidehasrelinquishedcontrolofthesemaphore(bywritingaone),theleftsidewillsucceedingainingcontrolofthesemaphore.
Iftheleftsidenolongerrequiresthesemaphore,aoneiswrittentocancelitsrequest.
SemaphoresareaccessedbyassertingSEMLOW.
TheSEMpinfunctionsasachipselectforthesemaphorelatches(CEmustremainHIGHduringSEMLOW).
A0–2representsthesemaphoreaddress.
OEandR/Wareusedinthesamemannerasanormalmemoryaccess.
Whenwritingorreadingasemaphore,theotheraddresspinshavenoeffect.
Whenwritingtothesemaphore,onlyI/O0isused.
Ifazeroiswrittentotheleftportofanavailablesemaphore,aonewillappearatthesamesemaphoreaddressontherightport.
Thatsemaphorecannowonlybemodifiedbythesideshowingzero(theleftportinthiscase).
Iftheleftportnowrelinquishescontrolbywritingaonetothesemaphore,thesemaphorewillbesettooneforbothsides.
However,iftherightporthadrequestedthesemaphore(writtenazero)whiletheleftporthadcontrol,therightportwouldimmediatelyownthesemaphoreassoonastheleftportreleasedit.
Table3showssamplesemaphoreoperations.
Whenreadingasemaphore,alldatalinesoutputthesemaphorevalue.
Thereadvalueislatchedinanoutputregistertopreventthesemaphorefromchangingstateduringawritefromtheotherport.
IfbothportsattempttoaccessthesemaphorewithintSPSofeachother,thesemaphorewilldefinitelybeobtainedbyonesideortheother,butthereisnoguaranteewhichsidewillcontrolthesemaphore.
[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage7of20MaximumRatings[10](Abovewhichtheusefullifemaybeimpaired.
Foruserguide-lines,nottested.
)StorageTemperature65°Cto+150°CAmbientTemperaturewithPowerApplied.
55°Cto+125°CSupplyVoltagetoGroundPotential.
0.
5Vto+4.
6VDCVoltageAppliedtoOutputsinHighZState.
0.
5VtoVCC+0.
5VDCInputVoltage[11]0.
5VtoVCC+0.
5VOutputCurrentintoOutputs(LOW)20mAStaticDischargeVoltage.
2001VLatch-UpCurrent.
200mA.
OperatingRangeRangeAmbientTemperatureVCCCommercial0°Cto+70°C3.
3V±300mVIndustrial[12]–40°Cto+85°C3.
3V±300mVElectricalCharacteristicsOvertheOperatingRangeParameterDescriptionCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AV-20-25UnitMin.
Typ.
Max.
Min.
Typ.
Max.
VOHOutputHIGHVoltage(VCC=3.
3V)2.
42.
4VVOLOutputLOWVoltage0.
40.
4VVIHInputHIGHVoltage2.
02.
0VVILInputLOWVoltage0.
80.
8VIOZOutputLeakageCurrent–1010–1010AICCOperatingCurrent(VCC=Max.
,IOUT=0mA)OutputsDisabledCom'l.
120175115165mAInd.
[12]140195mAISB1StandbyCurrent(BothPortsTTLLevel)CEL&CER≥VIH,f=fMAX[13]Com'l.
35453040mAInd.
[12]4555mAISB2StandbyCurrent(OnePortTTLLevel)CEL|CER≥VIH,f=fMAX[13]Com'l.
751106595mAInd.
[12]85130mAISB3StandbyCurrent(BothPortsCMOSLevel)CEL&CER≥VCC–0.
2V,f=0[13]Com'l.
1050010500AInd.
[12]10500AISB4StandbyCurrent(OnePortCMOSLevel)CEL|CER≥VIH,f=fMAX[13]Com'l.
70956080mAInd.
[12]80105mACapacitance[14]ParameterDescriptionTestConditionsMax.
UnitCINInputCapacitanceTA=25°C,f=1MHz,VCC=3.
3V10pFCOUTOutputCapacitance10pFNotes:10.
TheVoltageonanyinputorI/Opincannotexceedthepowerpinduringpower-up.
11.
PulsewidthtRCafterVCCreachestheminimumoperatingvoltage(3.
0volts).
Notes:20.
Forinformationonport-to-portdelaythroughRAMcellsfromwritingporttoreadingport,refertoReadTimingwithBusywaveform.
21.
TestconditionsusedareLoad2.
22.
tBDDisacalculatedparameterandisthegreateroftWDD–tPWE(actual)ortDDD–tSD(actual).
23.
CE=VCC,Vin=GNDtoVCC,TA=25°C.
Thisparameterisguaranteedbutnottested.
tHDDataHoldFromWriteEnd00nstHZWE[18,19]R/WLOWtoHighZ1215nstLZWE[18,19]R/WHIGHtoLowZ33nstWDD[20]WritePulsetoDataDelay4050nstDDD[20]WriteDataValidtoReadDataValid3035nsBUSYTIMING[21]tBLABUSYLOWfromAddressMatch2020nstBHABUSYHIGHfromAddressMismatch2020nstBLCBUSYLOWfromCELOW2020nstBHCBUSYHIGHfromCEHIGH1617nstPSPortSet-UpforPriority55nstWBR/WHIGHafterBUSY(Slave)00nstWHR/WHIGHafterBUSYHIGH(Slave)1517nstBDD[22]BUSYHIGHtoDataValid2025nsINTERRUPTTIMING[21]tINSINTSetTime2020nstINRINTResetTime2020nsSEMAPHORETIMINGtSOPSEMFlagUpdatePulse(OEorSEM)1012nstSWRDSEMFlagWritetoReadTime55nstSPSSEMFlagContentionWindow55nstSAASEMAddressAccessTime2025nsSwitchingCharacteristicsOvertheOperatingRange[15](continued)ParameterDescriptionCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVUnit-20-25Min.
Max.
Min.
Max.
TimingParameterTestConditions[23]Max.
UnitICCDR1@VCCDR=2V50ADataRetentionMode3.
0V3.
0VVCC>2.
0VVCCtoVCC–0.
2VVCCCEtRCVIH[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage10of20SwitchingWaveformsNotes:24.
R/WisHIGHforreadcycles.
25.
DeviceiscontinuouslyselectedCE=VIL.
Thiswaveformcannotbeusedforsemaphorereads.
26.
OE=VIL.
27.
AddressvalidpriortoorcoincidentwithCEtransitionLOW.
28.
ToaccessRAM,CE=VIL,SEM=VIH.
Toaccesssemaphore,CE=VIH,SEM=VIL.
tRCtAAtOHADATAVALIDPREVIOUSDATAVALIDDATAOUTADDRESStOHAReadCycleNo.
1(EitherPortAddressAccess)[24,25,26]tACEtLZOEtDOEtHZOEtHZCEDATAVALIDtLZCEtPUtPDISBICCDATAOUTOECECURRENTReadCycleNo.
2(EitherPortCE/OEAccess)[24,27,28]DATAOUTtRCADDRESStAAtOHACEtLZCEtABEtHZCEtACEtLZCEReadCycleNo.
3(EitherPort)[24,26,27,28][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage11of20Notes:29.
R/WmustbeHIGHduringalladdresstransitions.
30.
Awriteoccursduringtheoverlap(tSCEortPWE)ofaLOWCEorSEM.
31.
tHAismeasuredfromtheearlierofCEorR/Wor(SEMorR/W)goingHIGHattheendofwritecycle.
32.
IfOEisLOWduringaR/Wcontrolledwritecycle,thewritepulsewidthmustbethelargeroftPWEor(tHZWE+tSD)toallowtheI/OdriverstoturnoffanddatatobeplacedonthebusfortherequiredtSD.
IfOEisHIGHduringanR/Wcontrolledwritecycle,thisrequirementdoesnotapplyandthewritepulsecanbeasshortasthespecifiedtPWE.
33.
Transitionismeasured±500mVfromsteadystatewitha5-pFload(includingscopeandjig).
Thisparameterissampledandnot100%tested.
34.
ToaccessRAM,CE=VIL,SEM=VIH.
35.
Duringthisperiod,theI/Opinsareintheoutputstate,andinputsignalsmustnotbeapplied.
36.
IftheCEorSEMLOWtransitionoccurssimultaneouslywithoraftertheR/WLOWtransition,theoutputsremaininthehigh-impedancestate.
SwitchingWaveforms(continued)tAWtWCtPWEtHDtSDtHACER/WOEDATAOUTDATAINADDRESStHZOEtSAtHZWEtLZWEWriteCycleNo.
1:R/WControlledTiming[29,30,31,32][33][33][32][34]Note35Note35tAWtWCtSCEtHDtSDtHACER/WDATAINADDRESStSAWriteCycleNo.
2:CEControlledTiming[29,30,31,36][34][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage12of20Notes:37.
CE=HIGHforthedurationoftheabovetiming(bothwriteandreadcycle).
38.
I/O0R=I/O0L=LOW(requestsemaphore);CER=CEL=HIGH.
39.
Semaphoresarereset(availabletobothports)atcyclestart.
40.
IftSPSisviolated,thesemaphorewilldefinitelybeobtainedbyonesideortheother,butwhichsidewillgetthesemaphoreisunpredictable.
SwitchingWaveforms(continued)tSOPtSAAVALIDADRESSVALIDADRESStHDDATAINVALIDDATAOUTVALIDtOHAtAWtHAtACEtSOPtSCEtSDtSAtPWEtSWRDtDOEWRITECYCLEREADCYCLEOER/WI/O0SEMA0–A2SemaphoreReadAfterWriteTiming,EitherSide[37]MATCHtSPSA0L–A2LMATCHR/WLSEMLA0R–A2RR/WRSEMRTimingDiagramofSemaphoreContention[38,39,40][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage13of20Note:41.
CEL=CER=LOW.
SwitchingWaveforms(continued)VALIDtDDDtWDDMATCHMATCHR/WRDATAINRDATAOUTLtWCADDRESSRtPWEVALIDtSDtHDADDRESSLtPStBLAtBHAtBDDBUSYLTimingDiagramofReadwithBUSY(M/S=HIGH)[41]tPWER/WBUSYtWBtWHWriteTimingwithBusyInput(M/S=LOW)[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage14of20Note:42.
IftPSisviolated,thebusysignalwillbeassertedononesideortheother,butthereisnoguaranteetowhichsideBUSYwillbeasserted.
SwitchingWaveforms(continued)ADDRESSMATCHtPStBLCtBHCADDRESSMATCHtPStBLCtBHCCERValidFirst:ADDRESSL,RBUSYRCELCERBUSYLCERCELADDRESSL,RBusyTimingDiagramNo.
1(CEArbitration)[42]CELValidFirst:ADDRESSMATCHtPSADDRESSLBUSYRADDRESSMISMATCHtRCortWCtBLAtBHAADDRESSRADDRESSMATCHADDRESSMISMATCHtPSADDRESSLBUSYLtRCortWCtBLAtBHAADDRESSRRightAddressValidFirst:BusyTimingDiagramNo.
2(AddressArbitration)[42]LeftAddressValidFirst[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage15of20Notes:43.
tHAdependsonwhichenablepin(CELorR/WL)isdeassertedfirst.
44.
tINSortINRdependsonwhichenablepin(CELorR/WL)isassertedlast.
SwitchingWaveforms(continued)InterruptTimingDiagramsWRITEFFF(SeeFunctionalDescription)tWCRightSideClearsINTR:tHAREADFFFtRCtINRWRITEFFE(SeeFunctionalDescription)tWCRightSideSetsINTL:LeftSideSetsINTR:LeftSideClearsINTL:READFFEtINRtRCADDRESSRCELR/WLINTLOELADDRESSRR/WRCERINTLADDRESSRCERR/WRINTROERADDRESSLR/WLCELINTRtINStHAtINS(SeeFunctionalDescription)(SeeFunctionalDescription)[43][44][44][44][43][44][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage16of20Table1.
Non-ContendingRead/WriteInputsOutputsCER/WOESEMI/O0–I/O8OperationHXXHHighZDeselected:Power-DownHHLLDataOutReadDatainSemaphoreFlagXXHXHighZI/OLinesDisabledHXLDataInWriteintoSemaphoreFlagLHLHDataOutReadLLXHDataInWriteLXXLNotAllowedTable2.
InterruptOperationExample(assumesBUSYL=BUSYR=HIGH)LeftPortRightPortFunctionR/WLCELOELA0L–14LINTLR/WRCEROERA0R–14RINTRSetRightINTRFlagLLXFFF[45]XXXXXL[46]ResetRightINTRFlagXXXXXXLLFFF[45]H[47]SetLeftINTLFlagXXXXL[47]LLX1FFE[45]XResetLeftINTLFlagXLL1FFE[45]H[46]XXXXXTable3.
SemaphoreOperationExampleFunctionI/O0–I/O8LeftI/O0–I/O8RightStatusNoaction11SemaphorefreeLeftportwrites0tosemaphore01LeftPorthassemaphoretokenRightportwrites0tosemaphore01Nochange.
RightsidehasnowriteaccesstosemaphoreLeftportwrites1tosemaphore10RightportobtainssemaphoretokenLeftportwrites0tosemaphore10Nochange.
LeftporthasnowriteaccesstosemaphoreRightportwrites1tosemaphore01LeftportobtainssemaphoretokenLeftportwrites1tosemaphore11SemaphorefreeRightportwrites0tosemaphore10RightporthassemaphoretokenRightportwrites1tosemaphore11SemaphorefreeLeftportwrites0tosemaphore01LeftporthassemaphoretokenLeftportwrites1tosemaphore11SemaphorefreeNote:45.
SeeFunctionalDescriptionforspecificaddressesbydevicepartnumber.
46.
IfBUSYL=L,thennochange.
47.
IfBUSYR=L,thennochange.
[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage17of20OrderingInformationPackageAvailabilityGuideDeviceOrganization68-PinPLCC64-PinTQFPCY7C138AV4Kx8XCY7C139AV4Kx9XCY7C144AV8Kx8XXCY7C145AV8Kx9XCY7C006AV16Kx8XXCY7C016AV16Kx9XCY7C007AV32Kx8XCY7C017AV32Kx9X4Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C138AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C138AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial4Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C139AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C139AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial8Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C144AV–20ACA6564-PinThinQuadFlatPackCommercialCY7C144AV–20JCJ8168-PinPlasticLeadedChipCarrier25CY7C144AV–25ACA6564-PinThinQuadFlatPackCommercialCY7C144AV-25AXCA6564-PinPb-FreeThinQuadFlatPackCY7C144AV–25JCJ8168-PinPlasticLeadedChipCarrierCY7C144AV-25JXCJ8168-PinPb-FreePlasticLeadedChipCarrier8Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C145AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C145AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial16Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C006AV–20ACA6564-PinThinQuadFlatPackCommercialCY7C006AV–20JCJ8168-PinPlasticLeadedChipCarrier25CY7C006AV–25ACA6564-PinThinQuadFlatPackCommercialCY7C006AV-25AXCA6564-PinPb-FreeThinQuadFlatPackCY7C006AV–25JCJ8168-PinPlasticLeadedChipCarrier[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage18of20OrderingInformation(continued)16Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C016AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C016AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial32Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C007AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercialCY7C007AV–20JIJ8168-PinPlasticLeadedChipCarrierIndustrial25CY7C007AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial32Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C017AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercialCY7C017AV–20JIJ8168-PinPlasticLeadedChipCarrierIndustrial25CY7C017AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage19of20CypressSemiconductorCorporation,2005.
Theinformationcontainedhereinissubjecttochangewithoutnotice.
CypressSemiconductorCorporationassumesnoresponsibilityfortheuseofanycircuitryotherthancircuitryembodiedinaCypressproduct.
Nordoesitconveyorimplyanylicenseunderpatentorotherrights.
Cypressproductsarenotwarrantednorintendedtobeusedformedical,lifesupport,lifesaving,criticalcontrolorsafetyapplications,unlesspursuanttoanexpresswrittenagreementwithCypress.
Furthermore,Cypressdoesnotauthorizeitsproductsforuseascriticalcomponentsinlife-supportsystemswhereamalfunctionorfailuremayreasonablybeexpectedtoresultinsignificantinjurytotheuser.
TheinclusionofCypressproductsinlife-supportsystemsapplicationimpliesthatthemanufacturerassumesallriskofsuchuseandindoingsoindemnifiesCypressagainstallcharges.
Allproductsandcompanynamesmentionedinthisdocumentmaybethetrademarksoftheirrespectiveholders.
PackageDiagrams64-LeadThinPlasticQuadFlatPack(14x14x1.
4mm)A6551-85046-*B64-LeadPb-FreeThinPlasticQuadFlatPack(14x14x1.
4mm)A6568-LeadPlasticLeadedChipCarrierJ8151-85005-*A68-LeadPb-FreePlasticLeadedChipCarrierJ81[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage20of20DocumentHistoryPageDocumentTitle:CY7C138AV/144AV/006AV/CY7C139AV/145AV/016AV/CY7C007AV/017AV3.
3V4K/8K/16K/32Kx8/9DualPortSRAMDocumentNumber:38-06051REV.
ECNNO.
IssueDateOrig.
ofChangeDescriptionofChange**11020312/02/01SZVChangefromSpecnumber:38-00837to38-06051*A12230112/27/02RBIPoweruprequirementsaddedtoMaximumRatingsInformation*B237623SeeECNYDTRemovedcrossinformationfromfeaturessection*C373615SeeECNPCXAddedPb-FreeLogoAddedPb-Freepartstoorderinginformation:CY7C144AV-25AXC,CY7C144AV-25JXC,CY7C006AV-25AXC[+]Feedback
3V4K/8K/16K/32Kx8/9Dual-PortStaticRAMCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVCypressSemiconductorCorporation3901NorthFirstStreetSanJoseCA95134408-943-2600Document#:38-06051Rev.
*CRevisedJune6,2005FeaturesTrueDual-Portedmemorycellswhichallowsimultaneousaccessofthesamememorylocation4K/8K/16K/32Kx8organizations(CY7C0138AV/144AV/006AV/007AV)4K/8K/16K/32Kx9organizations(CY7C0139AV/145AV/016AV/017AV)0.
35-micronCMOSforoptimumspeed/powerHigh-speedaccess:20/25nsLowoperatingpower—Active:ICC=115mA(typical)—Standby:ISB3=10A(typical)FullyasynchronousoperationAutomaticpower-downExpandabledatabusto16/18bitsormoreusingMaster/SlavechipselectwhenusingmorethanonedeviceOn-chiparbitrationlogicSemaphoresincludedtopermitsoftwarehandshakingbetweenportsINTflagforport-to-portcommunicationPinselectforMasterorSlaveCommercialandIndustrialTemperatureRangesAvailablein68-pinPLCC(all)and64-pinTQFP(7C006AV&7C144AV)Pb-FreepackagesavailableForthemostrecentinformation,visittheCypresswebsiteatwww.
cypress.
comNotes:1.
I/O0–I/O7forx8devices;I/O0–I/O8forx9devices.
2.
A0–A11for4Kdevices;A0–A12for8Kdevices;A0–A13for16Kdevices;A0–A14for32Kdevices;3.
BUSYisanoutputinmastermodeandaninputinslavemode.
I/OControlAddressDecodeA0L–A11–14LCELOELR/WLBUSYLI/OControlInterruptSemaphoreArbitrationSEMLINTLM/SA0L–A11–14LTrueDual-PortedRAMArrayA0R–A11–14RCEROERR/WRBUSYRSEMRINTRAddressDecodeA0R–A11–14R[1][1][3][3]R/WLOELI/O0L–I/O7/8LCELR/WROERI/O0R–I/O7/8RCER12–158/912–158/912–1512–15[2][2][2][2]LogicBlockDiagramCY7C138AVCY7C139AVCY7C144AVCY7C145AVCY7C006AVCY7C016AVCY7C007AVCY7C017AV3.
3V4K/8K/16K/32Kx8/9Dual-PortStaticRAM[+]Feedbackwww.
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*CPage2of20PinConfigurationsNotes:4.
I/O8LontheCY7C139AV.
5.
I/O8RontheCY7C139AV.
6.
I/O8LontheCY7C145AV.
7.
I/O8RontheCY7C145AV.
10111213141516171819202122232467TopView68-PinPLCC60595857565554535251504948313233343536373839404142435432168666564636261AA4LA3LA2LA1LA0LINTLBUSYLGNDM/SBUSYRINTRA0RI/O2LI/O3LI/O4LI/O5LGNDI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RVCCA27282930987647464544A1RA2RA3RA4RI/O3RI/O4RI/O5RI/O6R25266L7LA8LA9LAA10L11LVCCNCNCCELSEMLR/WLOELNCI/OI/O1L0LAA6R7RA8RA9RA10RNCNCCERSEMRR/WROERI/O7RGNDA11RA5RA5LNCCY7C138AV(4Kx8)[5][4]NCNCCY7C139AV(4Kx9)10111213141516171819202122232467TopView68-PinPLCC60595857565554535251504948313233343536373839404142435432168666564636261AA4LA3LA2LA1LA0LINTLBUSYLGNDM/SBUSYRINTRA0RI/O2LI/O3LI/O4LI/O5LGNDI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RVCCA27282930987647464544A1RA2RA3RA4RI/O3RI/O4RI/O5RI/O6R25266L7LA8LA9LAA10L11LVCCNCNCCELSEMLR/WLOELNCI/OI/O1L0LAA6R7RA8RA9RA10RNCNCCERSEMRR/WROERI/O7RGNDA11RA5RA5LNCA12LA12RCY7C144AV(8Kx8)[7][6]CY7C145AV(8Kx9)[+]Feedbackwww.
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*CPage3of20Notes:8.
I/OforCY7C016AVandCY7C017AVonly.
NCforotherparts.
9.
AddresslineforCY7C007AVandCY7C017AVonly.
NCforotherparts.
PinConfigurations(continued)64-PinTQFPTopView12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916GNDOERI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RI/O6RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRI/O7RA5RA12RA11RA10RA9RA8RA7RA6RNCCERSEMRR/WRVCCOELI/O1LI/O0LA5LA12LA11LA10LA9LA8LA7LA6LNCCELSEMLR/WLCY7C144AV(8Kx8)TopView68-PinPLCCVCCOELI/O1LI/O0LA12LA11LA10LA9LA8LA7LA6LA13LCELSEMLR/WLI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRGNDOERI/O7RA5RA12RA11RA10RA9RA8RA7RA6RA13RCERSEMRR/WRA5LI/O8LI/O6RCY7C006AV(16Kx8)2425261011121314154847464544404127422843293031323368346735663665376438633962611659585756555453525150496098765432117181920212223[8]A14R[9]A14L[9]CY7C007AV(32Kx8)CY7C016AV(16Kx9)CY7C017AV(32Kx9)I/O8R[8][+]Feedbackwww.
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*CPage4of20PinConfigurations(continued)64-PinTQFPTopView12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916GNDOERI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RI/O6RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRI/O7RA5RA12RA11RA10RA9RA8RA7RA6RA13RCERSEMRR/WRVCCOELI/O1LI/O0LA5LA12LA11LA10LA9LA8LA7LA6LA13LCELSEMLR/WLCY7C006AV(16Kx8)SelectionGuideCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AV-20CY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AV-25MaximumAccessTime(ns)2025TypicalOperatingCurrent(mA)120115TypicalStandbyCurrentforISB1(mA)(BothPortsTTLlevel)3530TypicalStandbyCurrentforISB3(A)(BothPortsCMOSlevel)10A10A[+]Feedbackwww.
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*CPage5of20ArchitectureTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVconsistofanarrayof4K,8K,16K,and32Kwordsof8and9bitseachofdual-portRAMcells,I/Oandaddresslines,andcontrolsignals(CE,OE,R/W).
Thesecontrolpinspermitindependentaccessforreadsorwritestoanylocationinmemory.
Tohandlesimultaneouswrites/readstothesamelocation,aBUSYpinisprovidedoneachport.
Twointerrupt(INT)pinscanbeutilizedforport-to-portcommuni-cation.
Twosemaphore(SEM)controlpinsareusedforallocatingsharedresources.
WiththeM/Spin,thedevicecanfunctionasamaster(BUSYpinsareoutputs)orasaslave(BUSYpinsareinputs).
Thedevicealsohasanautomaticpower-downfeaturecontrolledbyCE.
Eachportisprovidedwithitsownoutputenablecontrol(OE),whichallowsdatatobereadfromthedevice.
FunctionalDescriptionTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVarelow-powerCMOS4K,8K,16K,and32Kx8/9dual-portstaticRAMs.
Variousarbitrationschemesareincludedonthedevicestohandlesituationswhenmultipleprocessorsaccessthesamepieceofdata.
Twoportsareprovided,permittingindependent,asynchronousaccessforreadsandwritestoanylocationinmemory.
Thedevicescanbeutilizedasstandalone8/9-bitdual-portstaticRAMsormultipledevicescanbecombinedinordertofunctionasa16/18-bitorwidermaster/slavedual-portstaticRAM.
AnM/Spinisprovidedforimplementing16/18-bitorwidermemoryapplicationswithouttheneedforseparatemasterandslavedevicesoradditionaldiscretelogic.
Applicationareasincludeinterprocessor/multiprocessordesigns,communicationsstatusbuffering,anddual-portvideo/graphicsmemory.
Eachporthasindependentcontrolpins:ChipEnable(CE),ReadorWriteEnable(R/W),andOutputEnable(OE).
Twoflagsareprovidedoneachport(BUSYandINT).
BUSYsignalsthattheportistryingtoaccessthesamelocationcurrentlybeingaccessedbytheotherport.
TheInterruptflag(INT)permitscommunicationbetweenportsorsystemsbymeansofamailbox.
Thesemaphoresareusedtopassaflag,ortoken,fromoneporttotheothertoindicatethatasharedresourceisinuse.
Thesemaphorelogiciscomprisedofeightsharedlatches.
Onlyonesidecancontrolthelatch(semaphore)atanytime.
Controlofasemaphoreindicatesthatasharedresourceisinuse.
Anautomaticpower-downfeatureiscontrolledindependentlyoneachportbyaChipSelect(CE)pin.
ReadandWriteOperationsWhenwritingdatamustbesetupforadurationoftSDbeforetherisingedgeofR/Winordertoguaranteeavalidwrite.
AwriteoperationiscontrolledbyeithertheR/Wpin(seeWriteCycleNo.
1waveform)ortheCEpin(seeWriteCycleNo.
2waveform).
Requiredinputsfornon-contentionoperationsaresummarizedinTable1.
Ifalocationisbeingwrittentobyoneportandtheoppositeportattemptstoreadthatlocation,aport-to-portflowthroughdelaymustoccurbeforethedataisreadontheoutput;otherwisethedatareadisnotdeterministic.
DatawillbevalidontheporttDDDafterthedataispresentedontheotherport.
Whenreadingthedevice,theusermustassertboththeOEandCEpins.
DatawillbeavailabletACEafterCEortDOEafterOEisasserted.
Iftheuserwishestoaccessasemaphoreflag,thentheSEMpinmustbeassertedinsteadoftheCEpinandOEmustalsobeasserted.
InterruptsTheuppertwomemorylocationsmaybeusedformessagepassing.
Thehighestmemorylocation(FFFfortheCY7C138AV/9AV,1FFFfortheCY7C144AV/5AV,3FFFfortheCY7C006AV/16AV,7FFFfortheCY7C007AV/17AV)isthemailboxfortherightportandthesecond-highestmemorylocation(FFEfortheCY7C138AV/9AV,1FFEfortheCY7C144AV/5AV,3FFEfortheCY7C006AV/16AV,7FFEfortheCY7C007AV/17AV)isthemailboxfortheleftport.
Whenoneportwritestotheotherport'smailbox,aninterruptisgeneratedtotheowner.
Theinterruptisresetwhentheownerreadsthecontentsofthemailbox.
Themessageisuserdefined.
Eachportcanreadtheotherport'smailboxwithoutresettingtheinterrupt.
Theactivestateofthebusysignal(toaport)PinDefinitionsLeftPortRightPortDescriptionCELCERChipEnableR/WLR/WRRead/WriteEnableOELOEROutputEnableA0L–A14LA0R–A14RAddress(A0–A11for4Kdevices;A0–A12for8Kdevices;A0–A13for16Kdevices;A0–A14for32K)I/O0L–I/O8LI/O0R–I/O8RDataBusInput/Output(I/O0–I/O7forx8devicesandI/O0–I/O8forx9)SEMLSEMRSemaphoreEnableINTLINTRInterruptFlagBUSYLBUSYRBusyFlagM/SMasterorSlaveSelectVCCPowerGNDGroundNCNoConnect[+]Feedbackwww.
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*CPage6of20preventstheportfromsettingtheinterrupttothewinningport.
Also,anactivebusytoaportpreventsthatportfromreadingitsownmailboxand,thus,resettingtheinterrupttoit.
Ifanapplicationdoesnotrequiremessagepassing,donotconnecttheinterruptpintotheprocessor'sinterruptrequestinputpin.
TheoperationoftheinterruptsandtheirinteractionwithBusyaresummarizedinTable2.
BusyTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVprovideon-chiparbitrationtoresolvesimultaneousmemorylocationaccess(contention).
Ifbothports'CEsareassertedandanaddressmatchoccurswithintPSofeachother,thebusylogicwilldeterminewhichporthasaccess.
IftPSisviolated,oneportwilldefinitelygainpermissiontothelocation,butitisnotpredictablewhichportwillgetthatpermission.
BUSYwillbeassertedtBLAafteranaddressmatchortBLCafterCEistakenLOW.
Master/SlaveAnM/Spinisprovidedinordertoexpandthewordwidthbyconfiguringthedeviceaseitheramasteroraslave.
TheBUSYoutputofthemasterisconnectedtotheBUSYinputoftheslave.
Thiswillallowthedevicetointerfacetoamasterdevicewithnoexternalcomponents.
WritingtoslavedevicesmustbedelayeduntilaftertheBUSYinputhassettled(tBLCortBLA),otherwise,theslavechipmaybeginawritecycleduringacontentionsituation.
WhentiedHIGH,theM/Spinallowsthedevicetobeusedasamasterand,therefore,theBUSYlineisanoutput.
BUSYcanthenbeusedtosendthearbitrationoutcometoaslave.
SemaphoreOperationTheCY7C138AV/144AV/006AV/007AVandCY7C139AV/145AV/016AV/017AVprovideeightsemaphorelatches,whichareseparatefromthedual-portmemorylocations.
Semaphoresareusedtoreserveresourcesthataresharedbetweenthetwoports.
Thestateofthesemaphoreindicatesthataresourceisinuse.
Forexample,iftheleftportwantstorequestagivenresource,itsetsalatchbywritingazerotoasemaphorelocation.
Theleftportthenverifiesitssuccessinsettingthelatchbyreadingit.
Afterwritingtothesemaphore,SEMorOEmustbedeassertedfortSOPbeforeattemptingtoreadthesemaphore.
ThesemaphorevaluewillbeavailabletSWRD+tDOEaftertherisingedgeofthesemaphorewrite.
Iftheleftportwassuccessful(readsazero),itassumescontrolofthesharedresource,otherwise(readsaone)itassumestherightporthascontrolandcontinuestopollthesemaphore.
Whentherightsidehasrelinquishedcontrolofthesemaphore(bywritingaone),theleftsidewillsucceedingainingcontrolofthesemaphore.
Iftheleftsidenolongerrequiresthesemaphore,aoneiswrittentocancelitsrequest.
SemaphoresareaccessedbyassertingSEMLOW.
TheSEMpinfunctionsasachipselectforthesemaphorelatches(CEmustremainHIGHduringSEMLOW).
A0–2representsthesemaphoreaddress.
OEandR/Wareusedinthesamemannerasanormalmemoryaccess.
Whenwritingorreadingasemaphore,theotheraddresspinshavenoeffect.
Whenwritingtothesemaphore,onlyI/O0isused.
Ifazeroiswrittentotheleftportofanavailablesemaphore,aonewillappearatthesamesemaphoreaddressontherightport.
Thatsemaphorecannowonlybemodifiedbythesideshowingzero(theleftportinthiscase).
Iftheleftportnowrelinquishescontrolbywritingaonetothesemaphore,thesemaphorewillbesettooneforbothsides.
However,iftherightporthadrequestedthesemaphore(writtenazero)whiletheleftporthadcontrol,therightportwouldimmediatelyownthesemaphoreassoonastheleftportreleasedit.
Table3showssamplesemaphoreoperations.
Whenreadingasemaphore,alldatalinesoutputthesemaphorevalue.
Thereadvalueislatchedinanoutputregistertopreventthesemaphorefromchangingstateduringawritefromtheotherport.
IfbothportsattempttoaccessthesemaphorewithintSPSofeachother,thesemaphorewilldefinitelybeobtainedbyonesideortheother,butthereisnoguaranteewhichsidewillcontrolthesemaphore.
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*CPage7of20MaximumRatings[10](Abovewhichtheusefullifemaybeimpaired.
Foruserguide-lines,nottested.
)StorageTemperature65°Cto+150°CAmbientTemperaturewithPowerApplied.
55°Cto+125°CSupplyVoltagetoGroundPotential.
0.
5Vto+4.
6VDCVoltageAppliedtoOutputsinHighZState.
0.
5VtoVCC+0.
5VDCInputVoltage[11]0.
5VtoVCC+0.
5VOutputCurrentintoOutputs(LOW)20mAStaticDischargeVoltage.
2001VLatch-UpCurrent.
200mA.
OperatingRangeRangeAmbientTemperatureVCCCommercial0°Cto+70°C3.
3V±300mVIndustrial[12]–40°Cto+85°C3.
3V±300mVElectricalCharacteristicsOvertheOperatingRangeParameterDescriptionCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AV-20-25UnitMin.
Typ.
Max.
Min.
Typ.
Max.
VOHOutputHIGHVoltage(VCC=3.
3V)2.
42.
4VVOLOutputLOWVoltage0.
40.
4VVIHInputHIGHVoltage2.
02.
0VVILInputLOWVoltage0.
80.
8VIOZOutputLeakageCurrent–1010–1010AICCOperatingCurrent(VCC=Max.
,IOUT=0mA)OutputsDisabledCom'l.
120175115165mAInd.
[12]140195mAISB1StandbyCurrent(BothPortsTTLLevel)CEL&CER≥VIH,f=fMAX[13]Com'l.
35453040mAInd.
[12]4555mAISB2StandbyCurrent(OnePortTTLLevel)CEL|CER≥VIH,f=fMAX[13]Com'l.
751106595mAInd.
[12]85130mAISB3StandbyCurrent(BothPortsCMOSLevel)CEL&CER≥VCC–0.
2V,f=0[13]Com'l.
1050010500AInd.
[12]10500AISB4StandbyCurrent(OnePortCMOSLevel)CEL|CER≥VIH,f=fMAX[13]Com'l.
70956080mAInd.
[12]80105mACapacitance[14]ParameterDescriptionTestConditionsMax.
UnitCINInputCapacitanceTA=25°C,f=1MHz,VCC=3.
3V10pFCOUTOutputCapacitance10pFNotes:10.
TheVoltageonanyinputorI/Opincannotexceedthepowerpinduringpower-up.
11.
PulsewidthtRCafterVCCreachestheminimumoperatingvoltage(3.
0volts).
Notes:20.
Forinformationonport-to-portdelaythroughRAMcellsfromwritingporttoreadingport,refertoReadTimingwithBusywaveform.
21.
TestconditionsusedareLoad2.
22.
tBDDisacalculatedparameterandisthegreateroftWDD–tPWE(actual)ortDDD–tSD(actual).
23.
CE=VCC,Vin=GNDtoVCC,TA=25°C.
Thisparameterisguaranteedbutnottested.
tHDDataHoldFromWriteEnd00nstHZWE[18,19]R/WLOWtoHighZ1215nstLZWE[18,19]R/WHIGHtoLowZ33nstWDD[20]WritePulsetoDataDelay4050nstDDD[20]WriteDataValidtoReadDataValid3035nsBUSYTIMING[21]tBLABUSYLOWfromAddressMatch2020nstBHABUSYHIGHfromAddressMismatch2020nstBLCBUSYLOWfromCELOW2020nstBHCBUSYHIGHfromCEHIGH1617nstPSPortSet-UpforPriority55nstWBR/WHIGHafterBUSY(Slave)00nstWHR/WHIGHafterBUSYHIGH(Slave)1517nstBDD[22]BUSYHIGHtoDataValid2025nsINTERRUPTTIMING[21]tINSINTSetTime2020nstINRINTResetTime2020nsSEMAPHORETIMINGtSOPSEMFlagUpdatePulse(OEorSEM)1012nstSWRDSEMFlagWritetoReadTime55nstSPSSEMFlagContentionWindow55nstSAASEMAddressAccessTime2025nsSwitchingCharacteristicsOvertheOperatingRange[15](continued)ParameterDescriptionCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVUnit-20-25Min.
Max.
Min.
Max.
TimingParameterTestConditions[23]Max.
UnitICCDR1@VCCDR=2V50ADataRetentionMode3.
0V3.
0VVCC>2.
0VVCCtoVCC–0.
2VVCCCEtRCVIH[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage10of20SwitchingWaveformsNotes:24.
R/WisHIGHforreadcycles.
25.
DeviceiscontinuouslyselectedCE=VIL.
Thiswaveformcannotbeusedforsemaphorereads.
26.
OE=VIL.
27.
AddressvalidpriortoorcoincidentwithCEtransitionLOW.
28.
ToaccessRAM,CE=VIL,SEM=VIH.
Toaccesssemaphore,CE=VIH,SEM=VIL.
tRCtAAtOHADATAVALIDPREVIOUSDATAVALIDDATAOUTADDRESStOHAReadCycleNo.
1(EitherPortAddressAccess)[24,25,26]tACEtLZOEtDOEtHZOEtHZCEDATAVALIDtLZCEtPUtPDISBICCDATAOUTOECECURRENTReadCycleNo.
2(EitherPortCE/OEAccess)[24,27,28]DATAOUTtRCADDRESStAAtOHACEtLZCEtABEtHZCEtACEtLZCEReadCycleNo.
3(EitherPort)[24,26,27,28][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage11of20Notes:29.
R/WmustbeHIGHduringalladdresstransitions.
30.
Awriteoccursduringtheoverlap(tSCEortPWE)ofaLOWCEorSEM.
31.
tHAismeasuredfromtheearlierofCEorR/Wor(SEMorR/W)goingHIGHattheendofwritecycle.
32.
IfOEisLOWduringaR/Wcontrolledwritecycle,thewritepulsewidthmustbethelargeroftPWEor(tHZWE+tSD)toallowtheI/OdriverstoturnoffanddatatobeplacedonthebusfortherequiredtSD.
IfOEisHIGHduringanR/Wcontrolledwritecycle,thisrequirementdoesnotapplyandthewritepulsecanbeasshortasthespecifiedtPWE.
33.
Transitionismeasured±500mVfromsteadystatewitha5-pFload(includingscopeandjig).
Thisparameterissampledandnot100%tested.
34.
ToaccessRAM,CE=VIL,SEM=VIH.
35.
Duringthisperiod,theI/Opinsareintheoutputstate,andinputsignalsmustnotbeapplied.
36.
IftheCEorSEMLOWtransitionoccurssimultaneouslywithoraftertheR/WLOWtransition,theoutputsremaininthehigh-impedancestate.
SwitchingWaveforms(continued)tAWtWCtPWEtHDtSDtHACER/WOEDATAOUTDATAINADDRESStHZOEtSAtHZWEtLZWEWriteCycleNo.
1:R/WControlledTiming[29,30,31,32][33][33][32][34]Note35Note35tAWtWCtSCEtHDtSDtHACER/WDATAINADDRESStSAWriteCycleNo.
2:CEControlledTiming[29,30,31,36][34][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage12of20Notes:37.
CE=HIGHforthedurationoftheabovetiming(bothwriteandreadcycle).
38.
I/O0R=I/O0L=LOW(requestsemaphore);CER=CEL=HIGH.
39.
Semaphoresarereset(availabletobothports)atcyclestart.
40.
IftSPSisviolated,thesemaphorewilldefinitelybeobtainedbyonesideortheother,butwhichsidewillgetthesemaphoreisunpredictable.
SwitchingWaveforms(continued)tSOPtSAAVALIDADRESSVALIDADRESStHDDATAINVALIDDATAOUTVALIDtOHAtAWtHAtACEtSOPtSCEtSDtSAtPWEtSWRDtDOEWRITECYCLEREADCYCLEOER/WI/O0SEMA0–A2SemaphoreReadAfterWriteTiming,EitherSide[37]MATCHtSPSA0L–A2LMATCHR/WLSEMLA0R–A2RR/WRSEMRTimingDiagramofSemaphoreContention[38,39,40][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage13of20Note:41.
CEL=CER=LOW.
SwitchingWaveforms(continued)VALIDtDDDtWDDMATCHMATCHR/WRDATAINRDATAOUTLtWCADDRESSRtPWEVALIDtSDtHDADDRESSLtPStBLAtBHAtBDDBUSYLTimingDiagramofReadwithBUSY(M/S=HIGH)[41]tPWER/WBUSYtWBtWHWriteTimingwithBusyInput(M/S=LOW)[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage14of20Note:42.
IftPSisviolated,thebusysignalwillbeassertedononesideortheother,butthereisnoguaranteetowhichsideBUSYwillbeasserted.
SwitchingWaveforms(continued)ADDRESSMATCHtPStBLCtBHCADDRESSMATCHtPStBLCtBHCCERValidFirst:ADDRESSL,RBUSYRCELCERBUSYLCERCELADDRESSL,RBusyTimingDiagramNo.
1(CEArbitration)[42]CELValidFirst:ADDRESSMATCHtPSADDRESSLBUSYRADDRESSMISMATCHtRCortWCtBLAtBHAADDRESSRADDRESSMATCHADDRESSMISMATCHtPSADDRESSLBUSYLtRCortWCtBLAtBHAADDRESSRRightAddressValidFirst:BusyTimingDiagramNo.
2(AddressArbitration)[42]LeftAddressValidFirst[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage15of20Notes:43.
tHAdependsonwhichenablepin(CELorR/WL)isdeassertedfirst.
44.
tINSortINRdependsonwhichenablepin(CELorR/WL)isassertedlast.
SwitchingWaveforms(continued)InterruptTimingDiagramsWRITEFFF(SeeFunctionalDescription)tWCRightSideClearsINTR:tHAREADFFFtRCtINRWRITEFFE(SeeFunctionalDescription)tWCRightSideSetsINTL:LeftSideSetsINTR:LeftSideClearsINTL:READFFEtINRtRCADDRESSRCELR/WLINTLOELADDRESSRR/WRCERINTLADDRESSRCERR/WRINTROERADDRESSLR/WLCELINTRtINStHAtINS(SeeFunctionalDescription)(SeeFunctionalDescription)[43][44][44][44][43][44][+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage16of20Table1.
Non-ContendingRead/WriteInputsOutputsCER/WOESEMI/O0–I/O8OperationHXXHHighZDeselected:Power-DownHHLLDataOutReadDatainSemaphoreFlagXXHXHighZI/OLinesDisabledHXLDataInWriteintoSemaphoreFlagLHLHDataOutReadLLXHDataInWriteLXXLNotAllowedTable2.
InterruptOperationExample(assumesBUSYL=BUSYR=HIGH)LeftPortRightPortFunctionR/WLCELOELA0L–14LINTLR/WRCEROERA0R–14RINTRSetRightINTRFlagLLXFFF[45]XXXXXL[46]ResetRightINTRFlagXXXXXXLLFFF[45]H[47]SetLeftINTLFlagXXXXL[47]LLX1FFE[45]XResetLeftINTLFlagXLL1FFE[45]H[46]XXXXXTable3.
SemaphoreOperationExampleFunctionI/O0–I/O8LeftI/O0–I/O8RightStatusNoaction11SemaphorefreeLeftportwrites0tosemaphore01LeftPorthassemaphoretokenRightportwrites0tosemaphore01Nochange.
RightsidehasnowriteaccesstosemaphoreLeftportwrites1tosemaphore10RightportobtainssemaphoretokenLeftportwrites0tosemaphore10Nochange.
LeftporthasnowriteaccesstosemaphoreRightportwrites1tosemaphore01LeftportobtainssemaphoretokenLeftportwrites1tosemaphore11SemaphorefreeRightportwrites0tosemaphore10RightporthassemaphoretokenRightportwrites1tosemaphore11SemaphorefreeLeftportwrites0tosemaphore01LeftporthassemaphoretokenLeftportwrites1tosemaphore11SemaphorefreeNote:45.
SeeFunctionalDescriptionforspecificaddressesbydevicepartnumber.
46.
IfBUSYL=L,thennochange.
47.
IfBUSYR=L,thennochange.
[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage17of20OrderingInformationPackageAvailabilityGuideDeviceOrganization68-PinPLCC64-PinTQFPCY7C138AV4Kx8XCY7C139AV4Kx9XCY7C144AV8Kx8XXCY7C145AV8Kx9XCY7C006AV16Kx8XXCY7C016AV16Kx9XCY7C007AV32Kx8XCY7C017AV32Kx9X4Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C138AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C138AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial4Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C139AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C139AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial8Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C144AV–20ACA6564-PinThinQuadFlatPackCommercialCY7C144AV–20JCJ8168-PinPlasticLeadedChipCarrier25CY7C144AV–25ACA6564-PinThinQuadFlatPackCommercialCY7C144AV-25AXCA6564-PinPb-FreeThinQuadFlatPackCY7C144AV–25JCJ8168-PinPlasticLeadedChipCarrierCY7C144AV-25JXCJ8168-PinPb-FreePlasticLeadedChipCarrier8Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C145AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C145AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial16Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C006AV–20ACA6564-PinThinQuadFlatPackCommercialCY7C006AV–20JCJ8168-PinPlasticLeadedChipCarrier25CY7C006AV–25ACA6564-PinThinQuadFlatPackCommercialCY7C006AV-25AXCA6564-PinPb-FreeThinQuadFlatPackCY7C006AV–25JCJ8168-PinPlasticLeadedChipCarrier[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage18of20OrderingInformation(continued)16Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C016AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercial25CY7C016AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial32Kx83.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C007AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercialCY7C007AV–20JIJ8168-PinPlasticLeadedChipCarrierIndustrial25CY7C007AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial32Kx93.
3VAsynchronousDual-PortSRAMSpeed(ns)OrderingCodePackageNamePackageTypeOperatingRange20CY7C017AV–20JCJ8168-PinPlasticLeadedChipCarrierCommercialCY7C017AV–20JIJ8168-PinPlasticLeadedChipCarrierIndustrial25CY7C017AV–25JCJ8168-PinPlasticLeadedChipCarrierCommercial[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage19of20CypressSemiconductorCorporation,2005.
Theinformationcontainedhereinissubjecttochangewithoutnotice.
CypressSemiconductorCorporationassumesnoresponsibilityfortheuseofanycircuitryotherthancircuitryembodiedinaCypressproduct.
Nordoesitconveyorimplyanylicenseunderpatentorotherrights.
Cypressproductsarenotwarrantednorintendedtobeusedformedical,lifesupport,lifesaving,criticalcontrolorsafetyapplications,unlesspursuanttoanexpresswrittenagreementwithCypress.
Furthermore,Cypressdoesnotauthorizeitsproductsforuseascriticalcomponentsinlife-supportsystemswhereamalfunctionorfailuremayreasonablybeexpectedtoresultinsignificantinjurytotheuser.
TheinclusionofCypressproductsinlife-supportsystemsapplicationimpliesthatthemanufacturerassumesallriskofsuchuseandindoingsoindemnifiesCypressagainstallcharges.
Allproductsandcompanynamesmentionedinthisdocumentmaybethetrademarksoftheirrespectiveholders.
PackageDiagrams64-LeadThinPlasticQuadFlatPack(14x14x1.
4mm)A6551-85046-*B64-LeadPb-FreeThinPlasticQuadFlatPack(14x14x1.
4mm)A6568-LeadPlasticLeadedChipCarrierJ8151-85005-*A68-LeadPb-FreePlasticLeadedChipCarrierJ81[+]FeedbackCY7C138AV/144AV/006AVCY7C139AV/145AV/016AVCY7C007AV/017AVDocument#:38-06051Rev.
*CPage20of20DocumentHistoryPageDocumentTitle:CY7C138AV/144AV/006AV/CY7C139AV/145AV/016AV/CY7C007AV/017AV3.
3V4K/8K/16K/32Kx8/9DualPortSRAMDocumentNumber:38-06051REV.
ECNNO.
IssueDateOrig.
ofChangeDescriptionofChange**11020312/02/01SZVChangefromSpecnumber:38-00837to38-06051*A12230112/27/02RBIPoweruprequirementsaddedtoMaximumRatingsInformation*B237623SeeECNYDTRemovedcrossinformationfromfeaturessection*C373615SeeECNPCXAddedPb-FreeLogoAddedPb-Freepartstoorderinginformation:CY7C144AV-25AXC,CY7C144AV-25JXC,CY7C006AV-25AXC[+]Feedback
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